Attachment 90096 Details for Bug 71906 – Fix

[patch] Fix

0001-drm-i915-Implement-IPS-state-readout-for-BDW.patch (text/plain), 2.65 KB, created by Ville Syrjala on 2013-12-02 09:50:54 UTC

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Creator: Ville Syrjala

Created: 2013-12-02 09:50:54 UTC

Size: 2.65 KB

patch

obsolete

>From da363e1ea96feb83c9de5e00e4576805e4bf92bc Mon Sep 17 00:00:00 2001
>From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
>Date: Mon, 2 Dec 2013 11:41:24 +0200
>Subject: [PATCH] drm/i915: Implement IPS state readout for BDW
>MIME-Version: 1.0
>Content-Type: text/plain; charset=UTF-8
>Content-Transfer-Encoding: 8bit
>
>Use the mailbox interface to determine IPS state for BDW.
>
>Also give names to the magic IPS bits.
>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71906
>Signed-off-by: Ville SyrjÃ¤lÃ¤ <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h      |  1 +
> drivers/gpu/drm/i915/intel_display.c | 17 ++++++++++++++---
> 2 files changed, 15 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 3be449d..6a68e65 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -4988,6 +4988,7 @@
> #define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
> #define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
> #define   DISPLAY_IPS_CONTROL			0x19
>+#define    IPS_PCODE_CONTROL			(1 << 30)
> #define GEN6_PCODE_DATA				0x138128
> #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
> #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 0bb3d6d..466703a 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -3408,7 +3408,8 @@ void hsw_enable_ips(struct intel_crtc *crtc)
> 	assert_plane_enabled(dev_priv, crtc->plane);
> 	if (IS_BROADWELL(crtc->base.dev)) {
> 		mutex_lock(&dev_priv->rps.hw_lock);
>-		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
>+		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
>+						IPS_ENABLE | IPS_PCODE_CONTROL));
> 		mutex_unlock(&dev_priv->rps.hw_lock);
> 		/* Quoting Art Runyan: "its not safe to expect any particular
> 		 * value in IPS_CTL bit 31 after enabling IPS through the
>@@ -6977,8 +6978,18 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> 	if (intel_display_power_enabled(dev, pfit_domain))
> 		ironlake_get_pfit_config(crtc, pipe_config);
> 
>-	pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
>-				   (I915_READ(IPS_CTL) & IPS_ENABLE);
>+	if (hsw_crtc_supports_ips(crtc)) {
>+		if (IS_BROADWELL(dev)) {
>+			u32 val = 0;
>+
>+			mutex_lock(&dev_priv->rps.hw_lock);
>+			WARN_ON(sandybridge_pcode_read(dev_priv, DISPLAY_IPS_CONTROL, &val));
>+			mutex_unlock(&dev_priv->rps.hw_lock);
>+
>+			pipe_config->ips_enabled = val & IPS_ENABLE;
>+		} else
>+			pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
>+	}
> 
> 	pipe_config->pixel_multiplier = 1;
> 
>-- 
>1.8.3.2
>

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Attachments on bug 71906: 89619 | 90096 | 90215 | 90855

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