Attachment 90215 Details for Bug 71906 – Additional debug patch

[patch] Additional debug patch

0001-debug.patch (text/plain), 2.96 KB, created by Ville Syrjala on 2013-12-04 10:46:45 UTC

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Creator: Ville Syrjala

Created: 2013-12-04 10:46:45 UTC

Size: 2.96 KB

patch

obsolete

>From 01678de6ea0ee7528410d33bd8e0a0cbd7be2acc Mon Sep 17 00:00:00 2001
>From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
>Date: Wed, 4 Dec 2013 12:44:20 +0200
>Subject: [PATCH] debug
>
>---
> drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 466703a..1943b4d 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -3407,9 +3407,17 @@ void hsw_enable_ips(struct intel_crtc *crtc)
> 	 * for a vblank, so all we need to do here is to enable the IPS bit. */
> 	assert_plane_enabled(dev_priv, crtc->plane);
> 	if (IS_BROADWELL(crtc->base.dev)) {
>+		u32 val;
>+
> 		mutex_lock(&dev_priv->rps.hw_lock);
>+		val = 0xdeadbeef;
>+		WARN_ON(sandybridge_pcode_read(dev_priv, DISPLAY_IPS_CONTROL, &val));
>+		DRM_DEBUG_KMS("DISPLAY_IPS_CONTROL = %x\n", val);
> 		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
> 						IPS_ENABLE | IPS_PCODE_CONTROL));
>+		val = 0xdeadbeef;
>+		WARN_ON(sandybridge_pcode_read(dev_priv, DISPLAY_IPS_CONTROL, &val));
>+		DRM_DEBUG_KMS("DISPLAY_IPS_CONTROL = %x\n", val);
> 		mutex_unlock(&dev_priv->rps.hw_lock);
> 		/* Quoting Art Runyan: "its not safe to expect any particular
> 		 * value in IPS_CTL bit 31 after enabling IPS through the
>@@ -3439,8 +3447,16 @@ void hsw_disable_ips(struct intel_crtc *crtc)
> 
> 	assert_plane_enabled(dev_priv, crtc->plane);
> 	if (IS_BROADWELL(crtc->base.dev)) {
>+		u32 val;
>+
> 		mutex_lock(&dev_priv->rps.hw_lock);
>+		val = 0xdeadbeef;
>+		WARN_ON(sandybridge_pcode_read(dev_priv, DISPLAY_IPS_CONTROL, &val));
>+		DRM_DEBUG_KMS("DISPLAY_IPS_CONTROL = %x\n", val);
> 		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
>+		val = 0xdeadbeef;
>+		WARN_ON(sandybridge_pcode_read(dev_priv, DISPLAY_IPS_CONTROL, &val));
>+		DRM_DEBUG_KMS("DISPLAY_IPS_CONTROL = %x\n", val);
> 		mutex_unlock(&dev_priv->rps.hw_lock);
> 	} else
> 		I915_WRITE(IPS_CTL, 0);
>@@ -6983,13 +6999,16 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> 			u32 val = 0;
> 
> 			mutex_lock(&dev_priv->rps.hw_lock);
>+			val = 0xdeadbeef;
> 			WARN_ON(sandybridge_pcode_read(dev_priv, DISPLAY_IPS_CONTROL, &val));
>+			DRM_DEBUG_KMS("DISPLAY_IPS_CONTROL = %x\n", val);
> 			mutex_unlock(&dev_priv->rps.hw_lock);
> 
> 			pipe_config->ips_enabled = val & IPS_ENABLE;
> 		} else
> 			pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE;
> 	}
>+	DRM_DEBUG_KMS("ips_enabled = %d\n", pipe_config->ips_enabled);
> 
> 	pipe_config->pixel_multiplier = 1;
> 
>@@ -9621,6 +9640,9 @@ static int __intel_set_mode(struct drm_crtc *crtc,
> 	 * to set it here already despite that we pass it down the callchain.
> 	 */
> 	if (modeset_pipes) {
>+		DRM_DEBUG_KMS("old ips_enabled = %d\n", to_intel_crtc(crtc)->config.ips_enabled);
>+		DRM_DEBUG_KMS("new ips_enabled = %d\n", pipe_config->ips_enabled);
>+
> 		crtc->mode = *mode;
> 		/* mode_set/enable/disable functions rely on a correct pipe
> 		 * config. */
>-- 
>1.8.3.2
>

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