Attachment 92115 Details for Bug 73511 – [PATCH rebased] drm/radeon: add query to fetch the max engine clock.

[patch] [PATCH rebased] drm/radeon: add query to fetch the max engine clock.

0001-drm-radeon-add-query-to-fetch-the-max-engine-clock.patch (text/plain), 2.42 KB, created by Igor Gnatenko on 2014-01-15 07:26:28 UTC

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Creator: Igor Gnatenko

Created: 2014-01-15 07:26:28 UTC

Size: 2.42 KB

patch

obsolete

>From 5cfc43194c7ff16c0241efcf5cbad6164de40253 Mon Sep 17 00:00:00 2001
>From: Alex Deucher <alexander.deucher@amd.com>
>Date: Tue, 14 Jan 2014 14:44:16 -0500
>Subject: [PATCH] drm/radeon: add query to fetch the max engine clock.
>
>This is needed for reporting the max GPU engine clock
>in OpenCL.  This just reports the max possible engine
>clock, it does not take into account current conditions
>that may limit that clock.
>
>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>---
> drivers/gpu/drm/radeon/radeon_kms.c |  7 +++++++
> drivers/gpu/drm/radeon/rv770_dpm.c  | 14 ++++++--------
> 2 files changed, 13 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
>index 21d593c..ef7c456 100644
>--- a/drivers/gpu/drm/radeon/radeon_kms.c
>+++ b/drivers/gpu/drm/radeon/radeon_kms.c
>@@ -470,6 +470,13 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
> 			DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
> 		}
> 		break;
>+	case RADEON_INFO_MAX_SCLK:
>+		if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
>+		    rdev->pm.dpm_enabled)
>+			*value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
>+		else
>+			*value = rdev->pm.default_sclk * 10;
>+		break;
> 	default:
> 		DRM_DEBUG_KMS("Invalid request %d\n", info->request);
> 		return -EINVAL;
>diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c
>index 374499d..94456d8 100644
>--- a/drivers/gpu/drm/radeon/rv770_dpm.c
>+++ b/drivers/gpu/drm/radeon/rv770_dpm.c
>@@ -2244,14 +2244,12 @@ static void rv7xx_parse_pplib_clock_info(struct radeon_device *rdev,
> 		pl->vddci = vddci;
> 	}
> 
>-	if (rdev->family >= CHIP_BARTS) {
>-		if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
>-		    ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
>-			rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
>-			rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
>-			rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
>-			rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
>-		}
>+	if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
>+	    ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
>+		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
>+		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
>+		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
>+		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
> 	}
> }
> 
>-- 
>1.8.4.2
>

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