Attachment 92872 Details for Bug 73704 – quick_dump.py -a with i915.modeset=0, no plymouth

quick_dump.py -a with i915.modeset=0, no plymouth

quick-dump-nomodeset-no-plymouth.txt (text/plain), 35.10 KB, created by roberth on 2014-01-27 18:42:16 UTC

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Description:

Filename:

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Creator: roberth

Created: 2014-01-27 18:42:16 UTC

Size: 35.10 KB

patch

obsolete

>Forcing forcewake. Don't expect your system to work after this.
>  offset   |        base_power.txt        |   value   
>------------------------------------------------------
>0x0000a008 | GEN6_RPNSWREQ                | 0x00000000
>0x0000a00c | GEN6_RC_VIDEO_FREQ           | 0x00000000
>0x0000a010 | GEN6_RP_DOWN_TIMEOUT         | 0x000f4240
>0x0000a014 | GEN6_RP_INTERRUPT_LIMITS     | 0x00000000
>0x0000a024 | GEN6_RP_CONTROL              | 0x00000592
>0x0000a02c | GEN6_RP_UP_THRESHOLD         | 0x0000e8e8
>0x0000a068 | GEN6_RP_UP_EI                | 0x000101d0
>0x0000a06c | GEN6_RP_DOWN_EI              | 0x00055730
>0x0000a070 | GEN6_RP_IDLE_HYSTERSIS       | 0x0000000a
>0x0000a090 | GEN6_RC_CONTROL              | 0x11000000
>0x0000a094 | GEN6_RC_STATE                | 0x00000000
>0x0000a098 | GEN6_RC1_WAKE_RATE_LIMIT     | 0x00000000
>0x0000a09c | GEN6_RC6_WAKE_RATE_LIMIT     | 0x00280000
>0x0000a0a8 | GEN6_RC_EVALUATION_INTERVAL  | 0x0001e848
>0x0000a0ac | GEN6_RC_IDLE_HYSTERSIS       | 0x00000019
>0x0000a0b0 | GEN6_RC_SLEEP                | 0x00000000
>0x0000a0b4 | GEN6_RC1e_THRESHOLD          | 0x00000000
>0x0000a0b8 | GEN6_RC6_THRESHOLD           | 0x00000557
>0x00138108 | RC6_RESIDENCY_TIME           | 0xb8271d71
>0x0013810c | RC6p_RESIDENCY_TIME          | 0x20df8811
>0x00138110 | RC6pp_RESIDENCY_TIME         | 0x00000000
>
>  offset   |        base_rings.txt        |   value   
>------------------------------------------------------
>0x000020c0 | RENDER_INSTPM                | 0x00008000
>0x000120c0 | BSD_INSTPM                   | 0x00000000
>0x000220c0 | BLT_INSTPM                   | 0x00000000
>0x00002030 | RENDER_RING_TAIL             | 0x00000000
>0x00012030 | BSD_RING_TAIL                | 0x00000000
>0x00022030 | BLT_RING_TAIL                | 0x00000000
>0x00002034 | RENDER_RING_HEAD             | 0x00000000
>0x00012034 | BSD_RING_HEAD                | 0x00000000
>0x00022034 | BLT_RING_HEAD                | 0x00000000
>0x00002038 | RENDER_RING_START            | 0x00000000
>0x00012038 | BSD_RING_START               | 0x00000000
>0x00022038 | BLT_RING_START               | 0x00000000
>0x0000203c | RENDER_RING_CTL              | 0x00000000
>0x0001203c | BSD_RING_CTL                 | 0x00000000
>0x0002203c | BLT_RING_CTL                 | 0x00000000
>0x00002064 | RENDER_IPEIR                 | 0x00000000
>0x00012064 | BSD_IPEIR                    | 0x00000000
>0x00022064 | BLT_IPEIR                    | 0x00000000
>0x00002068 | RENDER_IPEHR                 | 0x11001061
>0x00012068 | BSD_IPEHR                    | 0x00000000
>0x00022068 | BLT_IPEHR                    | 0x00000000
>0x0000206c | RENDER_INSTDONE              | 0xfffffffe
>0x0001206c | BSD_INSTDONE                 | 0xfffffffe
>0x0002206c | BLT_INSTDONE                 | 0xfffffffe
>0x00002070 | RENDER_INSTPS                | 0x00000000
>0x00012070 | BSD_INSTPS                   | 0x00000000
>0x00022070 | BLT_INSTPS                   | 0x00000000
>0x00002074 | RENDER_RING_ACTHD            | 0x00000000
>0x00012074 | BSD_RING_ACTHD               | 0x00000000
>0x00022074 | BLT_RING_ACTHD               | 0x00000000
>0x00002078 | RENDER_FADDR                 | 0x00000000
>0x00012078 | BSD_FADDR                    | 0x00000000
>0x00022078 | BLT_FADDR                    | 0x00000000
>
>  offset   |        base_other.txt        |   value   
>------------------------------------------------------
>0x00002020 | PGETBL_CTL                   | 0x00000000
>0x0000209c | MI_MODE                      | 0x00000200
>0x00002180 | CCID                         | 0x00000000
>0x000040a0 | ERROR_GEN6                   | 0x00000000
>0x00002098 | RENDER_HWSTAM                | 0xffffffff
>0x00012098 | GEN6_BSD_HWSTAM              | 0xffffffff
>0x00022098 | GEN6_BLITTER_HWSTAM          | 0xffffffff
>
>  offset   |       base_display.txt       |   value   
>------------------------------------------------------
>0x00041000 | CPU_VGACNTRL                 | 0x00000000
>0x00042308 | PORT_DBG                     | 0x00000000
>0x00044030 | DIGITAL_PORT_HOTPLUG_CNTRL   | 0x00000000
>0x00046000 | FDI_PLL_BIOS_0               | 0x00000000
>0x00046004 | FDI_PLL_BIOS_1               | 0x00000000
>0x00046008 | FDI_PLL_BIOS_2               | 0x00000000
>0x0004600c | DISPLAY_PORT_PLL_BIOS_0      | 0x00000000
>0x00046010 | DISPLAY_PORT_PLL_BIOS_1      | 0x00000000
>0x00046014 | DISPLAY_PORT_PLL_BIOS_2      | 0x00000000
>0x00046030 | FDI_PLL_FREQ_CTL             | 0x00000000
>0x00048250 | BLC_PWM_CPU_CTL2             | 0x00000000
>0x00048254 | BLC_PWM_CPU_CTL              | 0x00000000
>0x00060000 | HTOTAL_A                     | 0x00000000
>0x00060004 | HBLANK_A                     | 0x00000000
>0x00060008 | HSYNC_A                      | 0x00000000
>0x0006000c | VTOTAL_A                     | 0x00000000
>0x00060010 | VBLANK_A                     | 0x00000000
>0x00060014 | VSYNC_A                      | 0x00000000
>0x0006001c | PIPEASRC                     | 0x00000000
>0x00060028 | VSYNCSHIFT_A                 | 0x00000000
>0x00060030 | PIPEA_DATA_M1                | 0x00000000
>0x00060034 | PIPEA_DATA_N1                | 0x00000000
>0x00060038 | PIPEA_DATA_M2                | 0x00000000
>0x0006003c | PIPEA_DATA_N2                | 0x00000000
>0x00060040 | PIPEA_LINK_M1                | 0x00000000
>0x00060044 | PIPEA_LINK_N1                | 0x00000000
>0x00060048 | PIPEA_LINK_M2                | 0x00000000
>0x0006004c | PIPEA_LINK_N2                | 0x00000000
>0x00060100 | FDI_TXA_CTL                  | 0x00000000
>0x00061000 | HTOTAL_B                     | 0x00000000
>0x00061004 | HBLANK_B                     | 0x00000000
>0x00061008 | HSYNC_B                      | 0x00000000
>0x0006100c | VTOTAL_B                     | 0x00000000
>0x00061010 | VBLANK_B                     | 0x00000000
>0x00061014 | VSYNC_B                      | 0x00000000
>0x0006101c | PIPEBSRC                     | 0x00000000
>0x00061028 | VSYNCSHIFT_B                 | 0x00000000
>0x00061030 | PIPEB_DATA_M1                | 0x00000000
>0x00061034 | PIPEB_DATA_N1                | 0x00000000
>0x00061038 | PIPEB_DATA_M2                | 0x00000000
>0x0006103c | PIPEB_DATA_N2                | 0x00000000
>0x00061040 | PIPEB_LINK_M1                | 0x00000000
>0x00061044 | PIPEB_LINK_N1                | 0x00000000
>0x00061048 | PIPEB_LINK_M2                | 0x00000000
>0x0006104c | PIPEB_LINK_N2                | 0x00000000
>0x00061100 | FDI_TXB_CTL                  | 0x00000000
>0x00062000 | HTOTAL_C                     | 0x00000000
>0x00062004 | HBLANK_C                     | 0x00000000
>0x00062008 | HSYNC_C                      | 0x00000000
>0x0006200c | VTOTAL_C                     | 0x00000000
>0x00062010 | VBLANK_C                     | 0x00000000
>0x00062014 | VSYNC_C                      | 0x00000000
>0x0006201c | PIPECSRC                     | 0x00000000
>0x00062028 | VSYNCSHIFT_C                 | 0x00000000
>0x00062030 | PIPEC_DATA_M1                | 0x00000000
>0x00062034 | PIPEC_DATA_N1                | 0x00000000
>0x00062038 | PIPEC_DATA_M2                | 0x00000000
>0x0006203c | PIPEC_DATA_N2                | 0x00000000
>0x00062040 | PIPEC_LINK_M1                | 0x00000000
>0x00062044 | PIPEC_LINK_N1                | 0x00000000
>0x00062048 | PIPEC_LINK_M2                | 0x00000000
>0x0006204c | PIPEC_LINK_N2                | 0x00000000
>0x00062100 | FDI_TXC_CTL                  | 0x00000000
>0x00064000 | CPU_eDP_A                    | 0x00000000
>0x00068070 | PFA_WIN_POS                  | 0x00000000
>0x00068074 | PFA_WIN_SIZE                 | 0x00000000
>0x00068080 | PFA_CTL_1                    | 0x00000000
>0x00068084 | PFA_CTL_2                    | 0x00000000
>0x00068088 | PFA_CTL_3                    | 0x00000000
>0x00068090 | PFA_CTL_4                    | 0x00000000
>0x00068870 | PFB_WIN_POS                  | 0x00000000
>0x00068874 | PFB_WIN_SIZE                 | 0x00000000
>0x00068880 | PFB_CTL_1                    | 0x00000000
>0x00068884 | PFB_CTL_2                    | 0x00000000
>0x00068888 | PFB_CTL_3                    | 0x00000000
>0x00068890 | PFB_CTL_4                    | 0x00000000
>0x00069070 | PFC_WIN_POS                  | 0x00000000
>0x00069074 | PFC_WIN_SIZE                 | 0x00000000
>0x00069080 | PFC_CTL_1                    | 0x00000000
>0x00069084 | PFC_CTL_2                    | 0x00000000
>0x00069088 | PFC_CTL_3                    | 0x00000000
>0x00069090 | PFC_CTL_4                    | 0x00000000
>0x00070008 | PIPEACONF                    | 0x00000000
>0x00070180 | DSPACNTR                     | 0x00000000
>0x00070184 | DSPABASE                     | 0x00000000
>0x00070188 | DSPASTRIDE                   | 0x00000000
>0x0007019c | DSPASURF                     | 0x00000000
>0x000701a4 | DSPATILEOFF                  | 0x00000000
>0x00071008 | PIPEBCONF                    | 0x00000000
>0x00071180 | DSPBCNTR                     | 0x00000000
>0x00071184 | DSPBBASE                     | 0x00000000
>0x00071188 | DSPBSTRIDE                   | 0x00000000
>0x0007119c | DSPBSURF                     | 0x00000000
>0x000711a4 | DSPBTILEOFF                  | 0x00000000
>0x00072008 | PIPECCONF                    | 0x00000000
>0x00072180 | DSPCCNTR                     | 0x00000000
>0x00072184 | DSPCBASE                     | 0x00000000
>0x00072188 | DSPCSTRIDE                   | 0x00000000
>0x0007219c | DSPCSURF                     | 0x00000000
>0x000721a4 | DSPCTILEOFF                  | 0x00000000
>0x000c6014 | PCH_DPLL_A                   | 0x00000000
>0x000c6018 | PCH_DPLL_B                   | 0x00000000
>0x000c6040 | PCH_FPA0                     | 0x00000000
>0x000c6044 | PCH_FPA1                     | 0x00000000
>0x000c6048 | PCH_FPB0                     | 0x00000000
>0x000c604c | PCH_FPB1                     | 0x00000000
>0x000c6200 | PCH_DREF_CONTROL             | 0x00000000
>0x000c6204 | PCH_RAWCLK_FREQ              | 0x00000000
>0x000c6208 | PCH_DPLL_TMR_CFG             | 0x00000000
>0x000c6210 | PCH_SSC4_PARMS               | 0x00000000
>0x000c6214 | PCH_SSC4_AUX_PARMS           | 0x00000000
>0x000c6300 | PCH_DPLL_ANALOG_CTL          | 0x00000000
>0x000c7000 | PCH_DPLL_SEL                 | 0x00000000
>0x000c7200 | PCH_PP_STATUS                | 0x00000000
>0x000c7204 | PCH_PP_CONTROL               | 0x00000000
>0x000c7208 | PCH_PP_ON_DELAYS             | 0x00000000
>0x000c720c | PCH_PP_OFF_DELAYS            | 0x00000000
>0x000c7210 | PCH_PP_DIVISOR               | 0x00000000
>0x000c8250 | BLC_PWM_PCH_CTL1             | 0x00000000
>0x000c8254 | BLC_PWM_PCH_CTL2             | 0x00000000
>0x000e0000 | TRANS_HTOTAL_A               | 0x00000000
>0x000e0004 | TRANS_HBLANK_A               | 0x00000000
>0x000e0008 | TRANS_HSYNC_A                | 0x00000000
>0x000e000c | TRANS_VTOTAL_A               | 0x00000000
>0x000e0010 | TRANS_VBLANK_A               | 0x00000000
>0x000e0014 | TRANS_VSYNC_A                | 0x00000000
>0x000e0028 | TRANS_VSYNCSHIFT_A           | 0x00000000
>0x000e0030 | TRANSA_DATA_M1               | 0x00000000
>0x000e0034 | TRANSA_DATA_N1               | 0x00000000
>0x000e0038 | TRANSA_DATA_M2               | 0x00000000
>0x000e003c | TRANSA_DATA_N2               | 0x00000000
>0x000e0040 | TRANSA_DP_LINK_M1            | 0x00000000
>0x000e0044 | TRANSA_DP_LINK_N1            | 0x00000000
>0x000e0048 | TRANSA_DP_LINK_M2            | 0x00000000
>0x000e004c | TRANSA_DP_LINK_N2            | 0x00000000
>0x000e0300 | TRANS_DP_CTL_A               | 0x00000000
>0x000e1000 | TRANS_HTOTAL_B               | 0x00000000
>0x000e1004 | TRANS_HBLANK_B               | 0x00000000
>0x000e1008 | TRANS_HSYNC_B                | 0x00000000
>0x000e100c | TRANS_VTOTAL_B               | 0x00000000
>0x000e1010 | TRANS_VBLANK_B               | 0x00000000
>0x000e1014 | TRANS_VSYNC_B                | 0x00000000
>0x000e1028 | TRANS_VSYNCSHIFT_B           | 0x00000000
>0x000e1030 | TRANSB_DATA_M1               | 0x00000000
>0x000e1034 | TRANSB_DATA_N1               | 0x00000000
>0x000e1038 | TRANSB_DATA_M2               | 0x00000000
>0x000e103c | TRANSB_DATA_N2               | 0x00000000
>0x000e1040 | TRANSB_DP_LINK_M1            | 0x00000000
>0x000e1044 | TRANSB_DP_LINK_N1            | 0x00000000
>0x000e1048 | TRANSB_DP_LINK_M2            | 0x00000000
>0x000e104c | TRANSB_DP_LINK_N2            | 0x00000000
>0x000e1100 | PCH_ADPA                     | 0x00000000
>0x000e1140 | HDMIB                        | 0x00000000
>0x000e1150 | HDMIC                        | 0x00000000
>0x000e1160 | HDMID                        | 0x00000000
>0x000e1180 | PCH_LVDS                     | 0x00000000
>0x000e1300 | TRANS_DP_CTL_B               | 0x00000000
>0x000e2000 | TRANS_HTOTAL_C               | 0x00000000
>0x000e2004 | TRANS_HBLANK_C               | 0x00000000
>0x000e2008 | TRANS_HSYNC_C                | 0x00000000
>0x000e200c | TRANS_VTOTAL_C               | 0x00000000
>0x000e2010 | TRANS_VBLANK_C               | 0x00000000
>0x000e2014 | TRANS_VSYNC_C                | 0x00000000
>0x000e2028 | TRANS_VSYNCSHIFT_C           | 0x00000000
>0x000e2030 | TRANSC_DATA_M1               | 0x00000000
>0x000e2034 | TRANSC_DATA_N1               | 0x00000000
>0x000e2038 | TRANSC_DATA_M2               | 0x00000000
>0x000e203c | TRANSC_DATA_N2               | 0x00000000
>0x000e2040 | TRANSC_DP_LINK_M1            | 0x00000000
>0x000e2044 | TRANSC_DP_LINK_N1            | 0x00000000
>0x000e2048 | TRANSC_DP_LINK_M2            | 0x00000000
>0x000e204c | TRANSC_DP_LINK_N2            | 0x00000000
>0x000e2300 | TRANS_DP_CTL_C               | 0x00000000
>0x000e4100 | PCH_DP_B                     | 0x00000000
>0x000e4200 | PCH_DP_C                     | 0x00000000
>0x000e4300 | PCH_DP_D                     | 0x00000000
>0x000f0008 | TRANSACONF                   | 0x00000000
>0x000f000c | FDI_RXA_CTL                  | 0x00000000
>0x000f0010 | FDI_RXA_MISC                 | 0x00000000
>0x000f0014 | FDI_RXA_IIR                  | 0x00000000
>0x000f0018 | FDI_RXA_IMR                  | 0x00000000
>0x000f0030 | FDI_RXA_TUSIZE1              | 0x00000000
>0x000f0038 | FDI_RXA_TUSIZE2              | 0x00000000
>0x000f1008 | TRANSBCONF                   | 0x00000000
>0x000f100c | FDI_RXB_CTL                  | 0x00000000
>0x000f1010 | FDI_RXB_MISC                 | 0x00000000
>0x000f1014 | FDI_RXB_IIR                  | 0x00000000
>0x000f1018 | FDI_RXB_IMR                  | 0x00000000
>0x000f1030 | FDI_RXB_TUSIZE1              | 0x00000000
>0x000f1038 | FDI_RXB_TUSIZE2              | 0x00000000
>0x000f2008 | TRANSCCONF                   | 0x00000000
>0x000f200c | FDI_RXC_CTL                  | 0x00000000
>0x000f2010 | FDI_RXC_MISC                 | 0x00000000
>0x000f2030 | FDI_RXC_TUSIZE1              | 0x00000000
>0x000f2038 | FDI_RXC_TUSIZE2              | 0x00000000
>0x000fe000 | FDI_PLL_CTL_1                | 0x00000000
>0x000fe004 | FDI_PLL_CTL_2                | 0x00000000
>
>  offset   |      base_interrupt.txt      |   value   
>------------------------------------------------------
>0x0000a168 | GEN6_PMINTRMSK               | 0x0000007e
>0x00044000 | DEISR                        | 0x00000000
>0x00044004 | DEIMR                        | 0x00000000
>0x00044008 | DEIIR                        | 0x00000000
>0x0004400c | DEIER                        | 0x00000000
>0x00044010 | GTISR                        | 0x00000000
>0x00044014 | GTIMR                        | 0xffffffff
>0x00044018 | GTIIR                        | 0x00000000
>0x0004401c | GTIER                        | 0x00000000
>0x00044020 | GEN6_PMISR                   | 0x00000000
>0x00044024 | GEN6_PMIMR                   | 0x03000000
>0x00044028 | GEN6_PMIIR                   | 0x00000000
>0x0004402c | GEN6_PMIER                   | 0x03000076
>0x000c4000 | SDEISR                       | 0x00000000
>0x000c4004 | SDEIMR                       | 0x00000000
>0x000c4008 | SDEIIR                       | 0x00000000
>0x000c400c | SDEIER                       | 0x00000000
>0x000020a8 | RENDER_IMR                   | 0xffffffff
>0x000120a8 | BSD_IMR                      | 0xffffffff
>0x000220a8 | BLT_IMR                      | 0xffffffff
>
>  offset   |       vlv_display.txt        |   value   
>------------------------------------------------------
>0x00186014 | DPLLA_CTRL                   | 0xf000a00f
>0x00186018 | DPLLB_CTRL                   | 0x20006000
>0x0018601c | DPLLAMD_CRTL                 | 0x00000003
>0x00186020 | DPLLBMD_CRTL                 | 0x00000003
>0x00186024 | RAWCLK_FREQ                  | 0x0000007d
>0x00186104 | D_STAT                       | 0x20d00400
>0x00186200 | DISPCLK_GATE_D               | 0x10000000
>0x00186204 | DPPSR_CGDIS                  | 0x00000a00
>0x00186210 | RAMCLK_GATE_D                | 0x00000000
>0x001c1000 | CPU_VGACNTRL                 | 0xffffffff
>0x001e0000 | HTOTAL_A                     | 0x083f063f
>0x001e0004 | HBLANK_A                     | 0x083f063f
>0x001e0008 | HSYNC_A                      | 0x06a70657
>0x001e000c | VTOTAL_A                     | 0x039d0383
>0x001e0010 | VBLANK_A                     | 0x039d0383
>0x001e0014 | VSYNC_A                      | 0x03870384
>0x001e001c | PIPEASRC                     | 0x063f0383
>0x001e0028 | VSYNCSHIFT_A                 | 0x00000000
>0x001e0030 | PIPEA_DATA_M1                | 0x7e3e8f5c
>0x001e0034 | PIPEA_DATA_N1                | 0x00800000
>0x001e0038 | PIPEA_DATA_M2                | 0x00000000
>0x001e003c | PIPEA_DATA_N2                | 0x00000000
>0x001e0040 | PIPEA_LINK_M1                | 0x000379be
>0x001e0044 | PIPEA_LINK_N1                | 0x00080000
>0x001e0048 | PIPEA_LINK_M2                | 0x00000000
>0x001e004c | PIPEA_LINK_N2                | 0x00000000
>0x001e1000 | HTOTAL_B                     | 0x00000000
>0x001e1004 | HBLANK_B                     | 0x00000000
>0x001e1008 | HSYNC_B                      | 0x00000000
>0x001e100c | VTOTAL_B                     | 0x00000000
>0x001e1010 | VBLANK_B                     | 0x00000000
>0x001e1014 | VSYNC_B                      | 0x00000000
>0x001e101c | PIPEBSRC                     | 0x00000000
>0x001e1028 | VSYNCSHIFT_B                 | 0x00000000
>0x001e1030 | PIPEB_DATA_M1                | 0x7e000000
>0x001e1034 | PIPEB_DATA_N1                | 0x00000000
>0x001e1038 | PIPEB_DATA_M2                | 0x00000000
>0x001e103c | PIPEB_DATA_N2                | 0x00000000
>0x001e1040 | PIPEB_LINK_M1                | 0x00000000
>0x001e1044 | PIPEB_LINK_N1                | 0x00000000
>0x001e1048 | PIPEB_LINK_M2                | 0x00000000
>0x001e104c | PIPEB_LINK_N2                | 0x00000000
>0x001e1100 | ADPA                         | 0x00000018
>0x001e1110 | PORT_HOTPLUG_EN              | 0x00000000
>0x001e1114 | PORT_HOTPLUG_STAT            | 0x00000000
>0x001e1140 | SDVO_HDMIB                   | 0x00000018
>0x001e1154 | SDVO_DP2                     | 0x00000000
>0x001e1160 | HDMIC                        | 0x0000001c
>0x001e1164 | PORT_HOTPLUG_CTRL            | 0x00000000
>0x001e4100 | DP_B                         | 0x00000018
>0x001e4200 | DP_C                         | 0xb00c001c
>0x001f002c | DPINVGTT                     | 0x00000000
>0x001f0030 | DSPARB                       | 0xc080c080
>0x001f0034 | FW1                          | 0x3f8f0f0f
>0x001f0038 | FW2                          | 0x0b0f0f0f
>0x001f003c | FW3                          | 0x00000000
>0x001f0070 | FW4                          | 0x00040404
>0x001f0074 | FW5                          | 0x04040404
>0x001f0078 | FW6                          | 0x00000078
>0x001f007c | FW7                          | 0x040f040f
>0x001f0050 | DDL1                         | 0x00000000
>0x001f0052 | DDL2                         | 0x00000000
>0x001f0060 | DSPARB2                      | 0x00001111
>0x001f0064 | DSPHOWM                      | 0x00000000
>0x001f0068 | DSPHOWM1                     | 0x00000000
>0x001f0008 | PIPEACONF                    | 0xc0000040
>0x001f0024 | PIPEASTAT                    | 0x00000607
>0x001f0180 | DSPACNTR                     | 0x98000000
>0x001f0184 | DSPABASE                     | 0x00000000
>0x001f0188 | DSPASTRIDE                   | 0x00001900
>0x001f019c | DSPASURF                     | 0x00000000
>0x001f01a4 | DSPATILEOFF                  | 0x00000000
>0x001f1008 | PIPEBCONF                    | 0x00000000
>0x001f1024 | PIPEBSTAT                    | 0x00000000
>0x001f1180 | DSPBCNTR                     | 0x00000000
>0x001f1184 | DSPBBASE                     | 0x00000000
>0x001f1188 | DSPBSTRIDE                   | 0x00000000
>0x001f119c | DSPBSURF                     | 0x00000000
>0x001f11a4 | DSPBTILEOFF                  | 0x00000000
>0x001f2008 | PIPECCONF                    | 0x00000000
>0x001f2180 | DSPCCNTR                     | 0x00000000
>0x001f2184 | DSPCBASE                     | 0x00000000
>0x001f2188 | DSPCSTRIDE                   | 0x00000000
>0x001f219c | DSPCSURF                     | 0x00000000
>0x001f21a4 | DSPCTILEOFF                  | 0x00000000
>0x001e1200 | PIPEA_PP_STATUS              | 0xc0000008
>0x001e1204 | PIPEA_PP_CONTROL             | 0x00000007
>0x001e1208 | PIPEA_PP_ON_DELAYS           | 0x87d0000a
>0x001e120c | PIPEA_PP_OFF_DELAYS          | 0x01f407d0
>0x001e1210 | PIPEA_PP_DIVISOR             | 0x00270f06
>0x001e1300 | PIPEB_PP_STATUS              | 0x00000000
>0x001e1304 | PIPEB_PP_CONTROL             | 0x00000002
>0x001e1308 | PIPEB_PP_ON_DELAYS           | 0x00000000
>0x001e130c | PIPEB_PP_OFF_DELAYS          | 0x00000000
>0x001e1310 | PIPEB_PP_DIVISOR             | 0x00270f04
>0x001e1250 | BLC_PWM_CTL2                 | 0x80000000
>0x001e1254 | BLC_PWM_CTL                  | 0xcb3fcb3f
>
>  offset   |         vlv_dsi.txt          |   value   
>------------------------------------------------------
>0x001e1190 | MIPIA_PORT_CTRL              | 0x00000000
>0x001e1194 | MIPIA_TEARING_CTRL           | 0x00000000
>0x001e11a0 | MIPIA_AUTOPWG                | 0x00000000
>0x0018b000 | MIPIA_DEVICE_READY           | 0x00000000
>0x0018b004 | MIPIA_INTR_STAT              | 0x00000000
>0x0018b008 | MIPIA_INTR_EN                | 0x00000000
>0x0018b00c | MIPIA_DSI_FUNC_PRG           | 0x00000001
>0x0018b010 | MIPIA_HS_TX_TIMEOUT          | 0x00000000
>0x0018b014 | MIPIA_LP_RX_TIMEOUT          | 0x00000000
>0x0018b018 | MIPIA_TURN_AROUND_TIMEOUT    | 0x00000000
>0x0018b01c | MIPIA_DEVICE_RESET_TIMER     | 0x00000000
>0x0018b020 | MIPIA_DPI_RESOLUTION         | 0x00000000
>0x0018b024 | MIPIA_DBI_FIFO_THROTTLE      | 0x00000000
>0x0018b028 | MIPIA_HSYNC_PADDING_COUNT    | 0x00000000
>0x0018b02c | MIPIA_HBP_COUNT              | 0x00000000
>0x0018b030 | MIPIA_HFP_COUNT              | 0x00000000
>0x0018b034 | MIPIA_HACTIVE_AREA_COUNT     | 0x00000000
>0x0018b038 | MIPIA_VSYNC_PADDING_COUNT    | 0x00000000
>0x0018b03c | MIPIA_VBP_COUNT              | 0x00000000
>0x0018b040 | MIPIA_VFP_COUNT              | 0x00000000
>0x0018b044 | MIPIA_HIGH_LOW_SWITCH_COUNT  | 0x00000000
>0x0018b048 | MIPIA_DPI_CONTROL            | 0x00000000
>0x0018b04c | MIPIA_DPI_DATA               | 0x00000000
>0x0018b050 | MIPIA_INIT_COUNT             | 0x00000000
>0x0018b054 | MIPIA_MAX_RETURN_PKT_SIZE    | 0x00000000
>0x0018b058 | MIPIA_VIDEO_MODE_FORMAT      | 0x00000000
>0x0018b05c | MIPIA_EOT_DISABLE            | 0x00000000
>0x0018b060 | MIPIA_LP_BYTECLK             | 0x00000000
>0x0018b064 | MIPIA_LP_GEN_DATA            | 0x00000000
>0x0018b068 | MIPIA_HS_GEN_DATA            | 0x00000000
>0x0018b06c | MIPIA_LP_GEN_CTRL            | 0x00000000
>0x0018b070 | MIPIA_HS_GEN_CTRL            | 0x00000000
>0x0018b074 | MIPIA_GEN_FIFO_STAT          | 0x0e060606
>0x0018b078 | MIPIA_HS_LS_DBI_ENABLE       | 0x00000000
>0x0018b080 | MIPIA_DPHY_PARAM             | 0x0b061a04
>0x0018b084 | MIPIA_DBI_BW_CTRL            | 0x00000000
>0x0018b088 | MIPIA_CLK_LANE_SWITCH_TIME_CNT | 0x00000000
>0x0018b08c | MIPIA_STOP_STATE_STALL       | 0x00000000
>0x0018b090 | MIPIA_INTR_STAT_REG_1        | 0x00000000
>0x0018b094 | MIPIA_INTR_EN_REG_1          | 0x00000000
>0x0018b100 | MIPIA_DBI_TYPEC_CTRL         | 0x00000200
>0x0018b104 | MIPIA_CTRL                   | 0x00000000
>0x0018b108 | MIPIA_DATA_ADDRESS           | 0x00000000
>0x0018b10c | MIPIA_DATA_LENGTH            | 0x00000000
>0x0018b110 | MIPIA_COMMAND_ADDRESS        | 0x00000000
>0x0018b114 | MIPIA_COMMAND_LENGTH         | 0x00000000
>0x0018b118 | MIPIA_READ_DATA_RETURN0      | 0x00000000
>0x0018b11c | MIPIA_READ_DATA_RETURN1      | 0x00000000
>0x0018b120 | MIPIA_READ_DATA_RETURN2      | 0x00000000
>0x0018b124 | MIPIA_READ_DATA_RETURN3      | 0x00000000
>0x0018b128 | MIPIA_READ_DATA_RETURN4      | 0x00000000
>0x0018b12c | MIPIA_READ_DATA_RETURN5      | 0x00000000
>0x0018b130 | MIPIA_READ_DATA_RETURN6      | 0x00000000
>0x0018b134 | MIPIA_READ_DATA_RETURN7      | 0x00000000
>0x0018b138 | MIPIA_READ_DATA_VALID        | 0x00000000
>0x001e1700 | MIPIB_PORT_CTRL              | 0x00000000
>0x001e1704 | MIPIB_TEARING_CTRL           | 0x00000000
>0x0018b800 | MIPIB_DEVICE_READY           | 0x00000000
>0x0018b804 | MIPIB_INTR_STAT              | 0x00000000
>0x0018b808 | MIPIB_INTR_EN                | 0x00000000
>0x0018b80c | MIPIB_DSI_FUNC_PRG           | 0x00000001
>0x0018b810 | MIPIB_HS_TX_TIMEOUT          | 0x00000000
>0x0018b814 | MIPIB_LP_RX_TIMEOUT          | 0x00000000
>0x0018b818 | MIPIB_TURN_AROUND_TIMEOUT    | 0x00000000
>0x0018b81c | MIPIB_DEVICE_RESET_TIMER     | 0x00000000
>0x0018b820 | MIPIB_DPI_RESOLUTION         | 0x00000000
>0x0018b824 | MIPIB_DBI_FIFO_THROTTLE      | 0x00000000
>0x0018b828 | MIPIB_HSYNC_PADDING_COUNT    | 0x00000000
>0x0018b82c | MIPIB_HBP_COUNT              | 0x00000000
>0x0018b830 | MIPIB_HFP_COUNT              | 0x00000000
>0x0018b834 | MIPIB_HACTIVE_AREA_COUNT     | 0x00000000
>0x0018b838 | MIPIB_VSYNC_PADDING_COUNT    | 0x00000000
>0x0018b83c | MIPIB_VBP_COUNT              | 0x00000000
>0x0018b840 | MIPIB_VFP_COUNT              | 0x00000000
>0x0018b844 | MIPIB_HIGH_LOW_SWITCH_COUNT  | 0x00000000
>0x0018b848 | MIPIB_DPI_CONTROL            | 0x00000000
>0x0018b84c | MIPIB_DPI_DATA               | 0x00000000
>0x0018b850 | MIPIB_INIT_COUNT             | 0x00000000
>0x0018b854 | MIPIB_MAX_RETURN_PKT_SIZE    | 0x00000000
>0x0018b858 | MIPIB_VIDEO_MODE_FORMAT      | 0x00000000
>0x0018b85c | MIPIB_EOT_DISABLE            | 0x00000000
>0x0018b860 | MIPIB_LP_BYTECLK             | 0x00000000
>0x0018b864 | MIPIB_LP_GEN_DATA            | 0x00000000
>0x0018b868 | MIPIB_HS_GEN_DATA            | 0x00000000
>0x0018b86c | MIPIB_LP_GEN_CTRL            | 0x00000000
>0x0018b870 | MIPIB_HS_GEN_CTRL            | 0x00000000
>0x0018b874 | MIPIB_GEN_FIFO_STAT          | 0x0e060606
>0x0018b878 | MIPIB_HS_LS_DBI_ENABLE       | 0x00000000
>0x0018b880 | MIPIB_DPHY_PARAM             | 0x0b061a04
>0x0018b884 | MIPIB_DBI_BW_CTRL            | 0x00000000
>0x0018b888 | MIPIB_CLK_LANE_SWITCH_TIME_CNT | 0x00000000
>0x0018b88c | MIPIB_STOP_STATE_STALL       | 0x00000000
>0x0018b890 | MIPIB_INTR_STAT_REG_1        | 0x00000000
>0x0018b894 | MIPIB_INTR_EN_REG_1          | 0x00000000
>0x0018b904 | MIPIB_CTRL                   | 0x00000000
>0x0018b908 | MIPIB_DATA_ADDRESS           | 0x00000000
>0x0018b90c | MIPIB_DATA_LENGTH            | 0x00000000
>0x0018b910 | MIPIB_COMMAND_ADDRESS        | 0x00000000
>0x0018b914 | MIPIB_COMMAND_LENGTH         | 0x00000000
>0x0018b918 | MIPIB_READ_DATA_RETURN0      | 0x00000000
>0x0018b91c | MIPIB_READ_DATA_RETURN1      | 0x00000000
>0x0018b920 | MIPIB_READ_DATA_RETURN2      | 0x00000000
>0x0018b924 | MIPIB_READ_DATA_RETURN3      | 0x00000000
>0x0018b928 | MIPIB_READ_DATA_RETURN4      | 0x00000000
>0x0018b92c | MIPIB_READ_DATA_RETURN5      | 0x00000000
>0x0018b930 | MIPIB_READ_DATA_RETURN6      | 0x00000000
>0x0018b934 | MIPIB_READ_DATA_RETURN7      | 0x00000000
>0x0018b938 | MIPIB_READ_DATA_VALID        | 0x00000000
>
>  offset   |      base_interrupt.txt      |   value   
>------------------------------------------------------
>0x0000a168 | GEN6_PMINTRMSK               | 0x0000007e
>0x00044000 | DEISR                        | 0x00000000
>0x00044004 | DEIMR                        | 0x00000000
>0x00044008 | DEIIR                        | 0x00000000
>0x0004400c | DEIER                        | 0x00000000
>0x00044010 | GTISR                        | 0x00000000
>0x00044014 | GTIMR                        | 0xffffffff
>0x00044018 | GTIIR                        | 0x00000000
>0x0004401c | GTIER                        | 0x00000000
>0x00044020 | GEN6_PMISR                   | 0x00000000
>0x00044024 | GEN6_PMIMR                   | 0x03000000
>0x00044028 | GEN6_PMIIR                   | 0x00000000
>0x0004402c | GEN6_PMIER                   | 0x03000076
>0x000c4000 | SDEISR                       | 0x00000000
>0x000c4004 | SDEIMR                       | 0x00000000
>0x000c4008 | SDEIIR                       | 0x00000000
>0x000c400c | SDEIER                       | 0x00000000
>0x000020a8 | RENDER_IMR                   | 0xffffffff
>0x000120a8 | BSD_IMR                      | 0xffffffff
>0x000220a8 | BLT_IMR                      | 0xffffffff
>
>  offset   |        base_other.txt        |   value   
>------------------------------------------------------
>0x00002020 | PGETBL_CTL                   | 0x00000000
>0x0000209c | MI_MODE                      | 0x00000200
>0x00002180 | CCID                         | 0x00000000
>0x000040a0 | ERROR_GEN6                   | 0x00000000
>0x00002098 | RENDER_HWSTAM                | 0xffffffff
>0x00012098 | GEN6_BSD_HWSTAM              | 0xffffffff
>0x00022098 | GEN6_BLITTER_HWSTAM          | 0xffffffff
>
>  offset   |        base_power.txt        |   value   
>------------------------------------------------------
>0x0000a008 | GEN6_RPNSWREQ                | 0x00000000
>0x0000a00c | GEN6_RC_VIDEO_FREQ           | 0x00000000
>0x0000a010 | GEN6_RP_DOWN_TIMEOUT         | 0x000f4240
>0x0000a014 | GEN6_RP_INTERRUPT_LIMITS     | 0x00000000
>0x0000a024 | GEN6_RP_CONTROL              | 0x00000592
>0x0000a02c | GEN6_RP_UP_THRESHOLD         | 0x0000e8e8
>0x0000a068 | GEN6_RP_UP_EI                | 0x000101d0
>0x0000a06c | GEN6_RP_DOWN_EI              | 0x00055730
>0x0000a070 | GEN6_RP_IDLE_HYSTERSIS       | 0x0000000a
>0x0000a090 | GEN6_RC_CONTROL              | 0x11000000
>0x0000a094 | GEN6_RC_STATE                | 0x00000000
>0x0000a098 | GEN6_RC1_WAKE_RATE_LIMIT     | 0x00000000
>0x0000a09c | GEN6_RC6_WAKE_RATE_LIMIT     | 0x00280000
>0x0000a0a8 | GEN6_RC_EVALUATION_INTERVAL  | 0x0001e848
>0x0000a0ac | GEN6_RC_IDLE_HYSTERSIS       | 0x00000019
>0x0000a0b0 | GEN6_RC_SLEEP                | 0x00000000
>0x0000a0b4 | GEN6_RC1e_THRESHOLD          | 0x00000000
>0x0000a0b8 | GEN6_RC6_THRESHOLD           | 0x00000557
>0x00138108 | RC6_RESIDENCY_TIME           | 0xb8271d71
>0x0013810c | RC6p_RESIDENCY_TIME          | 0x2166560b
>0x00138110 | RC6pp_RESIDENCY_TIME         | 0x00000000
>
>  offset   |        base_rings.txt        |   value   
>------------------------------------------------------
>0x000020c0 | RENDER_INSTPM                | 0x00008000
>0x000120c0 | BSD_INSTPM                   | 0x00000000
>0x000220c0 | BLT_INSTPM                   | 0x00000000
>0x00002030 | RENDER_RING_TAIL             | 0x00000000
>0x00012030 | BSD_RING_TAIL                | 0x00000000
>0x00022030 | BLT_RING_TAIL                | 0x00000000
>0x00002034 | RENDER_RING_HEAD             | 0x00000000
>0x00012034 | BSD_RING_HEAD                | 0x00000000
>0x00022034 | BLT_RING_HEAD                | 0x00000000
>0x00002038 | RENDER_RING_START            | 0x00000000
>0x00012038 | BSD_RING_START               | 0x00000000
>0x00022038 | BLT_RING_START               | 0x00000000
>0x0000203c | RENDER_RING_CTL              | 0x00000000
>0x0001203c | BSD_RING_CTL                 | 0x00000000
>0x0002203c | BLT_RING_CTL                 | 0x00000000
>0x00002064 | RENDER_IPEIR                 | 0x00000000
>0x00012064 | BSD_IPEIR                    | 0x00000000
>0x00022064 | BLT_IPEIR                    | 0x00000000
>0x00002068 | RENDER_IPEHR                 | 0x11001061
>0x00012068 | BSD_IPEHR                    | 0x00000000
>0x00022068 | BLT_IPEHR                    | 0x00000000
>0x0000206c | RENDER_INSTDONE              | 0xfffffffe
>0x0001206c | BSD_INSTDONE                 | 0xfffffffe
>0x0002206c | BLT_INSTDONE                 | 0xfffffffe
>0x00002070 | RENDER_INSTPS                | 0x00000000
>0x00012070 | BSD_INSTPS                   | 0x00000000
>0x00022070 | BLT_INSTPS                   | 0x00000000
>0x00002074 | RENDER_RING_ACTHD            | 0x00000000
>0x00012074 | BSD_RING_ACTHD               | 0x00000000
>0x00022074 | BLT_RING_ACTHD               | 0x00000000
>0x00002078 | RENDER_FADDR                 | 0x00000000
>0x00012078 | BSD_FADDR                    | 0x00000000
>0x00022078 | BLT_FADDR                    | 0x00000000
>
>  offset   |        gen7_other.txt        |   value   
>------------------------------------------------------
>0x0000229c | GFX_MODE_GEN7                | 0x00002800
>
>  offset   |         vlv_dpio.txt         |   value   
>------------------------------------------------------
>0x00182110 | DPIO_CTL                     | 0x00000001
>0x00000690 | DPIO_TX3_DW4_CH0             | 0x2b404d55
>0x00002a90 | DPIO_TX3_DW4_CH1             | 0x2b405555
>0x0000800c | DPIO_PLL_DW3_CH0             | 0x1142121b
>0x0000802c | DPIO_PLL_DW3_CH1             | 0x11411219
>0x00008014 | DPIO_PLL_DW5_CH0             | 0x0df40000
>0x00008034 | DPIO_PLL_DW5_CH1             | 0x00750080
>0x0000801c | DPIO_PLL_DW7_CH0             | 0x01c00000
>0x0000803c | DPIO_PLL_DW7_CH1             | 0x00000000
>0x00008040 | DPIO_PLL_DW8_CH0             | 0x00610080
>0x00008060 | DPIO_PLL_DW8_CH1             | 0x00610080
>0x0000c044 | DPIO_PLL_DW9_BCAST           | 0xffffffff
>0x00008044 | DPIO_PLL_DW9_CH0             | 0x00000000
>0x00008064 | DPIO_PLL_DW9_CH1             | 0x00000000
>0x00008048 | DPIO_PLL_DW10_CH0            | 0x00d0000f
>0x00008068 | DPIO_PLL_DW10_CH1            | 0x005f007f
>0x0000804c | DPIO_PLL_DW11_CH0            | 0xebeb1000
>0x0000806c | DPIO_PLL_DW11_CH1            | 0xebeb1000
>0x000080ac | DPIO_REF_DW13                | 0xb07f0100
>0x00008100 | DPIO_CMN_DW0                 | 0x00000610
>0x0000810c | DPIO_CMN_DW4                 | 0x54540000
>0x00008200 | DPIO_PCS_DW0_CH0             | 0xffffffff
>0x00008400 | DPIO_PCS_DW0_CH1             | 0xffffffff
>0x00008204 | DPIO_PCS_DW1_CH0             | 0xffffffff
>0x00008404 | DPIO_PCS_DW1_CH1             | 0xffffffff
>0x00000220 | DPIO_PCS01_DW8_CH0           | 0x000000c4
>0x00000420 | DPIO_PCS23_DW8_CH0           | 0x000000c4
>0x00002620 | DPIO_PCS01_DW8_CH1           | 0x001000c4
>0x00002820 | DPIO_PCS23_DW8_CH1           | 0x000000c4
>0x00008220 | DPIO_PCS_DW8_CH0             | 0xffffffff
>0x00008420 | DPIO_PCS_DW8_CH1             | 0xffffffff
>0x00008224 | DPIO_PCS_DW9_CH0             | 0xffffffff
>0x00008424 | DPIO_PCS_DW9_CH1             | 0xffffffff
>0x0000822c | DPIO_PCS_DW11_CH0            | 0xffffffff
>0x0000842c | DPIO_PCS_DW11_CH1            | 0xffffffff
>0x00008230 | DPIO_PCS_DW12_CH0            | 0xffffffff
>0x00008430 | DPIO_PCS_DW12_CH1            | 0xffffffff
>0x00008238 | DPIO_PCS_DW14_CH0            | 0xffffffff
>0x00008438 | DPIO_PCS_DW14_CH1            | 0xffffffff
>0x0000825c | DPIO_PCS_DW23_CH0            | 0xffffffff
>0x0000845c | DPIO_PCS_DW23_CH1            | 0xffffffff
>0x00008288 | DPIO_TX_DW2_CH0              | 0xffffffff
>0x00008488 | DPIO_TX_DW2_CH1              | 0xffffffff
>0x0000828c | DPIO_TX_DW3_CH0              | 0xffffffff
>0x0000848c | DPIO_TX_DW3_CH1              | 0xffffffff
>0x00008290 | DPIO_TX_DW4_CH0              | 0xffffffff
>0x00008490 | DPIO_TX_DW4_CH1              | 0xffffffff
>0x00008294 | DPIO_TX_DW5_CH0              | 0xffffffff
>0x00008494 | DPIO_TX_DW5_CH1              | 0xffffffff
>0x000082ac | DPIO_TX_DW11_CH0             | 0xffffffff
>0x000084ac | DPIO_TX_DW11_CH1             | 0xffffffff
>0x000082b8 | DPIO_TX_DW14_CH0             | 0xffffffff
>0x000084b8 | DPIO_TX_DW14_CH1             | 0xffffffff
>0x00002600 | lane1 ctl ddi1               | 0x00010080
>0x00002604 | lane1 ctl ddi1               | 0x00600060
>0x00002800 | lane2 ctl ddi1               | 0x00010080
>0x00002804 | lane3 ctl ddi1               | 0x00600060
>0x00000200 | lane1 ctl ddi0               | 0x00010080
>0x00000204 | lane1 ctl ddi0               | 0x00600060
>0x00000400 | lane2 ctl ddi0               | 0x00010080
>0x00000404 | lane3 ctl ddi0               | 0x00600060
>

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