Attachment 93147 Details for Bug 74256 – Patch to always emit workaround flushes, rather than being stingy about it

[patch] Patch to always emit workaround flushes, rather than being stingy about it

always-post-sync-nonzero.patch (text/plain), 4.06 KB, created by Kenneth Graunke on 2014-01-31 17:01:01 UTC

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Creator: Kenneth Graunke

Created: 2014-01-31 17:01:01 UTC

Size: 4.06 KB

patch

obsolete

>From e6b48a92e3e9944fbc419f925a5811317897bf55 Mon Sep 17 00:00:00 2001
>From: Kenneth Graunke <kenneth@whitecape.org>
>Date: Fri, 31 Jan 2014 08:29:04 +0000
>Subject: i965: Drop need_workaround_flush flag; always do post-sync workaround.
>
>The need_workaround_flush flag was an attempt to avoid doing the
>post-sync non-zero workaround flush unless it was actually necessary.
>
>Getting the tracking right is tricky; we've messed it up several times.
>
>The cost of getting this wrong is high: almost certainly a GPU hang.
>The cost of always doing the flush is low: it's just another flush,
>and on Sandybridge, we're doing piles of them anyway.  And every time
>we've added more post-sync non-zero workarounds, the system has become
>more stable.
>
>Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
>---
>diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
>index 8d098e6..bba7d97 100644
>--- a/src/mesa/drivers/dri/i965/brw_context.h
>+++ b/src/mesa/drivers/dri/i965/brw_context.h
>@@ -870,7 +870,6 @@ struct intel_batchbuffer {
>    drm_intel_bo *last_bo;
>    /** BO for post-sync nonzero writes for gen6 workaround. */
>    drm_intel_bo *workaround_bo;
>-   bool need_workaround_flush;
> 
>    struct cached_batch_item *cached_items;
> 
>diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
>index 39da953..e4c24e9 100644
>--- a/src/mesa/drivers/dri/i965/brw_draw.c
>+++ b/src/mesa/drivers/dri/i965/brw_draw.c
>@@ -276,9 +276,6 @@ static void brw_emit_prim(struct brw_context *brw,
>    OUT_BATCH(base_vertex_location);
>    ADVANCE_BATCH();
> 
>-   /* Only used on Sandybridge; harmless to set elsewhere. */
>-   brw->batch.need_workaround_flush = true;
>-
>    if (brw->always_flush_cache) {
>       intel_batchbuffer_emit_mi_flush(brw);
>    }
>diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
>index 90b9fbb..01db084 100644
>--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
>+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
>@@ -1010,9 +1010,6 @@ gen6_blorp_emit_primitive(struct brw_context *brw,
>    OUT_BATCH(0);
>    OUT_BATCH(0);
>    ADVANCE_BATCH();
>-
>-   /* Only used on Sandybridge; harmless to set elsewhere. */
>-   brw->batch.need_workaround_flush = true;
> }
> 
> /**
>@@ -1037,9 +1034,6 @@ gen6_blorp_exec(struct brw_context *brw,
> 
>    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
> 
>-   /* Emit workaround flushes when we switch from drawing to blorping. */
>-   brw->batch.need_workaround_flush = true;
>-
>    gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
>    gen6_emit_3dstate_sample_mask(brw,
>                                  params->dst.num_samples > 1 ?
>diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
>index caec312..efa4ab6 100644
>--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
>+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
>@@ -70,8 +70,6 @@ intel_batchbuffer_init(struct brw_context *brw)
> 						      4096, 4096);
>    }
> 
>-   brw->batch.need_workaround_flush = true;
>-
>    if (!brw->has_llc) {
>       brw->batch.cpu_map = malloc(BATCH_SZ);
>       brw->batch.map = brw->batch.cpu_map;
>@@ -206,11 +204,6 @@ brw_new_batch(struct brw_context *brw)
> 
>    brw->state.dirty.brw |= BRW_NEW_BATCH;
> 
>-   /* Assume that the last command before the start of our batch was a
>-    * primitive, for safety.
>-    */
>-   brw->batch.need_workaround_flush = true;
>-
>    brw->state_batch_count = 0;
> 
>    brw->ib.type = -1;
>@@ -610,17 +603,12 @@ gen7_emit_cs_stall_flush(struct brw_context *brw)
> void
> intel_emit_post_sync_nonzero_flush(struct brw_context *brw)
> {
>-   if (!brw->batch.need_workaround_flush)
>-      return;
>-
>    brw_emit_pipe_control_flush(brw,
>                                PIPE_CONTROL_CS_STALL |
>                                PIPE_CONTROL_STALL_AT_SCOREBOARD);
> 
>    brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_IMMEDIATE,
>                                brw->batch.workaround_bo, 0, 0, 0);
>-
>-   brw->batch.need_workaround_flush = false;
> }
> 
> /* Emit a pipelined flush to either flush render and texture cache for
>--
>cgit v0.9.0.2-2-gbebe

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