Attachment 94766 Details for Bug 70254 – drm/i915: Increase WM memory latency values on SNB with high pixel clock

[patch] drm/i915: Increase WM memory latency values on SNB with high pixel clock

0001-drm-i915-Increase-WM-memory-latency-values-on-SNB-wi.patch (text/plain), 4.51 KB, created by Ville Syrjala on 2014-02-26 13:16:26 UTC

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Creator: Ville Syrjala

Created: 2014-02-26 13:16:26 UTC

Size: 4.51 KB

patch

obsolete

>From 48b6914988f73ab56080421d89c6848ed1401e8b Mon Sep 17 00:00:00 2001
>From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
>Date: Wed, 26 Feb 2014 14:25:29 +0200
>Subject: [PATCH] drm/i915: Increase WM memory latency values on SNB with high
> pixel clock
>MIME-Version: 1.0
>Content-Type: text/plain; charset=UTF-8
>Content-Transfer-Encoding: 8bit
>
>On SNB the BIOS provided WM memory latency values seem insufficient to
>handle high resolution displays.
>
>In this particular case the display mode was a 2560x1440@60Hz, which
>makes the pixel clock 241.5 MHz. It was empirically found that a memory
>latency value if 1.2 usec is enough to avoid underruns, whereas the BIOS
>provided value of 0.7 usec was clearly too low. Incidentally 1.2 usec
>is what the typical BIOS provided values are on IVB systems.
>
>Increase the WM memory latency values to 1.2 usec when encountering a
>display mode with pixel clock exceeding 225 MHz. 225 MHz was chosen as
>the threshold simply because that's the documented limit of SNB with
>HDMI, so one might surmise that the hardware may have been tested up
>to that frequency. In theory the latency shouldn't depend on the pixel
>clock at all. So it may be that we should just increase the latency
>values across the board for all SNB systems. But for now I'm inclined
>to limit this quirk to only those cases that are proven to need it,
>as doing otherwise might cause some increase in power consumption for
>everyone.
>
>Cc: Robert N <crshman@gmail.com>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70254
>Signed-off-by: Ville SyrjÃ¤lÃ¤ <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/intel_display.c | 10 ++++++++++
> drivers/gpu/drm/i915/intel_drv.h     |  1 +
> drivers/gpu/drm/i915/intel_pm.c      | 33 +++++++++++++++++++++++++++++++++
> 3 files changed, 44 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index f19e6ea..e08cbcc 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -9698,6 +9698,16 @@ static int __intel_set_mode(struct drm_crtc *crtc,
> 		 */
> 		drm_calc_timestamping_constants(crtc,
> 						&pipe_config->adjusted_mode);
>+
>+
>+		/*
>+		 * The BIOS provided WM memory latency values are often
>+		 * inadequate for high resolution displays. Adjust them.
>+		 *
>+		 * FIXME not sure 225MHz is a good threshold.
>+		 */
>+		if (IS_GEN6(dev) && pipe_config->adjusted_mode.crtc_clock > 225000)
>+			snb_wm_latency_quirk(dev);
> 	}
> 
> 	/* Only after disabling all output pipelines that will be changed can we
>diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>index a4ffc02..3adf812 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -896,6 +896,7 @@ void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
> void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
> void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
> void ilk_wm_get_hw_state(struct drm_device *dev);
>+void snb_wm_latency_quirk(struct drm_device *dev);
> 
> 
> /* intel_sdvo.c */
>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>index a6b877a..56712a9 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -2101,6 +2101,39 @@ static void intel_setup_wm_latency(struct drm_device *dev)
> 	intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
> }
> 
>+static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
>+				    uint16_t wm[5], uint16_t min)
>+{
>+	int level, max_level = ilk_wm_max_level(dev_priv->dev);
>+
>+	if (wm[0] >= min)
>+		return false;
>+
>+	wm[0] = max(wm[0], min);
>+	for (level = 1; level <= max_level; level++)
>+		wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
>+
>+	return true;
>+}
>+
>+void snb_wm_latency_quirk(struct drm_device *dev)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	bool changed;
>+
>+	changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
>+		ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
>+		ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
>+
>+	if (!changed)
>+		return;
>+
>+	DRM_DEBUG_KMS("WM latency values increased due to high pixel clock\n");
>+	intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
>+	intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
>+	intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
>+}
>+
> static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
> 				      struct ilk_pipe_wm_parameters *p,
> 				      struct intel_wm_config *config)
>-- 
>1.8.3.2
>

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Attachments on bug 70254: 87256 | 87257 | 91827 | 92058 | 92059 | 92060 | 92061 | 92062 | 92063 | 92540 | 94766

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