Attachment 97522 Details for Bug 73320 – Work Around

[patch] Work Around

0001-emit-Error-when-attempting-to-spill-a-VGPR-to-memory.patch (text/plain), 2.65 KB, created by Tom Stellard on 2014-04-17 15:55:30 UTC

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Creator: Tom Stellard

Created: 2014-04-17 15:55:30 UTC

Size: 2.65 KB

patch

obsolete

>From 24cdf4966fd00ae205807a568bede455d239f45f Mon Sep 17 00:00:00 2001
>From: Darren <darren.powell@amd.com>
>Date: Wed, 16 Apr 2014 18:51:03 -0400
>Subject: [PATCH]  emit Error when attempting to spill a VGPR to memory
>
>---
> lib/Target/R600/SIInstrInfo.cpp | 30 ++++++++++++++++++++----------
> 1 file changed, 20 insertions(+), 10 deletions(-)
>
>diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp
>index 10fc7d7..36e9943 100644
>--- a/lib/Target/R600/SIInstrInfo.cpp
>+++ b/lib/Target/R600/SIInstrInfo.cpp
>@@ -192,25 +192,35 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
>                                       int FrameIndex,
>                                       const TargetRegisterClass *RC,
>                                       const TargetRegisterInfo *TRI) const {
>-  MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
>-  SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
>+  MachineFunction *MF = MBB.getParent();
>+  MachineRegisterInfo &MRI = MF->getRegInfo();
>+  SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
>   DebugLoc DL = MBB.findDebugLoc(MI);
>   unsigned KillFlag = isKill ? RegState::Kill : 0;
> 
>-  if (TRI->getCommonSubClass(RC, &AMDGPU::SGPR_32RegClass)) {
>+  if (RI.hasVGPRs(RC))
>+  {
>+    LLVMContext &Ctx = MF->getFunction()->getContext();
>+    const char *name = RC->getName();
>+    Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Can't spill VGPR!");
>+
>+  } else if (TRI->getCommonSubClass(RC, &AMDGPU::SGPR_32RegClass)) {
>     unsigned Lane = MFI->SpillTracker.getNextLane(MRI);
>-    BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32),
>-            MFI->SpillTracker.LaneVGPR)
>+    unsigned TgtReg = MFI->SpillTracker.LaneVGPR;
>+
>+    BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32),TgtReg)
>             .addReg(SrcReg, KillFlag)
>             .addImm(Lane);
>-    MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR,
>-                                    Lane);
>+    MFI->SpillTracker.addSpilledReg(FrameIndex, TgtReg,Lane);
>+
>   } else {
>     for (unsigned i = 0, e = RC->getSize() / 4; i != e; ++i) {
>-      unsigned SubReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
>-      BuildMI(MBB, MI, MBB.findDebugLoc(MI), get(AMDGPU::COPY), SubReg)
>+      unsigned TgtReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
>+
>+      BuildMI(MBB, MI, DL, get(AMDGPU::COPY), TgtReg)
>               .addReg(SrcReg, 0, RI.getSubRegFromChannel(i));
>-      storeRegToStackSlot(MBB, MI, SubReg, isKill, FrameIndex + i,
>+
>+      storeRegToStackSlot(MBB, MI, TgtReg, isKill, FrameIndex + i,
>                           &AMDGPU::SReg_32RegClass, TRI);
>     }
>   }
>-- 
>1.8.3.2
>

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