Attachment 98525 Details for Bug 55746 – intel_reg_dumper output

intel_reg_dumper output

intel_reg_dumper.txt (text/plain), 13.90 KB, created by Jorge Araya Navarro on 2014-05-05 22:44:40 UTC

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Creator: Jorge Araya Navarro

Created: 2014-05-05 22:44:40 UTC

Size: 13.90 KB

patch

obsolete

>                    PGETBL_CTL: 0x00000008
>                 INSTDONE_I965: 0xfffffffe
>                    INSTDONE_1: 0xffffffff
>                  CPU_VGACNTRL: 0x80000000 (disabled)
>    DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000
>                     RR_HW_CTL: 0x00000000 (low 0, high 0)
>                FDI_PLL_BIOS_0: 0x082b3019
>                FDI_PLL_BIOS_1: 0x00000000
>                FDI_PLL_BIOS_2: 0x00000000
>       DISPLAY_PORT_PLL_BIOS_0: 0x0807012b
>       DISPLAY_PORT_PLL_BIOS_1: 0x00000000
>       DISPLAY_PORT_PLL_BIOS_2: 0x00000000
>              FDI_PLL_FREQ_CTL: 0x00053687
>                     PIPEACONF: 0xc0000050 (enabled, active, pf-pd, rotate 0, 6bpc)
>                      HTOTAL_A: 0x059f04ff (1280 active, 1440 total)
>                      HBLANK_A: 0x059f04ff (1280 start, 1440 end)
>                       HSYNC_A: 0x054f052f (1328 start, 1360 end)
>                      VTOTAL_A: 0x0336031f (800 active, 823 total)
>                      VBLANK_A: 0x0336031f (800 start, 823 end)
>                       VSYNC_A: 0x03280322 (803 start, 809 end)
>                  VSYNCSHIFT_A: 0x00000000
>                      PIPEASRC: 0x04ff031f (1280, 800)
>                 PIPEA_DATA_M1: 0x7e25dddd (TU 64, val 0x25dddd 2481629)
>                 PIPEA_DATA_N1: 0x00400000 (val 0x400000 4194304)
>                 PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_M1: 0x00021a8c (val 0x21a8c 137868)
>                 PIPEA_LINK_N1: 0x00080000 (val 0x80000 524288)
>                 PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
>                      DSPACNTR: 0xd8004400 (enabled)
>                      DSPABASE: 0x00000000
>                    DSPASTRIDE: 0x00002800 (160)
>                      DSPASURF: 0x0049a000
>                   DSPATILEOFF: 0x00000000 (0, 0)
>                     PIPEBCONF: 0xc0000000 (enabled, active, pf-pd, rotate 0, 8bpc)
>                      HTOTAL_B: 0x067f04ff (1280 active, 1664 total)
>                      HBLANK_B: 0x067f04ff (1280 start, 1664 end)
>                       HSYNC_B: 0x05bf0537 (1336 start, 1472 end)
>                      VTOTAL_B: 0x02e902cf (720 active, 746 total)
>                      VBLANK_B: 0x02e902cf (720 start, 746 end)
>                       VSYNC_B: 0x02d302d0 (721 start, 724 end)
>                  VSYNCSHIFT_B: 0x00000000
>                      PIPEBSRC: 0x04ff02cf (1280, 720)
>                 PIPEB_DATA_M1: 0x7e34ef63 (TU 64, val 0x34ef63 3469155)
>                 PIPEB_DATA_N1: 0x00400000 (val 0x400000 4194304)
>                 PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_M1: 0x000234a4 (val 0x234a4 144548)
>                 PIPEB_LINK_N1: 0x00080000 (val 0x80000 524288)
>                 PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
>                      DSPBCNTR: 0xd8004400 (enabled)
>                      DSPBBASE: 0xffff7400
>                    DSPBSTRIDE: 0x00002800 (160)
>                      DSPBSURF: 0x004a4000
>                   DSPBTILEOFF: 0x00000000 (0, 0)
>                     PIPECCONF: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc)
>                      HTOTAL_C: 0x00000000 (1 active, 1 total)
>                      HBLANK_C: 0x00000000 (1 start, 1 end)
>                       HSYNC_C: 0x00000000 (1 start, 1 end)
>                      VTOTAL_C: 0x00000000 (1 active, 1 total)
>                      VBLANK_C: 0x00000000 (1 start, 1 end)
>                       VSYNC_C: 0x00000000 (1 start, 1 end)
>                  VSYNCSHIFT_C: 0x00000000
>                      PIPECSRC: 0x00000000 (1, 1)
>                 PIPEC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEC_DATA_N1: 0x00000000 (val 0x0 0)
>                 PIPEC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEC_DATA_N2: 0x00000000 (val 0x0 0)
>                 PIPEC_LINK_M1: 0x00000000 (val 0x0 0)
>                 PIPEC_LINK_N1: 0x00000000 (val 0x0 0)
>                 PIPEC_LINK_M2: 0x00000000 (val 0x0 0)
>                 PIPEC_LINK_N2: 0x00000000 (val 0x0 0)
>                      DSPCCNTR: 0x00000000 (disabled)
>                      DSPCBASE: 0x00000000
>                    DSPCSTRIDE: 0x00000000 (0)
>                      DSPCSURF: 0x00000000
>                   DSPCTILEOFF: 0x00000000 (0, 0)
>                     PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFA_CTL_2: 0x00007e70 (vscale 0.987793)
>                     PFA_CTL_3: 0x00003f38 (vscale initial phase 0.493896)
>                     PFA_CTL_4: 0x00007d80 (hscale 0.980469)
>                   PFA_WIN_POS: 0x00000000 (0, 0)
>                  PFA_WIN_SIZE: 0x00000000 (0, 0)
>                     PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFB_CTL_2: 0x00007e98 (vscale 0.989014)
>                     PFB_CTL_3: 0x00003f4c (vscale initial phase 0.494507)
>                     PFB_CTL_4: 0x00007d80 (hscale 0.980469)
>                   PFB_WIN_POS: 0x00000000 (0, 0)
>                  PFB_WIN_SIZE: 0x00000000 (0, 0)
>                     PFC_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                     PFC_CTL_2: 0x00000000 (vscale 0.000000)
>                     PFC_CTL_3: 0x00000000 (vscale initial phase 0.000000)
>                     PFC_CTL_4: 0x00000000 (hscale 0.000000)
>                   PFC_WIN_POS: 0x00000000 (0, 0)
>                  PFC_WIN_SIZE: 0x00000000 (0, 0)
>              PCH_DREF_CONTROL: 0x00001400 (cpu source disable, ssc_source enable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 disable, ssc4 disable)
>               PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
>              PCH_DPLL_TMR_CFG: 0x0271186a
>                PCH_SSC4_PARMS: 0x00000000
>            PCH_SSC4_AUX_PARMS: 0x00000000
>                  PCH_DPLL_SEL: 0x00000000 (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
>           PCH_DPLL_ANALOG_CTL: 0x00008000
>                    PCH_DPLL_A: 0x88046004 (enable, sdvo high speed no, mode LVDS, p2 Div 14, FPA0 P1 3, FPA1 P1 3, refclk SSC, sdvo/hdmi mul 1)
>                    PCH_DPLL_B: 0x84080008 (enable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 4, FPA1 P1 4, refclk default 120Mhz, sdvo/hdmi mul 1)
>                      PCH_FPA0: 0x00021007 (n = 2, m1 = 16, m2 = 7)
>                      PCH_FPA1: 0x00021007 (n = 2, m1 = 16, m2 = 7)
>                      PCH_FPB0: 0x00021007 (n = 2, m1 = 16, m2 = 7)
>                      PCH_FPB1: 0x00021007 (n = 2, m1 = 16, m2 = 7)
>                TRANS_HTOTAL_A: 0x059f04ff (1280 active, 1440 total)
>                TRANS_HBLANK_A: 0x059f04ff (1280 start, 1440 end)
>                 TRANS_HSYNC_A: 0x054f052f (1328 start, 1360 end)
>                TRANS_VTOTAL_A: 0x0336031f (800 active, 823 total)
>                TRANS_VBLANK_A: 0x0336031f (800 start, 823 end)
>                 TRANS_VSYNC_A: 0x03280322 (803 start, 809 end)
>            TRANS_VSYNCSHIFT_A: 0x00000000
>                TRANSA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSA_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                TRANS_HTOTAL_B: 0x067f04ff (1280 active, 1664 total)
>                TRANS_HBLANK_B: 0x067f04ff (1280 start, 1664 end)
>                 TRANS_HSYNC_B: 0x05bf0537 (1336 start, 1472 end)
>                TRANS_VTOTAL_B: 0x02e902cf (720 active, 746 total)
>                TRANS_VBLANK_B: 0x02e902cf (720 start, 746 end)
>                 TRANS_VSYNC_B: 0x02d302d0 (721 start, 724 end)
>            TRANS_VSYNCSHIFT_B: 0x00000000
>                TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSB_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total)
>                TRANS_HBLANK_C: 0x00000000 (1 start, 1 end)
>                 TRANS_HSYNC_C: 0x00000000 (1 start, 1 end)
>                TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total)
>                TRANS_VBLANK_C: 0x00000044 (69 start, 1 end)
>                 TRANS_VSYNC_C: 0x00000000 (1 start, 1 end)
>            TRANS_VSYNCSHIFT_C: 0x00000000
>                TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                TRANSC_DATA_N1: 0x00000000 (val 0x0 0)
>                TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                TRANSC_DATA_N2: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0)
>             TRANSC_DP_LINK_N2: 0x00ffffff (val 0xffffff 16777215)
>                    TRANSACONF: 0xc0000040 (enable, active, progressive)
>                    TRANSBCONF: 0xc0000000 (enable, active, progressive)
>                    TRANSCCONF: 0x00000000 (disable, inactive, progressive)
>                   FDI_TXA_CTL: 0xb0044000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                   FDI_TXB_CTL: 0xb0044000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                   FDI_TXC_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable)
>                   FDI_RXA_CTL: 0xb0022050 (enable, train pattern not train, port width X1, 6bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, PCDClk)
>                   FDI_RXB_CTL: 0xb0002050 (enable, train pattern not train, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, PCDClk)
>                   FDI_RXC_CTL: 0x00000000 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing disable, RawClk)
>                  DPAFE_BMFUNC: 0x00100040
>             DPAFE_DL_IREFCAL0: 0x00000020
>             DPAFE_DL_IREFCAL1: 0x0f810880
>              DPAFE_DP_IREFCAL: 0x00100040
>             PCH_DSPCLK_GATE_D: 0x100003a0
>              PCH_DSP_CHICKEN1: 0x00400000
>              PCH_DSP_CHICKEN2: 0x02600000
>              PCH_DSP_CHICKEN3: 0x00000000
>                  FDI_RXA_MISC: 0x00000080 (FDI Delay 128)
>                  FDI_RXB_MISC: 0x00000080 (FDI Delay 128)
>                  FDI_RXC_MISC: 0x00000000 (FDI Delay 0)
>               FDI_RXA_TUSIZE1: 0x7e000000
>               FDI_RXA_TUSIZE2: 0x7e000000
>               FDI_RXB_TUSIZE1: 0x7e000000
>               FDI_RXB_TUSIZE2: 0x7e000000
>               FDI_RXC_TUSIZE1: 0x00000000
>               FDI_RXC_TUSIZE2: 0x00000000
>                 FDI_PLL_CTL_1: 0x33505248
>                 FDI_PLL_CTL_2: 0x00000000
>                   FDI_RXA_IIR: 0x00000000
>                   FDI_RXA_IMR: 0x000000ff
>                   FDI_RXB_IIR: 0x00000000
>                   FDI_RXB_IMR: 0x000000ff
>                      PCH_ADPA: 0xc3f40010 (enabled, transcoder B, -hsync, +vsync)
>                         HDMIB: 0x00000018 (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync non-detected)
>                         HDMIC: 0x00000018 (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync non-detected)
>                         HDMID: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
>                      PCH_LVDS: 0x80300302 (enabled, pipe A, 18 bit, 1 channel)
>                     CPU_eDP_A: 0x00000018
>                      PCH_DP_B: 0x00000018
>                      PCH_DP_C: 0x00000018
>                      PCH_DP_D: 0x0000001c
>                TRANS_DP_CTL_A: 0x00000000 (enabled, pipe A, 18 bit, 1 channel)
>                TRANS_DP_CTL_B: 0x00000000 (enabled, pipe A, 18 bit, 1 channel)
>                TRANS_DP_CTL_C: 0x00000000 (enabled, pipe A, 18 bit, 1 channel)
>              BLC_PWM_CPU_CTL2: 0x80000000 (enable 1, pipe A)
>               BLC_PWM_CPU_CTL: 0x000012ed (cycle 4845)
>              BLC_PWM_PCH_CTL1: 0x80000000 (enable 1, override 0, inverted polarity 0)
>              BLC_PWM_PCH_CTL2: 0x13121312 (freq 4882, cycle 4882)
>                 PCH_PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>                PCH_PP_CONTROL: 0xabcd0001 (blacklight disabled, do not power down on reset, panel on)
>              PCH_PP_ON_DELAYS: 0x00e607d0
>             PCH_PP_OFF_DELAYS: 0x012c08fc
>                PCH_PP_DIVISOR: 0x00186905
>                      PORT_DBG: 0x00000000 (HW DRRS off)
>            RC6_RESIDENCY_TIME: 0xffffffff
>           RC6p_RESIDENCY_TIME: 0xffffffff
>          RC6pp_RESIDENCY_TIME: 0xffffffff

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Attachments on bug 55746: 68235 | 68236 | 98522 | 98523 | 98524 | 98525 | 98526

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