Attachment 98660 Details for Bug 78419 – dmesg

dmesg

kms_fbc_crc_page_flip.dmesg (text/plain), 124.76 KB, created by Guo Jinxian on 2014-05-08 03:50:39 UTC

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Creator: Guo Jinxian

Created: 2014-05-08 03:50:39 UTC

Size: 124.76 KB

patch

obsolete

>[   50.665688] [drm:intel_dump_pipe_config] adjusted mode:
>[   50.665691] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   50.665694] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   50.665696] [drm:intel_dump_pipe_config] port clock: 270000
>[   50.665698] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   50.665700] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   50.665702] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   50.665704] [drm:intel_dump_pipe_config] ips: 0
>[   50.665706] [drm:intel_dump_pipe_config] double wide: 0
>[   50.665712] [drm:ironlake_disable_fbc] disabled FBC
>[   50.694799] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   50.694806] [drm:intel_edp_backlight_off] 
>[   50.710938] [drm:intel_edp_panel_off] Turn eDP power off
>[   50.895652] [drm:wait_panel_off] Wait for panel power off time
>[   50.895657] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   50.950607] [drm:wait_panel_status] Wait complete
>[   50.950615] [drm:intel_update_fbc] no output, disabling
>[   50.961465] [drm:ironlake_update_primary_plane] Writing base 0E07D000 00000000 0 0 8192
>[   50.961471] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   50.961475] [drm:intel_crtc_mode_set] [ENCODER:13:TMDS-13] set [MODE:0:1920x1080]
>[   50.961478] [drm:intel_ddi_mode_set] Preparing DDI mode on port A, pipe B
>[   50.961480] [drm:intel_edp_panel_on] Turn eDP power on
>[   50.961484] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   51.496204] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[   51.496207] [drm:wait_panel_status] Wait complete
>[   51.496211] [drm:wait_panel_on] Wait for panel power on
>[   51.496215] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   51.705041] [drm:wait_panel_status] Wait complete
>[   51.705044] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   51.705051] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   51.706103] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   51.706546] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   51.706976] [drm:intel_dp_start_link_train] clock recovery OK
>[   51.707719] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   51.707921] [drm:intel_edp_backlight_on] 
>[   51.707927] [drm:intel_panel_enable_backlight] pipe B
>[   51.707932] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   51.707935] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   51.725025] [drm:intel_update_fbc] plane not A, disabling compression
>[   51.725031] [drm:intel_connector_check_state] [CONNECTOR:14:eDP-1]
>[   51.725035] [drm:check_encoder_state] [ENCODER:13:TMDS-13]
>[   51.725038] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[   51.725040] [drm:check_encoder_state] [ENCODER:24:TMDS-24]
>[   51.725042] [drm:check_crtc_state] [CRTC:5]
>[   51.725045] [drm:check_crtc_state] [CRTC:8]
>[   51.725053] [drm:check_crtc_state] [CRTC:11]
>[   51.725062] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[   51.725068] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[   52.024993] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   52.024999] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   52.025003] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   52.025006] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1]
>[   52.025009] [drm:intel_dp_detect] [CONNECTOR:14:eDP-1]
>[   52.025013] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   52.025020] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   52.025183] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[   52.025340] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[   52.025350] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   52.025354] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1] probed modes :
>[   52.025357] [drm:drm_mode_debug_printmodeline] Modeline 15:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   52.025361] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   52.025368] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   52.025371] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   52.025391] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   52.025396] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   52.076759] [drm:g4x_wait_for_vblank] vblank wait timed out
>[   52.076777] [drm:drm_mode_addfb2] [FB:43]
>[   52.086739] [drm:drm_mode_addfb2] [FB:44]
>[   52.096674] [drm:drm_mode_setcrtc] [CRTC:5]
>[   52.096681] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   52.096685] [drm:intel_crtc_set_config] [CRTC:5] [FB:44] #connectors=1 (x y) (0 0)
>[   52.096688] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[   52.096691] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0
>[   52.096694] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   52.096696] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[   52.096698] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[   52.096699] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[   52.096704] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[   52.096707] [drm:connected_sink_compute_bpp] [CONNECTOR:14:eDP-1] checking for sink bpp constrains
>[   52.096712] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   52.096714] [drm:intel_dp_compute_config] using min 2 lanes per VBT
>[   52.096716] [drm:intel_dp_compute_config] using min 06 link bw per VBT
>[   52.096722] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   52.096724] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   52.096727] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   52.096730] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A
>[   52.096731] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   52.096733] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   52.096736] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   52.096739] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   52.096751] [drm:intel_dump_pipe_config] requested mode:
>[   52.096759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   52.096768] [drm:intel_dump_pipe_config] adjusted mode:
>[   52.096778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   52.096787] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   52.096795] [drm:intel_dump_pipe_config] port clock: 270000
>[   52.096804] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   52.096812] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   52.096815] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   52.096818] [drm:intel_dump_pipe_config] ips: 1
>[   52.096820] [drm:intel_dump_pipe_config] double wide: 0
>[   52.108737] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   52.108745] [drm:intel_edp_backlight_off] 
>[   52.124876] [drm:intel_edp_panel_off] Turn eDP power off
>[   52.309592] [drm:wait_panel_off] Wait for panel power off time
>[   52.309597] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   52.364546] [drm:wait_panel_status] Wait complete
>[   52.364553] [drm:intel_update_fbc] no output, disabling
>[   52.375478] [drm:ironlake_update_primary_plane] Writing base 0207C000 00000000 0 0 8192
>[   52.375484] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   52.375488] [drm:intel_crtc_mode_set] [ENCODER:13:TMDS-13] set [MODE:0:1920x1080]
>[   52.375490] [drm:intel_ddi_mode_set] Preparing DDI mode on port A, pipe A
>[   52.375493] [drm:intel_edp_panel_on] Turn eDP power on
>[   52.375497] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   52.910141] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[   52.910144] [drm:wait_panel_status] Wait complete
>[   52.910148] [drm:wait_panel_on] Wait for panel power on
>[   52.910152] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   53.118980] [drm:wait_panel_status] Wait complete
>[   53.118987] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   53.118995] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   53.120053] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   53.120498] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   53.120929] [drm:intel_dp_start_link_train] clock recovery OK
>[   53.121674] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   53.121876] [drm:intel_edp_backlight_on] 
>[   53.121882] [drm:intel_panel_enable_backlight] pipe A
>[   53.121887] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   53.121890] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   53.140962] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   53.140968] [drm:intel_connector_check_state] [CONNECTOR:14:eDP-1]
>[   53.140972] [drm:check_encoder_state] [ENCODER:13:TMDS-13]
>[   53.140975] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[   53.140977] [drm:check_encoder_state] [ENCODER:24:TMDS-24]
>[   53.140980] [drm:check_crtc_state] [CRTC:5]
>[   53.140987] [drm:check_crtc_state] [CRTC:8]
>[   53.140990] [drm:check_crtc_state] [CRTC:11]
>[   53.190934] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   53.254666] [drm:gen8_irq_handler] *ERROR* Pipe A FIFO underrun
>[   53.454946] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   53.488266] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   53.505690] [drm:drm_mode_setcrtc] [CRTC:5]
>[   53.505695] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   53.505698] [drm:intel_crtc_set_config] [CRTC:5] [FB:43] #connectors=1 (x y) (0 0)
>[   53.505701] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=0, fb_changed=1
>[   53.505704] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   53.514946] [drm:ironlake_update_primary_plane] Writing base 0107C000 00000000 0 0 8192
>[   53.522676] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   53.522679] [drm:intel_update_fbc] disabling active FBC for update
>[   53.522681] [drm:ironlake_disable_fbc] disabled FBC
>[   53.522683] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   53.572645] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   53.837983] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   53.854653] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   53.904597] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   53.921269] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   54.238222] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   54.270998] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   54.288128] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   54.288134] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   54.288139] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   54.288142] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1]
>[   54.288145] [drm:intel_dp_detect] [CONNECTOR:14:eDP-1]
>[   54.288314] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[   54.288473] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[   54.288483] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   54.288487] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1] probed modes :
>[   54.288491] [drm:drm_mode_debug_printmodeline] Modeline 15:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   54.288495] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   54.288502] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   54.288505] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   54.288526] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf
>[   54.288530] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[   54.340060] [drm:g4x_wait_for_vblank] vblank wait timed out
>[   54.340074] [drm:drm_mode_addfb2] [FB:45]
>[   54.349991] [drm:drm_mode_addfb2] [FB:46]
>[   54.359879] [drm:drm_mode_setcrtc] [CRTC:8]
>[   54.359885] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   54.359888] [drm:intel_crtc_set_config] [CRTC:8] [FB:46] #connectors=1 (x y) (0 0)
>[   54.359892] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[   54.359894] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
>[   54.359897] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:8]
>[   54.359899] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[   54.359901] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[   54.359903] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[   54.359906] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 1
>[   54.359909] [drm:connected_sink_compute_bpp] [CONNECTOR:14:eDP-1] checking for sink bpp constrains
>[   54.359913] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   54.359915] [drm:intel_dp_compute_config] using min 2 lanes per VBT
>[   54.359917] [drm:intel_dp_compute_config] using min 06 link bw per VBT
>[   54.359923] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   54.359925] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   54.359929] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   54.359931] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe B
>[   54.359933] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   54.359935] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   54.359937] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   54.359940] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   54.359942] [drm:intel_dump_pipe_config] requested mode:
>[   54.359946] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   54.359947] [drm:intel_dump_pipe_config] adjusted mode:
>[   54.359950] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   54.359953] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   54.359955] [drm:intel_dump_pipe_config] port clock: 270000
>[   54.359957] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   54.359959] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   54.359961] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   54.359963] [drm:intel_dump_pipe_config] ips: 0
>[   54.359965] [drm:intel_dump_pipe_config] double wide: 0
>[   54.359973] [drm:ironlake_disable_fbc] disabled FBC
>[   54.389026] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   54.389033] [drm:intel_edp_backlight_off] 
>[   54.405165] [drm:intel_edp_panel_off] Turn eDP power off
>[   54.589881] [drm:wait_panel_off] Wait for panel power off time
>[   54.589886] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   54.644833] [drm:wait_panel_status] Wait complete
>[   54.644841] [drm:intel_update_fbc] no output, disabling
>[   54.655741] [drm:ironlake_update_primary_plane] Writing base 0407C000 00000000 0 0 8192
>[   54.655751] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   54.655754] [drm:intel_crtc_mode_set] [ENCODER:13:TMDS-13] set [MODE:0:1920x1080]
>[   54.655756] [drm:intel_ddi_mode_set] Preparing DDI mode on port A, pipe B
>[   54.655759] [drm:intel_edp_panel_on] Turn eDP power on
>[   54.655763] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   55.190432] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[   55.190434] [drm:wait_panel_status] Wait complete
>[   55.190438] [drm:wait_panel_on] Wait for panel power on
>[   55.190442] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   55.399267] [drm:wait_panel_status] Wait complete
>[   55.399270] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   55.399277] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   55.400324] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   55.400764] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   55.401194] [drm:intel_dp_start_link_train] clock recovery OK
>[   55.401935] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   55.402134] [drm:intel_edp_backlight_on] 
>[   55.402140] [drm:intel_panel_enable_backlight] pipe B
>[   55.402145] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   55.402148] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   55.419251] [drm:intel_update_fbc] plane not A, disabling compression
>[   55.419256] [drm:intel_connector_check_state] [CONNECTOR:14:eDP-1]
>[   55.419260] [drm:check_encoder_state] [ENCODER:13:TMDS-13]
>[   55.419263] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[   55.419265] [drm:check_encoder_state] [ENCODER:24:TMDS-24]
>[   55.419267] [drm:check_crtc_state] [CRTC:5]
>[   55.419270] [drm:check_crtc_state] [CRTC:8]
>[   55.419278] [drm:check_crtc_state] [CRTC:11]
>[   55.419287] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[   55.419293] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[   55.719220] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   55.719226] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   55.719230] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   55.719233] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1]
>[   55.719235] [drm:intel_dp_detect] [CONNECTOR:14:eDP-1]
>[   55.719239] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   55.719246] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   55.719408] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[   55.719566] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[   55.719575] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   55.719579] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1] probed modes :
>[   55.719583] [drm:drm_mode_debug_printmodeline] Modeline 15:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   55.719587] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   55.719594] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   55.719598] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   55.719617] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   55.719622] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   55.770987] [drm:g4x_wait_for_vblank] vblank wait timed out
>[   55.771003] [drm:drm_mode_addfb2] [FB:47]
>[   55.780966] [drm:drm_mode_addfb2] [FB:48]
>[   55.790910] [drm:drm_mode_setcrtc] [CRTC:5]
>[   55.790916] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   55.790920] [drm:intel_crtc_set_config] [CRTC:5] [FB:48] #connectors=1 (x y) (0 0)
>[   55.790923] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[   55.790926] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0
>[   55.790929] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   55.790930] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[   55.790932] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[   55.790934] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[   55.790937] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[   55.790941] [drm:connected_sink_compute_bpp] [CONNECTOR:14:eDP-1] checking for sink bpp constrains
>[   55.790945] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   55.790947] [drm:intel_dp_compute_config] using min 2 lanes per VBT
>[   55.790949] [drm:intel_dp_compute_config] using min 06 link bw per VBT
>[   55.790955] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   55.790957] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   55.790960] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   55.790963] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A
>[   55.790964] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   55.790966] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   55.790977] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   55.790983] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   55.790995] [drm:intel_dump_pipe_config] requested mode:
>[   55.791007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   55.791016] [drm:intel_dump_pipe_config] adjusted mode:
>[   55.791027] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   55.791039] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   55.791043] [drm:intel_dump_pipe_config] port clock: 270000
>[   55.791045] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   55.791047] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   55.791050] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   55.791051] [drm:intel_dump_pipe_config] ips: 1
>[   55.791053] [drm:intel_dump_pipe_config] double wide: 0
>[   55.802965] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   55.802972] [drm:intel_edp_backlight_off] 
>[   55.819102] [drm:intel_edp_panel_off] Turn eDP power off
>[   56.003818] [drm:wait_panel_off] Wait for panel power off time
>[   56.003823] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   56.058773] [drm:wait_panel_status] Wait complete
>[   56.058781] [drm:intel_update_fbc] no output, disabling
>[   56.069476] [drm:ironlake_update_primary_plane] Writing base 0607C000 00000000 0 0 8192
>[   56.069482] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   56.069486] [drm:intel_crtc_mode_set] [ENCODER:13:TMDS-13] set [MODE:0:1920x1080]
>[   56.069488] [drm:intel_ddi_mode_set] Preparing DDI mode on port A, pipe A
>[   56.069491] [drm:intel_edp_panel_on] Turn eDP power on
>[   56.069494] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   56.604368] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[   56.604371] [drm:wait_panel_status] Wait complete
>[   56.604375] [drm:wait_panel_on] Wait for panel power on
>[   56.604379] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   56.813208] [drm:wait_panel_status] Wait complete
>[   56.813211] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   56.813218] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   56.814263] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   56.814704] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   56.815135] [drm:intel_dp_start_link_train] clock recovery OK
>[   56.815878] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   56.816080] [drm:intel_edp_backlight_on] 
>[   56.816085] [drm:intel_panel_enable_backlight] pipe A
>[   56.816091] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   56.816094] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   56.835190] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   56.835195] [drm:intel_connector_check_state] [CONNECTOR:14:eDP-1]
>[   56.835199] [drm:check_encoder_state] [ENCODER:13:TMDS-13]
>[   56.835202] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[   56.835204] [drm:check_encoder_state] [ENCODER:24:TMDS-24]
>[   56.835207] [drm:check_crtc_state] [CRTC:5]
>[   56.835214] [drm:check_crtc_state] [CRTC:8]
>[   56.835217] [drm:check_crtc_state] [CRTC:11]
>[   56.885161] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   56.948870] [drm:gen8_irq_handler] *ERROR* Pipe A FIFO underrun
>[   57.149151] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   57.182470] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   57.199926] [drm:i915_gem_context_create_ioctl] HW context 1 created
>[   57.199929] [drm:i915_gem_context_create_ioctl] HW context 2 created
>[   57.200081] [drm:drm_mode_setcrtc] [CRTC:5]
>[   57.200085] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   57.200088] [drm:intel_crtc_set_config] [CRTC:5] [FB:47] #connectors=1 (x y) (0 0)
>[   57.200091] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=0, fb_changed=1
>[   57.200094] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   57.209638] [drm:ironlake_update_primary_plane] Writing base 0507C000 00000000 0 0 8192
>[   57.216904] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   57.216906] [drm:intel_update_fbc] disabling active FBC for update
>[   57.216908] [drm:ironlake_disable_fbc] disabled FBC
>[   57.216911] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   57.266873] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   57.532186] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   57.548857] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   57.598800] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   57.615472] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   57.932443] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   57.965202] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   57.982353] [drm:i915_gem_context_destroy_ioctl] HW context 1 destroyed
>[   57.982356] [drm:i915_gem_context_destroy_ioctl] HW context 2 destroyed
>[   57.982362] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   57.982367] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   57.982372] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   57.982375] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1]
>[   57.982377] [drm:intel_dp_detect] [CONNECTOR:14:eDP-1]
>[   57.982540] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[   57.982698] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[   57.982708] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   57.982711] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1] probed modes :
>[   57.982715] [drm:drm_mode_debug_printmodeline] Modeline 15:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   57.982719] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   57.982726] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   57.982730] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   57.982750] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf
>[   57.982754] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[   58.034288] [drm:g4x_wait_for_vblank] vblank wait timed out
>[   58.034301] [drm:drm_mode_addfb2] [FB:49]
>[   58.044264] [drm:drm_mode_addfb2] [FB:50]
>[   58.054194] [drm:drm_mode_setcrtc] [CRTC:8]
>[   58.054200] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   58.054203] [drm:intel_crtc_set_config] [CRTC:8] [FB:50] #connectors=1 (x y) (0 0)
>[   58.054207] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[   58.054210] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
>[   58.054212] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:8]
>[   58.054214] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[   58.054216] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[   58.054218] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[   58.054221] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 1
>[   58.054225] [drm:connected_sink_compute_bpp] [CONNECTOR:14:eDP-1] checking for sink bpp constrains
>[   58.054229] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   58.054231] [drm:intel_dp_compute_config] using min 2 lanes per VBT
>[   58.054233] [drm:intel_dp_compute_config] using min 06 link bw per VBT
>[   58.054239] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   58.054241] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   58.054245] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   58.054247] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe B
>[   58.054249] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   58.054251] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   58.054254] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   58.054256] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   58.054258] [drm:intel_dump_pipe_config] requested mode:
>[   58.054262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   58.054263] [drm:intel_dump_pipe_config] adjusted mode:
>[   58.054266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   58.054270] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   58.054281] [drm:intel_dump_pipe_config] port clock: 270000
>[   58.054283] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   58.054290] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   58.054301] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   58.054310] [drm:intel_dump_pipe_config] ips: 0
>[   58.054320] [drm:intel_dump_pipe_config] double wide: 0
>[   58.054343] [drm:ironlake_disable_fbc] disabled FBC
>[   58.082254] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   58.082261] [drm:intel_edp_backlight_off] 
>[   58.100392] [drm:intel_edp_panel_off] Turn eDP power off
>[   58.283110] [drm:wait_panel_off] Wait for panel power off time
>[   58.283115] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   58.338063] [drm:wait_panel_status] Wait complete
>[   58.338070] [drm:intel_update_fbc] no output, disabling
>[   58.348969] [drm:ironlake_update_primary_plane] Writing base 0707C000 00000000 0 0 8192
>[   58.348976] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   58.348979] [drm:intel_crtc_mode_set] [ENCODER:13:TMDS-13] set [MODE:0:1920x1080]
>[   58.348982] [drm:intel_ddi_mode_set] Preparing DDI mode on port A, pipe B
>[   58.348984] [drm:intel_edp_panel_on] Turn eDP power on
>[   58.348988] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   58.883657] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000
>[   58.894647] [drm:wait_panel_status] Wait complete
>[   58.894651] [drm:wait_panel_on] Wait for panel power on
>[   58.894655] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   59.103489] [drm:wait_panel_status] Wait complete
>[   59.103493] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   59.103500] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   59.104546] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   59.104986] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   59.105417] [drm:intel_dp_start_link_train] clock recovery OK
>[   59.106160] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   59.106362] [drm:intel_edp_backlight_on] 
>[   59.106367] [drm:intel_panel_enable_backlight] pipe B
>[   59.106373] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   59.106376] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   59.123473] [drm:intel_update_fbc] plane not A, disabling compression
>[   59.123477] [drm:intel_connector_check_state] [CONNECTOR:14:eDP-1]
>[   59.123482] [drm:check_encoder_state] [ENCODER:13:TMDS-13]
>[   59.123484] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[   59.123487] [drm:check_encoder_state] [ENCODER:24:TMDS-24]
>[   59.123489] [drm:check_crtc_state] [CRTC:5]
>[   59.123492] [drm:check_crtc_state] [CRTC:8]
>[   59.123500] [drm:check_crtc_state] [CRTC:11]
>[   59.123509] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[   59.123515] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[   59.423449] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   59.423455] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   59.423460] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   59.423462] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1]
>[   59.423465] [drm:intel_dp_detect] [CONNECTOR:14:eDP-1]
>[   59.423468] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   59.423475] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   59.423636] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[   59.423795] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[   59.423804] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   59.423808] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1] probed modes :
>[   59.423812] [drm:drm_mode_debug_printmodeline] Modeline 15:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   59.423816] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   59.423823] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   59.423827] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   59.423846] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   59.423851] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   59.475207] [drm:g4x_wait_for_vblank] vblank wait timed out
>[   59.475223] [drm:drm_mode_addfb2] [FB:51]
>[   59.485173] [drm:drm_mode_addfb2] [FB:52]
>[   59.495088] [drm:drm_mode_setcrtc] [CRTC:5]
>[   59.495095] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   59.495099] [drm:intel_crtc_set_config] [CRTC:5] [FB:52] #connectors=1 (x y) (0 0)
>[   59.495102] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[   59.495105] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0
>[   59.495108] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   59.495109] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[   59.495111] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[   59.495113] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[   59.495116] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[   59.495120] [drm:connected_sink_compute_bpp] [CONNECTOR:14:eDP-1] checking for sink bpp constrains
>[   59.495124] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   59.495126] [drm:intel_dp_compute_config] using min 2 lanes per VBT
>[   59.495128] [drm:intel_dp_compute_config] using min 06 link bw per VBT
>[   59.495134] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   59.495136] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   59.495140] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   59.495143] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A
>[   59.495145] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   59.495147] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   59.495149] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   59.495152] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   59.495154] [drm:intel_dump_pipe_config] requested mode:
>[   59.495157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   59.495159] [drm:intel_dump_pipe_config] adjusted mode:
>[   59.495162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   59.495166] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   59.495167] [drm:intel_dump_pipe_config] port clock: 270000
>[   59.495169] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   59.495172] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   59.495174] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   59.495175] [drm:intel_dump_pipe_config] ips: 1
>[   59.495177] [drm:intel_dump_pipe_config] double wide: 0
>[   59.506186] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   59.506193] [drm:intel_edp_backlight_off] 
>[   59.524323] [drm:intel_edp_panel_off] Turn eDP power off
>[   59.707039] [drm:wait_panel_off] Wait for panel power off time
>[   59.707044] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   59.761994] [drm:wait_panel_status] Wait complete
>[   59.762002] [drm:intel_update_fbc] no output, disabling
>[   59.772849] [drm:ironlake_update_primary_plane] Writing base 0A07C000 00000000 0 0 8192
>[   59.772859] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   59.772863] [drm:intel_crtc_mode_set] [ENCODER:13:TMDS-13] set [MODE:0:1920x1080]
>[   59.772865] [drm:intel_ddi_mode_set] Preparing DDI mode on port A, pipe A
>[   59.772868] [drm:intel_edp_panel_on] Turn eDP power on
>[   59.772872] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   60.307594] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[   60.307596] [drm:wait_panel_status] Wait complete
>[   60.307600] [drm:wait_panel_on] Wait for panel power on
>[   60.307604] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   60.516428] [drm:wait_panel_status] Wait complete
>[   60.516431] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   60.516438] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   60.517483] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.517924] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.518355] [drm:intel_dp_start_link_train] clock recovery OK
>[   60.519098] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   60.519302] [drm:intel_edp_backlight_on] 
>[   60.519307] [drm:intel_panel_enable_backlight] pipe A
>[   60.519312] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   60.519315] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   60.538411] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   60.538417] [drm:intel_connector_check_state] [CONNECTOR:14:eDP-1]
>[   60.538421] [drm:check_encoder_state] [ENCODER:13:TMDS-13]
>[   60.538424] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[   60.538426] [drm:check_encoder_state] [ENCODER:24:TMDS-24]
>[   60.538428] [drm:check_crtc_state] [CRTC:5]
>[   60.538435] [drm:check_crtc_state] [CRTC:8]
>[   60.538438] [drm:check_crtc_state] [CRTC:11]
>[   60.588382] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   60.652089] [drm:gen8_irq_handler] *ERROR* Pipe A FIFO underrun
>[   60.852370] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   60.885690] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   60.903138] [drm:drm_mode_setcrtc] [CRTC:5]
>[   60.903142] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   60.903145] [drm:intel_crtc_set_config] [CRTC:5] [FB:51] #connectors=1 (x y) (0 0)
>[   60.903148] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=0, fb_changed=1
>[   60.903151] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   60.912380] [drm:ironlake_update_primary_plane] Writing base 0907C000 00000000 0 0 8192
>[   60.920125] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   60.920127] [drm:intel_update_fbc] disabling active FBC for update
>[   60.920129] [drm:ironlake_disable_fbc] disabled FBC
>[   60.920132] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   60.970093] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   61.235406] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   61.252077] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   61.269907] [drm:ironlake_disable_fbc] disabled FBC
>[   61.285372] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   61.334822] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   61.601790] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   61.618462] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   61.935439] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   61.968192] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   61.985350] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   61.985356] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   61.985361] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   61.985364] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1]
>[   61.985367] [drm:intel_dp_detect] [CONNECTOR:14:eDP-1]
>[   61.985532] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[   61.985690] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[   61.985700] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   61.985703] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1] probed modes :
>[   61.985707] [drm:drm_mode_debug_printmodeline] Modeline 15:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   61.985711] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   61.985717] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   61.985721] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   61.985742] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf
>[   61.985746] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[   62.037285] [drm:g4x_wait_for_vblank] vblank wait timed out
>[   62.037299] [drm:drm_mode_addfb2] [FB:53]
>[   62.047195] [drm:drm_mode_addfb2] [FB:54]
>[   62.057100] [drm:drm_mode_setcrtc] [CRTC:8]
>[   62.057107] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   62.057110] [drm:intel_crtc_set_config] [CRTC:8] [FB:54] #connectors=1 (x y) (0 0)
>[   62.057114] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[   62.057116] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
>[   62.057119] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:8]
>[   62.057121] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[   62.057123] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[   62.057125] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[   62.057128] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 1
>[   62.057132] [drm:connected_sink_compute_bpp] [CONNECTOR:14:eDP-1] checking for sink bpp constrains
>[   62.057136] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   62.057138] [drm:intel_dp_compute_config] using min 2 lanes per VBT
>[   62.057140] [drm:intel_dp_compute_config] using min 06 link bw per VBT
>[   62.057146] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   62.057148] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   62.057151] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   62.057154] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe B
>[   62.057156] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   62.057157] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   62.057160] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   62.057163] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   62.057165] [drm:intel_dump_pipe_config] requested mode:
>[   62.057169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   62.057170] [drm:intel_dump_pipe_config] adjusted mode:
>[   62.057174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   62.057177] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   62.057179] [drm:intel_dump_pipe_config] port clock: 270000
>[   62.057181] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   62.057183] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   62.057185] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   62.057187] [drm:intel_dump_pipe_config] ips: 0
>[   62.057188] [drm:intel_dump_pipe_config] double wide: 0
>[   62.057194] [drm:ironlake_disable_fbc] disabled FBC
>[   62.086250] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   62.086256] [drm:intel_edp_backlight_off] 
>[   62.102388] [drm:intel_edp_panel_off] Turn eDP power off
>[   62.117061] usb 1-2: USB disconnect, device number 3
>[   62.287105] [drm:wait_panel_off] Wait for panel power off time
>[   62.287113] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   62.342059] [drm:wait_panel_status] Wait complete
>[   62.342067] [drm:intel_update_fbc] no output, disabling
>[   62.351563] [drm:ironlake_update_primary_plane] Writing base 0B07C000 00000000 0 0 8192
>[   62.351571] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   62.351575] [drm:intel_crtc_mode_set] [ENCODER:13:TMDS-13] set [MODE:0:1920x1080]
>[   62.351577] [drm:intel_ddi_mode_set] Preparing DDI mode on port A, pipe B
>[   62.351580] [drm:intel_edp_panel_on] Turn eDP power on
>[   62.351584] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   62.887654] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[   62.887657] [drm:wait_panel_status] Wait complete
>[   62.887661] [drm:wait_panel_on] Wait for panel power on
>[   62.887665] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   63.096492] [drm:wait_panel_status] Wait complete
>[   63.096496] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   63.096504] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   63.097560] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   63.098002] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   63.098433] [drm:intel_dp_start_link_train] clock recovery OK
>[   63.099176] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   63.099378] [drm:intel_edp_backlight_on] 
>[   63.099384] [drm:intel_panel_enable_backlight] pipe B
>[   63.099390] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   63.099393] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   63.116475] [drm:intel_update_fbc] plane not A, disabling compression
>[   63.116481] [drm:intel_connector_check_state] [CONNECTOR:14:eDP-1]
>[   63.116485] [drm:check_encoder_state] [ENCODER:13:TMDS-13]
>[   63.116488] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[   63.116490] [drm:check_encoder_state] [ENCODER:24:TMDS-24]
>[   63.116493] [drm:check_crtc_state] [CRTC:5]
>[   63.116495] [drm:check_crtc_state] [CRTC:8]
>[   63.116503] [drm:check_crtc_state] [CRTC:11]
>[   63.116514] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[   63.116520] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[   63.416438] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   63.416445] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   63.416450] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   63.416453] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1]
>[   63.416456] [drm:intel_dp_detect] [CONNECTOR:14:eDP-1]
>[   63.416460] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   63.416467] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   63.416628] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[   63.416786] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[   63.416796] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   63.416800] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1] probed modes :
>[   63.416804] [drm:drm_mode_debug_printmodeline] Modeline 15:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   63.416807] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   63.416814] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   63.416819] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   63.416840] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   63.416845] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   63.468210] [drm:g4x_wait_for_vblank] vblank wait timed out
>[   63.468226] [drm:drm_mode_addfb2] [FB:55]
>[   63.478198] [drm:drm_mode_addfb2] [FB:56]
>[   63.488109] [drm:drm_mode_setcrtc] [CRTC:5]
>[   63.488115] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   63.488119] [drm:intel_crtc_set_config] [CRTC:5] [FB:56] #connectors=1 (x y) (0 0)
>[   63.488122] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[   63.488125] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0
>[   63.488127] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   63.488129] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[   63.488131] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[   63.488133] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[   63.488136] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[   63.488140] [drm:connected_sink_compute_bpp] [CONNECTOR:14:eDP-1] checking for sink bpp constrains
>[   63.488144] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   63.488146] [drm:intel_dp_compute_config] using min 2 lanes per VBT
>[   63.488148] [drm:intel_dp_compute_config] using min 06 link bw per VBT
>[   63.488154] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   63.488156] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   63.488161] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   63.488163] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A
>[   63.488165] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   63.488167] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   63.488170] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   63.488172] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   63.488174] [drm:intel_dump_pipe_config] requested mode:
>[   63.488178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   63.488179] [drm:intel_dump_pipe_config] adjusted mode:
>[   63.488183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   63.488186] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   63.488188] [drm:intel_dump_pipe_config] port clock: 270000
>[   63.488190] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   63.488201] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   63.488211] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   63.488222] [drm:intel_dump_pipe_config] ips: 1
>[   63.488231] [drm:intel_dump_pipe_config] double wide: 0
>[   63.500188] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   63.500195] [drm:intel_edp_backlight_off] 
>[   63.516327] [drm:intel_edp_panel_off] Turn eDP power off
>[   63.632107] usb 1-2: new low-speed USB device number 5 using xhci_hcd
>[   63.701040] [drm:wait_panel_off] Wait for panel power off time
>[   63.701045] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   63.755998] [drm:wait_panel_status] Wait complete
>[   63.756005] [drm:intel_update_fbc] no output, disabling
>[   63.766696] [drm:ironlake_update_primary_plane] Writing base 0E07D000 00000000 0 0 8192
>[   63.766702] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   63.766705] [drm:intel_crtc_mode_set] [ENCODER:13:TMDS-13] set [MODE:0:1920x1080]
>[   63.766708] [drm:intel_ddi_mode_set] Preparing DDI mode on port A, pipe A
>[   63.766711] [drm:intel_edp_panel_on] Turn eDP power on
>[   63.766713] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   63.799239] usb 1-2: New USB device found, idVendor=046d, idProduct=c06a
>[   63.799244] usb 1-2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
>[   63.799247] usb 1-2: Product: USB Optical Mouse
>[   63.799249] usb 1-2: Manufacturer: Logitech
>[   63.799374] usb 1-2: ep 0x81 - rounding interval to 64 microframes, ep desc says 80 microframes
>[   63.801471] input: Logitech USB Optical Mouse as /devices/pci0000:00/0000:00:14.0/usb1/1-2/1-2:1.0/0003:046D:C06A.0003/input/input9
>[   63.801671] hid-generic 0003:046D:C06A.0003: input,hidraw1: USB HID v1.11 Mouse [Logitech USB Optical Mouse] on usb-0000:00:14.0-2/input0
>[   64.301598] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[   64.301604] [drm:wait_panel_status] Wait complete
>[   64.301608] [drm:wait_panel_on] Wait for panel power on
>[   64.301613] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   64.510431] [drm:wait_panel_status] Wait complete
>[   64.510435] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   64.510442] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   64.511505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   64.511954] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   64.512385] [drm:intel_dp_start_link_train] clock recovery OK
>[   64.513130] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   64.513335] [drm:intel_edp_backlight_on] 
>[   64.513341] [drm:intel_panel_enable_backlight] pipe A
>[   64.513346] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   64.513350] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   64.532415] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   64.532421] [drm:intel_connector_check_state] [CONNECTOR:14:eDP-1]
>[   64.532426] [drm:check_encoder_state] [ENCODER:13:TMDS-13]
>[   64.532429] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[   64.532431] [drm:check_encoder_state] [ENCODER:24:TMDS-24]
>[   64.532434] [drm:check_crtc_state] [CRTC:5]
>[   64.532441] [drm:check_crtc_state] [CRTC:8]
>[   64.532444] [drm:check_crtc_state] [CRTC:11]
>[   64.582384] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   64.646122] [drm:gen8_irq_handler] *ERROR* Pipe A FIFO underrun
>[   64.846402] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   64.879722] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   64.897141] [drm:drm_mode_setcrtc] [CRTC:5]
>[   64.897147] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   64.897150] [drm:intel_crtc_set_config] [CRTC:5] [FB:55] #connectors=1 (x y) (0 0)
>[   64.897153] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=0, fb_changed=1
>[   64.897156] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   64.906392] [drm:ironlake_update_primary_plane] Writing base 0D07D000 00000000 0 0 8192
>[   64.914128] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   64.914130] [drm:intel_update_fbc] disabling active FBC for update
>[   64.914133] [drm:ironlake_disable_fbc] disabled FBC
>[   64.914135] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   64.964096] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   65.229438] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   65.246109] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   65.263911] [drm:ironlake_disable_fbc] disabled FBC
>[   65.279401] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   65.328821] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   65.595822] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   65.612494] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   65.929442] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   65.962223] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   65.979354] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   65.979361] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   65.979365] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   65.979368] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1]
>[   65.979371] [drm:intel_dp_detect] [CONNECTOR:14:eDP-1]
>[   65.979535] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[   65.979695] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[   65.979705] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   65.979710] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1] probed modes :
>[   65.979714] [drm:drm_mode_debug_printmodeline] Modeline 15:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   65.979718] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   65.979725] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   65.979729] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   65.979749] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf
>[   65.979753] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[   66.031287] [drm:g4x_wait_for_vblank] vblank wait timed out
>[   66.031302] [drm:drm_mode_addfb2] [FB:57]
>[   66.041243] [drm:drm_mode_addfb2] [FB:58]
>[   66.051199] [drm:drm_mode_setcrtc] [CRTC:8]
>[   66.051205] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   66.051209] [drm:intel_crtc_set_config] [CRTC:8] [FB:58] #connectors=1 (x y) (0 0)
>[   66.051212] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[   66.051215] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
>[   66.051218] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:8]
>[   66.051219] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[   66.051222] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[   66.051223] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[   66.051227] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 1
>[   66.051230] [drm:connected_sink_compute_bpp] [CONNECTOR:14:eDP-1] checking for sink bpp constrains
>[   66.051235] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   66.051236] [drm:intel_dp_compute_config] using min 2 lanes per VBT
>[   66.051238] [drm:intel_dp_compute_config] using min 06 link bw per VBT
>[   66.051245] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   66.051247] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   66.051250] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   66.051253] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe B
>[   66.051255] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   66.051256] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   66.051259] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   66.051262] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   66.051264] [drm:intel_dump_pipe_config] requested mode:
>[   66.051267] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   66.051278] [drm:intel_dump_pipe_config] adjusted mode:
>[   66.051284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   66.051297] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   66.051306] [drm:intel_dump_pipe_config] port clock: 270000
>[   66.051316] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   66.051328] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   66.051337] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   66.051347] [drm:intel_dump_pipe_config] ips: 0
>[   66.051352] [drm:intel_dump_pipe_config] double wide: 0
>[   66.051360] [drm:ironlake_disable_fbc] disabled FBC
>[   66.079254] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   66.079260] [drm:intel_edp_backlight_off] 
>[   66.097392] [drm:intel_edp_panel_off] Turn eDP power off
>[   66.280108] [drm:wait_panel_off] Wait for panel power off time
>[   66.280112] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   66.335062] [drm:wait_panel_status] Wait complete
>[   66.335069] [drm:intel_update_fbc] no output, disabling
>[   66.345962] [drm:ironlake_update_primary_plane] Writing base 0307C000 00000000 0 0 8192
>[   66.345968] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   66.345971] [drm:intel_crtc_mode_set] [ENCODER:13:TMDS-13] set [MODE:0:1920x1080]
>[   66.345973] [drm:intel_ddi_mode_set] Preparing DDI mode on port A, pipe B
>[   66.345976] [drm:intel_edp_panel_on] Turn eDP power on
>[   66.345980] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   66.880656] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[   66.880661] [drm:wait_panel_status] Wait complete
>[   66.880665] [drm:wait_panel_on] Wait for panel power on
>[   66.880669] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   67.089496] [drm:wait_panel_status] Wait complete
>[   67.089499] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   67.089506] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   67.090557] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   67.090999] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   67.091429] [drm:intel_dp_start_link_train] clock recovery OK
>[   67.092172] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   67.092374] [drm:intel_edp_backlight_on] 
>[   67.092380] [drm:intel_panel_enable_backlight] pipe B
>[   67.092385] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   67.092388] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   67.109479] [drm:intel_update_fbc] plane not A, disabling compression
>[   67.109484] [drm:intel_connector_check_state] [CONNECTOR:14:eDP-1]
>[   67.109488] [drm:check_encoder_state] [ENCODER:13:TMDS-13]
>[   67.109491] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[   67.109493] [drm:check_encoder_state] [ENCODER:24:TMDS-24]
>[   67.109495] [drm:check_crtc_state] [CRTC:5]
>[   67.109498] [drm:check_crtc_state] [CRTC:8]
>[   67.109506] [drm:check_crtc_state] [CRTC:11]
>[   67.109516] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[   67.109522] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[   67.409443] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   67.409451] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   67.409455] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   67.409458] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1]
>[   67.409461] [drm:intel_dp_detect] [CONNECTOR:14:eDP-1]
>[   67.409465] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   67.409472] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   67.409634] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[   67.409792] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[   67.409801] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   67.409805] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1] probed modes :
>[   67.409809] [drm:drm_mode_debug_printmodeline] Modeline 15:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   67.409812] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   67.409819] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   67.409823] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   67.409843] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   67.409848] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   67.461214] [drm:g4x_wait_for_vblank] vblank wait timed out
>[   67.461231] [drm:drm_mode_addfb2] [FB:59]
>[   67.471150] [drm:drm_mode_addfb2] [FB:60]
>[   67.481077] [drm:drm_mode_setcrtc] [CRTC:5]
>[   67.481083] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   67.481086] [drm:intel_crtc_set_config] [CRTC:5] [FB:60] #connectors=1 (x y) (0 0)
>[   67.481090] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[   67.481093] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0
>[   67.481096] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   67.481098] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[   67.481100] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[   67.481102] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[   67.481105] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[   67.481109] [drm:connected_sink_compute_bpp] [CONNECTOR:14:eDP-1] checking for sink bpp constrains
>[   67.481113] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   67.481115] [drm:intel_dp_compute_config] using min 2 lanes per VBT
>[   67.481116] [drm:intel_dp_compute_config] using min 06 link bw per VBT
>[   67.481123] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   67.481125] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   67.481128] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   67.481130] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A
>[   67.481132] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   67.481134] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   67.481137] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   67.481140] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   67.481141] [drm:intel_dump_pipe_config] requested mode:
>[   67.481145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   67.481147] [drm:intel_dump_pipe_config] adjusted mode:
>[   67.481150] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   67.481153] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   67.481155] [drm:intel_dump_pipe_config] port clock: 270000
>[   67.481156] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   67.481159] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   67.481161] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   67.481163] [drm:intel_dump_pipe_config] ips: 1
>[   67.481164] [drm:intel_dump_pipe_config] double wide: 0
>[   67.492193] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   67.492200] [drm:intel_edp_backlight_off] 
>[   67.510330] [drm:intel_edp_panel_off] Turn eDP power off
>[   67.693046] [drm:wait_panel_off] Wait for panel power off time
>[   67.693050] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   67.748002] [drm:wait_panel_status] Wait complete
>[   67.748009] [drm:intel_update_fbc] no output, disabling
>[   67.758845] [drm:ironlake_update_primary_plane] Writing base 0107C000 00000000 0 0 8192
>[   67.758851] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   67.758854] [drm:intel_crtc_mode_set] [ENCODER:13:TMDS-13] set [MODE:0:1920x1080]
>[   67.758857] [drm:intel_ddi_mode_set] Preparing DDI mode on port A, pipe A
>[   67.758860] [drm:intel_edp_panel_on] Turn eDP power on
>[   67.758864] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   68.293599] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[   68.293602] [drm:wait_panel_status] Wait complete
>[   68.293606] [drm:wait_panel_on] Wait for panel power on
>[   68.293609] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   68.502435] [drm:wait_panel_status] Wait complete
>[   68.502438] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   68.502445] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   68.503493] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   68.503935] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   68.504366] [drm:intel_dp_start_link_train] clock recovery OK
>[   68.505112] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   68.505313] [drm:intel_edp_backlight_on] 
>[   68.505318] [drm:intel_panel_enable_backlight] pipe A
>[   68.505324] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   68.505327] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   68.524418] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   68.524423] [drm:intel_connector_check_state] [CONNECTOR:14:eDP-1]
>[   68.524427] [drm:check_encoder_state] [ENCODER:13:TMDS-13]
>[   68.524430] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[   68.524432] [drm:check_encoder_state] [ENCODER:24:TMDS-24]
>[   68.524435] [drm:check_crtc_state] [CRTC:5]
>[   68.524442] [drm:check_crtc_state] [CRTC:8]
>[   68.524445] [drm:check_crtc_state] [CRTC:11]
>[   68.574388] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   68.638103] [drm:gen8_irq_handler] *ERROR* Pipe A FIFO underrun
>[   68.838383] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   68.871704] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   68.889145] [drm:drm_mode_setcrtc] [CRTC:5]
>[   68.889149] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   68.889152] [drm:intel_crtc_set_config] [CRTC:5] [FB:59] #connectors=1 (x y) (0 0)
>[   68.889155] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=0, fb_changed=1
>[   68.889158] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   68.898388] [drm:ironlake_update_primary_plane] Writing base 0407C000 00000000 0 0 8192
>[   68.906132] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   68.906134] [drm:intel_update_fbc] disabling active FBC for update
>[   68.906136] [drm:ironlake_disable_fbc] disabled FBC
>[   68.906139] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   68.956101] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   69.221421] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   69.238090] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   69.255914] [drm:ironlake_disable_fbc] disabled FBC
>[   69.271382] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   69.320826] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   69.587804] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   69.604476] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   69.921444] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   69.954205] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   69.971358] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   69.971366] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   69.971371] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   69.971374] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1]
>[   69.971377] [drm:intel_dp_detect] [CONNECTOR:14:eDP-1]
>[   69.971542] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[   69.971702] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[   69.971711] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   69.971715] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1] probed modes :
>[   69.971719] [drm:drm_mode_debug_printmodeline] Modeline 15:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   69.971723] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   69.971730] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   69.971735] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   69.971756] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf
>[   69.971760] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[   70.023292] [drm:g4x_wait_for_vblank] vblank wait timed out
>[   70.023305] [drm:drm_mode_addfb2] [FB:61]
>[   70.033226] [drm:drm_mode_addfb2] [FB:62]
>[   70.043185] [drm:drm_mode_setcrtc] [CRTC:8]
>[   70.043191] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   70.043195] [drm:intel_crtc_set_config] [CRTC:8] [FB:62] #connectors=1 (x y) (0 0)
>[   70.043198] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[   70.043200] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
>[   70.043203] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:8]
>[   70.043205] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[   70.043207] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[   70.043209] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[   70.043212] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 1
>[   70.043216] [drm:connected_sink_compute_bpp] [CONNECTOR:14:eDP-1] checking for sink bpp constrains
>[   70.043220] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   70.043222] [drm:intel_dp_compute_config] using min 2 lanes per VBT
>[   70.043224] [drm:intel_dp_compute_config] using min 06 link bw per VBT
>[   70.043230] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   70.043232] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   70.043236] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   70.043238] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe B
>[   70.043240] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   70.043242] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   70.043244] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   70.043247] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   70.043249] [drm:intel_dump_pipe_config] requested mode:
>[   70.043253] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   70.043254] [drm:intel_dump_pipe_config] adjusted mode:
>[   70.043257] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   70.043261] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   70.043262] [drm:intel_dump_pipe_config] port clock: 270000
>[   70.043264] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   70.043267] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   70.043269] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   70.043270] [drm:intel_dump_pipe_config] ips: 0
>[   70.043282] [drm:intel_dump_pipe_config] double wide: 0
>[   70.043291] [drm:ironlake_disable_fbc] disabled FBC
>[   70.071258] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   70.071265] [drm:intel_edp_backlight_off] 
>[   70.089396] [drm:intel_edp_panel_off] Turn eDP power off
>[   70.272112] [drm:wait_panel_off] Wait for panel power off time
>[   70.272117] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   70.327066] [drm:wait_panel_status] Wait complete
>[   70.327074] [drm:intel_update_fbc] no output, disabling
>[   70.337970] [drm:ironlake_update_primary_plane] Writing base 0807C000 00000000 0 0 8192
>[   70.337977] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   70.337980] [drm:intel_crtc_mode_set] [ENCODER:13:TMDS-13] set [MODE:0:1920x1080]
>[   70.337983] [drm:intel_ddi_mode_set] Preparing DDI mode on port A, pipe B
>[   70.337985] [drm:intel_edp_panel_on] Turn eDP power on
>[   70.337989] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   70.872661] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000
>[   70.883650] [drm:wait_panel_status] Wait complete
>[   70.883654] [drm:wait_panel_on] Wait for panel power on
>[   70.883658] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   71.092491] [drm:wait_panel_status] Wait complete
>[   71.092495] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   71.092502] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   71.093550] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   71.093992] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   71.094422] [drm:intel_dp_start_link_train] clock recovery OK
>[   71.095167] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   71.095368] [drm:intel_edp_backlight_on] 
>[   71.095374] [drm:intel_panel_enable_backlight] pipe B
>[   71.095379] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   71.095382] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   71.112475] [drm:intel_update_fbc] plane not A, disabling compression
>[   71.112479] [drm:intel_connector_check_state] [CONNECTOR:14:eDP-1]
>[   71.112483] [drm:check_encoder_state] [ENCODER:13:TMDS-13]
>[   71.112486] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[   71.112488] [drm:check_encoder_state] [ENCODER:24:TMDS-24]
>[   71.112491] [drm:check_crtc_state] [CRTC:5]
>[   71.112494] [drm:check_crtc_state] [CRTC:8]
>[   71.112501] [drm:check_crtc_state] [CRTC:11]
>[   71.112511] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[   71.112517] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[   71.412443] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   71.412451] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   71.412455] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   71.412458] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1]
>[   71.412460] [drm:intel_dp_detect] [CONNECTOR:14:eDP-1]
>[   71.412463] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   71.412470] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   71.412631] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[   71.412790] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[   71.412798] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   71.412802] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1] probed modes :
>[   71.412806] [drm:drm_mode_debug_printmodeline] Modeline 15:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   71.412810] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   71.412818] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   71.412822] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   71.412843] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   71.412848] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   71.464210] [drm:g4x_wait_for_vblank] vblank wait timed out
>[   71.464227] [drm:drm_mode_addfb2] [FB:63]
>[   71.474097] [drm:drm_mode_addfb2] [FB:64]
>[   71.484025] [drm:drm_mode_setcrtc] [CRTC:5]
>[   71.484032] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   71.484035] [drm:intel_crtc_set_config] [CRTC:5] [FB:64] #connectors=1 (x y) (0 0)
>[   71.484038] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[   71.484040] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0
>[   71.484043] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   71.484045] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[   71.484047] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[   71.484049] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[   71.484052] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[   71.484055] [drm:connected_sink_compute_bpp] [CONNECTOR:14:eDP-1] checking for sink bpp constrains
>[   71.484059] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   71.484061] [drm:intel_dp_compute_config] using min 2 lanes per VBT
>[   71.484063] [drm:intel_dp_compute_config] using min 06 link bw per VBT
>[   71.484069] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   71.484071] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   71.484074] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   71.484077] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A
>[   71.484079] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   71.484080] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   71.484083] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   71.484086] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   71.484088] [drm:intel_dump_pipe_config] requested mode:
>[   71.484091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   71.484093] [drm:intel_dump_pipe_config] adjusted mode:
>[   71.484096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   71.484099] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   71.484101] [drm:intel_dump_pipe_config] port clock: 270000
>[   71.484103] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   71.484105] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   71.484107] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   71.484109] [drm:intel_dump_pipe_config] ips: 1
>[   71.484111] [drm:intel_dump_pipe_config] double wide: 0
>[   71.495189] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   71.495196] [drm:intel_edp_backlight_off] 
>[   71.513326] [drm:intel_edp_panel_off] Turn eDP power off
>[   71.696042] [drm:wait_panel_off] Wait for panel power off time
>[   71.696046] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   71.750998] [drm:wait_panel_status] Wait complete
>[   71.751005] [drm:intel_update_fbc] no output, disabling
>[   71.761873] [drm:ironlake_update_primary_plane] Writing base 0507C000 00000000 0 0 8192
>[   71.761879] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   71.761882] [drm:intel_crtc_mode_set] [ENCODER:13:TMDS-13] set [MODE:0:1920x1080]
>[   71.761885] [drm:intel_ddi_mode_set] Preparing DDI mode on port A, pipe A
>[   71.761888] [drm:intel_edp_panel_on] Turn eDP power on
>[   71.761891] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   72.296595] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[   72.296597] [drm:wait_panel_status] Wait complete
>[   72.296601] [drm:wait_panel_on] Wait for panel power on
>[   72.296605] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   72.505431] [drm:wait_panel_status] Wait complete
>[   72.505434] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   72.505441] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   72.506489] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   72.506931] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   72.507361] [drm:intel_dp_start_link_train] clock recovery OK
>[   72.508104] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   72.508305] [drm:intel_edp_backlight_on] 
>[   72.508311] [drm:intel_panel_enable_backlight] pipe A
>[   72.508316] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   72.508319] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   72.527414] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   72.527419] [drm:intel_connector_check_state] [CONNECTOR:14:eDP-1]
>[   72.527424] [drm:check_encoder_state] [ENCODER:13:TMDS-13]
>[   72.527426] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[   72.527428] [drm:check_encoder_state] [ENCODER:24:TMDS-24]
>[   72.527431] [drm:check_crtc_state] [CRTC:5]
>[   72.527438] [drm:check_crtc_state] [CRTC:8]
>[   72.527441] [drm:check_crtc_state] [CRTC:11]
>[   72.577383] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   72.641096] [drm:gen8_irq_handler] *ERROR* Pipe A FIFO underrun
>[   72.841376] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   72.874697] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   72.892141] [drm:drm_mode_setcrtc] [CRTC:5]
>[   72.892145] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   72.892148] [drm:intel_crtc_set_config] [CRTC:5] [FB:63] #connectors=1 (x y) (0 0)
>[   72.892151] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=0, fb_changed=1
>[   72.892154] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   72.901380] [drm:ironlake_update_primary_plane] Writing base 0707C000 00000000 0 0 8192
>[   72.909128] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   72.909130] [drm:intel_update_fbc] disabling active FBC for update
>[   72.909132] [drm:ironlake_disable_fbc] disabled FBC
>[   72.909134] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   72.959097] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   73.224414] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   73.241087] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   73.258911] [drm:ironlake_disable_fbc] disabled FBC
>[   73.274376] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   73.323822] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   73.590797] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   73.607468] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   73.924444] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   73.957198] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   73.974355] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   73.974363] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   73.974369] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   73.974372] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1]
>[   73.974374] [drm:intel_dp_detect] [CONNECTOR:14:eDP-1]
>[   73.974537] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[   73.974696] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[   73.974704] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   73.974708] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1] probed modes :
>[   73.974712] [drm:drm_mode_debug_printmodeline] Modeline 15:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   73.974716] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   73.974723] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   73.974728] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   73.974749] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf
>[   73.974753] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[   74.026288] [drm:g4x_wait_for_vblank] vblank wait timed out
>[   74.026302] [drm:drm_mode_addfb2] [FB:65]
>[   74.036209] [drm:drm_mode_addfb2] [FB:66]
>[   74.046113] [drm:drm_mode_setcrtc] [CRTC:8]
>[   74.046120] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   74.046124] [drm:intel_crtc_set_config] [CRTC:8] [FB:66] #connectors=1 (x y) (0 0)
>[   74.046127] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[   74.046129] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
>[   74.046132] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:8]
>[   74.046134] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[   74.046136] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[   74.046138] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[   74.046141] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 1
>[   74.046145] [drm:connected_sink_compute_bpp] [CONNECTOR:14:eDP-1] checking for sink bpp constrains
>[   74.046150] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   74.046151] [drm:intel_dp_compute_config] using min 2 lanes per VBT
>[   74.046153] [drm:intel_dp_compute_config] using min 06 link bw per VBT
>[   74.046160] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   74.046162] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   74.046165] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   74.046168] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe B
>[   74.046169] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   74.046171] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   74.046174] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   74.046177] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   74.046179] [drm:intel_dump_pipe_config] requested mode:
>[   74.046182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   74.046184] [drm:intel_dump_pipe_config] adjusted mode:
>[   74.046187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   74.046190] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   74.046192] [drm:intel_dump_pipe_config] port clock: 270000
>[   74.046194] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   74.046196] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   74.046199] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   74.046200] [drm:intel_dump_pipe_config] ips: 0
>[   74.046202] [drm:intel_dump_pipe_config] double wide: 0
>[   74.046218] [drm:ironlake_disable_fbc] disabled FBC
>[   74.075255] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   74.075261] [drm:intel_edp_backlight_off] 
>[   74.091394] [drm:intel_edp_panel_off] Turn eDP power off
>[   74.276107] [drm:wait_panel_off] Wait for panel power off time
>[   74.276112] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   74.331062] [drm:wait_panel_status] Wait complete
>[   74.331069] [drm:intel_update_fbc] no output, disabling
>[   74.341978] [drm:ironlake_update_primary_plane] Writing base 0A07C000 00000000 0 0 8192
>[   74.341988] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   74.341992] [drm:intel_crtc_mode_set] [ENCODER:13:TMDS-13] set [MODE:0:1920x1080]
>[   74.341994] [drm:intel_ddi_mode_set] Preparing DDI mode on port A, pipe B
>[   74.341996] [drm:intel_edp_panel_on] Turn eDP power on
>[   74.342000] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   74.876657] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[   74.876660] [drm:wait_panel_status] Wait complete
>[   74.876664] [drm:wait_panel_on] Wait for panel power on
>[   74.876668] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   75.085495] [drm:wait_panel_status] Wait complete
>[   75.085499] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   75.085505] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   75.086551] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   75.086993] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   75.087426] [drm:intel_dp_start_link_train] clock recovery OK
>[   75.088170] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   75.088371] [drm:intel_edp_backlight_on] 
>[   75.088376] [drm:intel_panel_enable_backlight] pipe B
>[   75.088382] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   75.088385] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   75.105478] [drm:intel_update_fbc] plane not A, disabling compression
>[   75.105483] [drm:intel_connector_check_state] [CONNECTOR:14:eDP-1]
>[   75.105487] [drm:check_encoder_state] [ENCODER:13:TMDS-13]
>[   75.105490] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[   75.105492] [drm:check_encoder_state] [ENCODER:24:TMDS-24]
>[   75.105495] [drm:check_crtc_state] [CRTC:5]
>[   75.105498] [drm:check_crtc_state] [CRTC:8]
>[   75.105505] [drm:check_crtc_state] [CRTC:11]
>[   75.105515] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[   75.105521] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[   75.405462] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   75.405470] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   75.405475] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   75.405478] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1]
>[   75.405480] [drm:intel_dp_detect] [CONNECTOR:14:eDP-1]
>[   75.405484] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   75.405491] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   75.405652] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[   75.405812] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[   75.405821] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   75.405825] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1] probed modes :
>[   75.405829] [drm:drm_mode_debug_printmodeline] Modeline 15:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   75.405833] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   75.405840] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   75.405845] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   75.405865] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   75.405870] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   75.457214] [drm:g4x_wait_for_vblank] vblank wait timed out
>[   75.457229] [drm:drm_mode_addfb2] [FB:67]
>[   75.467168] [drm:drm_mode_addfb2] [FB:68]
>[   75.477077] [drm:drm_mode_setcrtc] [CRTC:5]
>[   75.477084] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   75.477087] [drm:intel_crtc_set_config] [CRTC:5] [FB:68] #connectors=1 (x y) (0 0)
>[   75.477092] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[   75.477094] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0
>[   75.477097] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   75.477099] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[   75.477101] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[   75.477102] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[   75.477106] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[   75.477109] [drm:connected_sink_compute_bpp] [CONNECTOR:14:eDP-1] checking for sink bpp constrains
>[   75.477113] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   75.477115] [drm:intel_dp_compute_config] using min 2 lanes per VBT
>[   75.477117] [drm:intel_dp_compute_config] using min 06 link bw per VBT
>[   75.477124] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   75.477126] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   75.477129] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   75.477131] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A
>[   75.477133] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   75.477135] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   75.477138] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   75.477141] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   75.477142] [drm:intel_dump_pipe_config] requested mode:
>[   75.477146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   75.477148] [drm:intel_dump_pipe_config] adjusted mode:
>[   75.477151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   75.477154] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   75.477156] [drm:intel_dump_pipe_config] port clock: 270000
>[   75.477157] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   75.477160] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   75.477162] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   75.477163] [drm:intel_dump_pipe_config] ips: 1
>[   75.477165] [drm:intel_dump_pipe_config] double wide: 0
>[   75.488193] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   75.488199] [drm:intel_edp_backlight_off] 
>[   75.506329] [drm:intel_edp_panel_off] Turn eDP power off
>[   75.689045] [drm:wait_panel_off] Wait for panel power off time
>[   75.689050] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   75.744002] [drm:wait_panel_status] Wait complete
>[   75.744009] [drm:intel_update_fbc] no output, disabling
>[   75.754903] [drm:ironlake_update_primary_plane] Writing base 0B07C000 00000000 0 0 8192
>[   75.754910] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   75.754913] [drm:intel_crtc_mode_set] [ENCODER:13:TMDS-13] set [MODE:0:1920x1080]
>[   75.754915] [drm:intel_ddi_mode_set] Preparing DDI mode on port A, pipe A
>[   75.754918] [drm:intel_edp_panel_on] Turn eDP power on
>[   75.754922] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   76.289599] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[   76.289601] [drm:wait_panel_status] Wait complete
>[   76.289605] [drm:wait_panel_on] Wait for panel power on
>[   76.289609] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   76.498435] [drm:wait_panel_status] Wait complete
>[   76.498438] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   76.498445] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   76.499493] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   76.499933] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   76.500364] [drm:intel_dp_start_link_train] clock recovery OK
>[   76.501107] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   76.501309] [drm:intel_edp_backlight_on] 
>[   76.501314] [drm:intel_panel_enable_backlight] pipe A
>[   76.501320] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   76.501323] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   76.520418] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   76.520423] [drm:intel_connector_check_state] [CONNECTOR:14:eDP-1]
>[   76.520427] [drm:check_encoder_state] [ENCODER:13:TMDS-13]
>[   76.520430] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[   76.520432] [drm:check_encoder_state] [ENCODER:24:TMDS-24]
>[   76.520435] [drm:check_crtc_state] [CRTC:5]
>[   76.520442] [drm:check_crtc_state] [CRTC:8]
>[   76.520445] [drm:check_crtc_state] [CRTC:11]
>[   76.570387] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   76.634099] [drm:gen8_irq_handler] *ERROR* Pipe A FIFO underrun
>[   76.834379] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   76.867699] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   76.885152] [drm:i915_gem_context_create_ioctl] HW context 1 created
>[   76.885156] [drm:i915_gem_context_create_ioctl] HW context 2 created
>[   76.885306] [drm:drm_mode_setcrtc] [CRTC:5]
>[   76.885311] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   76.885314] [drm:intel_crtc_set_config] [CRTC:5] [FB:67] #connectors=1 (x y) (0 0)
>[   76.885317] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=0, fb_changed=1
>[   76.885320] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   76.894868] [drm:ironlake_update_primary_plane] Writing base 0C07C000 00000000 0 0 8192
>[   76.902132] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   76.902135] [drm:intel_update_fbc] disabling active FBC for update
>[   76.902137] [drm:ironlake_disable_fbc] disabled FBC
>[   76.902139] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   76.952101] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   77.217416] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   77.234088] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   77.251919] [drm:ironlake_disable_fbc] disabled FBC
>[   77.267379] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[   77.316828] [drm:gen7_enable_fbc] enabled fbc on plane A
>[   77.583800] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   77.600472] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   77.917448] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[   77.950200] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[   77.967356] [drm:i915_gem_context_destroy_ioctl] HW context 1 destroyed
>[   77.967359] [drm:i915_gem_context_destroy_ioctl] HW context 2 destroyed
>[   77.967365] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   77.967375] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   77.967380] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   77.967383] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1]
>[   77.967385] [drm:intel_dp_detect] [CONNECTOR:14:eDP-1]
>[   77.967548] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[   77.967706] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[   77.967715] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   77.967719] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1] probed modes :
>[   77.967723] [drm:drm_mode_debug_printmodeline] Modeline 15:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   77.967727] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[   77.967734] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   77.967740] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[   77.967762] [drm:pipe_crc_set_source] collecting CRCs for pipe B, pf
>[   77.967766] [drm:pipe_crc_set_source] stopping CRCs for pipe B
>[   78.019292] [drm:g4x_wait_for_vblank] vblank wait timed out
>[   78.019306] [drm:drm_mode_addfb2] [FB:69]
>[   78.029323] [drm:drm_mode_addfb2] [FB:70]
>[   78.039254] [drm:drm_mode_setcrtc] [CRTC:8]
>[   78.039261] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[   78.039265] [drm:intel_crtc_set_config] [CRTC:8] [FB:70] #connectors=1 (x y) (0 0)
>[   78.039268] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[   78.039271] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
>[   78.039285] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:8]
>[   78.039292] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[   78.039300] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[   78.039303] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[   78.039307] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 1
>[   78.039312] [drm:connected_sink_compute_bpp] [CONNECTOR:14:eDP-1] checking for sink bpp constrains
>[   78.039318] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   78.039321] [drm:intel_dp_compute_config] using min 2 lanes per VBT
>[   78.039323] [drm:intel_dp_compute_config] using min 06 link bw per VBT
>[   78.039332] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   78.039335] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   78.039340] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   78.039353] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe B
>[   78.039361] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   78.039363] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   78.039367] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   78.039378] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   78.039384] [drm:intel_dump_pipe_config] requested mode:
>[   78.039389] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   78.039391] [drm:intel_dump_pipe_config] adjusted mode:
>[   78.039396] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   78.039401] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   78.039404] [drm:intel_dump_pipe_config] port clock: 270000
>[   78.039406] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   78.039410] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   78.039413] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   78.039416] [drm:intel_dump_pipe_config] ips: 0
>[   78.039418] [drm:intel_dump_pipe_config] double wide: 0
>[   78.039437] [drm:ironlake_disable_fbc] disabled FBC
>[   78.067258] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   78.067266] [drm:intel_edp_backlight_off] 
>[   78.085405] [drm:intel_edp_panel_off] Turn eDP power off
>[   78.268111] [drm:wait_panel_off] Wait for panel power off time
>[   78.268117] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   78.323066] [drm:wait_panel_status] Wait complete
>[   78.323074] [drm:intel_update_fbc] no output, disabling
>[   78.334652] [drm:ironlake_update_primary_plane] Writing base 0E07D000 00000000 0 0 8192
>[   78.334656] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   78.334660] [drm:intel_crtc_mode_set] [ENCODER:13:TMDS-13] set [MODE:0:1920x1080]
>[   78.334663] [drm:intel_ddi_mode_set] Preparing DDI mode on port A, pipe B
>[   78.334665] [drm:intel_edp_panel_on] Turn eDP power on
>[   78.334669] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   78.868659] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000
>[   78.879650] [drm:wait_panel_status] Wait complete
>[   78.879654] [drm:wait_panel_on] Wait for panel power on
>[   78.879658] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   79.088492] [drm:wait_panel_status] Wait complete
>[   79.088499] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   79.088506] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   79.089565] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   79.090013] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   79.090444] [drm:intel_dp_start_link_train] clock recovery OK
>[   79.091194] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   79.091396] [drm:intel_edp_backlight_on] 
>[   79.091402] [drm:intel_panel_enable_backlight] pipe B
>[   79.091408] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   79.091411] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   79.108475] [drm:intel_update_fbc] plane not A, disabling compression
>[   79.108481] [drm:intel_connector_check_state] [CONNECTOR:14:eDP-1]
>[   79.108485] [drm:check_encoder_state] [ENCODER:13:TMDS-13]
>[   79.108488] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[   79.108490] [drm:check_encoder_state] [ENCODER:24:TMDS-24]
>[   79.108493] [drm:check_crtc_state] [CRTC:5]
>[   79.108496] [drm:check_crtc_state] [CRTC:8]
>[   79.108504] [drm:check_crtc_state] [CRTC:11]
>[   79.108514] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[   79.108520] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[   79.408523] [drm:intel_crtc_cursor_set] cursor off
>[   79.408525] [drm:intel_crtc_set_config] [CRTC:5] [FB:28] #connectors=1 (x y) (0 0)
>[   79.408527] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[   79.408529] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0
>[   79.408531] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   79.408532] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[   79.408533] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[   79.408534] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[   79.408536] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[   79.408539] [drm:connected_sink_compute_bpp] [CONNECTOR:14:eDP-1] checking for sink bpp constrains
>[   79.408541] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   79.408542] [drm:intel_dp_compute_config] using min 2 lanes per VBT
>[   79.408543] [drm:intel_dp_compute_config] using min 06 link bw per VBT
>[   79.408549] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   79.408550] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   79.408552] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   79.408554] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A
>[   79.408555] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   79.408556] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   79.408558] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   79.408560] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   79.408560] [drm:intel_dump_pipe_config] requested mode:
>[   79.408564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   79.408565] [drm:intel_dump_pipe_config] adjusted mode:
>[   79.408567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   79.408570] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   79.408571] [drm:intel_dump_pipe_config] port clock: 270000
>[   79.408572] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   79.408573] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   79.408575] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   79.408576] [drm:intel_dump_pipe_config] ips: 1
>[   79.408576] [drm:intel_dump_pipe_config] double wide: 0
>[   79.426239] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   79.426245] [drm:intel_edp_backlight_off] 
>[   79.442229] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   79.442235] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   79.442390] [drm:intel_edp_panel_off] Turn eDP power off
>[   79.627091] [drm:wait_panel_off] Wait for panel power off time
>[   79.627095] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   79.682046] [drm:wait_panel_status] Wait complete
>[   79.682051] [drm:intel_update_fbc] no output, disabling
>[   79.682067] [drm:ironlake_update_primary_plane] Writing base 00880000 00000000 0 0 7680
>[   79.682072] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   79.682074] [drm:intel_crtc_mode_set] [ENCODER:13:TMDS-13] set [MODE:0:1920x1080]
>[   79.682075] [drm:intel_ddi_mode_set] Preparing DDI mode on port A, pipe A
>[   79.682077] [drm:intel_edp_panel_on] Turn eDP power on
>[   79.682080] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   80.227643] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000
>[   80.271603] [drm:wait_panel_status] Wait complete
>[   80.271606] [drm:wait_panel_on] Wait for panel power on
>[   80.271609] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   80.480446] [drm:wait_panel_status] Wait complete
>[   80.480448] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[   80.480454] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   80.481504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   80.481944] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   80.482375] [drm:intel_dp_start_link_train] clock recovery OK
>[   80.483116] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   80.483316] [drm:intel_edp_backlight_on] 
>[   80.483321] [drm:intel_panel_enable_backlight] pipe A
>[   80.483326] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   80.483328] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[   80.502429] [drm:intel_update_fbc] framebuffer not tiled or fenced, disabling compression
>[   80.502432] [drm:intel_connector_check_state] [CONNECTOR:14:eDP-1]
>[   80.502435] [drm:check_encoder_state] [ENCODER:13:TMDS-13]
>[   80.502437] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[   80.502438] [drm:check_encoder_state] [ENCODER:24:TMDS-24]
>[   80.502439] [drm:check_crtc_state] [CRTC:5]
>[   80.502446] [drm:check_crtc_state] [CRTC:8]
>[   80.502448] [drm:check_crtc_state] [CRTC:11]
>[   80.502451] [drm:intel_crtc_cursor_set] cursor off
>[   80.502452] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[   80.502454] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[   80.502455] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   80.502456] [drm:intel_crtc_cursor_set] cursor off
>[   80.502458] [drm:intel_crtc_set_config] [CRTC:11] [NOFB]
>[   80.502459] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:11], mode_changed=0, fb_changed=0
>[   80.502460] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   80.531271] [drm:intel_crtc_cursor_set] cursor off
>[   80.531278] [drm:intel_crtc_set_config] [CRTC:5] [FB:28] #connectors=1 (x y) (0 0)
>[   80.531283] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=0, fb_changed=0
>[   80.531286] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   80.531289] [drm:intel_crtc_cursor_set] cursor off
>[   80.531291] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[   80.531294] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[   80.531296] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   80.531298] [drm:intel_crtc_cursor_set] cursor off
>[   80.531300] [drm:intel_crtc_set_config] [CRTC:11] [NOFB]
>[   80.531303] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:11], mode_changed=0, fb_changed=0
>[   80.531305] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[   81.090996] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[   81.091006] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  113.824783] [drm:i915_gem_open] 
>[  113.824812] [drm:intel_crtc_cursor_set] cursor off
>[  113.824816] [drm:intel_crtc_set_config] [CRTC:5] [FB:28] #connectors=1 (x y) (0 0)
>[  113.824821] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=0, fb_changed=0
>[  113.824824] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[  113.824827] [drm:intel_crtc_cursor_set] cursor off
>[  113.824829] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  113.824831] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  113.824834] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[  113.824836] [drm:intel_crtc_cursor_set] cursor off
>[  113.824838] [drm:intel_crtc_set_config] [CRTC:11] [NOFB]
>[  113.824840] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:11], mode_changed=0, fb_changed=0
>[  113.824842] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[  113.824852] [drm:i915_gem_open] 
>[  113.825231] [drm:i915_gem_open] 
>[  113.825246] [drm:i915_gem_open] 
>[  113.825350] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[  113.825358] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[  113.825374] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[  113.825377] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[  113.825381] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[  113.825384] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1]
>[  113.825387] [drm:intel_dp_detect] [CONNECTOR:14:eDP-1]
>[  113.825392] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[  113.825400] [drm:_edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  113.825566] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[  113.825725] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[  113.825736] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  113.825741] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:14:eDP-1] probed modes :
>[  113.825745] [drm:drm_mode_debug_printmodeline] Modeline 15:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  113.825749] [drm:drm_mode_getconnector] [CONNECTOR:14:?]
>[  113.825756] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[  113.825759] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[3]
>[  113.825777] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[  113.825782] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[  113.841429] [drm:drm_mode_addfb2] [FB:29]
>[  113.851688] [drm:drm_mode_addfb2] [FB:30]
>[  113.861772] [drm:drm_mode_setcrtc] [CRTC:5]
>[  113.861778] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[  113.861781] [drm:intel_crtc_set_config] [CRTC:5] [FB:30] #connectors=1 (x y) (0 0)
>[  113.861786] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=0, fb_changed=1
>[  113.861788] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[  113.872219] [drm:ironlake_update_primary_plane] Writing base 0207C000 00000000 0 0 8192
>[  113.875388] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[  113.875392] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[  113.925357] [drm:gen7_enable_fbc] enabled fbc on plane A
>[  113.990466] [drm:gen8_irq_handler] *ERROR* Pipe A FIFO underrun
>[  114.190751] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[  114.224067] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[  114.241113] [drm:drm_mode_setcrtc] [CRTC:5]
>[  114.241118] [drm:drm_mode_setcrtc] [CONNECTOR:14:eDP-1]
>[  114.241121] [drm:intel_crtc_set_config] [CRTC:5] [FB:29] #connectors=1 (x y) (0 0)
>[  114.241124] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=0, fb_changed=1
>[  114.241127] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[  114.250586] [drm:ironlake_update_primary_plane] Writing base 0107C000 00000000 0 0 8192
>[  114.258100] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[  114.258102] [drm:intel_update_fbc] disabling active FBC for update
>[  114.258105] [drm:ironlake_disable_fbc] disabled FBC
>[  114.258107] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[  114.308068] [drm:gen7_enable_fbc] enabled fbc on plane A
>[  114.573785] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[  114.607104] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[  114.624872] [drm:ironlake_disable_fbc] disabled FBC
>[  114.640401] [drm:i915_setup_compression] reserved 16777216 bytes of contiguous stolen space for FBC
>[  114.657051] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[  114.673722] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[  114.689784] [drm:gen7_enable_fbc] enabled fbc on plane A
>[  114.990634] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[  115.023451] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[  115.040628] [drm:intel_crtc_cursor_set] cursor off
>[  115.040632] [drm:intel_crtc_set_config] [CRTC:5] [FB:28] #connectors=1 (x y) (0 0)
>[  115.040635] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=0, fb_changed=1
>[  115.040636] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[  115.040641] [drm:ironlake_update_primary_plane] Writing base 00880000 00000000 0 0 7680
>[  115.058499] [drm:intel_update_fbc] framebuffer not tiled or fenced, disabling compression
>[  115.058500] [drm:intel_update_fbc] unsupported config, disabling FBC
>[  115.058502] [drm:ironlake_disable_fbc] disabled FBC
>[  115.058503] [drm:intel_edp_psr_match_conditions] PSR disable by flag
>[  115.058506] [drm:intel_crtc_cursor_set] cursor off
>[  115.058507] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  115.058509] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  115.058511] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[  115.058513] [drm:intel_crtc_cursor_set] cursor off
>[  115.058514] [drm:intel_crtc_set_config] [CRTC:11] [NOFB]
>[  115.058516] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:11], mode_changed=0, fb_changed=0
>[  115.058517] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[  115.067983] [drm:intel_crtc_cursor_set] cursor off
>[  115.067987] [drm:intel_crtc_set_config] [CRTC:5] [FB:28] #connectors=1 (x y) (0 0)
>[  115.067991] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=0, fb_changed=0
>[  115.067994] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[  115.067997] [drm:intel_crtc_cursor_set] cursor off
>[  115.067998] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  115.068001] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  115.068003] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[  115.068005] [drm:intel_crtc_cursor_set] cursor off
>[  115.068007] [drm:intel_crtc_set_config] [CRTC:11] [NOFB]
>[  115.068009] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:11], mode_changed=0, fb_changed=0
>[  115.068011] [drm:intel_modeset_stage_output_state] [CONNECTOR:14:eDP-1] to [CRTC:5]
>[  116.824183] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[  116.824193] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  123.756758] usb 1-2: USB disconnect, device number 5
>[  125.271846] usb 1-2: new low-speed USB device number 6 using xhci_hcd
>[  125.438937] usb 1-2: New USB device found, idVendor=046d, idProduct=c06a
>[  125.438982] usb 1-2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
>[  125.439031] usb 1-2: Product: USB Optical Mouse
>[  125.439061] usb 1-2: Manufacturer: Logitech
>[  125.439193] usb 1-2: ep 0x81 - rounding interval to 64 microframes, ep desc says 80 microframes
>[  125.441287] input: Logitech USB Optical Mouse as /devices/pci0000:00/0000:00:14.0/usb1/1-2/1-2:1.0/0003:046D:C06A.0004/input/input10
>[  125.441658] hid-generic 0003:046D:C06A.0004: input,hidraw1: USB HID v1.11 Mouse [Logitech USB Optical Mouse] on usb-0000:00:14.0-2/input0

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Attachments on bug 78419: 98660

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