Attachment 98788 Details for Bug 77587 – Use MMIO for PDPs

[patch] Use MMIO for PDPs

0001-drm-i915-bdw-Use-MMIO-for-loading-PDPs.patch (text/plain), 2.38 KB, created by Ben Widawsky on 2014-05-09 22:33:26 UTC

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Creator: Ben Widawsky

Created: 2014-05-09 22:33:26 UTC

Size: 2.38 KB

patch

obsolete

>From 17ef4e5850c6fc48a3af2ca89aea19fec7298ace Mon Sep 17 00:00:00 2001
>From: Ben Widawsky <benjamin.widawsky@intel.com>
>Date: Fri, 9 May 2014 15:09:26 -0700
>Subject: [PATCH] drm/i915/bdw: Use MMIO for loading PDPs
>
>This is a partial-functional backport of:
>commit eeb9488e751a0a6401e7516a893efaf9d1f77fb5
>Author: Ben Widawsky <ben@bwidawsk.net>
>Date:   Fri Dec 6 14:11:10 2013 -0800
>
>    drm/i915: Extract mm switching to function
>
>In that commit, the new mm switching function introduced the ability to
>either load the page tables via the ring, or via MMIO. The issue we have
>is during reset, we do not have the ability to use the rings. Trying to
>do so will fail, and prevent our Aliasing PPGTT from coming back. In
>current upstream, we use the MMIO on reset, and LRI for everything else.
>
>Here however, we always use the MMIO (in spite of what docs say, I've
>used this for a long time, and it's never *not* worked.). During
>development, we were using MMIO, and it was changed toward the end on
>code review. We do not have enough of the other code in place to be as
>smart as we are for current upstream.
>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77587
>Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
>---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>index 04bdc29..25d56dc 100644
>--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>@@ -213,12 +213,20 @@ static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
> 
> /* Broadwell Page Directory Pointer Descriptors */
> static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
>-			   uint64_t val)
>+			  uint64_t val, bool synchronous)
> {
>+	struct drm_i915_private *dev_priv = ring->dev->dev_private;
> 	int ret;
> 
> 	BUG_ON(entry >= 4);
> 
>+	if (synchronous) {
>+		I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
>+		I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
>+		return 0;
>+	}
>+
>+
> 	ret = intel_ring_begin(ring, 6);
> 	if (ret)
> 		return ret;
>@@ -252,7 +260,7 @@ static int gen8_ppgtt_enable(struct drm_device *dev)
> 	for (i = used_pd - 1; i >= 0; i--) {
> 		dma_addr_t addr = ppgtt->pd_dma_addr[i];
> 		for_each_ring(ring, dev_priv, j) {
>-			ret = gen8_write_pdp(ring, i, addr);
>+			ret = gen8_write_pdp(ring, i, addr, true);
> 			if (ret)
> 				goto err_out;
> 		}
>-- 
>1.9.2
>

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Attachments on bug 77587: 97527 | 98788

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