Attachment 100923 Details for Bug 78439 – dmesg (3.16) with debug info

dmesg (3.16) with debug info

dmesg (text/plain), 249.72 KB, created by Andrius Štikonas on 2014-06-12 14:59:38 UTC

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Creator: Andrius Štikonas

Created: 2014-06-12 14:59:38 UTC

Size: 249.72 KB

patch

obsolete

>[  103.342514] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.342521] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.342526] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.342534] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.342550] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.342554] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.342558] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.342561] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.342701] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.342710] nouveau T[   VBIOS][0000:02:00.0] 0xbddb[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00001000
>[  103.342718] nouveau T[   VBIOS][0000:02:00.0] 0xbde8[0]: AUXCH	AUX[0x00000102] 0x01
>[  103.342723] nouveau T[   VBIOS][0000:02:00.0] 0xbdee[0]: 	AUX[0x00000102] &= 0xdf |= 0x00
>[  103.342727] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.342880] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.342887] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817720
>[  103.342893] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.342899] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.342905] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.342914] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.342931] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.342934] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.342938] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.342941] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.343082] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.343089] nouveau T[   VBIOS][0000:02:00.0] 0xbdf0[0]: DONE
>[  103.343093] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training complete
>[  103.394698] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: HPD: 4
>[  103.394733] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000100 2
>[  103.394897] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  103.394904] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0000840a
>[  103.394911] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.394918] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.394924] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.394933] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 3
>[  103.395100] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  103.395103] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.395107] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.395111] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.395116] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.395120] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: no inter-lane alignment
>[  103.395126] nouveau T[   VBIOS][0000:02:00.0] 0xc000[0]: SUB_DIRECT	0xbd11
>[  103.395128] nouveau T[   VBIOS][0000:02:00.0] 0xbd11[1]: NV_REG	R[0x00e800] &= 0xfffffeff |= 0x00000100
>[  103.395133] nouveau T[   VBIOS][0000:02:00.0] 0xbd1e[1]: NV_REG	R[0x00e820] &= 0xfffffeff |= 0x00000100
>[  103.395138] nouveau T[   VBIOS][0000:02:00.0] 0xbd2b[1]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[  103.395143] nouveau T[   VBIOS][0000:02:00.0] 0xbd38[1]: NV_REG	R[0x6061c128] &= 0x7fffffff |= 0x80000000
>[  103.395148] nouveau T[   VBIOS][0000:02:00.0] 0xbd45[1]: NV_REG	R[0x40614300] &= 0xfcffffff |= 0x03000000
>[  103.395152] nouveau T[   VBIOS][0000:02:00.0] 0xbd52[1]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.395154] nouveau T[   VBIOS][0000:02:00.0] 0xbd5b[1]: ZM_REG	R[0x4061c010] = 0x0060152f
>[  103.395156] nouveau T[   VBIOS][0000:02:00.0] 0xbd64[1]: ZM_REG	R[0x4061c014] = 0x00020000
>[  103.395158] nouveau T[   VBIOS][0000:02:00.0] 0xbd6d[1]: SUB_DIRECT	0x4860
>[  103.395160] nouveau T[   VBIOS][0000:02:00.0] 0x4860[2]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[  103.395164] nouveau T[   VBIOS][0000:02:00.0] 0x486d[2]: TIME	0x0064
>[  103.395266] nouveau T[   VBIOS][0000:02:00.0] 0x4870[2]: CONDITION	0x06
>[  103.395269] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.395274] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[  103.395278] nouveau T[   VBIOS][0000:02:00.0] 0x487f[2]: RESUME
>[  103.395280] nouveau T[   VBIOS][0000:02:00.0] 0x4880[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[  103.395285] nouveau T[   VBIOS][0000:02:00.0] 0x488d[2]: TIME	0x0064
>[  103.395386] nouveau T[   VBIOS][0000:02:00.0] 0x4890[2]: CONDITION	0x06
>[  103.395389] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.395393] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[  103.395398] nouveau T[   VBIOS][0000:02:00.0] 0x489f[2]: RESUME
>[  103.395400] nouveau T[   VBIOS][0000:02:00.0] 0x48a0[2]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[  103.395404] nouveau T[   VBIOS][0000:02:00.0] 0x48ad[2]: TIME	0x0064
>[  103.395506] nouveau T[   VBIOS][0000:02:00.0] 0x48b0[2]: CONDITION	0x06
>[  103.395508] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.395513] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[ ]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[  103.395514] nouveau T[   VBIOS][0000:02:00.0] 0x48bf[ ]: RESUME
>[  103.395516] nouveau T[   VBIOS][0000:02:00.0] 0x48c0[2]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[  103.395520] nouveau T[   VBIOS][0000:02:00.0] 0x48cd[2]: TIME	0x0064
>[  103.395622] nouveau T[   VBIOS][0000:02:00.0] 0x48d0[2]: CONDITION	0x06
>[  103.395625] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.395629] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[ ]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[  103.395631] nouveau T[   VBIOS][0000:02:00.0] 0x48df[ ]: RESUME
>[  103.395632] nouveau T[   VBIOS][0000:02:00.0] 0x48e0[2]: DONE
>[  103.395634] nouveau T[   VBIOS][0000:02:00.0] 0xbd70[1]: NV_REG	R[0x40614300] &= 0xfffcffff |= 0x00010000
>[  103.395639] nouveau T[   VBIOS][0000:02:00.0] 0xbd7d[1]: TIME	0x0032
>[  103.395691] nouveau T[   VBIOS][0000:02:00.0] 0xbd80[1]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[  103.395696] nouveau T[   VBIOS][0000:02:00.0] 0xbd8d[1]: NV_REG	R[0x4061c034] &= 0x7feeffff |= 0x80000000
>[  103.395700] nouveau T[   VBIOS][0000:02:00.0] 0xbd9a[1]: TIME	0x000a
>[  103.395712] nouveau T[   VBIOS][0000:02:00.0] 0xbd9d[1]: CONDITION_TIME	0x15 0xff
>[  103.395714] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: 	[0x15] (R[0x4061c034] & 0x80000000) == 0x00000000
>[  103.395719] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[  103.395724] nouveau T[   VBIOS][0000:02:00.0] 0xbdad[1]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00000000
>[  103.395727] nouveau T[   VBIOS][0000:02:00.0] 0xbdba[1]: AUXCH	AUX[0x00000102] 0x01
>[  103.395729] nouveau T[   VBIOS][0000:02:00.0] 0xbdc0[1]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[  103.395731] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.395883] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.395885] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.395889] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.395893] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.395897] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.395902] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.395915] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.395916] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.395918] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.395919] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.396058] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.396061] nouveau T[   VBIOS][0000:02:00.0] 0xbdc2[1]: DP_CONDITION	0x05 0x15
>[  103.396063] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x0000000d 1
>[  103.396211] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.396214] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.396217] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.396222] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.396226] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.396231] nouveau T[   VBIOS][0000:02:00.0] 0xbdc5[ ]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[  103.396233] nouveau T[   VBIOS][0000:02:00.0] 0xbdd2[ ]: AUXCH	AUX[0x0000010a] 0x01
>[  103.396235] nouveau T[   VBIOS][0000:02:00.0] 0xbdd8[ ]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[  103.396237] nouveau T[   VBIOS][0000:02:00.0] 0xbdda[ ]: DONE
>[  103.396239] nouveau T[   VBIOS][0000:02:00.0] 0xc003[ ]: DP_CONDITION	0x00 0x08
>[  103.396241] nouveau T[   VBIOS][0000:02:00.0] 0xc006[ ]: SUB_DIRECT	0xc2a1
>[  103.396243] nouveau T[   VBIOS][0000:02:00.0] 0xc009[ ]: NOT
>[  103.396245] nouveau T[   VBIOS][0000:02:00.0] 0xc00a[0]: SUB_DIRECT	0xc2a1
>[  103.396247] nouveau T[   VBIOS][0000:02:00.0] 0xc2a1[1]: DONE
>[  103.396248] nouveau T[   VBIOS][0000:02:00.0] 0xc00d[0]: RESUME
>[  103.396250] nouveau T[   VBIOS][0000:02:00.0] 0xc00e[0]: DONE
>[  103.396252] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: 4 lanes at 270000 KB/s
>[  103.396254] nouveau T[   VBIOS][0000:02:00.0] 0xbdf1[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.396255] nouveau T[   VBIOS][0000:02:00.0] 0xbdfa[0]: DONE
>[  103.396279] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000100 2
>[  103.396293] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x0000840a
>[  103.396295] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.396297] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.396298] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.396444] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  103.396447] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 1
>[  103.396450] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.396601] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.396603] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000020
>[  103.396607] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.396611] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.396616] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.396621] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.396636] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000021
>[  103.396638] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.396639] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.396641] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.396778] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.396783] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 00 00
>[  103.396794] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 00 00
>[  103.396805] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 00 00
>[  103.396815] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 00 00
>[  103.396825] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.396838] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.396840] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.396841] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.396843] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.397003] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.397106] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.397299] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.397304] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801111
>[  103.397310] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  103.397315] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.397319] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.397325] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 11 11 80 00 00 00
>[  103.397328] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 2
>[  103.397333] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.397485] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.397490] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801121
>[  103.397495] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  103.397500] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.397504] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.397509] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.397524] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000022
>[  103.397527] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.397531] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.397534] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.397675] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.398080] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.398269] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.398271] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01811777
>[  103.398275] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.398279] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.398283] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.398288] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 17 81 01 88 88
>[  103.398290] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 10 00
>[  103.398301] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 10 00
>[  103.398311] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 10 00
>[  103.398321] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 10 00
>[  103.398331] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.398344] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x10101010
>[  103.398345] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.398347] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.398348] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.398509] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.398912] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.399106] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.399108] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817777
>[  103.399112] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.399116] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.399121] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.399125] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 77 81 01 88 88
>[  103.399127] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 10 00
>[  103.399137] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 10 00
>[  103.399148] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 10 00
>[  103.399158] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 10 00
>[  103.399168] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.399181] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x10101010
>[  103.399183] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.399185] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.399186] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.399347] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.399350] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 0
>[  103.399352] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.399502] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.399504] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817722
>[  103.399508] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.399513] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.399517] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.399522] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.399535] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.399537] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.399538] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.399540] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.399678] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.399682] nouveau T[   VBIOS][0000:02:00.0] 0xbddb[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00001000
>[  103.399687] nouveau T[   VBIOS][0000:02:00.0] 0xbde8[0]: AUXCH	AUX[0x00000102] 0x01
>[  103.399689] nouveau T[   VBIOS][0000:02:00.0] 0xbdee[0]: 	AUX[0x00000102] &= 0xdf |= 0x00
>[  103.399691] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.399843] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.399846] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817720
>[  103.399850] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.399854] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.399858] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.399863] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.399876] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.399877] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.399879] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.399880] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.400018] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.400023] nouveau T[   VBIOS][0000:02:00.0] 0xbdf0[0]: DONE
>[  103.400024] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training complete
>[  103.454877] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: HPD: 4
>[  103.454918] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000100 2
>[  103.455085] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  103.455093] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0000840a
>[  103.455100] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.455107] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.455114] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.455122] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 3
>[  103.455295] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  103.455303] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.455310] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.455317] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.455324] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.455331] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: no inter-lane alignment
>[  103.455345] nouveau T[   VBIOS][0000:02:00.0] 0xc000[0]: SUB_DIRECT	0xbd11
>[  103.455351] nouveau T[   VBIOS][0000:02:00.0] 0xbd11[1]: NV_REG	R[0x00e800] &= 0xfffffeff |= 0x00000100
>[  103.455360] nouveau T[   VBIOS][0000:02:00.0] 0xbd1e[1]: NV_REG	R[0x00e820] &= 0xfffffeff |= 0x00000100
>[  103.455369] nouveau T[   VBIOS][0000:02:00.0] 0xbd2b[1]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[  103.455378] nouveau T[   VBIOS][0000:02:00.0] 0xbd38[1]: NV_REG	R[0x6061c128] &= 0x7fffffff |= 0x80000000
>[  103.455386] nouveau T[   VBIOS][0000:02:00.0] 0xbd45[1]: NV_REG	R[0x40614300] &= 0xfcffffff |= 0x03000000
>[  103.455394] nouveau T[   VBIOS][0000:02:00.0] 0xbd52[1]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.455399] nouveau T[   VBIOS][0000:02:00.0] 0xbd5b[1]: ZM_REG	R[0x4061c010] = 0x0060152f
>[  103.455404] nouveau T[   VBIOS][0000:02:00.0] 0xbd64[1]: ZM_REG	R[0x4061c014] = 0x00020000
>[  103.455409] nouveau T[   VBIOS][0000:02:00.0] 0xbd6d[1]: SUB_DIRECT	0x4860
>[  103.455415] nouveau T[   VBIOS][0000:02:00.0] 0x4860[2]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[  103.455423] nouveau T[   VBIOS][0000:02:00.0] 0x486d[2]: TIME	0x0064
>[  103.455529] nouveau T[   VBIOS][0000:02:00.0] 0x4870[2]: CONDITION	0x06
>[  103.455536] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.455546] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[  103.455554] nouveau T[   VBIOS][0000:02:00.0] 0x487f[2]: RESUME
>[  103.455559] nouveau T[   VBIOS][0000:02:00.0] 0x4880[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[  103.455567] nouveau T[   VBIOS][0000:02:00.0] 0x488d[2]: TIME	0x0064
>[  103.455673] nouveau T[   VBIOS][0000:02:00.0] 0x4890[2]: CONDITION	0x06
>[  103.455680] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.455688] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[  103.455696] nouveau T[   VBIOS][0000:02:00.0] 0x489f[2]: RESUME
>[  103.455701] nouveau T[   VBIOS][0000:02:00.0] 0x48a0[2]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[  103.455709] nouveau T[   VBIOS][0000:02:00.0] 0x48ad[2]: TIME	0x0064
>[  103.455814] nouveau T[   VBIOS][0000:02:00.0] 0x48b0[2]: CONDITION	0x06
>[  103.455821] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.455830] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[ ]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[  103.455835] nouveau T[   VBIOS][0000:02:00.0] 0x48bf[ ]: RESUME
>[  103.455842] nouveau T[   VBIOS][0000:02:00.0] 0x48c0[2]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[  103.455850] nouveau T[   VBIOS][0000:02:00.0] 0x48cd[2]: TIME	0x0064
>[  103.455956] nouveau T[   VBIOS][0000:02:00.0] 0x48d0[2]: CONDITION	0x06
>[  103.455963] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.455972] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[ ]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[  103.455976] nouveau T[   VBIOS][0000:02:00.0] 0x48df[ ]: RESUME
>[  103.455981] nouveau T[   VBIOS][0000:02:00.0] 0x48e0[2]: DONE
>[  103.455987] nouveau T[   VBIOS][0000:02:00.0] 0xbd70[1]: NV_REG	R[0x40614300] &= 0xfffcffff |= 0x00010000
>[  103.455994] nouveau T[   VBIOS][0000:02:00.0] 0xbd7d[1]: TIME	0x0032
>[  103.456050] nouveau T[   VBIOS][0000:02:00.0] 0xbd80[1]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[  103.456059] nouveau T[   VBIOS][0000:02:00.0] 0xbd8d[1]: NV_REG	R[0x4061c034] &= 0x7feeffff |= 0x80000000
>[  103.456067] nouveau T[   VBIOS][0000:02:00.0] 0xbd9a[1]: TIME	0x000a
>[  103.456083] nouveau T[   VBIOS][0000:02:00.0] 0xbd9d[1]: CONDITION_TIME	0x15 0xff
>[  103.456090] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: 	[0x15] (R[0x4061c034] & 0x80000000) == 0x00000000
>[  103.456099] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[  103.456107] nouveau T[   VBIOS][0000:02:00.0] 0xbdad[1]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00000000
>[  103.456116] nouveau T[   VBIOS][0000:02:00.0] 0xbdba[1]: AUXCH	AUX[0x00000102] 0x01
>[  103.456122] nouveau T[   VBIOS][0000:02:00.0] 0xbdc0[1]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[  103.456128] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.456285] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.456293] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.456300] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.456307] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.456314] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.456323] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.456340] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.456344] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.456349] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.456353] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.456494] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.456504] nouveau T[   VBIOS][0000:02:00.0] 0xbdc2[1]: DP_CONDITION	0x05 0x15
>[  103.456509] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x0000000d 1
>[  103.456663] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.456671] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.456678] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.456684] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.456691] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.456701] nouveau T[   VBIOS][0000:02:00.0] 0xbdc5[ ]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[  103.456706] nouveau T[   VBIOS][0000:02:00.0] 0xbdd2[ ]: AUXCH	AUX[0x0000010a] 0x01
>[  103.456713] nouveau T[   VBIOS][0000:02:00.0] 0xbdd8[ ]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[  103.456718] nouveau T[   VBIOS][0000:02:00.0] 0xbdda[ ]: DONE
>[  103.456723] nouveau T[   VBIOS][0000:02:00.0] 0xc003[ ]: DP_CONDITION	0x00 0x08
>[  103.456728] nouveau T[   VBIOS][0000:02:00.0] 0xc006[ ]: SUB_DIRECT	0xc2a1
>[  103.456733] nouveau T[   VBIOS][0000:02:00.0] 0xc009[ ]: NOT
>[  103.456737] nouveau T[   VBIOS][0000:02:00.0] 0xc00a[0]: SUB_DIRECT	0xc2a1
>[  103.456742] nouveau T[   VBIOS][0000:02:00.0] 0xc2a1[1]: DONE
>[  103.456746] nouveau T[   VBIOS][0000:02:00.0] 0xc00d[0]: RESUME
>[  103.456750] nouveau T[   VBIOS][0000:02:00.0] 0xc00e[0]: DONE
>[  103.456756] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: 4 lanes at 270000 KB/s
>[  103.456762] nouveau T[   VBIOS][0000:02:00.0] 0xbdf1[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.456767] nouveau T[   VBIOS][0000:02:00.0] 0xbdfa[0]: DONE
>[  103.456797] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000100 2
>[  103.456815] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x0000840a
>[  103.456821] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.456825] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.456829] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.456981] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  103.456990] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 1
>[  103.456998] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.457151] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.457160] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000020
>[  103.457167] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.457174] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.457181] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.457189] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.457206] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000021
>[  103.457210] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.457215] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.457219] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.457365] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.457375] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 00 00
>[  103.457392] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 00 00
>[  103.457408] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 00 00
>[  103.457423] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 00 00
>[  103.457439] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.457457] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.457462] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.457466] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.457471] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.457638] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.457748] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.457944] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.457952] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801111
>[  103.457959] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  103.457966] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.457973] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.457982] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 11 11 80 00 00 00
>[  103.457987] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 2
>[  103.457995] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.458152] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.458160] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801121
>[  103.458167] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  103.458174] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.458180] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.458188] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.458206] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000022
>[  103.458210] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.458215] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.458219] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.458361] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.458771] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.458968] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.458976] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817777
>[  103.458983] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30324444
>[  103.458990] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.458997] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.459006] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 77 81 01 44 44
>[  103.459011] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 08 00
>[  103.459028] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 08 00
>[  103.459044] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 08 00
>[  103.459060] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 08 00
>[  103.459075] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.459094] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x08080808
>[  103.459098] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.459102] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.459107] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.459274] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.459284] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 0
>[  103.459292] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.459448] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.459456] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817722
>[  103.459463] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30324444
>[  103.459470] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.459477] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.459485] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.459503] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.459509] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.459513] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.459517] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.459661] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.459671] nouveau T[   VBIOS][0000:02:00.0] 0xbddb[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00001000
>[  103.459679] nouveau T[   VBIOS][0000:02:00.0] 0xbde8[0]: AUXCH	AUX[0x00000102] 0x01
>[  103.459685] nouveau T[   VBIOS][0000:02:00.0] 0xbdee[0]: 	AUX[0x00000102] &= 0xdf |= 0x00
>[  103.459691] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.459847] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.459855] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817720
>[  103.459863] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30324444
>[  103.459870] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.459877] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.459885] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.459903] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.459908] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.459912] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.459917] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.460057] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.460066] nouveau T[   VBIOS][0000:02:00.0] 0xbdf0[0]: DONE
>[  103.460071] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training complete
>[  103.511850] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: HPD: 4
>[  103.511891] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000100 2
>[  103.512061] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  103.512072] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0000840a
>[  103.512082] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.512092] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.512101] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.512114] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 3
>[  103.512289] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  103.512299] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.512309] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.512318] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.512328] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.512339] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: no inter-lane alignment
>[  103.512359] nouveau T[   VBIOS][0000:02:00.0] 0xc000[0]: SUB_DIRECT	0xbd11
>[  103.512369] nouveau T[   VBIOS][0000:02:00.0] 0xbd11[1]: NV_REG	R[0x00e800] &= 0xfffffeff |= 0x00000100
>[  103.512381] nouveau T[   VBIOS][0000:02:00.0] 0xbd1e[1]: NV_REG	R[0x00e820] &= 0xfffffeff |= 0x00000100
>[  103.512394] nouveau T[   VBIOS][0000:02:00.0] 0xbd2b[1]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[  103.512407] nouveau T[   VBIOS][0000:02:00.0] 0xbd38[1]: NV_REG	R[0x6061c128] &= 0x7fffffff |= 0x80000000
>[  103.512419] nouveau T[   VBIOS][0000:02:00.0] 0xbd45[1]: NV_REG	R[0x40614300] &= 0xfcffffff |= 0x03000000
>[  103.512431] nouveau T[   VBIOS][0000:02:00.0] 0xbd52[1]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.512440] nouveau T[   VBIOS][0000:02:00.0] 0xbd5b[1]: ZM_REG	R[0x4061c010] = 0x0060152f
>[  103.512449] nouveau T[   VBIOS][0000:02:00.0] 0xbd64[1]: ZM_REG	R[0x4061c014] = 0x00020000
>[  103.512457] nouveau T[   VBIOS][0000:02:00.0] 0xbd6d[1]: SUB_DIRECT	0x4860
>[  103.512466] nouveau T[   VBIOS][0000:02:00.0] 0x4860[2]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[  103.512476] nouveau T[   VBIOS][0000:02:00.0] 0x486d[2]: TIME	0x0064
>[  103.512586] nouveau T[   VBIOS][0000:02:00.0] 0x4870[2]: CONDITION	0x06
>[  103.512598] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.512611] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[  103.512622] nouveau T[   VBIOS][0000:02:00.0] 0x487f[2]: RESUME
>[  103.512631] nouveau T[   VBIOS][0000:02:00.0] 0x4880[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[  103.512641] nouveau T[   VBIOS][0000:02:00.0] 0x488d[2]: TIME	0x0064
>[  103.512749] nouveau T[   VBIOS][0000:02:00.0] 0x4890[2]: CONDITION	0x06
>[  103.512760] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.512773] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[  103.512783] nouveau T[   VBIOS][0000:02:00.0] 0x489f[2]: RESUME
>[  103.512792] nouveau T[   VBIOS][0000:02:00.0] 0x48a0[2]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[  103.512802] nouveau T[   VBIOS][0000:02:00.0] 0x48ad[2]: TIME	0x0064
>[  103.512911] nouveau T[   VBIOS][0000:02:00.0] 0x48b0[2]: CONDITION	0x06
>[  103.512922] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.512934] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[ ]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[  103.512941] nouveau T[   VBIOS][0000:02:00.0] 0x48bf[ ]: RESUME
>[  103.512950] nouveau T[   VBIOS][0000:02:00.0] 0x48c0[2]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[  103.512961] nouveau T[   VBIOS][0000:02:00.0] 0x48cd[2]: TIME	0x0064
>[  103.513069] nouveau T[   VBIOS][0000:02:00.0] 0x48d0[2]: CONDITION	0x06
>[  103.513080] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.513093] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[ ]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[  103.513100] nouveau T[   VBIOS][0000:02:00.0] 0x48df[ ]: RESUME
>[  103.513107] nouveau T[   VBIOS][0000:02:00.0] 0x48e0[2]: DONE
>[  103.513116] nouveau T[   VBIOS][0000:02:00.0] 0xbd70[1]: NV_REG	R[0x40614300] &= 0xfffcffff |= 0x00010000
>[  103.513127] nouveau T[   VBIOS][0000:02:00.0] 0xbd7d[1]: TIME	0x0032
>[  103.513186] nouveau T[   VBIOS][0000:02:00.0] 0xbd80[1]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[  103.513199] nouveau T[   VBIOS][0000:02:00.0] 0xbd8d[1]: NV_REG	R[0x4061c034] &= 0x7feeffff |= 0x80000000
>[  103.513210] nouveau T[   VBIOS][0000:02:00.0] 0xbd9a[1]: TIME	0x000a
>[  103.513229] nouveau T[   VBIOS][0000:02:00.0] 0xbd9d[1]: CONDITION_TIME	0x15 0xff
>[  103.513241] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: 	[0x15] (R[0x4061c034] & 0x80000000) == 0x00000000
>[  103.513253] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[  103.513265] nouveau T[   VBIOS][0000:02:00.0] 0xbdad[1]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00000000
>[  103.513277] nouveau T[   VBIOS][0000:02:00.0] 0xbdba[1]: AUXCH	AUX[0x00000102] 0x01
>[  103.513286] nouveau T[   VBIOS][0000:02:00.0] 0xbdc0[1]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[  103.513295] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.513452] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.513462] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.513471] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.513481] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.513490] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.513501] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.513523] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.513532] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.513539] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.513546] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.513690] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.513703] nouveau T[   VBIOS][0000:02:00.0] 0xbdc2[1]: DP_CONDITION	0x05 0x15
>[  103.513712] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x0000000d 1
>[  103.513869] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.513880] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.513889] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.513899] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.513908] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.513920] nouveau T[   VBIOS][0000:02:00.0] 0xbdc5[ ]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[  103.513929] nouveau T[   VBIOS][0000:02:00.0] 0xbdd2[ ]: AUXCH	AUX[0x0000010a] 0x01
>[  103.513938] nouveau T[   VBIOS][0000:02:00.0] 0xbdd8[ ]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[  103.513946] nouveau T[   VBIOS][0000:02:00.0] 0xbdda[ ]: DONE
>[  103.513954] nouveau T[   VBIOS][0000:02:00.0] 0xc003[ ]: DP_CONDITION	0x00 0x08
>[  103.513962] nouveau T[   VBIOS][0000:02:00.0] 0xc006[ ]: SUB_DIRECT	0xc2a1
>[  103.513969] nouveau T[   VBIOS][0000:02:00.0] 0xc009[ ]: NOT
>[  103.513976] nouveau T[   VBIOS][0000:02:00.0] 0xc00a[0]: SUB_DIRECT	0xc2a1
>[  103.513983] nouveau T[   VBIOS][0000:02:00.0] 0xc2a1[1]: DONE
>[  103.513990] nouveau T[   VBIOS][0000:02:00.0] 0xc00d[0]: RESUME
>[  103.513996] nouveau T[   VBIOS][0000:02:00.0] 0xc00e[0]: DONE
>[  103.514005] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: 4 lanes at 270000 KB/s
>[  103.514014] nouveau T[   VBIOS][0000:02:00.0] 0xbdf1[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.514021] nouveau T[   VBIOS][0000:02:00.0] 0xbdfa[0]: DONE
>[  103.514059] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000100 2
>[  103.514079] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x0000840a
>[  103.514086] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.514092] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.514099] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.514279] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  103.514292] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 1
>[  103.514303] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.514461] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.514472] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000020
>[  103.514481] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.514491] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.514500] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.514511] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.514531] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000021
>[  103.514538] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.514544] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.514554] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.514702] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.514716] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 00 00
>[  103.514739] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 00 00
>[  103.514760] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 00 00
>[  103.514780] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 00 00
>[  103.514799] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.514820] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.514827] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.514834] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.514841] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.515010] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.515124] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.515325] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.515336] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801111
>[  103.515346] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  103.515356] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.515365] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.515377] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 11 11 80 00 00 00
>[  103.515385] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 2
>[  103.515396] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.515553] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.515564] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801121
>[  103.515574] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  103.515583] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.515593] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.515604] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.515625] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000022
>[  103.515633] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.515640] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.515646] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.515795] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.516209] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.516411] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.516422] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01811777
>[  103.516432] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.516441] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.516450] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.516461] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 17 81 01 88 88
>[  103.516471] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 10 00
>[  103.516492] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 10 00
>[  103.516513] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 10 00
>[  103.516534] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 10 00
>[  103.516555] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.516575] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x10101010
>[  103.516582] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.516589] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.516596] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.516765] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.517178] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.517380] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.517390] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817777
>[  103.517399] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.517409] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.517418] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.517429] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 77 81 01 88 88
>[  103.517438] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 10 00
>[  103.517461] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 10 00
>[  103.517482] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 10 00
>[  103.517506] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 10 00
>[  103.517526] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.517547] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x10101010
>[  103.517553] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.517560] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.517567] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.517738] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.517750] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 0
>[  103.517761] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.517920] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.517931] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817722
>[  103.517943] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.517952] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.517962] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.517973] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.517994] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.518001] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.518008] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.518015] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.518160] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.518174] nouveau T[   VBIOS][0000:02:00.0] 0xbddb[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00001000
>[  103.518186] nouveau T[   VBIOS][0000:02:00.0] 0xbde8[0]: AUXCH	AUX[0x00000102] 0x01
>[  103.518195] nouveau T[   VBIOS][0000:02:00.0] 0xbdee[0]: 	AUX[0x00000102] &= 0xdf |= 0x00
>[  103.518204] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.518362] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.518372] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817720
>[  103.518382] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.518391] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.518401] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.518412] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.518432] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.518441] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.518448] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.518455] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.518603] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.518614] nouveau T[   VBIOS][0000:02:00.0] 0xbdf0[0]: DONE
>[  103.518622] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training complete
>[  103.569596] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: HPD: 2
>[  103.569622] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000000 16
>[  103.569640] nouveau D[     I2C][0000:02:00.0] AUXCH(1): sink not detected
>[  103.569648] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: aux power -> demand
>[  103.569655] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> NULL
>[  103.569668] nouveau D[     DRM] unplugged DP-1
>[  103.569720] nouveau D[     I2C][0000:02:00.0] PAD:S:00: -> PORT:06
>[  103.569858] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: HPD: 1
>[  103.570827] nouveau D[     I2C][0000:02:00.0] PAD:S:00: -> NULL
>[  103.570841] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> PORT:0b
>[  103.570846] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000000 8
>[  103.571057] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[  103.571064] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01840a11
>[  103.571071] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.571078] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.571084] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.571094] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> NULL
>[  103.571099] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[  103.571102] nouveau D[     DRM] encoder: 4x270000
>[  103.571106] nouveau D[     DRM] maximum: 4x270000
>[  103.571117] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> PORT:0b
>[  103.571122] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 4: 0x00000050 1
>[  103.571140] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.571144] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.571148] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.571152] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.571295] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  103.571302] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 1: 0x00000050 1
>[  103.571456] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[  103.571463] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01840a00
>[  103.571469] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.571476] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.571483] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.571493] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> NULL
>[  103.571504] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> PORT:0b
>[  103.571509] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 4: 0x00000050 1
>[  103.571526] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.571530] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.571534] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.571538] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.571679] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  103.571687] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.571966] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.571973] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xffffff00
>[  103.571980] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00ffffff
>[  103.571986] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x2846f022
>[  103.571993] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.572001] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.572280] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.572287] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x04011520
>[  103.572293] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x781a29a5
>[  103.572300] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xa4c53726
>[  103.572307] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x259b4c55
>[  103.572314] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.572597] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.572604] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xa1545012
>[  103.572611] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x40810008
>[  103.572618] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01018081
>[  103.572624] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01010101
>[  103.572632] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.572915] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.572922] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01010101
>[  103.572929] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x299a0101
>[  103.572935] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x8451d0a0
>[  103.572942] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x98503022
>[  103.572950] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.573233] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.573240] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xff980036
>[  103.573246] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x1c000010
>[  103.573253] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xfd000000
>[  103.573259] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x184c3200
>[  103.573267] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.573547] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.573553] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a010e53
>[  103.573560] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20202020
>[  103.573567] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00002020
>[  103.573574] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x4c00fc00
>[  103.573581] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.573860] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.573867] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30393141
>[  103.573873] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20200a35
>[  103.573880] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20202020
>[  103.573887] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xff000000
>[  103.573894] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 1: 0x00000050 16
>[  103.574180] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[  103.574191] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x434e4300
>[  103.574200] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30323331
>[  103.574209] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.574217] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.574230] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> NULL
>[  103.574249] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> PORT:0b
>[  103.574258] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000000 16
>[  103.574539] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110900f 0x10000010
>[  103.574550] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01840a11
>[  103.574560] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.574570] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.574579] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.574591] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: aux power -> always
>[  103.574599] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000100 2
>[  103.574767] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  103.574778] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0184840a
>[  103.574788] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.574798] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.574807] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.574818] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 3
>[  103.574995] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  103.575006] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01800000
>[  103.575015] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.575024] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.575033] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.575044] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: no inter-lane alignment
>[  103.575082] nouveau T[   VBIOS][0000:02:00.0] 0xc000[0]: SUB_DIRECT	0xbd11
>[  103.575093] nouveau T[   VBIOS][0000:02:00.0] 0xbd11[1]: NV_REG	R[0x00e800] &= 0xfffffeff |= 0x00000100
>[  103.575104] nouveau T[   VBIOS][0000:02:00.0] 0xbd1e[1]: NV_REG	R[0x00e820] &= 0xfffffeff |= 0x00000100
>[  103.575117] nouveau T[   VBIOS][0000:02:00.0] 0xbd2b[1]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[  103.575129] nouveau T[   VBIOS][0000:02:00.0] 0xbd38[1]: NV_REG	R[0x6061c128] &= 0x7fffffff |= 0x80000000
>[  103.575141] nouveau T[   VBIOS][0000:02:00.0] 0xbd45[1]: NV_REG	R[0x40614300] &= 0xfcffffff |= 0x03000000
>[  103.575153] nouveau T[   VBIOS][0000:02:00.0] 0xbd52[1]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.575162] nouveau T[   VBIOS][0000:02:00.0] 0xbd5b[1]: ZM_REG	R[0x4061c010] = 0x0060152f
>[  103.575170] nouveau T[   VBIOS][0000:02:00.0] 0xbd64[1]: ZM_REG	R[0x4061c014] = 0x00020000
>[  103.575178] nouveau T[   VBIOS][0000:02:00.0] 0xbd6d[1]: SUB_DIRECT	0x4860
>[  103.575187] nouveau T[   VBIOS][0000:02:00.0] 0x4860[2]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[  103.575197] nouveau T[   VBIOS][0000:02:00.0] 0x486d[2]: TIME	0x0064
>[  103.575307] nouveau T[   VBIOS][0000:02:00.0] 0x4870[2]: CONDITION	0x06
>[  103.575318] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.575331] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[  103.575341] nouveau T[   VBIOS][0000:02:00.0] 0x487f[2]: RESUME
>[  103.575350] nouveau T[   VBIOS][0000:02:00.0] 0x4880[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[  103.575360] nouveau T[   VBIOS][0000:02:00.0] 0x488d[2]: TIME	0x0064
>[  103.575469] nouveau T[   VBIOS][0000:02:00.0] 0x4890[2]: CONDITION	0x06
>[  103.575480] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.575492] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[  103.575502] nouveau T[   VBIOS][0000:02:00.0] 0x489f[2]: RESUME
>[  103.575511] nouveau T[   VBIOS][0000:02:00.0] 0x48a0[2]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[  103.575521] nouveau T[   VBIOS][0000:02:00.0] 0x48ad[2]: TIME	0x0064
>[  103.575629] nouveau T[   VBIOS][0000:02:00.0] 0x48b0[2]: CONDITION	0x06
>[  103.575641] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.575653] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[ ]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[  103.575661] nouveau T[   VBIOS][0000:02:00.0] 0x48bf[ ]: RESUME
>[  103.575670] nouveau T[   VBIOS][0000:02:00.0] 0x48c0[2]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[  103.575680] nouveau T[   VBIOS][0000:02:00.0] 0x48cd[2]: TIME	0x0064
>[  103.575789] nouveau T[   VBIOS][0000:02:00.0] 0x48d0[2]: CONDITION	0x06
>[  103.575800] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.575813] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[ ]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[  103.575820] nouveau T[   VBIOS][0000:02:00.0] 0x48df[ ]: RESUME
>[  103.575827] nouveau T[   VBIOS][0000:02:00.0] 0x48e0[2]: DONE
>[  103.575836] nouveau T[   VBIOS][0000:02:00.0] 0xbd70[1]: NV_REG	R[0x40614300] &= 0xfffcffff |= 0x00010000
>[  103.575846] nouveau T[   VBIOS][0000:02:00.0] 0xbd7d[1]: TIME	0x0032
>[  103.575905] nouveau T[   VBIOS][0000:02:00.0] 0xbd80[1]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[  103.575919] nouveau T[   VBIOS][0000:02:00.0] 0xbd8d[1]: NV_REG	R[0x4061c034] &= 0x7feeffff |= 0x80000000
>[  103.575930] nouveau T[   VBIOS][0000:02:00.0] 0xbd9a[1]: TIME	0x000a
>[  103.575948] nouveau T[   VBIOS][0000:02:00.0] 0xbd9d[1]: CONDITION_TIME	0x15 0xff
>[  103.575959] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: 	[0x15] (R[0x4061c034] & 0x80000000) == 0x00000000
>[  103.575971] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[  103.575983] nouveau T[   VBIOS][0000:02:00.0] 0xbdad[1]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00000000
>[  103.575994] nouveau T[   VBIOS][0000:02:00.0] 0xbdba[1]: AUXCH	AUX[0x00000102] 0x01
>[  103.576003] nouveau T[   VBIOS][0000:02:00.0] 0xbdc0[1]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[  103.576013] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.576172] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.576183] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01800000
>[  103.576192] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.576201] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.576212] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.576224] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.576245] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.576252] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.576259] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.576265] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.576409] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.576422] nouveau T[   VBIOS][0000:02:00.0] 0xbdc2[1]: DP_CONDITION	0x05 0x15
>[  103.576431] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x0000000d 1
>[  103.576588] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.576599] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01800000
>[  103.576608] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.576618] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.576627] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.576640] nouveau T[   VBIOS][0000:02:00.0] 0xbdc5[ ]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[  103.576649] nouveau T[   VBIOS][0000:02:00.0] 0xbdd2[ ]: AUXCH	AUX[0x0000010a] 0x01
>[  103.576658] nouveau T[   VBIOS][0000:02:00.0] 0xbdd8[ ]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[  103.576665] nouveau T[   VBIOS][0000:02:00.0] 0xbdda[ ]: DONE
>[  103.576675] nouveau T[   VBIOS][0000:02:00.0] 0xc003[ ]: DP_CONDITION	0x00 0x08
>[  103.576683] nouveau T[   VBIOS][0000:02:00.0] 0xc006[ ]: SUB_DIRECT	0xc2a1
>[  103.576690] nouveau T[   VBIOS][0000:02:00.0] 0xc009[ ]: NOT
>[  103.576697] nouveau T[   VBIOS][0000:02:00.0] 0xc00a[0]: SUB_DIRECT	0xc2a1
>[  103.576704] nouveau T[   VBIOS][0000:02:00.0] 0xc2a1[1]: DONE
>[  103.576711] nouveau T[   VBIOS][0000:02:00.0] 0xc00d[0]: RESUME
>[  103.576718] nouveau T[   VBIOS][0000:02:00.0] 0xc00e[0]: DONE
>[  103.576727] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: 4 lanes at 270000 KB/s
>[  103.576736] nouveau T[   VBIOS][0000:02:00.0] 0xbdf1[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.576743] nouveau T[   VBIOS][0000:02:00.0] 0xbdfa[0]: DONE
>[  103.576776] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000100 2
>[  103.576797] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x0000840a
>[  103.576804] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.576811] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.576818] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.576972] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  103.576985] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 1
>[  103.576996] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.577157] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.577168] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01800020
>[  103.577177] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.577186] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.577196] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.577207] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.577226] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000021
>[  103.577233] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.577239] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.577246] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.577389] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.577403] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 00 00
>[  103.577427] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 00 00
>[  103.577448] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 00 00
>[  103.577470] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 00 00
>[  103.577490] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.577510] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.577517] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.577524] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.577531] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.577702] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.577817] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.578018] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.578029] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801111
>[  103.578039] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.578051] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.578060] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.578072] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 11 11 80 00 00 00
>[  103.578080] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 2
>[  103.578091] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.578249] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.578260] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801121
>[  103.578270] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.578279] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.578288] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.578299] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.578319] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000022
>[  103.578325] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.578332] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.578338] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.578482] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.578895] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.579097] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.579108] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01811777
>[  103.579118] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.579127] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.579136] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.579150] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 17 81 01 88 88
>[  103.579159] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 10 00
>[  103.579182] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 10 00
>[  103.579202] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 10 00
>[  103.579223] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 10 00
>[  103.579243] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.579264] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x10101010
>[  103.579270] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.579277] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.579284] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.579452] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.579866] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.580070] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.580081] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817777
>[  103.580091] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.580101] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.580110] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.580121] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 77 81 01 88 88
>[  103.580130] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 10 00
>[  103.580152] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 10 00
>[  103.580173] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 10 00
>[  103.580193] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 10 00
>[  103.580213] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.580235] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x10101010
>[  103.580244] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.580251] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.580257] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.580429] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.580441] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 0
>[  103.580452] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.580610] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.580620] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817722
>[  103.580629] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.580639] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.580647] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.580658] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.580679] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.580686] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.580693] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.580700] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.580844] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.580858] nouveau T[   VBIOS][0000:02:00.0] 0xbddb[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00001000
>[  103.580870] nouveau T[   VBIOS][0000:02:00.0] 0xbde8[0]: AUXCH	AUX[0x00000102] 0x01
>[  103.580881] nouveau T[   VBIOS][0000:02:00.0] 0xbdee[0]: 	AUX[0x00000102] &= 0xdf |= 0x00
>[  103.580890] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.581048] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.581058] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817720
>[  103.581068] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.581077] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.581086] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.581097] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.581117] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.581124] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.581130] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.581136] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.581280] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.581292] nouveau T[   VBIOS][0000:02:00.0] 0xbdf0[0]: DONE
>[  103.581299] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training complete
>[  103.581372] nouveau D[     DRM] plugged DP-1
>[  103.581401] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000100 2
>[  103.581567] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  103.581577] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0181840a
>[  103.581587] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.581596] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.581605] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.581617] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 3
>[  103.581793] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  103.581803] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817777
>[  103.581813] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.581823] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.581832] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.581852] nouveau D[     I2C][0000:02:00.0] PAD:S:00: -> PORT:06
>[  103.582948] nouveau D[     I2C][0000:02:00.0] PAD:S:00: -> NULL
>[  103.582962] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000000 8
>[  103.583179] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[  103.583190] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01840a11
>[  103.583199] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.583209] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.583218] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.583228] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[  103.583234] nouveau D[     DRM] encoder: 4x270000
>[  103.583240] nouveau D[     DRM] maximum: 4x270000
>[  103.583249] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 4: 0x00000050 1
>[  103.583269] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.583276] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.583283] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.583289] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.583434] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  103.583445] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 1: 0x00000050 1
>[  103.583603] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[  103.583614] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01840a00
>[  103.583623] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.583633] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.583643] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.583655] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 4: 0x00000050 1
>[  103.583676] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.583683] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.583689] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.583696] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.583841] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  103.583853] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.584141] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.584151] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xffffff00
>[  103.584161] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00ffffff
>[  103.584170] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x2846f022
>[  103.584179] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.584190] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.584475] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.584486] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x04011520
>[  103.584496] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x781a29a5
>[  103.584506] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xa4c53726
>[  103.584516] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x259b4c55
>[  103.584526] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.584811] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.584822] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xa1545012
>[  103.584831] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x40810008
>[  103.584841] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01018081
>[  103.584850] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01010101
>[  103.584861] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.585146] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.585156] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01010101
>[  103.585166] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x299a0101
>[  103.585176] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x8451d0a0
>[  103.585186] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x98503022
>[  103.585197] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.585483] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.585494] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xff980036
>[  103.585503] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x1c000010
>[  103.585513] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xfd000000
>[  103.585522] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x184c3200
>[  103.585533] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.585823] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.585834] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a010e53
>[  103.585844] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20202020
>[  103.585854] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00002020
>[  103.585864] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x4c00fc00
>[  103.585875] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.586161] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.586172] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30393141
>[  103.586181] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20200a35
>[  103.586191] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20202020
>[  103.586200] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xff000000
>[  103.586211] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 1: 0x00000050 16
>[  103.586496] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[  103.586507] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x434e4300
>[  103.586516] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30323331
>[  103.586526] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.586536] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.628337] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: HPD: 2
>[  103.628387] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000000 16
>[  103.628413] nouveau D[     I2C][0000:02:00.0] AUXCH(1): sink not detected
>[  103.628425] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: aux power -> demand
>[  103.628435] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> NULL
>[  103.628451] nouveau D[     DRM] unplugged DP-1
>[  103.628505] nouveau D[     I2C][0000:02:00.0] PAD:S:00: -> PORT:06
>[  103.628585] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: HPD: 1
>[  103.629611] nouveau D[     I2C][0000:02:00.0] PAD:S:00: -> NULL
>[  103.629627] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> PORT:0b
>[  103.629633] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000000 8
>[  103.629844] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[  103.629851] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01840a11
>[  103.629858] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.629864] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.629871] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.629881] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> NULL
>[  103.629886] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[  103.629890] nouveau D[     DRM] encoder: 4x270000
>[  103.629893] nouveau D[     DRM] maximum: 4x270000
>[  103.629904] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> PORT:0b
>[  103.629909] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 4: 0x00000050 1
>[  103.629927] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.629931] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.629935] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.629939] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.630081] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  103.630089] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 1: 0x00000050 1
>[  103.630243] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[  103.630250] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01840a00
>[  103.630257] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.630263] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.630270] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.630280] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> NULL
>[  103.630290] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> PORT:0b
>[  103.630295] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 4: 0x00000050 1
>[  103.630313] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.630317] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.630321] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.630325] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.630466] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  103.630474] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.630757] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.630764] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xffffff00
>[  103.630771] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00ffffff
>[  103.630778] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x2846f022
>[  103.630784] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.630792] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.631075] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.631082] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x04011520
>[  103.631089] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x781a29a5
>[  103.631095] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xa4c53726
>[  103.631102] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x259b4c55
>[  103.631110] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.631393] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.631399] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xa1545012
>[  103.631406] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x40810008
>[  103.631413] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01018081
>[  103.631419] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01010101
>[  103.631427] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.631710] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.631716] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01010101
>[  103.631723] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x299a0101
>[  103.631729] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x8451d0a0
>[  103.631736] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x98503022
>[  103.631743] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.632026] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.632033] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xff980036
>[  103.632040] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x1c000010
>[  103.632046] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xfd000000
>[  103.632053] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x184c3200
>[  103.632060] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.632343] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.632350] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a010e53
>[  103.632357] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20202020
>[  103.632363] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00002020
>[  103.632370] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x4c00fc00
>[  103.632377] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.632656] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.632663] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30393141
>[  103.632669] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20200a35
>[  103.632676] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20202020
>[  103.632683] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xff000000
>[  103.632690] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 1: 0x00000050 16
>[  103.632973] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[  103.632980] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x434e4300
>[  103.632987] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30323331
>[  103.632993] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.633000] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.633010] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> NULL
>[  103.633024] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> PORT:0b
>[  103.633029] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000000 16
>[  103.633304] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110900f 0x10000010
>[  103.633310] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01840a11
>[  103.633317] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.633323] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.633330] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.633338] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: aux power -> always
>[  103.633343] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000100 2
>[  103.633504] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  103.633511] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0184840a
>[  103.633517] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.633524] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.633531] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.633539] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 3
>[  103.633708] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  103.633714] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01800000
>[  103.633721] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.633727] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.633734] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.633742] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: no inter-lane alignment
>[  103.633759] nouveau T[   VBIOS][0000:02:00.0] 0xc000[0]: SUB_DIRECT	0xbd11
>[  103.633766] nouveau T[   VBIOS][0000:02:00.0] 0xbd11[1]: NV_REG	R[0x00e800] &= 0xfffffeff |= 0x00000100
>[  103.633774] nouveau T[   VBIOS][0000:02:00.0] 0xbd1e[1]: NV_REG	R[0x00e820] &= 0xfffffeff |= 0x00000100
>[  103.633783] nouveau T[   VBIOS][0000:02:00.0] 0xbd2b[1]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[  103.633792] nouveau T[   VBIOS][0000:02:00.0] 0xbd38[1]: NV_REG	R[0x6061c128] &= 0x7fffffff |= 0x80000000
>[  103.633800] nouveau T[   VBIOS][0000:02:00.0] 0xbd45[1]: NV_REG	R[0x40614300] &= 0xfcffffff |= 0x03000000
>[  103.633808] nouveau T[   VBIOS][0000:02:00.0] 0xbd52[1]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.633814] nouveau T[   VBIOS][0000:02:00.0] 0xbd5b[1]: ZM_REG	R[0x4061c010] = 0x0060152f
>[  103.633819] nouveau T[   VBIOS][0000:02:00.0] 0xbd64[1]: ZM_REG	R[0x4061c014] = 0x00020000
>[  103.633824] nouveau T[   VBIOS][0000:02:00.0] 0xbd6d[1]: SUB_DIRECT	0x4860
>[  103.633830] nouveau T[   VBIOS][0000:02:00.0] 0x4860[2]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[  103.633837] nouveau T[   VBIOS][0000:02:00.0] 0x486d[2]: TIME	0x0064
>[  103.633942] nouveau T[   VBIOS][0000:02:00.0] 0x4870[2]: CONDITION	0x06
>[  103.633949] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.633957] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[  103.633965] nouveau T[   VBIOS][0000:02:00.0] 0x487f[2]: RESUME
>[  103.633970] nouveau T[   VBIOS][0000:02:00.0] 0x4880[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[  103.633977] nouveau T[   VBIOS][0000:02:00.0] 0x488d[2]: TIME	0x0064
>[  103.634084] nouveau T[   VBIOS][0000:02:00.0] 0x4890[2]: CONDITION	0x06
>[  103.634097] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.634109] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[  103.634119] nouveau T[   VBIOS][0000:02:00.0] 0x489f[2]: RESUME
>[  103.634128] nouveau T[   VBIOS][0000:02:00.0] 0x48a0[2]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[  103.634139] nouveau T[   VBIOS][0000:02:00.0] 0x48ad[2]: TIME	0x0064
>[  103.634244] nouveau T[   VBIOS][0000:02:00.0] 0x48b0[2]: CONDITION	0x06
>[  103.634249] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.634257] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[ ]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[  103.634261] nouveau T[   VBIOS][0000:02:00.0] 0x48bf[ ]: RESUME
>[  103.634265] nouveau T[   VBIOS][0000:02:00.0] 0x48c0[2]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[  103.634272] nouveau T[   VBIOS][0000:02:00.0] 0x48cd[2]: TIME	0x0064
>[  103.634375] nouveau T[   VBIOS][0000:02:00.0] 0x48d0[2]: CONDITION	0x06
>[  103.634380] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.634386] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[ ]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[  103.634389] nouveau T[   VBIOS][0000:02:00.0] 0x48df[ ]: RESUME
>[  103.634392] nouveau T[   VBIOS][0000:02:00.0] 0x48e0[2]: DONE
>[  103.634395] nouveau T[   VBIOS][0000:02:00.0] 0xbd70[1]: NV_REG	R[0x40614300] &= 0xfffcffff |= 0x00010000
>[  103.634401] nouveau T[   VBIOS][0000:02:00.0] 0xbd7d[1]: TIME	0x0032
>[  103.634455] nouveau T[   VBIOS][0000:02:00.0] 0xbd80[1]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[  103.634461] nouveau T[   VBIOS][0000:02:00.0] 0xbd8d[1]: NV_REG	R[0x4061c034] &= 0x7feeffff |= 0x80000000
>[  103.634466] nouveau T[   VBIOS][0000:02:00.0] 0xbd9a[1]: TIME	0x000a
>[  103.634480] nouveau T[   VBIOS][0000:02:00.0] 0xbd9d[1]: CONDITION_TIME	0x15 0xff
>[  103.634484] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: 	[0x15] (R[0x4061c034] & 0x80000000) == 0x00000000
>[  103.634490] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[  103.634496] nouveau T[   VBIOS][0000:02:00.0] 0xbdad[1]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00000000
>[  103.634501] nouveau T[   VBIOS][0000:02:00.0] 0xbdba[1]: AUXCH	AUX[0x00000102] 0x01
>[  103.634505] nouveau T[   VBIOS][0000:02:00.0] 0xbdc0[1]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[  103.634508] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.634661] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.634667] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01800000
>[  103.634672] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.634677] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.634682] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.634689] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.634705] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.634708] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.634710] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.634713] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.634852] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.634859] nouveau T[   VBIOS][0000:02:00.0] 0xbdc2[1]: DP_CONDITION	0x05 0x15
>[  103.634862] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x0000000d 1
>[  103.635014] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.635019] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01800000
>[  103.635024] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.635030] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.635035] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.635041] nouveau T[   VBIOS][0000:02:00.0] 0xbdc5[ ]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[  103.635044] nouveau T[   VBIOS][0000:02:00.0] 0xbdd2[ ]: AUXCH	AUX[0x0000010a] 0x01
>[  103.635048] nouveau T[   VBIOS][0000:02:00.0] 0xbdd8[ ]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[  103.635050] nouveau T[   VBIOS][0000:02:00.0] 0xbdda[ ]: DONE
>[  103.635053] nouveau T[   VBIOS][0000:02:00.0] 0xc003[ ]: DP_CONDITION	0x00 0x08
>[  103.635056] nouveau T[   VBIOS][0000:02:00.0] 0xc006[ ]: SUB_DIRECT	0xc2a1
>[  103.635059] nouveau T[   VBIOS][0000:02:00.0] 0xc009[ ]: NOT
>[  103.635061] nouveau T[   VBIOS][0000:02:00.0] 0xc00a[0]: SUB_DIRECT	0xc2a1
>[  103.635064] nouveau T[   VBIOS][0000:02:00.0] 0xc2a1[1]: DONE
>[  103.635067] nouveau T[   VBIOS][0000:02:00.0] 0xc00d[0]: RESUME
>[  103.635069] nouveau T[   VBIOS][0000:02:00.0] 0xc00e[0]: DONE
>[  103.635072] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: 4 lanes at 270000 KB/s
>[  103.635077] nouveau T[   VBIOS][0000:02:00.0] 0xbdf1[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.635079] nouveau T[   VBIOS][0000:02:00.0] 0xbdfa[0]: DONE
>[  103.635106] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000100 2
>[  103.635122] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x0000840a
>[  103.635124] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.635127] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.635129] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.635277] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  103.635283] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 1
>[  103.635289] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.635444] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.635450] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01800020
>[  103.635455] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.635460] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.635465] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.635471] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.635487] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000021
>[  103.635489] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.635492] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.635495] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.635637] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.635645] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 00 00
>[  103.635660] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 00 00
>[  103.635673] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 00 00
>[  103.635688] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 00 00
>[  103.635701] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.635718] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.635723] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.635727] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.635730] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.635896] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.636005] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.636197] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.636204] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801111
>[  103.636210] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.636216] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.636222] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.636229] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 11 11 80 00 00 00
>[  103.636233] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 2
>[  103.636240] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.636395] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.636401] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801121
>[  103.636406] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.636410] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.636415] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.636421] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.636436] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000022
>[  103.636439] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.636441] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.636443] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.636581] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.636988] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.637180] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.637185] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01811777
>[  103.637190] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.637195] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.637200] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.637206] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 17 81 01 88 88
>[  103.637209] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 10 00
>[  103.637221] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 10 00
>[  103.637233] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 10 00
>[  103.637244] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 10 00
>[  103.637255] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.637270] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x10101010
>[  103.637272] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.637275] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.637277] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.637441] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.637847] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.638040] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.638045] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817777
>[  103.638050] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.638055] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.638060] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.638065] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 77 81 01 88 88
>[  103.638068] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 10 00
>[  103.638080] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 10 00
>[  103.638091] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 10 00
>[  103.638103] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 10 00
>[  103.638114] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.638130] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x10101010
>[  103.638132] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.638135] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.638137] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.638302] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.638308] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 0
>[  103.638313] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.638464] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.638469] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817722
>[  103.638474] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.638479] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.638484] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.638489] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.638504] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.638506] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.638509] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.638511] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.638648] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.638655] nouveau T[   VBIOS][0000:02:00.0] 0xbddb[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00001000
>[  103.638661] nouveau T[   VBIOS][0000:02:00.0] 0xbde8[0]: AUXCH	AUX[0x00000102] 0x01
>[  103.638664] nouveau T[   VBIOS][0000:02:00.0] 0xbdee[0]: 	AUX[0x00000102] &= 0xdf |= 0x00
>[  103.638667] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.638821] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.638826] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817720
>[  103.638831] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.638836] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.638840] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.638846] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.638861] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.638863] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.638866] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.638868] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.639007] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.639012] nouveau T[   VBIOS][0000:02:00.0] 0xbdf0[0]: DONE
>[  103.639014] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training complete
>[  103.639032] nouveau D[     DRM] plugged DP-1
>[  103.639052] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000100 2
>[  103.639214] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  103.639220] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0181840a
>[  103.639224] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.639229] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.639234] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.639239] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 3
>[  103.639405] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  103.639411] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817777
>[  103.639416] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.639420] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.639425] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.639436] nouveau D[     I2C][0000:02:00.0] PAD:S:00: -> PORT:06
>[  103.640503] nouveau D[     I2C][0000:02:00.0] PAD:S:00: -> NULL
>[  103.640508] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000000 8
>[  103.640718] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[  103.640724] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01840a11
>[  103.640729] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.640734] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.640739] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.640744] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[  103.640747] nouveau D[     DRM] encoder: 4x270000
>[  103.640753] nouveau D[     DRM] maximum: 4x270000
>[  103.640758] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 4: 0x00000050 1
>[  103.640775] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.640778] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.640782] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.640785] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.640928] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  103.640935] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 1: 0x00000050 1
>[  103.641086] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[  103.641092] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01840a00
>[  103.641097] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.641102] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.641108] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.641114] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 4: 0x00000050 1
>[  103.641129] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.641132] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.641134] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.641137] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.641275] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  103.641281] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.641560] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.641565] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xffffff00
>[  103.641570] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00ffffff
>[  103.641576] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x2846f022
>[  103.641581] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.641586] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.641865] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.641870] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x04011520
>[  103.641875] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x781a29a5
>[  103.641880] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xa4c53726
>[  103.641886] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x259b4c55
>[  103.641891] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.642170] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.642175] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xa1545012
>[  103.642180] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x40810008
>[  103.642185] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01018081
>[  103.642189] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01010101
>[  103.642195] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.642475] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.642481] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01010101
>[  103.642486] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x299a0101
>[  103.642491] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x8451d0a0
>[  103.642496] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x98503022
>[  103.642501] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.642779] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.642785] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xff980036
>[  103.642790] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x1c000010
>[  103.642794] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xfd000000
>[  103.642799] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x184c3200
>[  103.642804] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.643082] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.643088] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a010e53
>[  103.643092] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20202020
>[  103.643097] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00002020
>[  103.643102] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x4c00fc00
>[  103.643107] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.643385] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.643391] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30393141
>[  103.643395] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20200a35
>[  103.643400] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20202020
>[  103.643405] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xff000000
>[  103.643410] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 1: 0x00000050 16
>[  103.643690] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[  103.643695] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x434e4300
>[  103.643699] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30323331
>[  103.643704] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.643709] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.691757] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: HPD: 4
>[  103.691797] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000100 2
>[  103.691964] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  103.691972] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0000840a
>[  103.691978] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.691985] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.691992] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.691999] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 3
>[  103.692172] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  103.692179] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.692186] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.692193] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.692199] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.692207] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: no inter-lane alignment
>[  103.692220] nouveau T[   VBIOS][0000:02:00.0] 0xc000[0]: SUB_DIRECT	0xbd11
>[  103.692226] nouveau T[   VBIOS][0000:02:00.0] 0xbd11[1]: NV_REG	R[0x00e800] &= 0xfffffeff |= 0x00000100
>[  103.692234] nouveau T[   VBIOS][0000:02:00.0] 0xbd1e[1]: NV_REG	R[0x00e820] &= 0xfffffeff |= 0x00000100
>[  103.692243] nouveau T[   VBIOS][0000:02:00.0] 0xbd2b[1]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[  103.692251] nouveau T[   VBIOS][0000:02:00.0] 0xbd38[1]: NV_REG	R[0x6061c128] &= 0x7fffffff |= 0x80000000
>[  103.692259] nouveau T[   VBIOS][0000:02:00.0] 0xbd45[1]: NV_REG	R[0x40614300] &= 0xfcffffff |= 0x03000000
>[  103.692266] nouveau T[   VBIOS][0000:02:00.0] 0xbd52[1]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.692271] nouveau T[   VBIOS][0000:02:00.0] 0xbd5b[1]: ZM_REG	R[0x4061c010] = 0x0060152f
>[  103.692277] nouveau T[   VBIOS][0000:02:00.0] 0xbd64[1]: ZM_REG	R[0x4061c014] = 0x00020000
>[  103.692281] nouveau T[   VBIOS][0000:02:00.0] 0xbd6d[1]: SUB_DIRECT	0x4860
>[  103.692286] nouveau T[   VBIOS][0000:02:00.0] 0x4860[2]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[  103.692294] nouveau T[   VBIOS][0000:02:00.0] 0x486d[2]: TIME	0x0064
>[  103.692400] nouveau T[   VBIOS][0000:02:00.0] 0x4870[2]: CONDITION	0x06
>[  103.692407] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.692415] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[  103.692422] nouveau T[   VBIOS][0000:02:00.0] 0x487f[2]: RESUME
>[  103.692428] nouveau T[   VBIOS][0000:02:00.0] 0x4880[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[  103.692435] nouveau T[   VBIOS][0000:02:00.0] 0x488d[2]: TIME	0x0064
>[  103.692540] nouveau T[   VBIOS][0000:02:00.0] 0x4890[2]: CONDITION	0x06
>[  103.692547] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.692555] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[  103.692562] nouveau T[   VBIOS][0000:02:00.0] 0x489f[2]: RESUME
>[  103.692567] nouveau T[   VBIOS][0000:02:00.0] 0x48a0[2]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[  103.692574] nouveau T[   VBIOS][0000:02:00.0] 0x48ad[2]: TIME	0x0064
>[  103.692681] nouveau T[   VBIOS][0000:02:00.0] 0x48b0[2]: CONDITION	0x06
>[  103.692687] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.692696] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[ ]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[  103.692700] nouveau T[   VBIOS][0000:02:00.0] 0x48bf[ ]: RESUME
>[  103.692705] nouveau T[   VBIOS][0000:02:00.0] 0x48c0[2]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[  103.692712] nouveau T[   VBIOS][0000:02:00.0] 0x48cd[2]: TIME	0x0064
>[  103.692817] nouveau T[   VBIOS][0000:02:00.0] 0x48d0[2]: CONDITION	0x06
>[  103.692824] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.692832] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[ ]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[  103.692836] nouveau T[   VBIOS][0000:02:00.0] 0x48df[ ]: RESUME
>[  103.692840] nouveau T[   VBIOS][0000:02:00.0] 0x48e0[2]: DONE
>[  103.692845] nouveau T[   VBIOS][0000:02:00.0] 0xbd70[1]: NV_REG	R[0x40614300] &= 0xfffcffff |= 0x00010000
>[  103.692853] nouveau T[   VBIOS][0000:02:00.0] 0xbd7d[1]: TIME	0x0032
>[  103.692909] nouveau T[   VBIOS][0000:02:00.0] 0xbd80[1]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[  103.692917] nouveau T[   VBIOS][0000:02:00.0] 0xbd8d[1]: NV_REG	R[0x4061c034] &= 0x7feeffff |= 0x80000000
>[  103.692925] nouveau T[   VBIOS][0000:02:00.0] 0xbd9a[1]: TIME	0x000a
>[  103.692940] nouveau T[   VBIOS][0000:02:00.0] 0xbd9d[1]: CONDITION_TIME	0x15 0xff
>[  103.692946] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: 	[0x15] (R[0x4061c034] & 0x80000000) == 0x00000000
>[  103.692954] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[  103.692963] nouveau T[   VBIOS][0000:02:00.0] 0xbdad[1]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00000000
>[  103.692971] nouveau T[   VBIOS][0000:02:00.0] 0xbdba[1]: AUXCH	AUX[0x00000102] 0x01
>[  103.692976] nouveau T[   VBIOS][0000:02:00.0] 0xbdc0[1]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[  103.692982] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.693137] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.693145] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.693152] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.693158] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.693166] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.693174] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.693191] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.693195] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.693199] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.693203] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.693346] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.693355] nouveau T[   VBIOS][0000:02:00.0] 0xbdc2[1]: DP_CONDITION	0x05 0x15
>[  103.693360] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x0000000d 1
>[  103.693517] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.693524] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.693531] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.693538] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.693544] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.693553] nouveau T[   VBIOS][0000:02:00.0] 0xbdc5[ ]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[  103.693558] nouveau T[   VBIOS][0000:02:00.0] 0xbdd2[ ]: AUXCH	AUX[0x0000010a] 0x01
>[  103.693563] nouveau T[   VBIOS][0000:02:00.0] 0xbdd8[ ]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[  103.693567] nouveau T[   VBIOS][0000:02:00.0] 0xbdda[ ]: DONE
>[  103.693572] nouveau T[   VBIOS][0000:02:00.0] 0xc003[ ]: DP_CONDITION	0x00 0x08
>[  103.693577] nouveau T[   VBIOS][0000:02:00.0] 0xc006[ ]: SUB_DIRECT	0xc2a1
>[  103.693581] nouveau T[   VBIOS][0000:02:00.0] 0xc009[ ]: NOT
>[  103.693587] nouveau T[   VBIOS][0000:02:00.0] 0xc00a[0]: SUB_DIRECT	0xc2a1
>[  103.693591] nouveau T[   VBIOS][0000:02:00.0] 0xc2a1[1]: DONE
>[  103.693595] nouveau T[   VBIOS][0000:02:00.0] 0xc00d[0]: RESUME
>[  103.693599] nouveau T[   VBIOS][0000:02:00.0] 0xc00e[0]: DONE
>[  103.693604] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: 4 lanes at 270000 KB/s
>[  103.693609] nouveau T[   VBIOS][0000:02:00.0] 0xbdf1[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.693613] nouveau T[   VBIOS][0000:02:00.0] 0xbdfa[0]: DONE
>[  103.693642] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000100 2
>[  103.693660] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x0000840a
>[  103.693664] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.693668] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.693672] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.693823] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  103.693831] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 1
>[  103.693838] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.693996] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.694003] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000020
>[  103.694010] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.694016] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.694023] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.694041] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.694059] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000021
>[  103.694063] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.694067] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.694071] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.694214] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.694223] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 00 00
>[  103.694239] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 00 00
>[  103.694254] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 00 00
>[  103.694269] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 00 00
>[  103.694284] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.694302] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.694306] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.694310] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.694314] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.694481] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.694591] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.694789] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.694796] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801111
>[  103.694803] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  103.694809] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.694816] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.694824] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 11 11 80 00 00 00
>[  103.694829] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 2
>[  103.694838] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.694993] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.695001] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801121
>[  103.695007] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  103.695014] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.695021] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.695028] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.695046] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000022
>[  103.695051] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.695055] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.695058] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.695202] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.695612] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.695807] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.695814] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01811777
>[  103.695821] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.695827] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.695834] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.695842] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 17 81 01 88 88
>[  103.695847] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 10 00
>[  103.695864] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 10 00
>[  103.695880] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 10 00
>[  103.695897] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 10 00
>[  103.695912] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.695929] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x10101010
>[  103.695933] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.695937] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.695941] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.696105] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.696515] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.696711] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.696718] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817777
>[  103.696725] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.696732] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.696738] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.696747] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 77 81 01 88 88
>[  103.696752] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 10 00
>[  103.696769] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 10 00
>[  103.696785] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 10 00
>[  103.696800] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 10 00
>[  103.696814] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.696832] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x10101010
>[  103.696836] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.696840] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.696844] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.697011] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.697020] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 0
>[  103.697027] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.697184] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.697192] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817722
>[  103.697199] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.697205] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.697212] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.697219] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.697236] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.697240] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.697244] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.697248] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.697392] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.697401] nouveau T[   VBIOS][0000:02:00.0] 0xbddb[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00001000
>[  103.697409] nouveau T[   VBIOS][0000:02:00.0] 0xbde8[0]: AUXCH	AUX[0x00000102] 0x01
>[  103.697415] nouveau T[   VBIOS][0000:02:00.0] 0xbdee[0]: 	AUX[0x00000102] &= 0xdf |= 0x00
>[  103.697420] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.697576] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.697583] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817720
>[  103.697590] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.697597] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.697606] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.697614] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.697632] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.697636] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.697640] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.697644] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.697787] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.697795] nouveau T[   VBIOS][0000:02:00.0] 0xbdf0[0]: DONE
>[  103.697799] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training complete
>[  103.749351] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: HPD: 4
>[  103.749390] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000100 2
>[  103.749561] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  103.749573] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0000840a
>[  103.749578] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.749583] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.749588] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.749593] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 3
>[  103.749763] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  103.749768] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.749773] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.749778] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.749783] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.749788] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: no inter-lane alignment
>[  103.749795] nouveau T[   VBIOS][0000:02:00.0] 0xc000[0]: SUB_DIRECT	0xbd11
>[  103.749799] nouveau T[   VBIOS][0000:02:00.0] 0xbd11[1]: NV_REG	R[0x00e800] &= 0xfffffeff |= 0x00000100
>[  103.749804] nouveau T[   VBIOS][0000:02:00.0] 0xbd1e[1]: NV_REG	R[0x00e820] &= 0xfffffeff |= 0x00000100
>[  103.749810] nouveau T[   VBIOS][0000:02:00.0] 0xbd2b[1]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[  103.749816] nouveau T[   VBIOS][0000:02:00.0] 0xbd38[1]: NV_REG	R[0x6061c128] &= 0x7fffffff |= 0x80000000
>[  103.749822] nouveau T[   VBIOS][0000:02:00.0] 0xbd45[1]: NV_REG	R[0x40614300] &= 0xfcffffff |= 0x03000000
>[  103.749827] nouveau T[   VBIOS][0000:02:00.0] 0xbd52[1]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.749830] nouveau T[   VBIOS][0000:02:00.0] 0xbd5b[1]: ZM_REG	R[0x4061c010] = 0x0060152f
>[  103.749833] nouveau T[   VBIOS][0000:02:00.0] 0xbd64[1]: ZM_REG	R[0x4061c014] = 0x00020000
>[  103.749835] nouveau T[   VBIOS][0000:02:00.0] 0xbd6d[1]: SUB_DIRECT	0x4860
>[  103.749838] nouveau T[   VBIOS][0000:02:00.0] 0x4860[2]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[  103.749843] nouveau T[   VBIOS][0000:02:00.0] 0x486d[2]: TIME	0x0064
>[  103.749946] nouveau T[   VBIOS][0000:02:00.0] 0x4870[2]: CONDITION	0x06
>[  103.749950] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.749956] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[  103.749961] nouveau T[   VBIOS][0000:02:00.0] 0x487f[2]: RESUME
>[  103.749964] nouveau T[   VBIOS][0000:02:00.0] 0x4880[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[  103.749969] nouveau T[   VBIOS][0000:02:00.0] 0x488d[2]: TIME	0x0064
>[  103.750072] nouveau T[   VBIOS][0000:02:00.0] 0x4890[2]: CONDITION	0x06
>[  103.750075] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.750081] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[  103.750086] nouveau T[   VBIOS][0000:02:00.0] 0x489f[2]: RESUME
>[  103.750089] nouveau T[   VBIOS][0000:02:00.0] 0x48a0[2]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[  103.750094] nouveau T[   VBIOS][0000:02:00.0] 0x48ad[2]: TIME	0x0064
>[  103.750197] nouveau T[   VBIOS][0000:02:00.0] 0x48b0[2]: CONDITION	0x06
>[  103.750201] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.750207] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[ ]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[  103.750209] nouveau T[   VBIOS][0000:02:00.0] 0x48bf[ ]: RESUME
>[  103.750212] nouveau T[   VBIOS][0000:02:00.0] 0x48c0[2]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[  103.750217] nouveau T[   VBIOS][0000:02:00.0] 0x48cd[2]: TIME	0x0064
>[  103.750320] nouveau T[   VBIOS][0000:02:00.0] 0x48d0[2]: CONDITION	0x06
>[  103.750324] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.750331] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[ ]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[  103.750334] nouveau T[   VBIOS][0000:02:00.0] 0x48df[ ]: RESUME
>[  103.750336] nouveau T[   VBIOS][0000:02:00.0] 0x48e0[2]: DONE
>[  103.750339] nouveau T[   VBIOS][0000:02:00.0] 0xbd70[1]: NV_REG	R[0x40614300] &= 0xfffcffff |= 0x00010000
>[  103.750345] nouveau T[   VBIOS][0000:02:00.0] 0xbd7d[1]: TIME	0x0032
>[  103.750399] nouveau T[   VBIOS][0000:02:00.0] 0xbd80[1]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[  103.750406] nouveau T[   VBIOS][0000:02:00.0] 0xbd8d[1]: NV_REG	R[0x4061c034] &= 0x7feeffff |= 0x80000000
>[  103.750412] nouveau T[   VBIOS][0000:02:00.0] 0xbd9a[1]: TIME	0x000a
>[  103.750425] nouveau T[   VBIOS][0000:02:00.0] 0xbd9d[1]: CONDITION_TIME	0x15 0xff
>[  103.750429] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: 	[0x15] (R[0x4061c034] & 0x80000000) == 0x00000000
>[  103.750435] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[  103.750441] nouveau T[   VBIOS][0000:02:00.0] 0xbdad[1]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00000000
>[  103.750447] nouveau T[   VBIOS][0000:02:00.0] 0xbdba[1]: AUXCH	AUX[0x00000102] 0x01
>[  103.750450] nouveau T[   VBIOS][0000:02:00.0] 0xbdc0[1]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[  103.750454] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.750604] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.750609] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.750614] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.750619] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.750624] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.750630] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.750646] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.750648] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.750650] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.750653] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.750792] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.750798] nouveau T[   VBIOS][0000:02:00.0] 0xbdc2[1]: DP_CONDITION	0x05 0x15
>[  103.750801] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x0000000d 1
>[  103.750951] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.750956] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.750961] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.750966] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.750971] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.750978] nouveau T[   VBIOS][0000:02:00.0] 0xbdc5[ ]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[  103.750981] nouveau T[   VBIOS][0000:02:00.0] 0xbdd2[ ]: AUXCH	AUX[0x0000010a] 0x01
>[  103.750983] nouveau T[   VBIOS][0000:02:00.0] 0xbdd8[ ]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[  103.750986] nouveau T[   VBIOS][0000:02:00.0] 0xbdda[ ]: DONE
>[  103.750989] nouveau T[   VBIOS][0000:02:00.0] 0xc003[ ]: DP_CONDITION	0x00 0x08
>[  103.750991] nouveau T[   VBIOS][0000:02:00.0] 0xc006[ ]: SUB_DIRECT	0xc2a1
>[  103.750993] nouveau T[   VBIOS][0000:02:00.0] 0xc009[ ]: NOT
>[  103.750996] nouveau T[   VBIOS][0000:02:00.0] 0xc00a[0]: SUB_DIRECT	0xc2a1
>[  103.750998] nouveau T[   VBIOS][0000:02:00.0] 0xc2a1[1]: DONE
>[  103.751000] nouveau T[   VBIOS][0000:02:00.0] 0xc00d[0]: RESUME
>[  103.751002] nouveau T[   VBIOS][0000:02:00.0] 0xc00e[0]: DONE
>[  103.751005] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: 4 lanes at 270000 KB/s
>[  103.751008] nouveau T[   VBIOS][0000:02:00.0] 0xbdf1[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.751011] nouveau T[   VBIOS][0000:02:00.0] 0xbdfa[0]: DONE
>[  103.751037] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000100 2
>[  103.751053] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x0000840a
>[  103.751055] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.751058] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.751060] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.751205] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  103.751211] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 1
>[  103.751217] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.751367] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.751372] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000020
>[  103.751376] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.751381] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.751386] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.751392] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.751407] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000021
>[  103.751409] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.751411] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.751414] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.751552] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.751558] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 00 00
>[  103.751570] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 00 00
>[  103.751582] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 00 00
>[  103.751593] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 00 00
>[  103.751605] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.751620] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.751623] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.751625] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.751627] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.751791] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.751899] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.752093] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.752098] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801111
>[  103.752103] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  103.752109] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.752114] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.752120] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 11 11 80 00 00 00
>[  103.752123] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 2
>[  103.752129] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.752280] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.752286] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801121
>[  103.752291] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  103.752297] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.752302] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.752308] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.752324] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000022
>[  103.752327] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.752330] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.752332] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.752471] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.752878] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.753071] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.753077] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817777
>[  103.753082] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30324444
>[  103.753088] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.753093] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.753099] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 77 81 01 44 44
>[  103.753103] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 08 00
>[  103.753115] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 08 00
>[  103.753128] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 08 00
>[  103.753139] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 08 00
>[  103.753151] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.753167] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x08080808
>[  103.753170] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.753172] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.753175] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.753341] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.753347] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 0
>[  103.753353] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.753506] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.753512] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817722
>[  103.753517] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30324444
>[  103.753522] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.753527] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.753533] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.753549] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.753551] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.753555] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.753557] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.753696] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.753703] nouveau T[   VBIOS][0000:02:00.0] 0xbddb[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00001000
>[  103.753709] nouveau T[   VBIOS][0000:02:00.0] 0xbde8[0]: AUXCH	AUX[0x00000102] 0x01
>[  103.753713] nouveau T[   VBIOS][0000:02:00.0] 0xbdee[0]: 	AUX[0x00000102] &= 0xdf |= 0x00
>[  103.753717] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.753869] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.753875] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817720
>[  103.753880] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30324444
>[  103.753885] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.753891] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.753897] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.753913] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.753916] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.753918] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.753921] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.754064] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.754077] nouveau T[   VBIOS][0000:02:00.0] 0xbdf0[0]: DONE
>[  103.754085] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training complete
>[  103.806203] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: HPD: 4
>[  103.806239] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000100 2
>[  103.806412] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  103.806425] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0000840a
>[  103.806429] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.806434] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.806439] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.806445] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 3
>[  103.806614] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  103.806620] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.806625] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.806630] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.806634] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.806640] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: no inter-lane alignment
>[  103.806647] nouveau T[   VBIOS][0000:02:00.0] 0xc000[0]: SUB_DIRECT	0xbd11
>[  103.806650] nouveau T[   VBIOS][0000:02:00.0] 0xbd11[1]: NV_REG	R[0x00e800] &= 0xfffffeff |= 0x00000100
>[  103.806656] nouveau T[   VBIOS][0000:02:00.0] 0xbd1e[1]: NV_REG	R[0x00e820] &= 0xfffffeff |= 0x00000100
>[  103.806662] nouveau T[   VBIOS][0000:02:00.0] 0xbd2b[1]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[  103.806667] nouveau T[   VBIOS][0000:02:00.0] 0xbd38[1]: NV_REG	R[0x6061c128] &= 0x7fffffff |= 0x80000000
>[  103.806673] nouveau T[   VBIOS][0000:02:00.0] 0xbd45[1]: NV_REG	R[0x40614300] &= 0xfcffffff |= 0x03000000
>[  103.806678] nouveau T[   VBIOS][0000:02:00.0] 0xbd52[1]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.806681] nouveau T[   VBIOS][0000:02:00.0] 0xbd5b[1]: ZM_REG	R[0x4061c010] = 0x0060152f
>[  103.806684] nouveau T[   VBIOS][0000:02:00.0] 0xbd64[1]: ZM_REG	R[0x4061c014] = 0x00020000
>[  103.806687] nouveau T[   VBIOS][0000:02:00.0] 0xbd6d[1]: SUB_DIRECT	0x4860
>[  103.806689] nouveau T[   VBIOS][0000:02:00.0] 0x4860[2]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[  103.806694] nouveau T[   VBIOS][0000:02:00.0] 0x486d[2]: TIME	0x0064
>[  103.806797] nouveau T[   VBIOS][0000:02:00.0] 0x4870[2]: CONDITION	0x06
>[  103.806802] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.806807] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[  103.806812] nouveau T[   VBIOS][0000:02:00.0] 0x487f[2]: RESUME
>[  103.806815] nouveau T[   VBIOS][0000:02:00.0] 0x4880[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[  103.806820] nouveau T[   VBIOS][0000:02:00.0] 0x488d[2]: TIME	0x0064
>[  103.806923] nouveau T[   VBIOS][0000:02:00.0] 0x4890[2]: CONDITION	0x06
>[  103.806926] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.806932] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[  103.806937] nouveau T[   VBIOS][0000:02:00.0] 0x489f[2]: RESUME
>[  103.806940] nouveau T[   VBIOS][0000:02:00.0] 0x48a0[2]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[  103.806945] nouveau T[   VBIOS][0000:02:00.0] 0x48ad[2]: TIME	0x0064
>[  103.807048] nouveau T[   VBIOS][0000:02:00.0] 0x48b0[2]: CONDITION	0x06
>[  103.807052] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.807058] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[ ]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[  103.807060] nouveau T[   VBIOS][0000:02:00.0] 0x48bf[ ]: RESUME
>[  103.807063] nouveau T[   VBIOS][0000:02:00.0] 0x48c0[2]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[  103.807068] nouveau T[   VBIOS][0000:02:00.0] 0x48cd[2]: TIME	0x0064
>[  103.807171] nouveau T[   VBIOS][0000:02:00.0] 0x48d0[2]: CONDITION	0x06
>[  103.807175] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.807181] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[ ]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[  103.807183] nouveau T[   VBIOS][0000:02:00.0] 0x48df[ ]: RESUME
>[  103.807185] nouveau T[   VBIOS][0000:02:00.0] 0x48e0[2]: DONE
>[  103.807188] nouveau T[   VBIOS][0000:02:00.0] 0xbd70[1]: NV_REG	R[0x40614300] &= 0xfffcffff |= 0x00010000
>[  103.807193] nouveau T[   VBIOS][0000:02:00.0] 0xbd7d[1]: TIME	0x0032
>[  103.807247] nouveau T[   VBIOS][0000:02:00.0] 0xbd80[1]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[  103.807253] nouveau T[   VBIOS][0000:02:00.0] 0xbd8d[1]: NV_REG	R[0x4061c034] &= 0x7feeffff |= 0x80000000
>[  103.807258] nouveau T[   VBIOS][0000:02:00.0] 0xbd9a[1]: TIME	0x000a
>[  103.807270] nouveau T[   VBIOS][0000:02:00.0] 0xbd9d[1]: CONDITION_TIME	0x15 0xff
>[  103.807274] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: 	[0x15] (R[0x4061c034] & 0x80000000) == 0x00000000
>[  103.807279] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[  103.807285] nouveau T[   VBIOS][0000:02:00.0] 0xbdad[1]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00000000
>[  103.807290] nouveau T[   VBIOS][0000:02:00.0] 0xbdba[1]: AUXCH	AUX[0x00000102] 0x01
>[  103.807293] nouveau T[   VBIOS][0000:02:00.0] 0xbdc0[1]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[  103.807297] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.807448] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.807454] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.807459] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.807463] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.807468] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.807474] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.807489] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.807491] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.807494] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.807496] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.807634] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.807640] nouveau T[   VBIOS][0000:02:00.0] 0xbdc2[1]: DP_CONDITION	0x05 0x15
>[  103.807643] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x0000000d 1
>[  103.807794] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.807800] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.807805] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.807809] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.807814] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.807820] nouveau T[   VBIOS][0000:02:00.0] 0xbdc5[ ]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[  103.807823] nouveau T[   VBIOS][0000:02:00.0] 0xbdd2[ ]: AUXCH	AUX[0x0000010a] 0x01
>[  103.807826] nouveau T[   VBIOS][0000:02:00.0] 0xbdd8[ ]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[  103.807828] nouveau T[   VBIOS][0000:02:00.0] 0xbdda[ ]: DONE
>[  103.807831] nouveau T[   VBIOS][0000:02:00.0] 0xc003[ ]: DP_CONDITION	0x00 0x08
>[  103.807833] nouveau T[   VBIOS][0000:02:00.0] 0xc006[ ]: SUB_DIRECT	0xc2a1
>[  103.807836] nouveau T[   VBIOS][0000:02:00.0] 0xc009[ ]: NOT
>[  103.807838] nouveau T[   VBIOS][0000:02:00.0] 0xc00a[0]: SUB_DIRECT	0xc2a1
>[  103.807840] nouveau T[   VBIOS][0000:02:00.0] 0xc2a1[1]: DONE
>[  103.807842] nouveau T[   VBIOS][0000:02:00.0] 0xc00d[0]: RESUME
>[  103.807844] nouveau T[   VBIOS][0000:02:00.0] 0xc00e[0]: DONE
>[  103.807847] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: 4 lanes at 270000 KB/s
>[  103.807850] nouveau T[   VBIOS][0000:02:00.0] 0xbdf1[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.807852] nouveau T[   VBIOS][0000:02:00.0] 0xbdfa[0]: DONE
>[  103.807880] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000100 2
>[  103.807896] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x0000840a
>[  103.807898] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.807900] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.807902] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.808048] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  103.808054] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 1
>[  103.808059] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.808210] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.808216] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000020
>[  103.808220] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.808226] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.808230] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.808236] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.808251] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000021
>[  103.808253] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.808256] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.808258] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.808397] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.808403] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 00 00
>[  103.808415] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 00 00
>[  103.808427] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 00 00
>[  103.808438] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 00 00
>[  103.808450] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.808466] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.808468] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.808471] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.808473] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.808638] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.808744] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.808936] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.808942] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801111
>[  103.808947] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  103.808951] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.808956] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.808962] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 11 11 80 00 00 00
>[  103.808965] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 2
>[  103.808970] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.809121] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.809127] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801121
>[  103.809131] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  103.809137] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.809142] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.809147] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.809162] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000022
>[  103.809164] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.809167] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.809169] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.809310] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.809717] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.809910] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.809915] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01811777
>[  103.809920] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.809925] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.809930] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.809936] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 17 81 01 88 88
>[  103.809939] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 10 00
>[  103.809951] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 10 00
>[  103.809962] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 10 00
>[  103.809973] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 10 00
>[  103.809985] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.810000] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x10101010
>[  103.810002] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.810005] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.810007] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.810171] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.810578] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.810771] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.810776] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817777
>[  103.810781] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.810786] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.810791] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.810796] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 77 81 01 88 88
>[  103.810799] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 10 00
>[  103.810811] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 10 00
>[  103.810822] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 10 00
>[  103.810834] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 10 00
>[  103.810845] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.810861] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x10101010
>[  103.810863] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.810865] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.810867] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.811033] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.811039] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 0
>[  103.811044] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.811195] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.811201] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817722
>[  103.811206] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.811210] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.811215] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.811221] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.811236] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.811238] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.811240] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.811242] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.811381] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.811388] nouveau T[   VBIOS][0000:02:00.0] 0xbddb[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00001000
>[  103.811393] nouveau T[   VBIOS][0000:02:00.0] 0xbde8[0]: AUXCH	AUX[0x00000102] 0x01
>[  103.811396] nouveau T[   VBIOS][0000:02:00.0] 0xbdee[0]: 	AUX[0x00000102] &= 0xdf |= 0x00
>[  103.811399] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.811550] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.811555] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817720
>[  103.811560] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.811565] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.811570] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.811576] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.811594] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.811597] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.811600] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.811602] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.811742] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.811749] nouveau T[   VBIOS][0000:02:00.0] 0xbdf0[0]: DONE
>[  103.811753] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training complete
>[  103.901043] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: HPD: 2
>[  103.901083] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000000 16
>[  103.901108] nouveau D[     I2C][0000:02:00.0] AUXCH(1): sink not detected
>[  103.901120] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: aux power -> demand
>[  103.901130] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> NULL
>[  103.901146] nouveau D[     DRM] unplugged DP-1
>[  103.901204] nouveau D[     I2C][0000:02:00.0] PAD:S:00: -> PORT:06
>[  103.901235] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: HPD: 1
>[  103.902331] nouveau D[     I2C][0000:02:00.0] PAD:S:00: -> NULL
>[  103.902351] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> PORT:0b
>[  103.902359] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000000 8
>[  103.902577] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[  103.902588] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01840a11
>[  103.902598] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.902607] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.902617] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.902629] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> NULL
>[  103.902637] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[  103.902643] nouveau D[     DRM] encoder: 4x270000
>[  103.902649] nouveau D[     DRM] maximum: 4x270000
>[  103.902664] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> PORT:0b
>[  103.902672] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 4: 0x00000050 1
>[  103.902691] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.902698] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.902704] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.902711] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.902854] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  103.902867] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 1: 0x00000050 1
>[  103.903025] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[  103.903036] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01840a00
>[  103.903046] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.903055] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.903065] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.903078] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> NULL
>[  103.903093] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> PORT:0b
>[  103.903101] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 4: 0x00000050 1
>[  103.903121] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.903128] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.903135] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.903141] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.903286] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  103.903298] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.903584] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.903594] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xffffff00
>[  103.903604] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00ffffff
>[  103.903614] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x2846f022
>[  103.903623] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.903634] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.903919] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.903929] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x04011520
>[  103.903957] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x781a29a5
>[  103.903967] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xa4c53726
>[  103.903976] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x259b4c55
>[  103.903987] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.904273] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.904284] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xa1545012
>[  103.904293] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x40810008
>[  103.904304] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01018081
>[  103.904313] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01010101
>[  103.904325] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.904610] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.904620] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01010101
>[  103.904630] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x299a0101
>[  103.904640] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x8451d0a0
>[  103.904649] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x98503022
>[  103.904659] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.904946] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.904956] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xff980036
>[  103.904965] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x1c000010
>[  103.904975] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xfd000000
>[  103.904984] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x184c3200
>[  103.904994] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.905280] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.905291] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a010e53
>[  103.905301] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20202020
>[  103.905310] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00002020
>[  103.905319] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x4c00fc00
>[  103.905330] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.905616] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.905626] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30393141
>[  103.905636] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20200a35
>[  103.905645] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20202020
>[  103.905654] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xff000000
>[  103.905665] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 1: 0x00000050 16
>[  103.905952] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[  103.905962] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x434e4300
>[  103.905971] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30323331
>[  103.905981] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.905991] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.906004] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> NULL
>[  103.906024] nouveau D[     I2C][0000:02:00.0] PAD:S:01: -> PORT:0b
>[  103.906033] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000000 16
>[  103.906316] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110900f 0x10000010
>[  103.906328] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01840a11
>[  103.906338] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.906347] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.906357] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.906368] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: aux power -> always
>[  103.906377] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000100 2
>[  103.906541] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  103.906552] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0184840a
>[  103.906561] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.906571] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.906580] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.906592] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 3
>[  103.906765] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  103.906775] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01800000
>[  103.906785] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.906795] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.906804] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.906815] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: no inter-lane alignment
>[  103.906843] nouveau T[   VBIOS][0000:02:00.0] 0xc000[0]: SUB_DIRECT	0xbd11
>[  103.906853] nouveau T[   VBIOS][0000:02:00.0] 0xbd11[1]: NV_REG	R[0x00e800] &= 0xfffffeff |= 0x00000100
>[  103.906865] nouveau T[   VBIOS][0000:02:00.0] 0xbd1e[1]: NV_REG	R[0x00e820] &= 0xfffffeff |= 0x00000100
>[  103.906877] nouveau T[   VBIOS][0000:02:00.0] 0xbd2b[1]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[  103.906889] nouveau T[   VBIOS][0000:02:00.0] 0xbd38[1]: NV_REG	R[0x6061c128] &= 0x7fffffff |= 0x80000000
>[  103.906901] nouveau T[   VBIOS][0000:02:00.0] 0xbd45[1]: NV_REG	R[0x40614300] &= 0xfcffffff |= 0x03000000
>[  103.906912] nouveau T[   VBIOS][0000:02:00.0] 0xbd52[1]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.906921] nouveau T[   VBIOS][0000:02:00.0] 0xbd5b[1]: ZM_REG	R[0x4061c010] = 0x0060152f
>[  103.906929] nouveau T[   VBIOS][0000:02:00.0] 0xbd64[1]: ZM_REG	R[0x4061c014] = 0x00020000
>[  103.906937] nouveau T[   VBIOS][0000:02:00.0] 0xbd6d[1]: SUB_DIRECT	0x4860
>[  103.906946] nouveau T[   VBIOS][0000:02:00.0] 0x4860[2]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[  103.906956] nouveau T[   VBIOS][0000:02:00.0] 0x486d[2]: TIME	0x0064
>[  103.907065] nouveau T[   VBIOS][0000:02:00.0] 0x4870[2]: CONDITION	0x06
>[  103.907077] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.907090] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[  103.907100] nouveau T[   VBIOS][0000:02:00.0] 0x487f[2]: RESUME
>[  103.907108] nouveau T[   VBIOS][0000:02:00.0] 0x4880[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[  103.907119] nouveau T[   VBIOS][0000:02:00.0] 0x488d[2]: TIME	0x0064
>[  103.907228] nouveau T[   VBIOS][0000:02:00.0] 0x4890[2]: CONDITION	0x06
>[  103.907239] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.907252] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[  103.907261] nouveau T[   VBIOS][0000:02:00.0] 0x489f[2]: RESUME
>[  103.907270] nouveau T[   VBIOS][0000:02:00.0] 0x48a0[2]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[  103.907280] nouveau T[   VBIOS][0000:02:00.0] 0x48ad[2]: TIME	0x0064
>[  103.907389] nouveau T[   VBIOS][0000:02:00.0] 0x48b0[2]: CONDITION	0x06
>[  103.907401] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.907413] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[ ]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[  103.907420] nouveau T[   VBIOS][0000:02:00.0] 0x48bf[ ]: RESUME
>[  103.907429] nouveau T[   VBIOS][0000:02:00.0] 0x48c0[2]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[  103.907440] nouveau T[   VBIOS][0000:02:00.0] 0x48cd[2]: TIME	0x0064
>[  103.907548] nouveau T[   VBIOS][0000:02:00.0] 0x48d0[2]: CONDITION	0x06
>[  103.907559] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.907571] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[ ]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[  103.907578] nouveau T[   VBIOS][0000:02:00.0] 0x48df[ ]: RESUME
>[  103.907585] nouveau T[   VBIOS][0000:02:00.0] 0x48e0[2]: DONE
>[  103.907594] nouveau T[   VBIOS][0000:02:00.0] 0xbd70[1]: NV_REG	R[0x40614300] &= 0xfffcffff |= 0x00010000
>[  103.907604] nouveau T[   VBIOS][0000:02:00.0] 0xbd7d[1]: TIME	0x0032
>[  103.907665] nouveau T[   VBIOS][0000:02:00.0] 0xbd80[1]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[  103.907678] nouveau T[   VBIOS][0000:02:00.0] 0xbd8d[1]: NV_REG	R[0x4061c034] &= 0x7feeffff |= 0x80000000
>[  103.907688] nouveau T[   VBIOS][0000:02:00.0] 0xbd9a[1]: TIME	0x000a
>[  103.907707] nouveau T[   VBIOS][0000:02:00.0] 0xbd9d[1]: CONDITION_TIME	0x15 0xff
>[  103.907717] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: 	[0x15] (R[0x4061c034] & 0x80000000) == 0x00000000
>[  103.907729] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[  103.907742] nouveau T[   VBIOS][0000:02:00.0] 0xbdad[1]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00000000
>[  103.907753] nouveau T[   VBIOS][0000:02:00.0] 0xbdba[1]: AUXCH	AUX[0x00000102] 0x01
>[  103.907762] nouveau T[   VBIOS][0000:02:00.0] 0xbdc0[1]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[  103.907771] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.907930] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.907941] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01800000
>[  103.907951] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.907961] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.907970] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.907982] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.908005] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.908013] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.908020] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.908026] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.908171] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.908185] nouveau T[   VBIOS][0000:02:00.0] 0xbdc2[1]: DP_CONDITION	0x05 0x15
>[  103.908194] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x0000000d 1
>[  103.908351] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.908361] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01800000
>[  103.908371] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.908380] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.908389] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.908401] nouveau T[   VBIOS][0000:02:00.0] 0xbdc5[ ]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[  103.908410] nouveau T[   VBIOS][0000:02:00.0] 0xbdd2[ ]: AUXCH	AUX[0x0000010a] 0x01
>[  103.908419] nouveau T[   VBIOS][0000:02:00.0] 0xbdd8[ ]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[  103.908427] nouveau T[   VBIOS][0000:02:00.0] 0xbdda[ ]: DONE
>[  103.908435] nouveau T[   VBIOS][0000:02:00.0] 0xc003[ ]: DP_CONDITION	0x00 0x08
>[  103.908442] nouveau T[   VBIOS][0000:02:00.0] 0xc006[ ]: SUB_DIRECT	0xc2a1
>[  103.908452] nouveau T[   VBIOS][0000:02:00.0] 0xc009[ ]: NOT
>[  103.908459] nouveau T[   VBIOS][0000:02:00.0] 0xc00a[0]: SUB_DIRECT	0xc2a1
>[  103.908465] nouveau T[   VBIOS][0000:02:00.0] 0xc2a1[1]: DONE
>[  103.908472] nouveau T[   VBIOS][0000:02:00.0] 0xc00d[0]: RESUME
>[  103.908479] nouveau T[   VBIOS][0000:02:00.0] 0xc00e[0]: DONE
>[  103.908488] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: 4 lanes at 270000 KB/s
>[  103.908497] nouveau T[   VBIOS][0000:02:00.0] 0xbdf1[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.908504] nouveau T[   VBIOS][0000:02:00.0] 0xbdfa[0]: DONE
>[  103.908537] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000100 2
>[  103.908557] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x0000840a
>[  103.908563] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.908569] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.908576] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.908729] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  103.908742] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 1
>[  103.908753] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.908912] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.908923] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01800020
>[  103.908933] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.908943] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.908952] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.908965] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.908986] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000021
>[  103.908993] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.909000] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.909007] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.909152] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.909166] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 00 00
>[  103.909189] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 00 00
>[  103.909209] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 00 00
>[  103.909229] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 00 00
>[  103.909249] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.909270] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.909277] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.909284] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.909291] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.909459] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.909572] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.909772] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.909783] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801111
>[  103.909793] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.909802] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.909811] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.909823] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 11 11 80 00 00 00
>[  103.909831] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 2
>[  103.909842] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.910000] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.910011] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801121
>[  103.910021] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.910030] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.910039] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.910050] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.910070] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000022
>[  103.910077] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.910085] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.910091] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.910235] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.910649] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.910848] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.910859] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01811777
>[  103.910869] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.910879] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.910888] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.910900] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 17 81 01 88 88
>[  103.910909] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 10 00
>[  103.910931] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 10 00
>[  103.910952] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 10 00
>[  103.910973] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 10 00
>[  103.910993] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.911015] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x10101010
>[  103.911022] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.911029] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.911036] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.911207] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.911622] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.911821] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.911831] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817777
>[  103.911841] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.911851] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.911860] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.911872] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 77 81 01 88 88
>[  103.911881] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 10 00
>[  103.911903] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 10 00
>[  103.911924] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 10 00
>[  103.911945] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 10 00
>[  103.911965] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.911986] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x10101010
>[  103.911993] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.911999] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.912006] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.912175] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.912187] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 0
>[  103.912198] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.912356] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.912367] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817722
>[  103.912377] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.912386] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.912396] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.912407] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.912430] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.912437] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.912444] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.912451] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.912596] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.912611] nouveau T[   VBIOS][0000:02:00.0] 0xbddb[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00001000
>[  103.912622] nouveau T[   VBIOS][0000:02:00.0] 0xbde8[0]: AUXCH	AUX[0x00000102] 0x01
>[  103.912631] nouveau T[   VBIOS][0000:02:00.0] 0xbdee[0]: 	AUX[0x00000102] &= 0xdf |= 0x00
>[  103.912640] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.912798] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.912809] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817720
>[  103.912819] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.912828] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.912837] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.912848] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.912869] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.912875] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.912882] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.912889] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.913034] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.913046] nouveau T[   VBIOS][0000:02:00.0] 0xbdf0[0]: DONE
>[  103.913054] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training complete
>[  103.913084] nouveau D[     DRM] plugged DP-1
>[  103.913113] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000100 2
>[  103.913279] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  103.913289] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0181840a
>[  103.913299] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.913309] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.913318] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.913329] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 3
>[  103.913506] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  103.913518] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817777
>[  103.913528] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00018888
>[  103.913537] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.913546] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.913567] nouveau D[     I2C][0000:02:00.0] PAD:S:00: -> PORT:06
>[  103.914667] nouveau D[     I2C][0000:02:00.0] PAD:S:00: -> NULL
>[  103.914673] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000000 8
>[  103.914883] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[  103.914890] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01840a11
>[  103.914896] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.914902] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.914908] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.914915] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[  103.914918] nouveau D[     DRM] encoder: 4x270000
>[  103.914921] nouveau D[     DRM] maximum: 4x270000
>[  103.914929] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 4: 0x00000050 1
>[  103.914945] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.914947] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.914951] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.914953] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.915092] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  103.915098] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 1: 0x00000050 1
>[  103.915250] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[  103.915256] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01840a00
>[  103.915261] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  103.915267] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00060202
>[  103.915272] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.915278] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 4: 0x00000050 1
>[  103.915294] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.915296] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.915300] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.915302] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.915441] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  103.915447] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.915727] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.915733] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xffffff00
>[  103.915738] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00ffffff
>[  103.915743] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x2846f022
>[  103.915749] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.915755] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.916036] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.916042] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x04011520
>[  103.916047] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x781a29a5
>[  103.916052] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xa4c53726
>[  103.916058] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x259b4c55
>[  103.916063] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.916344] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.916349] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xa1545012
>[  103.916355] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x40810008
>[  103.916360] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01018081
>[  103.916365] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01010101
>[  103.916371] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.916651] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.916657] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01010101
>[  103.916662] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x299a0101
>[  103.916667] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x8451d0a0
>[  103.916672] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x98503022
>[  103.916678] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.916958] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.916964] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xff980036
>[  103.916969] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x1c000010
>[  103.916974] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xfd000000
>[  103.916979] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x184c3200
>[  103.916985] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.917265] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.917271] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a010e53
>[  103.917276] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20202020
>[  103.917281] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00002020
>[  103.917286] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x4c00fc00
>[  103.917292] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  103.917573] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  103.917579] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30393141
>[  103.917584] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20200a35
>[  103.917589] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20202020
>[  103.917594] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xff000000
>[  103.917600] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 1: 0x00000050 16
>[  103.917881] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[  103.917886] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x434e4300
>[  103.917892] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30323331
>[  103.917897] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.917902] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.960295] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: HPD: 4
>[  103.960317] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000100 2
>[  103.960482] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  103.960493] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0000840a
>[  103.960503] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.960513] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.960523] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.960535] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 3
>[  103.960714] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  103.960725] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.960735] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.960745] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.960754] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.960765] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: no inter-lane alignment
>[  103.960786] nouveau T[   VBIOS][0000:02:00.0] 0xc000[0]: SUB_DIRECT	0xbd11
>[  103.960796] nouveau T[   VBIOS][0000:02:00.0] 0xbd11[1]: NV_REG	R[0x00e800] &= 0xfffffeff |= 0x00000100
>[  103.960808] nouveau T[   VBIOS][0000:02:00.0] 0xbd1e[1]: NV_REG	R[0x00e820] &= 0xfffffeff |= 0x00000100
>[  103.960820] nouveau T[   VBIOS][0000:02:00.0] 0xbd2b[1]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[  103.960833] nouveau T[   VBIOS][0000:02:00.0] 0xbd38[1]: NV_REG	R[0x6061c128] &= 0x7fffffff |= 0x80000000
>[  103.960845] nouveau T[   VBIOS][0000:02:00.0] 0xbd45[1]: NV_REG	R[0x40614300] &= 0xfcffffff |= 0x03000000
>[  103.960856] nouveau T[   VBIOS][0000:02:00.0] 0xbd52[1]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.960865] nouveau T[   VBIOS][0000:02:00.0] 0xbd5b[1]: ZM_REG	R[0x4061c010] = 0x0060152f
>[  103.960874] nouveau T[   VBIOS][0000:02:00.0] 0xbd64[1]: ZM_REG	R[0x4061c014] = 0x00020000
>[  103.960881] nouveau T[   VBIOS][0000:02:00.0] 0xbd6d[1]: SUB_DIRECT	0x4860
>[  103.960890] nouveau T[   VBIOS][0000:02:00.0] 0x4860[2]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[  103.960901] nouveau T[   VBIOS][0000:02:00.0] 0x486d[2]: TIME	0x0064
>[  103.961009] nouveau T[   VBIOS][0000:02:00.0] 0x4870[2]: CONDITION	0x06
>[  103.961020] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.961033] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[  103.961043] nouveau T[   VBIOS][0000:02:00.0] 0x487f[2]: RESUME
>[  103.961052] nouveau T[   VBIOS][0000:02:00.0] 0x4880[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[  103.961062] nouveau T[   VBIOS][0000:02:00.0] 0x488d[2]: TIME	0x0064
>[  103.961170] nouveau T[   VBIOS][0000:02:00.0] 0x4890[2]: CONDITION	0x06
>[  103.961181] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.961193] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[  103.961203] nouveau T[   VBIOS][0000:02:00.0] 0x489f[2]: RESUME
>[  103.961212] nouveau T[   VBIOS][0000:02:00.0] 0x48a0[2]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[  103.961223] nouveau T[   VBIOS][0000:02:00.0] 0x48ad[2]: TIME	0x0064
>[  103.961331] nouveau T[   VBIOS][0000:02:00.0] 0x48b0[2]: CONDITION	0x06
>[  103.961341] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.961353] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[ ]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[  103.961361] nouveau T[   VBIOS][0000:02:00.0] 0x48bf[ ]: RESUME
>[  103.961371] nouveau T[   VBIOS][0000:02:00.0] 0x48c0[2]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[  103.961380] nouveau T[   VBIOS][0000:02:00.0] 0x48cd[2]: TIME	0x0064
>[  103.961491] nouveau T[   VBIOS][0000:02:00.0] 0x48d0[2]: CONDITION	0x06
>[  103.961502] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  103.961514] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[ ]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[  103.961521] nouveau T[   VBIOS][0000:02:00.0] 0x48df[ ]: RESUME
>[  103.961528] nouveau T[   VBIOS][0000:02:00.0] 0x48e0[2]: DONE
>[  103.961537] nouveau T[   VBIOS][0000:02:00.0] 0xbd70[1]: NV_REG	R[0x40614300] &= 0xfffcffff |= 0x00010000
>[  103.961548] nouveau T[   VBIOS][0000:02:00.0] 0xbd7d[1]: TIME	0x0032
>[  103.961608] nouveau T[   VBIOS][0000:02:00.0] 0xbd80[1]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[  103.961620] nouveau T[   VBIOS][0000:02:00.0] 0xbd8d[1]: NV_REG	R[0x4061c034] &= 0x7feeffff |= 0x80000000
>[  103.961631] nouveau T[   VBIOS][0000:02:00.0] 0xbd9a[1]: TIME	0x000a
>[  103.961649] nouveau T[   VBIOS][0000:02:00.0] 0xbd9d[1]: CONDITION_TIME	0x15 0xff
>[  103.961660] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: 	[0x15] (R[0x4061c034] & 0x80000000) == 0x00000000
>[  103.961672] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[  103.961685] nouveau T[   VBIOS][0000:02:00.0] 0xbdad[1]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00000000
>[  103.961697] nouveau T[   VBIOS][0000:02:00.0] 0xbdba[1]: AUXCH	AUX[0x00000102] 0x01
>[  103.961707] nouveau T[   VBIOS][0000:02:00.0] 0xbdc0[1]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[  103.961716] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.961877] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.961888] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.961897] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.961907] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.961917] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.961928] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.961948] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.961955] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.961962] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.961969] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.962115] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.962128] nouveau T[   VBIOS][0000:02:00.0] 0xbdc2[1]: DP_CONDITION	0x05 0x15
>[  103.962137] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x0000000d 1
>[  103.962297] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.962308] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  103.962317] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.962327] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.962336] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.962348] nouveau T[   VBIOS][0000:02:00.0] 0xbdc5[ ]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[  103.962357] nouveau T[   VBIOS][0000:02:00.0] 0xbdd2[ ]: AUXCH	AUX[0x0000010a] 0x01
>[  103.962366] nouveau T[   VBIOS][0000:02:00.0] 0xbdd8[ ]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[  103.962374] nouveau T[   VBIOS][0000:02:00.0] 0xbdda[ ]: DONE
>[  103.962381] nouveau T[   VBIOS][0000:02:00.0] 0xc003[ ]: DP_CONDITION	0x00 0x08
>[  103.962391] nouveau T[   VBIOS][0000:02:00.0] 0xc006[ ]: SUB_DIRECT	0xc2a1
>[  103.962398] nouveau T[   VBIOS][0000:02:00.0] 0xc009[ ]: NOT
>[  103.962405] nouveau T[   VBIOS][0000:02:00.0] 0xc00a[0]: SUB_DIRECT	0xc2a1
>[  103.962412] nouveau T[   VBIOS][0000:02:00.0] 0xc2a1[1]: DONE
>[  103.962418] nouveau T[   VBIOS][0000:02:00.0] 0xc00d[0]: RESUME
>[  103.962425] nouveau T[   VBIOS][0000:02:00.0] 0xc00e[0]: DONE
>[  103.962434] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: 4 lanes at 270000 KB/s
>[  103.962443] nouveau T[   VBIOS][0000:02:00.0] 0xbdf1[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  103.962450] nouveau T[   VBIOS][0000:02:00.0] 0xbdfa[0]: DONE
>[  103.962483] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000100 2
>[  103.962504] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x0000840a
>[  103.962511] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.962517] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.962524] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.962677] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  103.962689] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 1
>[  103.962700] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.962864] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.962876] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000020
>[  103.962886] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  103.962895] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.962905] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.962916] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.962937] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000021
>[  103.962943] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.962950] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.962957] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.963102] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.963115] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 00 00
>[  103.963138] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 00 00
>[  103.963160] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 00 00
>[  103.963181] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 00 00
>[  103.963201] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.963222] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.963229] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.963236] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.963243] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.963412] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.963526] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.963725] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.963736] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801111
>[  103.963745] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  103.963754] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.963763] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.963775] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 11 11 80 00 00 00
>[  103.963783] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 2
>[  103.963794] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.963983] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.963994] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801121
>[  103.964003] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  103.964012] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.964022] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.964033] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.964056] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000022
>[  103.964062] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.964068] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.964075] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.964224] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.964638] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.964838] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.964852] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01811777
>[  103.964862] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.964872] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.964881] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.964893] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 17 81 01 88 88
>[  103.964902] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 10 00
>[  103.964924] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 10 00
>[  103.964945] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 10 00
>[  103.964966] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 10 00
>[  103.964986] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.965007] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x10101010
>[  103.965013] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.965023] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.965029] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.965200] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.965613] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  103.965814] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  103.965824] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817777
>[  103.965833] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.965843] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.965853] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.965865] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 77 81 01 88 88
>[  103.965874] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 10 00
>[  103.965896] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 10 00
>[  103.965916] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 10 00
>[  103.965937] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 10 00
>[  103.965957] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  103.965977] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x10101010
>[  103.965984] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.965991] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.965997] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.966169] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  103.966181] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 0
>[  103.966193] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.966352] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.966363] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817722
>[  103.966372] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.966385] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.966395] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.966406] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.966426] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  103.966433] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.966440] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.966447] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.966592] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.966607] nouveau T[   VBIOS][0000:02:00.0] 0xbddb[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00001000
>[  103.966618] nouveau T[   VBIOS][0000:02:00.0] 0xbde8[0]: AUXCH	AUX[0x00000102] 0x01
>[  103.966627] nouveau T[   VBIOS][0000:02:00.0] 0xbdee[0]: 	AUX[0x00000102] &= 0xdf |= 0x00
>[  103.966636] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  103.966794] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  103.966805] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817720
>[  103.966815] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30328888
>[  103.966824] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  103.966834] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  103.966846] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  103.966868] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.966875] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.966881] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.966888] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  103.967037] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  103.967048] nouveau T[   VBIOS][0000:02:00.0] 0xbdf0[0]: DONE
>[  103.967056] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training complete
>[  104.044706] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: HPD: 4
>[  104.044755] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000100 2
>[  104.044924] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  104.044934] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0000840a
>[  104.044944] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  104.044953] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.044963] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.044974] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 3
>[  104.045149] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  104.045160] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  104.045170] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  104.045180] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.045189] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.045200] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: no inter-lane alignment
>[  104.045221] nouveau T[   VBIOS][0000:02:00.0] 0xc000[0]: SUB_DIRECT	0xbd11
>[  104.045232] nouveau T[   VBIOS][0000:02:00.0] 0xbd11[1]: NV_REG	R[0x00e800] &= 0xfffffeff |= 0x00000100
>[  104.045244] nouveau T[   VBIOS][0000:02:00.0] 0xbd1e[1]: NV_REG	R[0x00e820] &= 0xfffffeff |= 0x00000100
>[  104.045256] nouveau T[   VBIOS][0000:02:00.0] 0xbd2b[1]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[  104.045268] nouveau T[   VBIOS][0000:02:00.0] 0xbd38[1]: NV_REG	R[0x6061c128] &= 0x7fffffff |= 0x80000000
>[  104.045280] nouveau T[   VBIOS][0000:02:00.0] 0xbd45[1]: NV_REG	R[0x40614300] &= 0xfcffffff |= 0x03000000
>[  104.045292] nouveau T[   VBIOS][0000:02:00.0] 0xbd52[1]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  104.045301] nouveau T[   VBIOS][0000:02:00.0] 0xbd5b[1]: ZM_REG	R[0x4061c010] = 0x0060152f
>[  104.045309] nouveau T[   VBIOS][0000:02:00.0] 0xbd64[1]: ZM_REG	R[0x4061c014] = 0x00020000
>[  104.045317] nouveau T[   VBIOS][0000:02:00.0] 0xbd6d[1]: SUB_DIRECT	0x4860
>[  104.045326] nouveau T[   VBIOS][0000:02:00.0] 0x4860[2]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[  104.045339] nouveau T[   VBIOS][0000:02:00.0] 0x486d[2]: TIME	0x0064
>[  104.045448] nouveau T[   VBIOS][0000:02:00.0] 0x4870[2]: CONDITION	0x06
>[  104.045459] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  104.045472] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[  104.045483] nouveau T[   VBIOS][0000:02:00.0] 0x487f[2]: RESUME
>[  104.045491] nouveau T[   VBIOS][0000:02:00.0] 0x4880[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[  104.045504] nouveau T[   VBIOS][0000:02:00.0] 0x488d[2]: TIME	0x0064
>[  104.045612] nouveau T[   VBIOS][0000:02:00.0] 0x4890[2]: CONDITION	0x06
>[  104.045623] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  104.045636] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[  104.045646] nouveau T[   VBIOS][0000:02:00.0] 0x489f[2]: RESUME
>[  104.045655] nouveau T[   VBIOS][0000:02:00.0] 0x48a0[2]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[  104.045665] nouveau T[   VBIOS][0000:02:00.0] 0x48ad[2]: TIME	0x0064
>[  104.045773] nouveau T[   VBIOS][0000:02:00.0] 0x48b0[2]: CONDITION	0x06
>[  104.045783] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  104.045795] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[ ]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[  104.045803] nouveau T[   VBIOS][0000:02:00.0] 0x48bf[ ]: RESUME
>[  104.045812] nouveau T[   VBIOS][0000:02:00.0] 0x48c0[2]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[  104.045823] nouveau T[   VBIOS][0000:02:00.0] 0x48cd[2]: TIME	0x0064
>[  104.045933] nouveau T[   VBIOS][0000:02:00.0] 0x48d0[2]: CONDITION	0x06
>[  104.045944] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  104.045956] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[ ]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[  104.045963] nouveau T[   VBIOS][0000:02:00.0] 0x48df[ ]: RESUME
>[  104.045970] nouveau T[   VBIOS][0000:02:00.0] 0x48e0[2]: DONE
>[  104.045979] nouveau T[   VBIOS][0000:02:00.0] 0xbd70[1]: NV_REG	R[0x40614300] &= 0xfffcffff |= 0x00010000
>[  104.045989] nouveau T[   VBIOS][0000:02:00.0] 0xbd7d[1]: TIME	0x0032
>[  104.046049] nouveau T[   VBIOS][0000:02:00.0] 0xbd80[1]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[  104.046062] nouveau T[   VBIOS][0000:02:00.0] 0xbd8d[1]: NV_REG	R[0x4061c034] &= 0x7feeffff |= 0x80000000
>[  104.046072] nouveau T[   VBIOS][0000:02:00.0] 0xbd9a[1]: TIME	0x000a
>[  104.046091] nouveau T[   VBIOS][0000:02:00.0] 0xbd9d[1]: CONDITION_TIME	0x15 0xff
>[  104.046101] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: 	[0x15] (R[0x4061c034] & 0x80000000) == 0x00000000
>[  104.046113] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[  104.046125] nouveau T[   VBIOS][0000:02:00.0] 0xbdad[1]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00000000
>[  104.046137] nouveau T[   VBIOS][0000:02:00.0] 0xbdba[1]: AUXCH	AUX[0x00000102] 0x01
>[  104.046146] nouveau T[   VBIOS][0000:02:00.0] 0xbdc0[1]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[  104.046158] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  104.046316] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  104.046327] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  104.046336] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  104.046346] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.046355] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.046367] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  104.046387] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  104.046394] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.046400] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.046407] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.046553] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  104.046559] nouveau T[   VBIOS][0000:02:00.0] 0xbdc2[1]: DP_CONDITION	0x05 0x15
>[  104.046563] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x0000000d 1
>[  104.046721] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  104.046732] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  104.046742] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  104.046752] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.046761] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.046774] nouveau T[   VBIOS][0000:02:00.0] 0xbdc5[ ]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[  104.046783] nouveau T[   VBIOS][0000:02:00.0] 0xbdd2[ ]: AUXCH	AUX[0x0000010a] 0x01
>[  104.046792] nouveau T[   VBIOS][0000:02:00.0] 0xbdd8[ ]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[  104.046800] nouveau T[   VBIOS][0000:02:00.0] 0xbdda[ ]: DONE
>[  104.046808] nouveau T[   VBIOS][0000:02:00.0] 0xc003[ ]: DP_CONDITION	0x00 0x08
>[  104.046815] nouveau T[   VBIOS][0000:02:00.0] 0xc006[ ]: SUB_DIRECT	0xc2a1
>[  104.046822] nouveau T[   VBIOS][0000:02:00.0] 0xc009[ ]: NOT
>[  104.046830] nouveau T[   VBIOS][0000:02:00.0] 0xc00a[0]: SUB_DIRECT	0xc2a1
>[  104.046836] nouveau T[   VBIOS][0000:02:00.0] 0xc2a1[1]: DONE
>[  104.046843] nouveau T[   VBIOS][0000:02:00.0] 0xc00d[0]: RESUME
>[  104.046849] nouveau T[   VBIOS][0000:02:00.0] 0xc00e[0]: DONE
>[  104.046858] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: 4 lanes at 270000 KB/s
>[  104.046867] nouveau T[   VBIOS][0000:02:00.0] 0xbdf1[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  104.046874] nouveau T[   VBIOS][0000:02:00.0] 0xbdfa[0]: DONE
>[  104.046911] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000100 2
>[  104.046932] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x0000840a
>[  104.046938] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.046945] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.046951] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.047105] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  104.047118] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 1
>[  104.047129] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  104.047287] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  104.047298] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000020
>[  104.047307] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  104.047316] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.047326] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.047337] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  104.047357] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000021
>[  104.047363] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.047370] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.047376] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.047522] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  104.047535] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 00 00
>[  104.047558] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 00 00
>[  104.047578] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 00 00
>[  104.047599] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 00 00
>[  104.047619] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  104.047639] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.047646] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.047653] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.047660] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.047832] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  104.047947] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  104.048144] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  104.048156] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801111
>[  104.048165] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  104.048175] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.048184] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.048196] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 11 11 80 00 00 00
>[  104.048204] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 2
>[  104.048217] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  104.048375] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  104.048386] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801121
>[  104.048395] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  104.048404] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.048414] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.048425] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  104.048445] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000022
>[  104.048452] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.048458] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.048465] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.048610] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  104.049024] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  104.049225] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  104.049236] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817777
>[  104.049245] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30324444
>[  104.049255] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.049265] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.049276] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 77 81 01 44 44
>[  104.049285] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 08 00
>[  104.049307] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 08 00
>[  104.049328] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 08 00
>[  104.049349] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 08 00
>[  104.049368] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  104.049388] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x08080808
>[  104.049395] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.049402] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.049408] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.049577] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  104.049590] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 0
>[  104.049602] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  104.049759] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  104.049770] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817722
>[  104.049782] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30324444
>[  104.049792] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.049801] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.049813] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  104.049834] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  104.049841] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.049848] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.049854] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.049999] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  104.050013] nouveau T[   VBIOS][0000:02:00.0] 0xbddb[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00001000
>[  104.050024] nouveau T[   VBIOS][0000:02:00.0] 0xbde8[0]: AUXCH	AUX[0x00000102] 0x01
>[  104.050033] nouveau T[   VBIOS][0000:02:00.0] 0xbdee[0]: 	AUX[0x00000102] &= 0xdf |= 0x00
>[  104.050042] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  104.050200] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  104.050210] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817720
>[  104.050220] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30324444
>[  104.050229] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.050239] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.050250] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  104.050271] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.050278] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.050285] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.050292] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.050436] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  104.050447] nouveau T[   VBIOS][0000:02:00.0] 0xbdf0[0]: DONE
>[  104.050455] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training complete
>[  104.102580] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: HPD: 4
>[  104.102620] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000100 2
>[  104.102790] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  104.102801] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0000840a
>[  104.102811] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  104.102820] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.102831] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.102844] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 3
>[  104.103017] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  104.103028] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  104.103037] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  104.103047] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.103056] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.103067] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: no inter-lane alignment
>[  104.103087] nouveau T[   VBIOS][0000:02:00.0] 0xc000[0]: SUB_DIRECT	0xbd11
>[  104.103097] nouveau T[   VBIOS][0000:02:00.0] 0xbd11[1]: NV_REG	R[0x00e800] &= 0xfffffeff |= 0x00000100
>[  104.103109] nouveau T[   VBIOS][0000:02:00.0] 0xbd1e[1]: NV_REG	R[0x00e820] &= 0xfffffeff |= 0x00000100
>[  104.103121] nouveau T[   VBIOS][0000:02:00.0] 0xbd2b[1]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[  104.103134] nouveau T[   VBIOS][0000:02:00.0] 0xbd38[1]: NV_REG	R[0x6061c128] &= 0x7fffffff |= 0x80000000
>[  104.103145] nouveau T[   VBIOS][0000:02:00.0] 0xbd45[1]: NV_REG	R[0x40614300] &= 0xfcffffff |= 0x03000000
>[  104.103157] nouveau T[   VBIOS][0000:02:00.0] 0xbd52[1]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  104.103165] nouveau T[   VBIOS][0000:02:00.0] 0xbd5b[1]: ZM_REG	R[0x4061c010] = 0x0060152f
>[  104.103173] nouveau T[   VBIOS][0000:02:00.0] 0xbd64[1]: ZM_REG	R[0x4061c014] = 0x00020000
>[  104.103181] nouveau T[   VBIOS][0000:02:00.0] 0xbd6d[1]: SUB_DIRECT	0x4860
>[  104.103191] nouveau T[   VBIOS][0000:02:00.0] 0x4860[2]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[  104.103201] nouveau T[   VBIOS][0000:02:00.0] 0x486d[2]: TIME	0x0064
>[  104.103310] nouveau T[   VBIOS][0000:02:00.0] 0x4870[2]: CONDITION	0x06
>[  104.103323] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  104.103335] nouveau T[   VBIOS][0000:02:00.0] 0x4872[2]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[  104.103345] nouveau T[   VBIOS][0000:02:00.0] 0x487f[2]: RESUME
>[  104.103354] nouveau T[   VBIOS][0000:02:00.0] 0x4880[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[  104.103364] nouveau T[   VBIOS][0000:02:00.0] 0x488d[2]: TIME	0x0064
>[  104.103473] nouveau T[   VBIOS][0000:02:00.0] 0x4890[2]: CONDITION	0x06
>[  104.103483] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  104.103495] nouveau T[   VBIOS][0000:02:00.0] 0x4892[2]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[  104.103505] nouveau T[   VBIOS][0000:02:00.0] 0x489f[2]: RESUME
>[  104.103515] nouveau T[   VBIOS][0000:02:00.0] 0x48a0[2]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[  104.103526] nouveau T[   VBIOS][0000:02:00.0] 0x48ad[2]: TIME	0x0064
>[  104.103634] nouveau T[   VBIOS][0000:02:00.0] 0x48b0[2]: CONDITION	0x06
>[  104.103645] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  104.103657] nouveau T[   VBIOS][0000:02:00.0] 0x48b2[ ]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[  104.103664] nouveau T[   VBIOS][0000:02:00.0] 0x48bf[ ]: RESUME
>[  104.103674] nouveau T[   VBIOS][0000:02:00.0] 0x48c0[2]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[  104.103684] nouveau T[   VBIOS][0000:02:00.0] 0x48cd[2]: TIME	0x0064
>[  104.103792] nouveau T[   VBIOS][0000:02:00.0] 0x48d0[2]: CONDITION	0x06
>[  104.103803] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[2]: 	[0x06] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  104.103815] nouveau T[   VBIOS][0000:02:00.0] 0x48d2[ ]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[  104.103822] nouveau T[   VBIOS][0000:02:00.0] 0x48df[ ]: RESUME
>[  104.103829] nouveau T[   VBIOS][0000:02:00.0] 0x48e0[2]: DONE
>[  104.103838] nouveau T[   VBIOS][0000:02:00.0] 0xbd70[1]: NV_REG	R[0x40614300] &= 0xfffcffff |= 0x00010000
>[  104.103848] nouveau T[   VBIOS][0000:02:00.0] 0xbd7d[1]: TIME	0x0032
>[  104.103929] nouveau T[   VBIOS][0000:02:00.0] 0xbd80[1]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[  104.103942] nouveau T[   VBIOS][0000:02:00.0] 0xbd8d[1]: NV_REG	R[0x4061c034] &= 0x7feeffff |= 0x80000000
>[  104.103952] nouveau T[   VBIOS][0000:02:00.0] 0xbd9a[1]: TIME	0x000a
>[  104.103971] nouveau T[   VBIOS][0000:02:00.0] 0xbd9d[1]: CONDITION_TIME	0x15 0xff
>[  104.103982] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: 	[0x15] (R[0x4061c034] & 0x80000000) == 0x00000000
>[  104.103994] nouveau T[   VBIOS][0000:02:00.0] 0xbda0[1]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[  104.104006] nouveau T[   VBIOS][0000:02:00.0] 0xbdad[1]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00000000
>[  104.104017] nouveau T[   VBIOS][0000:02:00.0] 0xbdba[1]: AUXCH	AUX[0x00000102] 0x01
>[  104.104026] nouveau T[   VBIOS][0000:02:00.0] 0xbdc0[1]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[  104.104035] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  104.104192] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  104.104203] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  104.104213] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  104.104223] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.104234] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.104246] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  104.104266] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  104.104273] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.104280] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.104287] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.104431] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  104.104444] nouveau T[   VBIOS][0000:02:00.0] 0xbdc2[1]: DP_CONDITION	0x05 0x15
>[  104.104452] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x0000000d 1
>[  104.104611] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  104.104622] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  104.104631] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  104.104641] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.104651] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.104663] nouveau T[   VBIOS][0000:02:00.0] 0xbdc5[ ]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[  104.104671] nouveau T[   VBIOS][0000:02:00.0] 0xbdd2[ ]: AUXCH	AUX[0x0000010a] 0x01
>[  104.104680] nouveau T[   VBIOS][0000:02:00.0] 0xbdd8[ ]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[  104.104688] nouveau T[   VBIOS][0000:02:00.0] 0xbdda[ ]: DONE
>[  104.104695] nouveau T[   VBIOS][0000:02:00.0] 0xc003[ ]: DP_CONDITION	0x00 0x08
>[  104.104703] nouveau T[   VBIOS][0000:02:00.0] 0xc006[ ]: SUB_DIRECT	0xc2a1
>[  104.104710] nouveau T[   VBIOS][0000:02:00.0] 0xc009[ ]: NOT
>[  104.104717] nouveau T[   VBIOS][0000:02:00.0] 0xc00a[0]: SUB_DIRECT	0xc2a1
>[  104.104724] nouveau T[   VBIOS][0000:02:00.0] 0xc2a1[1]: DONE
>[  104.104732] nouveau T[   VBIOS][0000:02:00.0] 0xc00d[0]: RESUME
>[  104.104738] nouveau T[   VBIOS][0000:02:00.0] 0xc00e[0]: DONE
>[  104.104748] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: 4 lanes at 270000 KB/s
>[  104.104757] nouveau T[   VBIOS][0000:02:00.0] 0xbdf1[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  104.104764] nouveau T[   VBIOS][0000:02:00.0] 0xbdfa[0]: DONE
>[  104.104796] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000100 2
>[  104.104816] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x0000840a
>[  104.104823] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.104830] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.104837] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.104992] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  104.105005] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 1
>[  104.105016] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  104.105173] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  104.105184] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000020
>[  104.105194] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320080
>[  104.105204] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.105213] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.105228] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  104.105248] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000021
>[  104.105255] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.105262] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.105269] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.105417] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  104.105430] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 00 00
>[  104.105453] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 00 00
>[  104.105473] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 00 00
>[  104.105494] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 00 00
>[  104.105514] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  104.105535] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.105542] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.105549] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.105556] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.105723] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  104.105830] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  104.106031] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  104.106042] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801111
>[  104.106051] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  104.106061] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.106070] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.106083] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 11 11 80 00 00 00
>[  104.106091] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 2
>[  104.106102] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  104.106259] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  104.106269] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00801121
>[  104.106278] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  104.106288] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.106297] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.106308] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  104.106329] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000022
>[  104.106336] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.106346] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.106353] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.106497] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  104.106911] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000202 6
>[  104.107113] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  104.107124] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817777
>[  104.107134] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  104.107143] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.107152] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.107164] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: status 77 77 81 01 00 00
>[  104.107173] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 0 00 00
>[  104.107195] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 1 00 00
>[  104.107215] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 2 00 00
>[  104.107236] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: config lane 3 00 00
>[  104.107256] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000103 4
>[  104.107277] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.107284] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.107291] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.107298] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.107469] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  104.107482] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training pattern 0
>[  104.107493] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  104.107653] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  104.107663] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817722
>[  104.107673] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  104.107683] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.107692] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.107704] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  104.107725] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000020
>[  104.107734] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.107740] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.107747] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.107895] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  104.107909] nouveau T[   VBIOS][0000:02:00.0] 0xbddb[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00001000
>[  104.107921] nouveau T[   VBIOS][0000:02:00.0] 0xbde8[0]: AUXCH	AUX[0x00000102] 0x01
>[  104.107930] nouveau T[   VBIOS][0000:02:00.0] 0xbdee[0]: 	AUX[0x00000102] &= 0xdf |= 0x00
>[  104.107939] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000102 1
>[  104.108097] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  104.108107] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01817720
>[  104.108116] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30320000
>[  104.108126] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  104.108135] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  104.108146] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 8: 0x00000102 1
>[  104.108167] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.108174] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.108181] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.108187] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  104.108333] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  104.108345] nouveau T[   VBIOS][0000:02:00.0] 0xbdf0[0]: DONE
>[  104.108352] nouveau D[   PDISP][0000:02:00.0] 02:0006:0344: training complete
>[  112.020787] nouveau D[     I2C][0000:02:00.0] PAD:X:03: -> PORT:02
>[  112.021737] nouveau D[     I2C][0000:02:00.0] PAD:X:03: -> NULL
>[  112.021739] nouveau D[     I2C][0000:02:00.0] PAD:X:03: -> PORT:02
>[  112.022685] nouveau D[     I2C][0000:02:00.0] PAD:X:03: -> NULL
>[  112.022686] nouveau D[     I2C][0000:02:00.0] PAD:X:03: -> PORT:02
>[  112.052952] nouveau D[     I2C][0000:02:00.0] PAD:X:03: -> NULL
>[  112.054316] nouveau D[     DRM] native mode from preferred
>[  112.054399] nouveau D[     I2C][0000:02:00.0] PAD:S:00: -> PORT:06
>[  112.055465] nouveau D[     I2C][0000:02:00.0] PAD:S:00: -> NULL
>[  112.055474] nouveau D[     I2C][0000:02:00.0] PAD:S:00: -> PORT:06
>[  112.056537] nouveau D[     I2C][0000:02:00.0] PAD:S:00: -> NULL
>[  112.056548] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 9: 0x00000000 8
>[  112.056755] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[  112.056759] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01840a11
>[  112.056764] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  112.056768] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  112.056772] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  112.056777] nouveau D[     DRM] display: 4x270000 dpcd 0x11
>[  112.056778] nouveau D[     DRM] encoder: 4x270000
>[  112.056780] nouveau D[     DRM] maximum: 4x270000
>[  112.056782] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 4: 0x00000050 1
>[  112.056796] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  112.056798] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  112.056799] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  112.056801] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  112.056939] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  112.056942] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 1: 0x00000050 1
>[  112.057091] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[  112.057094] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01840a00
>[  112.057098] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00010000
>[  112.057102] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  112.057106] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  112.057111] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 4: 0x00000050 1
>[  112.057124] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  112.057126] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  112.057127] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  112.057129] nouveau D[     I2C][0000:02:00.0] AUXCH(1): wr 0x00000000
>[  112.057267] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  112.057271] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  112.057547] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  112.057550] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xffffff00
>[  112.057554] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00ffffff
>[  112.057558] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x2846f022
>[  112.057562] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00000000
>[  112.057567] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  112.057843] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  112.057845] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x04011520
>[  112.057849] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x781a29a5
>[  112.057853] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xa4c53726
>[  112.057857] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x259b4c55
>[  112.057862] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  112.058138] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  112.058140] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xa1545012
>[  112.058144] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x40810008
>[  112.058148] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01018081
>[  112.058152] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01010101
>[  112.058156] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  112.058433] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  112.058435] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x01010101
>[  112.058439] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x299a0101
>[  112.058443] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x8451d0a0
>[  112.058447] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x98503022
>[  112.058452] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  112.058729] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  112.058732] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xff980036
>[  112.058736] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x1c000010
>[  112.058740] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xfd000000
>[  112.058744] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x184c3200
>[  112.058749] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  112.059025] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  112.059028] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a010e53
>[  112.059031] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20202020
>[  112.059035] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x00002020
>[  112.059039] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x4c00fc00
>[  112.059044] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 5: 0x00000050 16
>[  112.059319] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  112.059322] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30393141
>[  112.059326] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20200a35
>[  112.059330] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x20202020
>[  112.059334] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xff000000
>[  112.059338] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 1: 0x00000050 16
>[  112.059615] nouveau D[     I2C][0000:02:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[  112.059618] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x434e4300
>[  112.059622] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x30323331
>[  112.059626] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0x0a353736
>[  112.059630] nouveau D[     I2C][0000:02:00.0] AUXCH(1): rd 0xf7002020
>[  112.059639] nouveau D[     DRM] native mode from preferred
>[  116.061527] ath5k: ath5k_hw_get_isr: ISR: 0x00000080 IMR: 0x00000000
>[  145.077287] nouveau D[   PDISP][0000:02:00.0] supervisor 0x00000010 0x000000a0
>[  145.077290] nouveau D[   PDISP][0000:02:00.0] Core:
>[  145.077298] nouveau D[   PDISP][0000:02:00.0] 	0x0084: 0x019e02e2 -> 0x00000000
>[  145.077305] nouveau D[   PDISP][0000:02:00.0] 	0x0088: 0xcafe0000              
>[  145.077308] nouveau D[   PDISP][0000:02:00.0] Core - DAC 0:
>[  145.077315] nouveau D[   PDISP][0000:02:00.0] 	0x0400: 0x00000000              
>[  145.077322] nouveau D[   PDISP][0000:02:00.0] 	0x0404: 0x00000000              
>[  145.077328] nouveau D[   PDISP][0000:02:00.0] 	0x0420: 0x00010000              
>[  145.077330] nouveau D[   PDISP][0000:02:00.0] Core - DAC 1:
>[  145.077337] nouveau D[   PDISP][0000:02:00.0] 	0x0480: 0x00000000              
>[  145.077344] nouveau D[   PDISP][0000:02:00.0] 	0x0484: 0x00000000              
>[  145.077351] nouveau D[   PDISP][0000:02:00.0] 	0x04a0: 0x00010000              
>[  145.077353] nouveau D[   PDISP][0000:02:00.0] Core - DAC 2:
>[  145.077360] nouveau D[   PDISP][0000:02:00.0] 	0x0500: 0x00000000              
>[  145.077367] nouveau D[   PDISP][0000:02:00.0] 	0x0504: 0x00000000              
>[  145.077373] nouveau D[   PDISP][0000:02:00.0] 	0x0520: 0x00010000              
>[  145.077375] nouveau D[   PDISP][0000:02:00.0] Core - SOR 0:
>[  145.077383] nouveau D[   PDISP][0000:02:00.0] 	0x0600: 0x00003000 -> 0x00003001
>[  145.077385] nouveau D[   PDISP][0000:02:00.0] Core - SOR 1:
>[  145.077392] nouveau D[   PDISP][0000:02:00.0] 	0x0640: 0x00000000              
>[  145.077394] nouveau D[   PDISP][0000:02:00.0] Core - SOR 2:
>[  145.077401] nouveau D[   PDISP][0000:02:00.0] 	0x0680: 0x00051802              
>[  145.077403] nouveau D[   PDISP][0000:02:00.0] Core - SOR 3:
>[  145.077409] nouveau D[   PDISP][0000:02:00.0] 	0x06c0: 0x00000000              
>[  145.077412] nouveau D[   PDISP][0000:02:00.0] Core - PIOR 0:
>[  145.077418] nouveau D[   PDISP][0000:02:00.0] 	0x0700: 0x00000000              
>[  145.077420] nouveau D[   PDISP][0000:02:00.0] Core - PIOR 1:
>[  145.077427] nouveau D[   PDISP][0000:02:00.0] 	0x0740: 0x00000000              
>[  145.077429] nouveau D[   PDISP][0000:02:00.0] Core - PIOR 2:
>[  145.077436] nouveau D[   PDISP][0000:02:00.0] 	0x0780: 0x00000000              
>[  145.077438] nouveau D[   PDISP][0000:02:00.0] Core - HEAD 0:
>[  145.077445] nouveau D[   PDISP][0000:02:00.0] 	0x0800: 0x00000000              
>[  145.077452] nouveau D[   PDISP][0000:02:00.0] 	0x0804: 0x00811558              
>[  145.077457] nouveau D[   PDISP][0000:02:00.0] 	0x0808: 0x00000000              
>[  145.077463] nouveau D[   PDISP][0000:02:00.0] 	0x080c: 0x00000000              
>[  145.077469] nouveau D[   PDISP][0000:02:00.0] 	0x0810: 0x00000000              
>[  145.077475] nouveau D[   PDISP][0000:02:00.0] 	0x0814: 0x031605da              
>[  145.077481] nouveau D[   PDISP][0000:02:00.0] 	0x0818: 0x0003001f              
>[  145.077487] nouveau D[   PDISP][0000:02:00.0] 	0x081c: 0x00140053              
>[  145.077492] nouveau D[   PDISP][0000:02:00.0] 	0x0820: 0x031405a9              
>[  145.077498] nouveau D[   PDISP][0000:02:00.0] 	0x0824: 0x00000001              
>[  145.077504] nouveau D[   PDISP][0000:02:00.0] 	0x0828: 0x00000000              
>[  145.077510] nouveau D[   PDISP][0000:02:00.0] 	0x082c: 0x00000000              
>[  145.077515] nouveau D[   PDISP][0000:02:00.0] 	0x0830: 0x00000000              
>[  145.077521] nouveau D[   PDISP][0000:02:00.0] 	0x0838: 0x00000000              
>[  145.077527] nouveau D[   PDISP][0000:02:00.0] 	0x0840: 0x40000000 -> 0xc0000000
>[  145.077533] nouveau D[   PDISP][0000:02:00.0] 	0x0844: 0x00000410              
>[  145.077539] nouveau D[   PDISP][0000:02:00.0] 	0x0848: 0x00000000              
>[  145.077545] nouveau D[   PDISP][0000:02:00.0] 	0x084c: 0x00000000              
>[  145.077551] nouveau D[   PDISP][0000:02:00.0] 	0x085c: 0x00000000 -> 0x01000000
>[  145.077557] nouveau D[   PDISP][0000:02:00.0] 	0x0860: 0x00005a00 -> 0x00000600
>[  145.077562] nouveau D[   PDISP][0000:02:00.0] 	0x0864: 0x00000000              
>[  145.077568] nouveau D[   PDISP][0000:02:00.0] 	0x0868: 0x03000400 -> 0x038405a0
>[  145.077574] nouveau D[   PDISP][0000:02:00.0] 	0x086c: 0x00004004 -> 0x00101700
>[  145.077580] nouveau D[   PDISP][0000:02:00.0] 	0x0870: 0x0000cf00              
>[  145.077586] nouveau D[   PDISP][0000:02:00.0] 	0x0874: 0x00000000 -> 0x01000003
>[  145.077592] nouveau D[   PDISP][0000:02:00.0] 	0x0878: 0x00000000              
>[  145.077598] nouveau D[   PDISP][0000:02:00.0] 	0x0880: 0x05000000              
>[  145.077604] nouveau D[   PDISP][0000:02:00.0] 	0x0884: 0x00000430              
>[  145.077610] nouveau D[   PDISP][0000:02:00.0] 	0x089c: 0x00000000              
>[  145.077616] nouveau D[   PDISP][0000:02:00.0] 	0x08a0: 0x00000011              
>[  145.077622] nouveau D[   PDISP][0000:02:00.0] 	0x08a4: 0x00000000              
>[  145.077627] nouveau D[   PDISP][0000:02:00.0] 	0x08a8: 0x00040000              
>[  145.077633] nouveau D[   PDISP][0000:02:00.0] 	0x08c0: 0x00000000              
>[  145.077640] nouveau D[   PDISP][0000:02:00.0] 	0x08c4: 0x00000000              
>[  145.077646] nouveau D[   PDISP][0000:02:00.0] 	0x08c8: 0x03000400 -> 0x03000556
>[  145.077652] nouveau D[   PDISP][0000:02:00.0] 	0x08d4: 0x00000000              
>[  145.077658] nouveau D[   PDISP][0000:02:00.0] 	0x08d8: 0x03000556              
>[  145.077663] nouveau D[   PDISP][0000:02:00.0] 	0x08dc: 0x03000556              
>[  145.077669] nouveau D[   PDISP][0000:02:00.0] 	0x0900: 0x00000311              
>[  145.077675] nouveau D[   PDISP][0000:02:00.0] 	0x0904: 0x00000100              
>[  145.077681] nouveau D[   PDISP][0000:02:00.0] 	0x0910: 0x00000000              
>[  145.077687] nouveau D[   PDISP][0000:02:00.0] 	0x0914: 0x00000000              
>[  145.077688] nouveau D[   PDISP][0000:02:00.0] Core - HEAD 1:
>[  145.077694] nouveau D[   PDISP][0000:02:00.0] 	0x0c00: 0x00000000              
>[  145.077699] nouveau D[   PDISP][0000:02:00.0] 	0x0c04: 0x0081a004              
>[  145.077705] nouveau D[   PDISP][0000:02:00.0] 	0x0c08: 0x00000000              
>[  145.077712] nouveau D[   PDISP][0000:02:00.0] 	0x0c0c: 0x00000000              
>[  145.077717] nouveau D[   PDISP][0000:02:00.0] 	0x0c10: 0x00000000              
>[  145.077723] nouveau D[   PDISP][0000:02:00.0] 	0x0c14: 0x03a60770              
>[  145.077729] nouveau D[   PDISP][0000:02:00.0] 	0x0c18: 0x00050097              
>[  145.077735] nouveau D[   PDISP][0000:02:00.0] 	0x0c1c: 0x001e017f              
>[  145.077741] nouveau D[   PDISP][0000:02:00.0] 	0x0c20: 0x03a2071f              
>[  145.077746] nouveau D[   PDISP][0000:02:00.0] 	0x0c24: 0x00000001              
>[  145.077752] nouveau D[   PDISP][0000:02:00.0] 	0x0c28: 0x00000000              
>[  145.077758] nouveau D[   PDISP][0000:02:00.0] 	0x0c2c: 0x00000000              
>[  145.077764] nouveau D[   PDISP][0000:02:00.0] 	0x0c30: 0x00000000              
>[  145.077770] nouveau D[   PDISP][0000:02:00.0] 	0x0c38: 0x00000000              
>[  145.077776] nouveau D[   PDISP][0000:02:00.0] 	0x0c40: 0xc0000000              
>[  145.077782] nouveau D[   PDISP][0000:02:00.0] 	0x0c44: 0x00000470              
>[  145.077788] nouveau D[   PDISP][0000:02:00.0] 	0x0c48: 0x00000000              
>[  145.077794] nouveau D[   PDISP][0000:02:00.0] 	0x0c4c: 0x00000000              
>[  145.077800] nouveau D[   PDISP][0000:02:00.0] 	0x0c5c: 0x01000000              
>[  145.077805] nouveau D[   PDISP][0000:02:00.0] 	0x0c60: 0x0001a600              
>[  145.077811] nouveau D[   PDISP][0000:02:00.0] 	0x0c64: 0x00000000              
>[  145.077817] nouveau D[   PDISP][0000:02:00.0] 	0x0c68: 0x038405a0              
>[  145.077823] nouveau D[   PDISP][0000:02:00.0] 	0x0c6c: 0x00005a04              
>[  145.077828] nouveau D[   PDISP][0000:02:00.0] 	0x0c70: 0x0000cf00              
>[  145.077834] nouveau D[   PDISP][0000:02:00.0] 	0x0c74: 0x01000002              
>[  145.077840] nouveau D[   PDISP][0000:02:00.0] 	0x0c78: 0x00000000              
>[  145.077846] nouveau D[   PDISP][0000:02:00.0] 	0x0c80: 0x05000000              
>[  145.077852] nouveau D[   PDISP][0000:02:00.0] 	0x0c84: 0x00000490              
>[  145.077857] nouveau D[   PDISP][0000:02:00.0] 	0x0c9c: 0x00000000              
>[  145.077863] nouveau D[   PDISP][0000:02:00.0] 	0x0ca0: 0x00000002              
>[  145.077869] nouveau D[   PDISP][0000:02:00.0] 	0x0ca4: 0x00000000              
>[  145.077875] nouveau D[   PDISP][0000:02:00.0] 	0x0ca8: 0x00040000              
>[  145.077881] nouveau D[   PDISP][0000:02:00.0] 	0x0cc0: 0x00000000              
>[  145.077887] nouveau D[   PDISP][0000:02:00.0] 	0x0cc4: 0x00000000              
>[  145.077893] nouveau D[   PDISP][0000:02:00.0] 	0x0cc8: 0x038405a0              
>[  145.077899] nouveau D[   PDISP][0000:02:00.0] 	0x0cd4: 0x00000000              
>[  145.077905] nouveau D[   PDISP][0000:02:00.0] 	0x0cd8: 0x038405a0              
>[  145.077910] nouveau D[   PDISP][0000:02:00.0] 	0x0cdc: 0x038405a0              
>[  145.077916] nouveau D[   PDISP][0000:02:00.0] 	0x0d00: 0x00000311              
>[  145.077922] nouveau D[   PDISP][0000:02:00.0] 	0x0d04: 0x00000100              
>[  145.077928] nouveau D[   PDISP][0000:02:00.0] 	0x0d10: 0x00000000              
>[  145.077934] nouveau D[   PDISP][0000:02:00.0] 	0x0d14: 0x00000000              
>[  145.077974] nouveau D[   PDISP][0000:02:00.0] supervisor 0x00000020 0x000000b0
>[  145.078024] nouveau T[   VBIOS][0000:02:00.0] 0xb6e5[0]: SUB_DIRECT	0xb7d5
>[  145.078026] nouveau T[   VBIOS][0000:02:00.0] 0xb7d5[1]: NV_REG	R[0x4061c00c] &= 0xfffffffe |= 0x00000000
>[  145.078032] nouveau T[   VBIOS][0000:02:00.0] 0xb7e2[1]: NV_REG	R[0x4061c00c] &= 0xfffffffe |= 0x00000001
>[  145.078036] nouveau T[   VBIOS][0000:02:00.0] 0xb7ef[1]: TIME	0x3e80
>[  145.094037] nouveau T[   VBIOS][0000:02:00.0] 0xb7f2[1]: NV_REG	R[0x4061c00c] &= 0xfffffffe |= 0x00000000
>[  145.094042] nouveau T[   VBIOS][0000:02:00.0] 0xb7ff[1]: DONE
>[  145.094044] nouveau T[   VBIOS][0000:02:00.0] 0xb6e8[0]: ZM_REG_SEQUENCE	0x05
>[  145.094046] nouveau T[   VBIOS][0000:02:00.0] 0xb6ee[0]: 		R[0x4061c00c] = 0x01060200
>[  145.094048] nouveau T[   VBIOS][0000:02:00.0] 0xb6f2[0]: 		R[0x4061c010] = 0x0200000a
>[  145.094050] nouveau T[   VBIOS][0000:02:00.0] 0xb6f6[0]: 		R[0x4061c014] = 0x00000000
>[  145.094052] nouveau T[   VBIOS][0000:02:00.0] 0xb6fa[0]: 		R[0x4061c018] = 0x000f4af8
>[  145.094054] nouveau T[   VBIOS][0000:02:00.0] 0xb6fe[0]: 		R[0x4061c01c] = 0x0001caf8
>[  145.094055] nouveau T[   VBIOS][0000:02:00.0] 0xb702[0]: SUB_DIRECT	0xb82b
>[  145.094057] nouveau T[   VBIOS][0000:02:00.0] 0xb82b[1]: NV_REG	R[0x00e1e4] &= 0xfffffffc |= 0x00000000
>[  145.094062] nouveau T[   VBIOS][0000:02:00.0] 0xb838[1]: NV_REG	R[0x00e100] &= 0xfff7ffff |= 0x00080000
>[  145.094065] nouveau T[   VBIOS][0000:02:00.0] 0xb845[1]: ZM_REG_SEQUENCE	0x02
>[  145.094067] nouveau T[   VBIOS][0000:02:00.0] 0xb84b[1]: 		R[0x4061c118] = 0x18181818
>[  145.094068] nouveau T[   VBIOS][0000:02:00.0] 0xb84f[1]: 		R[0x4061c11c] = 0x00000018
>[  145.094070] nouveau T[   VBIOS][0000:02:00.0] 0xb853[1]: ZM_REG_SEQUENCE	0x02
>[  145.094072] nouveau T[   VBIOS][0000:02:00.0] 0xb859[1]: 		R[0x4061c198] = 0x18181818
>[  145.094073] nouveau T[   VBIOS][0000:02:00.0] 0xb85d[1]: 		R[0x4061c19c] = 0x00000018
>[  145.094075] nouveau T[   VBIOS][0000:02:00.0] 0xb861[1]: SUB_DIRECT	0xc2a1
>[  145.094076] nouveau T[   VBIOS][0000:02:00.0] 0xc2a1[2]: DONE
>[  145.094078] nouveau T[   VBIOS][0000:02:00.0] 0xb864[1]: SUB_DIRECT	0xc2a1
>[  145.094079] nouveau T[   VBIOS][0000:02:00.0] 0xc2a1[2]: DONE
>[  145.094080] nouveau T[   VBIOS][0000:02:00.0] 0xb867[1]: DONE
>[  145.094082] nouveau T[   VBIOS][0000:02:00.0] 0xb705[0]: SUB_DIRECT	0xb868
>[  145.094083] nouveau T[   VBIOS][0000:02:00.0] 0xb868[1]: DONE
>[  145.094084] nouveau T[   VBIOS][0000:02:00.0] 0xb708[0]: DONE
>[  145.627152] nouveau D[   PDISP][0000:02:00.0] supervisor 0x00000040 0x000000b0
>[  145.627171] nouveau T[   VBIOS][0000:02:00.0] 0xb869[0]: DONE

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Attachments on bug 78439: 98687 | 98688 | 98689 | 100920 | 100923 | 100924 | 101180 | 101204 | 101299 | 115643 | 115644

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