Attachment 101252 Details for Bug 80010 – xlog0.txt

xlog0.txt

xlog0.txt (text/plain), 13.73 KB, created by Thomas Rohwer on 2014-06-17 16:58:24 UTC

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Creator: Thomas Rohwer

Created: 2014-06-17 16:58:24 UTC

Size: 13.73 KB

patch

obsolete

>                           DCC: 0x000f0002 (dual channel interleaved, XOR randomization: enabled, XOR bit: 11)
>                     CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
>                        C0DRB0: 0x000f0002 (0x0002)
>                        C0DRB1: 0x0010000f (0x000f)
>                        C0DRB2: 0x00000010 (0x0010)
>                        C0DRB3: 0x0e000000 (0x0000)
>                        C1DRB0: 0x17cbe000 (0xe000)
>                        C1DRB1: 0x000017cb (0x17cb)
>                        C1DRB2: 0x00000000 (0x0000)
>                        C1DRB3: 0x00000000 (0x0000)
>                       C0DRA01: 0x00030e00 (0x0e00)
>                       C0DRA23: 0x000c0003 (0x0003)
>                       C1DRA01: 0x00000000 (0x0000)
>                       C1DRA23: 0x00000000 (0x0000)
>                    PGETBL_CTL: 0xbff80001
>             VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>             VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>                 VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>                     DPLL_TEST: 0x00010001 ()
>                  CACHE_MODE_0: 0x00006800
>                       D_STATE: 0x00000000
>                 DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
>                RENCLK_GATE_D1: 0x00000000
>                RENCLK_GATE_D2: 0x00000000
>                         SDVOB: 0x0008001c (disabled, pipe A, stall disabled, detected)
>                         SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
>                       SDVOUDI: 0x00000000
>                        DSPARB: 0x00001d9c
>                        FW_BLC: 0x00000000
>                       FW_BLC2: 0x00000000
>                   FW_BLC_SELF: 0x00000000
>                        DSPFW1: 0x3f8f0f0f
>                        DSPFW2: 0x00000f0f
>                        DSPFW3: 0x00000000
>                          ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
>                          LVDS: 0xc230833c (enabled, pipe B, 18 bit, 2 channels)
>                          DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>                          DVOB: 0x0008001c (disabled, pipe A, no stall, +hsync, +vsync)
>                          DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
>                   DVOA_SRCDIM: 0x00000000
>                   DVOB_SRCDIM: 0x00000000
>                   DVOC_SRCDIM: 0x00000000
>                   BLC_PWM_CTL: 0xb8b1b8b0
>                  BLC_PWM_CTL2: 0xe0000000
>                    PP_CONTROL: 0x00000003 (power target: on)
>                     PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>                  PP_ON_DELAYS: 0x00fa09c4
>                 PP_OFF_DELAYS: 0x00fa09c4
>                    PP_DIVISOR: 0x00410903
>                  PFIT_CONTROL: 0xa0000000
>               PFIT_PGM_RATIOS: 0x06180618
>               PORT_HOTPLUG_EN: 0x00000020
>             PORT_HOTPLUG_STAT: 0x00000000
>                      DSPACNTR: 0x00000000 (disabled, pipe A)
>                    DSPASTRIDE: 0x00000000 (0 bytes)
>                       DSPAPOS: 0x00000000 (0, 0)
>                      DSPASIZE: 0x00000000 (1, 1)
>                      DSPABASE: 0x00000000
>                      DSPASURF: 0x00000000
>                   DSPATILEOFF: 0x00000000
>                     PIPEACONF: 0x00000000 (disabled, inactive, progressive)
>                      PIPEASRC: 0x027f01df (640, 480)
>                     PIPEASTAT: 0x80000207 (status: FIFO_UNDERRUN VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>             PIPEA_GMCH_DATA_M: 0x00000000
>             PIPEA_GMCH_DATA_N: 0x00000000
>               PIPEA_DP_LINK_M: 0x00000000
>               PIPEA_DP_LINK_N: 0x00000000
>                 CURSOR_A_BASE: 0x00000000
>              CURSOR_A_CONTROL: 0x00000000
>             CURSOR_A_POSITION: 0x00000000
>                          FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>                          FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>                        DPLL_A: 0x04800c00 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
>                     DPLL_A_MD: 0x00000303
>                      HTOTAL_A: 0x031f027f (640 active, 800 total)
>                      HBLANK_A: 0x03170287 (648 start, 792 end)
>                       HSYNC_A: 0x02ef028f (656 start, 752 end)
>                      VTOTAL_A: 0x020c01df (480 active, 525 total)
>                      VBLANK_A: 0x020401e7 (488 start, 517 end)
>                       VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>                     BCLRPAT_A: 0x00000000
>                  VSYNCSHIFT_A: 0x00000000
>                      DSPBCNTR: 0x19000000 (disabled, pipe B)
>                    DSPBSTRIDE: 0x00001a40 (6720 bytes)
>                       DSPBPOS: 0x00000000 (0, 0)
>                      DSPBSIZE: 0x00000000 (1, 1)
>                      DSPBBASE: 0x00000000
>                      DSPBSURF: 0x00000000
>                   DSPBTILEOFF: 0x00000000
>                     PIPEBCONF: 0xc0000000 (enabled, active, progressive)
>                      PIPEBSRC: 0x027f018f (640, 400)
>                     PIPEBSTAT: 0x00000206 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
>             PIPEB_GMCH_DATA_M: 0x00000000
>             PIPEB_GMCH_DATA_N: 0x00000000
>               PIPEB_DP_LINK_M: 0x00000000
>               PIPEB_DP_LINK_N: 0x00000000
>                 CURSOR_B_BASE: 0x00000000
>              CURSOR_B_CONTROL: 0x00000000
>             CURSOR_B_POSITION: 0x00000000
>                          FPB0: 0x00021009 (n = 2, m1 = 16, m2 = 9)
>                          FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>                        DPLL_B: 0x99046a00 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 3, p2 = 7)
>                     DPLL_B_MD: 0x00000003
>                      HTOTAL_B: 0x075f068f (1680 active, 1888 total)
>                      HBLANK_B: 0x075f068f (1680 start, 1888 end)
>                       HSYNC_B: 0x06df06af (1712 start, 1760 end)
>                      VTOTAL_B: 0x04280419 (1050 active, 1065 total)
>                      VBLANK_B: 0x04280419 (1050 start, 1065 end)
>                       VSYNC_B: 0x041d041a (1051 start, 1054 end)
>                     BCLRPAT_B: 0x00000000
>                  VSYNCSHIFT_B: 0x00000000
>             VCLK_DIVISOR_VGA0: 0x00031108
>             VCLK_DIVISOR_VGA1: 0x00031406
>                 VCLK_POST_DIV: 0x00020002
>                      VGACNTRL: 0x22c4008e (enabled)
>                        TV_CTL: 0x00000000
>                        TV_DAC: 0x70000000
>                      TV_CSC_Y: 0x00000000
>                     TV_CSC_Y2: 0x00000000
>                      TV_CSC_U: 0x00000000
>                     TV_CSC_U2: 0x00000000
>                      TV_CSC_V: 0x00000000
>                     TV_CSC_V2: 0x00000000
>                  TV_CLR_KNOBS: 0x00000000
>                  TV_CLR_LEVEL: 0x00000000
>                    TV_H_CTL_1: 0x00000000
>                    TV_H_CTL_2: 0x00000000
>                    TV_H_CTL_3: 0x00000000
>                    TV_V_CTL_1: 0x00000000
>                    TV_V_CTL_2: 0x00000000
>                    TV_V_CTL_3: 0x00000000
>                    TV_V_CTL_4: 0x00000000
>                    TV_V_CTL_5: 0x00000000
>                    TV_V_CTL_6: 0x00000000
>                    TV_V_CTL_7: 0x00000000
>                   TV_SC_CTL_1: 0x00000000
>                   TV_SC_CTL_2: 0x00000000
>                   TV_SC_CTL_3: 0x00000000
>                    TV_WIN_POS: 0x00000000
>                   TV_WIN_SIZE: 0x00000000
>               TV_FILTER_CTL_1: 0x00000000
>               TV_FILTER_CTL_2: 0x00000000
>               TV_FILTER_CTL_3: 0x00000000
>                 TV_CC_CONTROL: 0x00000000
>                    TV_CC_DATA: 0x00000000
>                   TV_H_LUMA_0: 0x00000000
>                  TV_H_LUMA_59: 0x00000000
>                 TV_H_CHROMA_0: 0x00000000
>                TV_H_CHROMA_59: 0x00000000
>                  FBC_CFB_BASE: 0x00000000
>                   FBC_LL_BASE: 0x00000000
>                   FBC_CONTROL: 0x00000000
>                   FBC_COMMAND: 0x00000000
>                    FBC_STATUS: 0x20000000
>                  FBC_CONTROL2: 0x00000000
>                 FBC_FENCE_OFF: 0x00000000
>                   FBC_MOD_NUM: 0x00000000
>                       MI_MODE: 0x00000200
>                  MI_ARB_STATE: 0x00000044
>                MI_RDRET_STATE: 0x00000000
>                       ECOSKPD: 0x00000307
>                          DP_B: 0x00000000
>                DPB_AUX_CH_CTL: 0x00000000
>              DPB_AUX_CH_DATA1: 0x00000000
>              DPB_AUX_CH_DATA2: 0x00000000
>              DPB_AUX_CH_DATA3: 0x00000000
>              DPB_AUX_CH_DATA4: 0x00000000
>              DPB_AUX_CH_DATA5: 0x00000000
>                          DP_C: 0x00000000
>                DPC_AUX_CH_CTL: 0x00000000
>              DPC_AUX_CH_DATA1: 0x00000000
>              DPC_AUX_CH_DATA2: 0x00000000
>              DPC_AUX_CH_DATA3: 0x00000000
>              DPC_AUX_CH_DATA4: 0x00000000
>              DPC_AUX_CH_DATA5: 0x00000000
>                          DP_D: 0x00000000
>                DPD_AUX_CH_CTL: 0x00000000
>              DPD_AUX_CH_DATA1: 0x00000000
>              DPD_AUX_CH_DATA2: 0x00000000
>              DPD_AUX_CH_DATA3: 0x00000000
>              DPD_AUX_CH_DATA4: 0x00000000
>              DPD_AUX_CH_DATA5: 0x00000000
>                    AUD_CONFIG: 0x00000000
>              AUD_HDMIW_STATUS: 0x00000000
>                AUD_CONV_CHCNT: 0x00000000
>                 VIDEO_DIP_CTL: 0x00000600
>                 AUD_PINW_CNTR: 0x00000140
>                   AUD_CNTL_ST: 0x00001800
>                   AUD_PIN_CAP: 0x00000094
>                  AUD_PINW_CAP: 0x004013b5
>            AUD_PINW_UNSOLRESP: 0x00000000
>              AUD_OUT_DIG_CNVT: 0x00000001
>                 AUD_OUT_CWCAP: 0x00000219
>                   AUD_GRP_CAP: 0x00000004
>                      FENCE  0: 0x00000000 (enabled)
>                      FENCE  1: 0x00000000 (enabled)
>                      FENCE  2: 0x00000000 (enabled)
>                      FENCE  3: 0x00000000 (enabled)
>                      FENCE  4: 0x00000000 (enabled)
>                      FENCE  5: 0x00000000 (enabled)
>                      FENCE  6: 0x00000000 (enabled)
>                      FENCE  7: 0x00000000 (enabled)
>                      FENCE  8: 0x00000000 (enabled)
>                      FENCE  9: 0x00000000 (enabled)
>                     FENCE  10: 0x00000000 (enabled)
>                     FENCE  11: 0x00000000 (enabled)
>                     FENCE  12: 0x00000000 (enabled)
>                     FENCE  13: 0x00000000 (enabled)
>                     FENCE  14: 0x00000000 (enabled)
>                     FENCE  15: 0x00000000 (enabled)
>                 FENCE START 0: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>                   FENCE END 0: 0x00000000 (                                   0x00000000 end)
>                 FENCE START 1: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>                   FENCE END 1: 0x00000000 (                                   0x00000000 end)
>                 FENCE START 2: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>                   FENCE END 2: 0x00000000 (                                   0x00000000 end)
>                 FENCE START 3: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>                   FENCE END 3: 0x00000000 (                                   0x00000000 end)
>                 FENCE START 4: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>                   FENCE END 4: 0x00000000 (                                   0x00000000 end)
>                 FENCE START 5: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>                   FENCE END 5: 0x00000000 (                                   0x00000000 end)
>                 FENCE START 6: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>                   FENCE END 6: 0x00000000 (                                   0x00000000 end)
>                 FENCE START 7: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>                   FENCE END 7: 0x00000000 (                                   0x00000000 end)
>                 FENCE START 8: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>                   FENCE END 8: 0x00000000 (                                   0x00000000 end)
>                 FENCE START 9: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>                   FENCE END 9: 0x00000000 (                                   0x00000000 end)
>                FENCE START 10: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>                  FENCE END 10: 0x00000000 (                                   0x00000000 end)
>                FENCE START 11: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>                  FENCE END 11: 0x00000000 (                                   0x00000000 end)
>                FENCE START 12: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>                  FENCE END 12: 0x00000000 (                                   0x00000000 end)
>                FENCE START 13: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>                  FENCE END 13: 0x00000000 (                                   0x00000000 end)
>                FENCE START 14: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>                  FENCE END 14: 0x00000000 (                                   0x00000000 end)
>                FENCE START 15: 0x00000000 (disabled, X tile walk,  128 pitch, 0x00000000 start)
>                  FENCE END 15: 0x00000000 (                                   0x00000000 end)
>                       INST_PM: 0x00000000
>pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>SDVO phase shift 5 out of range -- probobly not an issue.
>pipe B dot 120238 n 2 m1 16 m2 9 p1 3 p2 7

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Attachments on bug 80010: 101023 | 101024 | 101026 | 101027 | 101252 | 101253

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