Attachment 101722 Details for Bug 80434 – after resume

after resume

intel_reg.3 (text/plain), 9.37 KB, created by Libin Yang on 2014-06-25 07:21:00 UTC

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Creator: Libin Yang

Created: 2014-06-25 07:21:00 UTC

Size: 9.37 KB

patch

obsolete

>             HSW_PWR_WELL_CTL1: 0x40000000
>             HSW_PWR_WELL_CTL2: 0xc0000000
>             HSW_PWR_WELL_CTL3: 0x40000000
>             HSW_PWR_WELL_CTL4: 0x40000000
>             HSW_PWR_WELL_CTL5: 0x0004050f
>             HSW_PWR_WELL_CTL6: 0x00000000
>           PIPE_DDI_FUNC_CTL_A: 0x00030000 (disabled, no port, HDMI, 8 bpc, +VSync, +HSync, EDP A ON, x1)
>           PIPE_DDI_FUNC_CTL_B: 0x92030002 (enabled, DDIB, DP SST, 8 bpc, +VSync, +HSync, EDP A ON, x2)
>           PIPE_DDI_FUNC_CTL_C: 0xa0010000 (enabled, DDIC, HDMI, 8 bpc, -VSync, +HSync, EDP A ON, x1)
>         PIPE_DDI_FUNC_CTL_EDP: 0x82000002 (enabled, no port, DP SST, 8 bpc, -VSync, -HSync, EDP A ON, x2)
>                   DP_TP_CTL_A: 0x80000300
>                   DP_TP_CTL_B: 0x80040300
>                   DP_TP_CTL_C: 0x00000000
>                   DP_TP_CTL_D: 0x00000000
>                   DP_TP_CTL_E: 0x00000000
>                DP_TP_STATUS_B: 0x00000000
>                DP_TP_STATUS_C: 0x00000000
>                DP_TP_STATUS_D: 0x00000000
>                DP_TP_STATUS_E: 0x00000000
>                 DDI_BUF_CTL_A: 0x80000003 (enabled not reversed x2 detected)
>                 DDI_BUF_CTL_B: 0x81000002 (enabled not reversed x2 not detected)
>                 DDI_BUF_CTL_C: 0x80000000 (enabled not reversed x1 not detected)
>                 DDI_BUF_CTL_D: 0x00000000 (disabled not reversed x1 not detected)
>                 DDI_BUF_CTL_E: 0x00000000 (disabled not reversed x1 not detected)
>                      SPLL_CTL: 0x00000000
>                     LCPLL_CTL: 0x44000000
>                    WRPLL_CTL1: 0xb035061f
>                    WRPLL_CTL2: 0x00202418
>                PORT_CLK_SEL_A: 0x20000000 (LCPLL 1350)
>                PORT_CLK_SEL_B: 0x20000000 (LCPLL 1350)
>                PORT_CLK_SEL_C: 0x80000000 (WRPLL 1)
>                PORT_CLK_SEL_D: 0xe0000000 (None)
>                PORT_CLK_SEL_E: 0xe0000000 (None)
>                PIPE_CLK_SEL_A: 0x00000000 (None)
>                PIPE_CLK_SEL_B: 0x40000000 (DDIB)
>                PIPE_CLK_SEL_C: 0x60000000 (DDIC)
>                     WM_PIPE_A: 0x00140002 (primary 20, sprite 0, pipe 2)
>                     WM_PIPE_B: 0x00150002 (primary 21, sprite 0, pipe 2)
>                     WM_PIPE_C: 0x00160002 (primary 22, sprite 0, pipe 2)
>                        WM_LP1: 0x8228f202 (enabled, latency 2, fbc 2, pri 242, cur 2)
>                        WM_LP2: 0x86425a02 (enabled, latency 6, fbc 4, pri 602, cur 2)
>                        WM_LP3: 0x884ad202 (enabled, latency 8, fbc 4, pri 722, cur 2)
>                    WM_LP1_SPR: 0x00000000
>                    WM_LP2_SPR: 0x00000000
>                    WM_LP3_SPR: 0x00000000
>                       WM_MISC: 0x00000000
>                     WM_SR_CNT: 0x00000000
>            PIPE_WM_LINETIME_A: 0x001f0078
>            PIPE_WM_LINETIME_B: 0x00210077
>            PIPE_WM_LINETIME_C: 0x001f006c
>                        WM_DBG: 0x80000000
>                   SFUSE_STRAP: 0x00000006 (display enabled, crt no, lane reversal no, port b yes, port c yes, port d no)
>                      PIPEASRC: 0x077f0437 (1920, 1080)
>                      DSPACNTR: 0xd9000000 (enabled)
>                    DSPASTRIDE: 0x00001e00 (120)
>                      DSPASURF: 0x0026d000
>                   DSPATILEOFF: 0x00000000 (0, 0)
>                      PIPEBSRC: 0x077f0437 (1920, 1080)
>                      DSPBCNTR: 0xd9000000 (enabled)
>                    DSPBSTRIDE: 0x00001e00 (120)
>                      DSPBSURF: 0x0026d000
>                   DSPBTILEOFF: 0x00000000 (0, 0)
>                      PIPECSRC: 0x077f04af (1920, 1200)
>                      DSPCCNTR: 0xd9000000 (enabled)
>                    DSPCSTRIDE: 0x00001e00 (120)
>                      DSPCSURF: 0x0026d000
>                   DSPCTILEOFF: 0x00000000 (0, 0)
>                     PIPEACONF: 0x40000000 (disabled, active, pf-pd, rotate 0, 8bpc)
>                      HTOTAL_A: 0x00000000 (1 active, 1 total)
>                      HBLANK_A: 0x00000000 (1 start, 1 end)
>                       HSYNC_A: 0x00000000 (1 start, 1 end)
>                      VTOTAL_A: 0x00000000 (1 active, 1 total)
>                      VBLANK_A: 0x00000000 (1 start, 1 end)
>                       VSYNC_A: 0x00000000 (1 start, 1 end)
>                  VSYNCSHIFT_A: 0x00000000
>                 PIPEA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEA_DATA_N1: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_M1: 0x00000000 (val 0x0 0)
>                 PIPEA_LINK_N1: 0x00000000 (val 0x0 0)
>                     PIPEBCONF: 0xc0000000 (enabled, active, pf-pd, rotate 0, 8bpc)
>                      HTOTAL_B: 0x0897077f (1920 active, 2200 total)
>                      HBLANK_B: 0x0897077f (1920 start, 2200 end)
>                       HSYNC_B: 0x080307d7 (2008 start, 2052 end)
>                      VTOTAL_B: 0x04640437 (1080 active, 1125 total)
>                      VBLANK_B: 0x04640437 (1080 start, 1125 end)
>                       VSYNC_B: 0x0440043b (1084 start, 1089 end)
>                  VSYNCSHIFT_B: 0x00000000
>                 PIPEB_DATA_M1: 0x7e699999 (TU 64, val 0x699999 6920601)
>                 PIPEB_DATA_N1: 0x00800000 (val 0x800000 8388608)
>                 PIPEB_LINK_M1: 0x00046666 (val 0x46666 288358)
>                 PIPEB_LINK_N1: 0x00080000 (val 0x80000 524288)
>                     PIPECCONF: 0xc0000000 (enabled, active, pf-pd, rotate 0, 8bpc)
>                      HTOTAL_C: 0x081f077f (1920 active, 2080 total)
>                      HBLANK_C: 0x081f077f (1920 start, 2080 end)
>                       HSYNC_C: 0x07cf07af (1968 start, 2000 end)
>                      VTOTAL_C: 0x04d204af (1200 active, 1235 total)
>                      VBLANK_C: 0x04d204af (1200 start, 1235 end)
>                       VSYNC_C: 0x04b804b2 (1203 start, 1209 end)
>                  VSYNCSHIFT_C: 0x00000000
>                 PIPEC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                 PIPEC_DATA_N1: 0x00000000 (val 0x0 0)
>                 PIPEC_LINK_M1: 0x00000000 (val 0x0 0)
>                 PIPEC_LINK_N1: 0x00000000 (val 0x0 0)
>                   PIPEEDPCONF: 0xc0000000 (enabled, active, pf-pd, rotate 0, 8bpc)
>                    HTOTAL_EDP: 0x081f077f (1920 active, 2080 total)
>                    HBLANK_EDP: 0x081f077f (1920 start, 2080 end)
>                     HSYNC_EDP: 0x07cb07ad (1966 start, 1996 end)
>                    VTOTAL_EDP: 0x04570437 (1080 active, 1112 total)
>                    VBLANK_EDP: 0x04570437 (1080 start, 1112 end)
>                     VSYNC_EDP: 0x043d0439 (1082 start, 1086 end)
>                VSYNCSHIFT_EDP: 0x00000000
>               PIPEEDP_DATA_M1: 0x7e62b020 (TU 64, val 0x62b020 6467616)
>               PIPEEDP_DATA_N1: 0x00800000 (val 0x800000 8388608)
>               PIPEEDP_LINK_M1: 0x00041cac (val 0x41cac 269484)
>               PIPEEDP_LINK_N1: 0x00080000 (val 0x80000 524288)
>                     PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                   PFA_WIN_POS: 0x00000000 (0, 0)
>                  PFA_WIN_SIZE: 0x00000000 (0, 0)
>                     PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                   PFB_WIN_POS: 0x00000000 (0, 0)
>                  PFB_WIN_SIZE: 0x00000000 (0, 0)
>                     PFC_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                   PFC_WIN_POS: 0x00000000 (0, 0)
>                  PFC_WIN_SIZE: 0x00000000 (0, 0)
>                TRANS_HTOTAL_A: 0x00000006 (7 active, 1 total)
>                TRANS_HBLANK_A: 0x00000006 (7 start, 1 end)
>                 TRANS_HSYNC_A: 0x00000006 (7 start, 1 end)
>                TRANS_VTOTAL_A: 0x00000006 (7 active, 1 total)
>                TRANS_VBLANK_A: 0x00000006 (7 start, 1 end)
>                 TRANS_VSYNC_A: 0x00000006 (7 start, 1 end)
>            TRANS_VSYNCSHIFT_A: 0x00000006
>                    TRANSACONF: 0x00000006 (disable, inactive, progressive)
>                  FDI_RXA_MISC: 0x00000006 (FDI Delay 6)
>               FDI_RXA_TUSIZE1: 0x00000006
>                   FDI_RXA_IIR: 0x00000006
>                   FDI_RXA_IMR: 0x00000006
>              BLC_PWM_CPU_CTL2: 0x00000000 (enable 0, pipe A, blinking 0, granularity 128)
>               BLC_PWM_CPU_CTL: 0x00000000 (cycle 0, freq 0)
>             BLC_PWM2_CPU_CTL2: 0x00000000 (enable 0, pipe A, blinking 0, granularity 128)
>              BLC_PWM2_CPU_CTL: 0x00000000 (cycle 0, freq 0)
>                  BLC_MISC_CTL: 0x00000000 (PWM1-PCH PWM2-CPU)
>              BLC_PWM_PCH_CTL1: 0xc0000000 (enable 1, override 1, inverted polarity 0)
>              BLC_PWM_PCH_CTL2: 0x03a903a9 (freq 937, cycle 937)
>                  UTIL_PIN_CTL: 0x00000000 (enable 0, transcoder A, mode data, data 0 inverted polarity 0)
>                 PCH_PP_STATUS: 0x80000008 (on, not ready, sequencing idle)
>                PCH_PP_CONTROL: 0xabcd0007 (blacklight enabled, power down on reset, panel on)
>              PCH_PP_ON_DELAYS: 0x07d00001
>             PCH_PP_OFF_DELAYS: 0x01f40001
>                PCH_PP_DIVISOR: 0x0004af06
>                   PIXCLK_GATE: 0x0004af06
>                        SDEISR: 0x00e00000 (port d:1, port c:1, port b:1, crt:0)
>            RC6_RESIDENCY_TIME: 0x006458f5

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Attachments on bug 80434: 101720 | 101721 | 101722

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