Attachment 102343 Details for Bug 80463 – dmesg

dmesg

patch102162patch.dmesg (text/plain), 125.79 KB, created by Guo Jinxian on 2014-07-07 03:37:52 UTC

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Creator: Guo Jinxian

Created: 2014-07-07 03:37:52 UTC

Size: 125.79 KB

patch

obsolete

>[  174.318906] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.318907] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  174.318908] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  174.318910] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  174.318911] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  174.318912] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  174.318914] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  174.318914] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  174.318915] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  174.318917] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  174.318918] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  174.318919] [drm:intel_dump_pipe_config] requested mode:
>[  174.318921] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.318922] [drm:intel_dump_pipe_config] adjusted mode:
>[  174.318924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.318926] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  174.318926] [drm:intel_dump_pipe_config] port clock: 65000
>[  174.318927] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  174.318929] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  174.318930] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  174.318931] [drm:intel_dump_pipe_config] ips: 0
>[  174.318932] [drm:intel_dump_pipe_config] double wide: 0
>[  174.318933] [drm:intel_display_power_get] enabling always-on
>[  174.318945] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  174.318946] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  174.318947] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  174.318955] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  174.320299] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  174.320301] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  174.320956] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  174.320958] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  174.320959] [drm:gen6_fdi_link_train] FDI train done.
>[  174.320962] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  174.320963] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  174.322835] [drm:intel_update_fbc] disabled per chip default
>[  174.322837] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.322841] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.322843] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.322845] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.322847] [drm:check_crtc_state] [CRTC:6]
>[  174.322856] [drm:check_crtc_state] [CRTC:10]
>[  174.322857] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.322861] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.322865] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.322866] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  174.322868] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.322869] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  174.322870] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.322871] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.322872] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  174.322873] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  174.356448] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  174.356456] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  174.356867] [drm:intel_update_fbc] no output, disabling
>[  174.356870] [drm:intel_display_power_put] disabling always-on
>[  174.356873] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.356876] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.356878] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.356880] [drm:check_crtc_state] [CRTC:6]
>[  174.356881] [drm:check_crtc_state] [CRTC:10]
>[  174.356882] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.356886] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.356893] [drm:drm_mode_setcrtc] [CRTC:10]
>[  174.356894] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  174.356896] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  174.356898] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.356900] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  174.356901] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  174.356902] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  174.356904] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.356905] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.356906] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  174.356907] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.356908] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  174.356910] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  174.356911] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  174.356913] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  174.356914] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  174.356915] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  174.356916] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  174.356917] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  174.356918] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  174.356920] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  174.356921] [drm:intel_dump_pipe_config] requested mode:
>[  174.356923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.356923] [drm:intel_dump_pipe_config] adjusted mode:
>[  174.356925] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.356927] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  174.356928] [drm:intel_dump_pipe_config] port clock: 65000
>[  174.356929] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  174.356930] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  174.356931] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  174.356932] [drm:intel_dump_pipe_config] ips: 0
>[  174.356933] [drm:intel_dump_pipe_config] double wide: 0
>[  174.356934] [drm:intel_display_power_get] enabling always-on
>[  174.356947] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  174.356948] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  174.356949] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  174.356957] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  174.358300] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  174.358302] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  174.358957] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  174.358959] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  174.358960] [drm:gen6_fdi_link_train] FDI train done.
>[  174.358963] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  174.358964] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  174.360836] [drm:intel_update_fbc] disabled per chip default
>[  174.360839] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.360842] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.360844] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.360846] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.360848] [drm:check_crtc_state] [CRTC:6]
>[  174.360857] [drm:check_crtc_state] [CRTC:10]
>[  174.360858] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.360862] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.360866] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.360867] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  174.360869] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.360870] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  174.360871] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.360872] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.360873] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  174.360874] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  174.394485] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  174.394493] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  174.394904] [drm:intel_update_fbc] no output, disabling
>[  174.394907] [drm:intel_display_power_put] disabling always-on
>[  174.394911] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.394913] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.394915] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.394917] [drm:check_crtc_state] [CRTC:6]
>[  174.394918] [drm:check_crtc_state] [CRTC:10]
>[  174.394919] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.394924] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.394930] [drm:drm_mode_setcrtc] [CRTC:10]
>[  174.394932] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  174.394933] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  174.394935] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.394937] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  174.394939] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  174.394940] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  174.394941] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.394942] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.394943] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  174.394944] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.394945] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  174.394947] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  174.394948] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  174.394950] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  174.394951] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  174.394952] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  174.394953] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  174.394954] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  174.394956] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  174.394957] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  174.394958] [drm:intel_dump_pipe_config] requested mode:
>[  174.394960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.394961] [drm:intel_dump_pipe_config] adjusted mode:
>[  174.394962] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.394964] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  174.394965] [drm:intel_dump_pipe_config] port clock: 65000
>[  174.394966] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  174.394967] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  174.394968] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  174.394969] [drm:intel_dump_pipe_config] ips: 0
>[  174.394970] [drm:intel_dump_pipe_config] double wide: 0
>[  174.394972] [drm:intel_display_power_get] enabling always-on
>[  174.394984] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  174.394985] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  174.394986] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  174.394994] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  174.396338] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  174.396340] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  174.396995] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  174.396997] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  174.396997] [drm:gen6_fdi_link_train] FDI train done.
>[  174.397000] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  174.397001] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  174.398873] [drm:intel_update_fbc] disabled per chip default
>[  174.398876] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.398879] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.398882] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.398884] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.398886] [drm:check_crtc_state] [CRTC:6]
>[  174.398895] [drm:check_crtc_state] [CRTC:10]
>[  174.398896] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.398899] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.398904] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.398905] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  174.398906] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.398907] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  174.398908] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.398909] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.398910] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  174.398912] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  174.432483] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  174.432491] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  174.432902] [drm:intel_update_fbc] no output, disabling
>[  174.432904] [drm:intel_display_power_put] disabling always-on
>[  174.432909] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.432911] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.432913] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.432915] [drm:check_crtc_state] [CRTC:6]
>[  174.432916] [drm:check_crtc_state] [CRTC:10]
>[  174.432917] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.432922] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.432928] [drm:drm_mode_setcrtc] [CRTC:10]
>[  174.432929] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  174.432931] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  174.432933] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.432935] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  174.432937] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  174.432938] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  174.432939] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.432940] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.432941] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  174.432942] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.432943] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  174.432945] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  174.432946] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  174.432948] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  174.432949] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  174.432950] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  174.432951] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  174.432952] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  174.432954] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  174.432955] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  174.432956] [drm:intel_dump_pipe_config] requested mode:
>[  174.432958] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.432959] [drm:intel_dump_pipe_config] adjusted mode:
>[  174.432960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.432962] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  174.432963] [drm:intel_dump_pipe_config] port clock: 65000
>[  174.432964] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  174.432965] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  174.432966] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  174.432967] [drm:intel_dump_pipe_config] ips: 0
>[  174.432968] [drm:intel_dump_pipe_config] double wide: 0
>[  174.432970] [drm:intel_display_power_get] enabling always-on
>[  174.432982] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  174.432983] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  174.432984] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  174.432992] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  174.434335] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  174.434337] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  174.434992] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  174.434994] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  174.434995] [drm:gen6_fdi_link_train] FDI train done.
>[  174.434997] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  174.434998] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  174.436870] [drm:intel_update_fbc] disabled per chip default
>[  174.436873] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.436877] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.436879] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.436881] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.436883] [drm:check_crtc_state] [CRTC:6]
>[  174.436892] [drm:check_crtc_state] [CRTC:10]
>[  174.436893] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.436896] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.436901] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.436902] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  174.436904] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.436905] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  174.436906] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.436907] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.436908] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  174.436909] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  174.470517] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  174.470524] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  174.470935] [drm:intel_update_fbc] no output, disabling
>[  174.470938] [drm:intel_display_power_put] disabling always-on
>[  174.470942] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.470945] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.470947] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.470949] [drm:check_crtc_state] [CRTC:6]
>[  174.470950] [drm:check_crtc_state] [CRTC:10]
>[  174.470951] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.470954] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.470961] [drm:drm_mode_setcrtc] [CRTC:10]
>[  174.470962] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  174.470964] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  174.470966] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.470967] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  174.470969] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  174.470970] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  174.470971] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.470972] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.470974] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  174.470975] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.470976] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  174.470977] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  174.470979] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  174.470980] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  174.470981] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  174.470982] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  174.470983] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  174.470984] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  174.470986] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  174.470987] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  174.470988] [drm:intel_dump_pipe_config] requested mode:
>[  174.470990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.470991] [drm:intel_dump_pipe_config] adjusted mode:
>[  174.470993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.470994] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  174.470995] [drm:intel_dump_pipe_config] port clock: 65000
>[  174.470996] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  174.470997] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  174.470999] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  174.471000] [drm:intel_dump_pipe_config] ips: 0
>[  174.471000] [drm:intel_dump_pipe_config] double wide: 0
>[  174.471002] [drm:intel_display_power_get] enabling always-on
>[  174.471014] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  174.471015] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  174.471016] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  174.471024] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  174.472368] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  174.472370] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  174.473025] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  174.473027] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  174.473028] [drm:gen6_fdi_link_train] FDI train done.
>[  174.473031] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  174.473032] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  174.474904] [drm:intel_update_fbc] disabled per chip default
>[  174.474906] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.474910] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.474912] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.474914] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.474916] [drm:check_crtc_state] [CRTC:6]
>[  174.474926] [drm:check_crtc_state] [CRTC:10]
>[  174.474927] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.474930] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.474934] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.474935] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  174.474936] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.474938] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  174.474938] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.474939] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.474940] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  174.474942] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  174.508518] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  174.508526] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  174.508937] [drm:intel_update_fbc] no output, disabling
>[  174.508940] [drm:intel_display_power_put] disabling always-on
>[  174.508944] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.508946] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.508948] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.508950] [drm:check_crtc_state] [CRTC:6]
>[  174.508951] [drm:check_crtc_state] [CRTC:10]
>[  174.508952] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.508956] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.508963] [drm:drm_mode_setcrtc] [CRTC:10]
>[  174.508964] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  174.508966] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  174.508968] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.508970] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  174.508971] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  174.508972] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  174.508974] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.508975] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.508976] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  174.508977] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.508978] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  174.508979] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  174.508981] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  174.508982] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  174.508984] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  174.508985] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  174.508986] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  174.508987] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  174.508988] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  174.508990] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  174.508990] [drm:intel_dump_pipe_config] requested mode:
>[  174.508992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.508993] [drm:intel_dump_pipe_config] adjusted mode:
>[  174.508995] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.508997] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  174.508997] [drm:intel_dump_pipe_config] port clock: 65000
>[  174.508998] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  174.509000] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  174.509001] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  174.509002] [drm:intel_dump_pipe_config] ips: 0
>[  174.509003] [drm:intel_dump_pipe_config] double wide: 0
>[  174.509004] [drm:intel_display_power_get] enabling always-on
>[  174.509017] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  174.509018] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  174.509019] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  174.509027] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  174.510370] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  174.510372] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  174.511027] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  174.511029] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  174.511030] [drm:gen6_fdi_link_train] FDI train done.
>[  174.511033] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  174.511034] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  174.512906] [drm:intel_update_fbc] disabled per chip default
>[  174.512909] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.512912] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.512914] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.512916] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.512918] [drm:check_crtc_state] [CRTC:6]
>[  174.512928] [drm:check_crtc_state] [CRTC:10]
>[  174.512929] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.512932] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.512937] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.512938] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  174.512939] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.512940] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  174.512941] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.512942] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.512943] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  174.512944] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  174.546555] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  174.546563] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  174.546973] [drm:intel_update_fbc] no output, disabling
>[  174.546976] [drm:intel_display_power_put] disabling always-on
>[  174.546980] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.546983] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.546984] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.546986] [drm:check_crtc_state] [CRTC:6]
>[  174.546987] [drm:check_crtc_state] [CRTC:10]
>[  174.546988] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.546992] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.546998] [drm:drm_mode_setcrtc] [CRTC:10]
>[  174.546999] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  174.547001] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  174.547003] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.547005] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  174.547006] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  174.547007] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  174.547009] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.547010] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.547011] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  174.547012] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.547013] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  174.547014] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  174.547016] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  174.547017] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  174.547019] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  174.547020] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  174.547021] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  174.547022] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  174.547023] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  174.547025] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  174.547026] [drm:intel_dump_pipe_config] requested mode:
>[  174.547027] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.547028] [drm:intel_dump_pipe_config] adjusted mode:
>[  174.547030] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.547032] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  174.547033] [drm:intel_dump_pipe_config] port clock: 65000
>[  174.547034] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  174.547035] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  174.547036] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  174.547037] [drm:intel_dump_pipe_config] ips: 0
>[  174.547038] [drm:intel_dump_pipe_config] double wide: 0
>[  174.547039] [drm:intel_display_power_get] enabling always-on
>[  174.547052] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  174.547053] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  174.547054] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  174.547062] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  174.548406] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  174.548408] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  174.549063] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  174.549065] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  174.549065] [drm:gen6_fdi_link_train] FDI train done.
>[  174.549068] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  174.549069] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  174.550941] [drm:intel_update_fbc] disabled per chip default
>[  174.550944] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.550947] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.550949] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.550951] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.550953] [drm:check_crtc_state] [CRTC:6]
>[  174.550963] [drm:check_crtc_state] [CRTC:10]
>[  174.550964] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.550967] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.550972] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.550973] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  174.550974] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.550975] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  174.550976] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.550977] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.550978] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  174.550980] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  174.584554] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  174.584561] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  174.584972] [drm:intel_update_fbc] no output, disabling
>[  174.584975] [drm:intel_display_power_put] disabling always-on
>[  174.584979] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.584981] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.584983] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.584986] [drm:check_crtc_state] [CRTC:6]
>[  174.584987] [drm:check_crtc_state] [CRTC:10]
>[  174.584988] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.584992] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.584998] [drm:drm_mode_setcrtc] [CRTC:10]
>[  174.584999] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  174.585001] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  174.585003] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.585005] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  174.585006] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  174.585007] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  174.585009] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.585010] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.585011] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  174.585012] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.585013] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  174.585015] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  174.585016] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  174.585018] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  174.585019] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  174.585020] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  174.585021] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  174.585022] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  174.585023] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  174.585025] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  174.585026] [drm:intel_dump_pipe_config] requested mode:
>[  174.585028] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.585028] [drm:intel_dump_pipe_config] adjusted mode:
>[  174.585030] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.585032] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  174.585033] [drm:intel_dump_pipe_config] port clock: 65000
>[  174.585034] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  174.585035] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  174.585036] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  174.585037] [drm:intel_dump_pipe_config] ips: 0
>[  174.585038] [drm:intel_dump_pipe_config] double wide: 0
>[  174.585039] [drm:intel_display_power_get] enabling always-on
>[  174.585052] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  174.585053] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  174.585054] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  174.585062] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  174.586405] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  174.586407] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  174.587063] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  174.587064] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  174.587065] [drm:gen6_fdi_link_train] FDI train done.
>[  174.587068] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  174.587069] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  174.588941] [drm:intel_update_fbc] disabled per chip default
>[  174.588944] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.588947] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.588949] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.588951] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.588953] [drm:check_crtc_state] [CRTC:6]
>[  174.588963] [drm:check_crtc_state] [CRTC:10]
>[  174.588964] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.588967] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.588972] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.588973] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  174.588974] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.588975] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  174.588976] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.588977] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.588978] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  174.588980] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  174.622588] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  174.622595] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  174.623006] [drm:intel_update_fbc] no output, disabling
>[  174.623009] [drm:intel_display_power_put] disabling always-on
>[  174.623014] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.623016] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.623018] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.623020] [drm:check_crtc_state] [CRTC:6]
>[  174.623021] [drm:check_crtc_state] [CRTC:10]
>[  174.623022] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.623026] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.623033] [drm:drm_mode_setcrtc] [CRTC:10]
>[  174.623034] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  174.623036] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  174.623038] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.623040] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  174.623041] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  174.623042] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  174.623044] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.623045] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.623046] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  174.623047] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.623048] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  174.623049] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  174.623051] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  174.623052] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  174.623054] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  174.623055] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  174.623056] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  174.623057] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  174.623058] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  174.623060] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  174.623060] [drm:intel_dump_pipe_config] requested mode:
>[  174.623062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.623063] [drm:intel_dump_pipe_config] adjusted mode:
>[  174.623065] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.623067] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  174.623068] [drm:intel_dump_pipe_config] port clock: 65000
>[  174.623069] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  174.623070] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  174.623071] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  174.623072] [drm:intel_dump_pipe_config] ips: 0
>[  174.623073] [drm:intel_dump_pipe_config] double wide: 0
>[  174.623074] [drm:intel_display_power_get] enabling always-on
>[  174.623087] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  174.623088] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  174.623089] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  174.623097] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  174.624440] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  174.624442] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  174.625098] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  174.625099] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  174.625100] [drm:gen6_fdi_link_train] FDI train done.
>[  174.625103] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  174.625104] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  174.626975] [drm:intel_update_fbc] disabled per chip default
>[  174.626978] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.626981] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.626983] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.626985] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.626987] [drm:check_crtc_state] [CRTC:6]
>[  174.626997] [drm:check_crtc_state] [CRTC:10]
>[  174.626998] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.627001] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.627006] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.627007] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  174.627008] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.627009] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  174.627010] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.627011] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.627012] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  174.627014] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  174.660587] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  174.660595] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  174.661006] [drm:intel_update_fbc] no output, disabling
>[  174.661009] [drm:intel_display_power_put] disabling always-on
>[  174.661013] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.661015] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.661017] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.661019] [drm:check_crtc_state] [CRTC:6]
>[  174.661020] [drm:check_crtc_state] [CRTC:10]
>[  174.661021] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.661026] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.661032] [drm:drm_mode_setcrtc] [CRTC:10]
>[  174.661033] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  174.661035] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  174.661037] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.661039] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  174.661040] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  174.661041] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  174.661042] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.661043] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.661045] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  174.661046] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.661047] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  174.661048] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  174.661050] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  174.661051] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  174.661052] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  174.661053] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  174.661054] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  174.661055] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  174.661057] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  174.661058] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  174.661059] [drm:intel_dump_pipe_config] requested mode:
>[  174.661061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.661062] [drm:intel_dump_pipe_config] adjusted mode:
>[  174.661064] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.661065] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  174.661066] [drm:intel_dump_pipe_config] port clock: 65000
>[  174.661067] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  174.661068] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  174.661070] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  174.661071] [drm:intel_dump_pipe_config] ips: 0
>[  174.661071] [drm:intel_dump_pipe_config] double wide: 0
>[  174.661073] [drm:intel_display_power_get] enabling always-on
>[  174.661085] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  174.661086] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  174.661087] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  174.661095] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  174.662439] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  174.662441] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  174.663096] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  174.663098] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  174.663099] [drm:gen6_fdi_link_train] FDI train done.
>[  174.663102] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  174.663103] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  174.664975] [drm:intel_update_fbc] disabled per chip default
>[  174.664977] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.664981] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.664983] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.664985] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.664987] [drm:check_crtc_state] [CRTC:6]
>[  174.664997] [drm:check_crtc_state] [CRTC:10]
>[  174.664998] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.665001] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.665006] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.665007] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  174.665008] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.665009] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  174.665010] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.665011] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.665012] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  174.665013] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  174.698625] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  174.698633] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  174.699044] [drm:intel_update_fbc] no output, disabling
>[  174.699047] [drm:intel_display_power_put] disabling always-on
>[  174.699051] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.699053] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.699055] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.699058] [drm:check_crtc_state] [CRTC:6]
>[  174.699059] [drm:check_crtc_state] [CRTC:10]
>[  174.699060] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.699064] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.699070] [drm:drm_mode_setcrtc] [CRTC:10]
>[  174.699071] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  174.699073] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  174.699075] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.699077] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  174.699078] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  174.699079] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  174.699080] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.699081] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.699083] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  174.699084] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.699085] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  174.699086] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  174.699088] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  174.699089] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  174.699090] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  174.699092] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  174.699092] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  174.699093] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  174.699095] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  174.699097] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  174.699097] [drm:intel_dump_pipe_config] requested mode:
>[  174.699099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.699100] [drm:intel_dump_pipe_config] adjusted mode:
>[  174.699102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.699104] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  174.699104] [drm:intel_dump_pipe_config] port clock: 65000
>[  174.699105] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  174.699107] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  174.699108] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  174.699109] [drm:intel_dump_pipe_config] ips: 0
>[  174.699110] [drm:intel_dump_pipe_config] double wide: 0
>[  174.699111] [drm:intel_display_power_get] enabling always-on
>[  174.699123] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  174.699124] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  174.699125] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  174.699133] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  174.700477] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  174.700479] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  174.701134] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  174.701136] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  174.701137] [drm:gen6_fdi_link_train] FDI train done.
>[  174.701140] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  174.701141] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  174.703013] [drm:intel_update_fbc] disabled per chip default
>[  174.703015] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.703019] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.703021] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.703023] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.703025] [drm:check_crtc_state] [CRTC:6]
>[  174.703035] [drm:check_crtc_state] [CRTC:10]
>[  174.703036] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.703039] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.703044] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.703044] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  174.703046] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.703047] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  174.703048] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.703049] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.703050] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  174.703051] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  174.736623] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  174.736631] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  174.737042] [drm:intel_update_fbc] no output, disabling
>[  174.737045] [drm:intel_display_power_put] disabling always-on
>[  174.737049] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.737051] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.737053] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.737055] [drm:check_crtc_state] [CRTC:6]
>[  174.737056] [drm:check_crtc_state] [CRTC:10]
>[  174.737057] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.737062] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.737068] [drm:drm_mode_setcrtc] [CRTC:10]
>[  174.737069] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  174.737071] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  174.737073] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.737075] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  174.737076] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  174.737078] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  174.737079] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.737080] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.737081] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  174.737082] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.737083] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  174.737085] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  174.737086] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  174.737088] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  174.737089] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  174.737090] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  174.737091] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  174.737092] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  174.737094] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  174.737095] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  174.737096] [drm:intel_dump_pipe_config] requested mode:
>[  174.737098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.737099] [drm:intel_dump_pipe_config] adjusted mode:
>[  174.737100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.737102] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  174.737103] [drm:intel_dump_pipe_config] port clock: 65000
>[  174.737104] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  174.737105] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  174.737106] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  174.737107] [drm:intel_dump_pipe_config] ips: 0
>[  174.737108] [drm:intel_dump_pipe_config] double wide: 0
>[  174.737110] [drm:intel_display_power_get] enabling always-on
>[  174.737122] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  174.737123] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  174.737124] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  174.737132] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  174.738476] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  174.738478] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  174.739133] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  174.739135] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  174.739136] [drm:gen6_fdi_link_train] FDI train done.
>[  174.739139] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  174.739140] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  174.741012] [drm:intel_update_fbc] disabled per chip default
>[  174.741014] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.741018] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.741020] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.741022] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.741024] [drm:check_crtc_state] [CRTC:6]
>[  174.741034] [drm:check_crtc_state] [CRTC:10]
>[  174.741035] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.741038] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.741043] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.741044] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  174.741045] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.741046] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  174.741047] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.741048] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.741049] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  174.741050] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  174.774657] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  174.774664] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  174.775075] [drm:intel_update_fbc] no output, disabling
>[  174.775078] [drm:intel_display_power_put] disabling always-on
>[  174.775082] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.775085] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.775087] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.775089] [drm:check_crtc_state] [CRTC:6]
>[  174.775090] [drm:check_crtc_state] [CRTC:10]
>[  174.775091] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.775095] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.775101] [drm:drm_mode_setcrtc] [CRTC:10]
>[  174.775103] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  174.775104] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  174.775106] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.775108] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  174.775109] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  174.775111] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  174.775112] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.775113] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.775114] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  174.775115] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.775116] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  174.775118] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  174.775119] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  174.775121] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  174.775122] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  174.775123] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  174.775124] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  174.775125] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  174.775127] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  174.775128] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  174.775129] [drm:intel_dump_pipe_config] requested mode:
>[  174.775131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.775132] [drm:intel_dump_pipe_config] adjusted mode:
>[  174.775133] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.775135] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  174.775136] [drm:intel_dump_pipe_config] port clock: 65000
>[  174.775137] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  174.775138] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  174.775139] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  174.775140] [drm:intel_dump_pipe_config] ips: 0
>[  174.775141] [drm:intel_dump_pipe_config] double wide: 0
>[  174.775143] [drm:intel_display_power_get] enabling always-on
>[  174.775155] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  174.775156] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  174.775157] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  174.775165] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  174.776509] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  174.776511] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  174.777166] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  174.777168] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  174.777169] [drm:gen6_fdi_link_train] FDI train done.
>[  174.777171] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  174.777172] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  174.779044] [drm:intel_update_fbc] disabled per chip default
>[  174.779047] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.779050] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.779053] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.779055] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.779057] [drm:check_crtc_state] [CRTC:6]
>[  174.779066] [drm:check_crtc_state] [CRTC:10]
>[  174.779067] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.779070] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.779075] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.779076] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  174.779078] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.779079] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  174.779080] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.779080] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.779082] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  174.779083] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  174.801850] [drm] Enabling RC6 states: RC6 on, RC6p off, RC6pp off
>[  174.805640] [drm:gen6_enable_rps] Overclocking supported. Max: 1350MHz, Overclock max: 1350MHz
>[  174.812661] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  174.812669] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  174.813080] [drm:intel_update_fbc] no output, disabling
>[  174.813083] [drm:intel_display_power_put] disabling always-on
>[  174.813087] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.813089] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.813091] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.813094] [drm:check_crtc_state] [CRTC:6]
>[  174.813095] [drm:check_crtc_state] [CRTC:10]
>[  174.813096] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.813100] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.813106] [drm:drm_mode_setcrtc] [CRTC:10]
>[  174.813107] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  174.813109] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  174.813111] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.813113] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  174.813114] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  174.813115] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  174.813117] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.813118] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.813119] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  174.813120] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.813121] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  174.813122] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  174.813124] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  174.813125] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  174.813127] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  174.813128] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  174.813129] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  174.813129] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  174.813131] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  174.813133] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  174.813133] [drm:intel_dump_pipe_config] requested mode:
>[  174.813135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.813136] [drm:intel_dump_pipe_config] adjusted mode:
>[  174.813138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.813140] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  174.813140] [drm:intel_dump_pipe_config] port clock: 65000
>[  174.813141] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  174.813143] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  174.813144] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  174.813145] [drm:intel_dump_pipe_config] ips: 0
>[  174.813146] [drm:intel_dump_pipe_config] double wide: 0
>[  174.813147] [drm:intel_display_power_get] enabling always-on
>[  174.813159] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  174.813160] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  174.813161] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  174.813169] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  174.814516] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  174.814518] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  174.815173] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  174.815175] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  174.815176] [drm:gen6_fdi_link_train] FDI train done.
>[  174.815179] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  174.815180] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  174.817052] [drm:intel_update_fbc] disabled per chip default
>[  174.817055] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.817059] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.817061] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.817063] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.817065] [drm:check_crtc_state] [CRTC:6]
>[  174.817075] [drm:check_crtc_state] [CRTC:10]
>[  174.817076] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.817079] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.817084] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.817085] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  174.817087] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.817088] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  174.817089] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.817090] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.817091] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  174.817092] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  174.850692] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  174.850699] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  174.851110] [drm:intel_update_fbc] no output, disabling
>[  174.851113] [drm:intel_display_power_put] disabling always-on
>[  174.851119] [drm:intel_runtime_suspend] Suspending device
>[  174.851128] [drm:intel_runtime_suspend] Device suspended
>[  174.851138] ------------[ cut here ]------------
>[  174.851151] WARNING: CPU: 0 PID: 3854 at drivers/gpu/drm/i915/intel_uncore.c:47 assert_device_not_suspended+0x35/0x3a [i915]()
>[  174.851152] Device suspended
>[  174.851153] Modules linked in: dm_mod joydev snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic iTCO_wdt iTCO_vendor_support ppdev dcdbas serio_raw pcspkr i2c_i801 snd_hda_intel snd_hda_controller snd_hda_codec snd_hwdep snd_pcm lpc_ich snd_timer mfd_core snd soundcore parport_pc parport tpm_tis tpm acpi_cpufreq i915 video button drm_kms_helper drm
>[  174.851166] CPU: 0 PID: 3854 Comm: pm_rpm Tainted: G        W     3.15.0-rc8_kcloud_c63bb6_20140707+ #132
>[  174.851167] Hardware name: Dell Inc. OptiPlex 990/0DXWW6, BIOS A02 02/26/2011
>[  174.851168]  00000000 f24d7d48 c1699f5c f24d7d58 c102cfd4 f81cbdf4 00000009 c2800000
>[  174.851171]  000e1100 c2800058 f24d7d60 c102d010 00000009 f24d7d58 f82195b9 f24d7d74
>[  174.851174]  f24d7d74 f81cbdf4 f8219595 0000002f f82195b9 f4d73800 f81cc54e c2800000
>[  174.851177] Call Trace:
>[  174.851181]  [<c1699f5c>] ? dump_stack+0x3e/0x4e
>[  174.851184]  [<c102cfd4>] ? warn_slowpath_common+0x64/0x7a
>[  174.851192]  [<f81cbdf4>] ? assert_device_not_suspended+0x35/0x3a [i915]
>[  174.851195]  [<c102d010>] ? warn_slowpath_fmt+0x26/0x2a
>[  174.851202]  [<f81cbdf4>] ? assert_device_not_suspended+0x35/0x3a [i915]
>[  174.851209]  [<f81cc54e>] ? gen6_read32+0x10/0x62 [i915]
>[  174.851218]  [<f81ea5f5>] ? intel_crt_get_hw_state+0x33/0x5e [i915]
>[  174.851228]  [<f81d8c52>] ? intel_connector_get_hw_state+0x15/0x17 [i915]
>[  174.851236]  [<f81dee7f>] ? intel_modeset_check_state+0x31/0x52d [i915]
>[  174.851245]  [<f81df3e1>] ? intel_set_mode+0x21/0x2a [i915]
>[  174.851253]  [<f81dfedb>] ? intel_crtc_set_config+0x6b4/0x934 [i915]
>[  174.851255]  [<c1697480>] ? printk+0x17/0x1c
>[  174.851261]  [<f8096826>] ? drm_mode_set_config_internal+0x39/0x8a [drm]
>[  174.851266]  [<f809934d>] ? drm_mode_setcrtc+0x31b/0x3fe [drm]
>[  174.851270]  [<f8099032>] ? drm_mode_setplane+0x13b/0x13b [drm]
>[  174.851274]  [<f808ea98>] ? drm_ioctl+0x38f/0x40a [drm]
>[  174.851278]  [<f8099032>] ? drm_mode_setplane+0x13b/0x13b [drm]
>[  174.851281]  [<c10644c4>] ? ktime_get+0x58/0xc8
>[  174.851285]  [<f808e709>] ? drm_copy_field+0x47/0x47 [drm]
>[  174.851287]  [<c10c7eef>] ? do_vfs_ioctl+0x35f/0x40f
>[  174.851289]  [<c106b1cf>] ? tick_program_event+0x1f/0x25
>[  174.851291]  [<c1041e78>] ? hrtimer_interrupt+0x12e/0x1de
>[  174.851293]  [<c10c7fdd>] ? SyS_ioctl+0x3e/0x61
>[  174.851295]  [<c16a2eac>] ? sysenter_do_call+0x12/0x22
>[  174.851296] ---[ end trace c7babcea469cea06 ]---
>[  174.851299] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.851300] ------------[ cut here ]------------
>[  174.851308] WARNING: CPU: 0 PID: 3854 at drivers/gpu/drm/i915/intel_display.c:5027 intel_modeset_check_state+0x7d/0x52d [i915]()
>[  174.851309] wrong connector dpms state
>[  174.851310] Modules linked in: dm_mod joydev snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic iTCO_wdt iTCO_vendor_support ppdev dcdbas serio_raw pcspkr i2c_i801 snd_hda_intel snd_hda_controller snd_hda_codec snd_hwdep snd_pcm lpc_ich snd_timer mfd_core snd soundcore parport_pc parport tpm_tis tpm acpi_cpufreq i915 video button drm_kms_helper drm
>[  174.851321] CPU: 0 PID: 3854 Comm: pm_rpm Tainted: G        W     3.15.0-rc8_kcloud_c63bb6_20140707+ #132
>[  174.851322] Hardware name: Dell Inc. OptiPlex 990/0DXWW6, BIOS A02 02/26/2011
>[  174.851323]  00000000 f24d7d80 c1699f5c f24d7d90 c102cfd4 f81deecb 00000009 f5a3bc00
>[  174.851325]  f4d73800 f532b6c0 f24d7d98 c102d010 00000009 f24d7d90 f821c94e f24d7dac
>[  174.851328]  f24d7ddc f81deecb f821a32a 000013a3 f821c94e c2800000 00000000 f4d73a00
>[  174.851331] Call Trace:
>[  174.851333]  [<c1699f5c>] ? dump_stack+0x3e/0x4e
>[  174.851335]  [<c102cfd4>] ? warn_slowpath_common+0x64/0x7a
>[  174.851343]  [<f81deecb>] ? intel_modeset_check_state+0x7d/0x52d [i915]
>[  174.851345]  [<c102d010>] ? warn_slowpath_fmt+0x26/0x2a
>[  174.851352]  [<f81deecb>] ? intel_modeset_check_state+0x7d/0x52d [i915]
>[  174.851360]  [<f81df3e1>] ? intel_set_mode+0x21/0x2a [i915]
>[  174.851368]  [<f81dfedb>] ? intel_crtc_set_config+0x6b4/0x934 [i915]
>[  174.851369]  [<c1697480>] ? printk+0x17/0x1c
>[  174.851374]  [<f8096826>] ? drm_mode_set_config_internal+0x39/0x8a [drm]
>[  174.851379]  [<f809934d>] ? drm_mode_setcrtc+0x31b/0x3fe [drm]
>[  174.851382]  [<f8099032>] ? drm_mode_setplane+0x13b/0x13b [drm]
>[  174.851386]  [<f808ea98>] ? drm_ioctl+0x38f/0x40a [drm]
>[  174.851389]  [<f8099032>] ? drm_mode_setplane+0x13b/0x13b [drm]
>[  174.851391]  [<c10644c4>] ? ktime_get+0x58/0xc8
>[  174.851395]  [<f808e709>] ? drm_copy_field+0x47/0x47 [drm]
>[  174.851397]  [<c10c7eef>] ? do_vfs_ioctl+0x35f/0x40f
>[  174.851398]  [<c106b1cf>] ? tick_program_event+0x1f/0x25
>[  174.851400]  [<c1041e78>] ? hrtimer_interrupt+0x12e/0x1de
>[  174.851402]  [<c10c7fdd>] ? SyS_ioctl+0x3e/0x61
>[  174.851403]  [<c16a2eac>] ? sysenter_do_call+0x12/0x22
>[  174.851404] ---[ end trace c7babcea469cea07 ]---
>[  174.851405] ------------[ cut here ]------------
>[  174.851413] WARNING: CPU: 0 PID: 3854 at drivers/gpu/drm/i915/intel_display.c:5029 intel_modeset_check_state+0x9c/0x52d [i915]()
>[  174.851414] active connector not linked to encoder
>[  174.851414] Modules linked in: dm_mod joydev snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic iTCO_wdt iTCO_vendor_support ppdev dcdbas serio_raw pcspkr i2c_i801 snd_hda_intel snd_hda_controller snd_hda_codec snd_hwdep snd_pcm lpc_ich snd_timer mfd_core snd soundcore parport_pc parport tpm_tis tpm acpi_cpufreq i915 video button drm_kms_helper drm
>[  174.851425] CPU: 0 PID: 3854 Comm: pm_rpm Tainted: G        W     3.15.0-rc8_kcloud_c63bb6_20140707+ #132
>[  174.851426] Hardware name: Dell Inc. OptiPlex 990/0DXWW6, BIOS A02 02/26/2011
>[  174.851427]  00000000 f24d7d80 c1699f5c f24d7d90 c102cfd4 f81deeea 00000009 f5a3bc00
>[  174.851430]  f4d73800 f532b6c0 f24d7d98 c102d010 00000009 f24d7d90 f821c96a f24d7dac
>[  174.851432]  f24d7ddc f81deeea f821a32a 000013a5 f821c96a c2800000 00000000 f4d73a00
>[  174.851435] Call Trace:
>[  174.851437]  [<c1699f5c>] ? dump_stack+0x3e/0x4e
>[  174.851439]  [<c102cfd4>] ? warn_slowpath_common+0x64/0x7a
>[  174.851446]  [<f81deeea>] ? intel_modeset_check_state+0x9c/0x52d [i915]
>[  174.851448]  [<c102d010>] ? warn_slowpath_fmt+0x26/0x2a
>[  174.851455]  [<f81deeea>] ? intel_modeset_check_state+0x9c/0x52d [i915]
>[  174.851463]  [<f81df3e1>] ? intel_set_mode+0x21/0x2a [i915]
>[  174.851471]  [<f81dfedb>] ? intel_crtc_set_config+0x6b4/0x934 [i915]
>[  174.851473]  [<c1697480>] ? printk+0x17/0x1c
>[  174.851477]  [<f8096826>] ? drm_mode_set_config_internal+0x39/0x8a [drm]
>[  174.851481]  [<f809934d>] ? drm_mode_setcrtc+0x31b/0x3fe [drm]
>[  174.851485]  [<f8099032>] ? drm_mode_setplane+0x13b/0x13b [drm]
>[  174.851488]  [<f808ea98>] ? drm_ioctl+0x38f/0x40a [drm]
>[  174.851492]  [<f8099032>] ? drm_mode_setplane+0x13b/0x13b [drm]
>[  174.851494]  [<c10644c4>] ? ktime_get+0x58/0xc8
>[  174.851497]  [<f808e709>] ? drm_copy_field+0x47/0x47 [drm]
>[  174.851499]  [<c10c7eef>] ? do_vfs_ioctl+0x35f/0x40f
>[  174.851501]  [<c106b1cf>] ? tick_program_event+0x1f/0x25
>[  174.851502]  [<c1041e78>] ? hrtimer_interrupt+0x12e/0x1de
>[  174.851504]  [<c10c7fdd>] ? SyS_ioctl+0x3e/0x61
>[  174.851505]  [<c16a2eac>] ? sysenter_do_call+0x12/0x22
>[  174.851507] ---[ end trace c7babcea469cea08 ]---
>[  174.851507] ------------[ cut here ]------------
>[  174.851515] WARNING: CPU: 0 PID: 3854 at drivers/gpu/drm/i915/intel_display.c:5031 intel_modeset_check_state+0xb9/0x52d [i915]()
>[  174.851516] encoder->connectors_active not set
>[  174.851516] Modules linked in: dm_mod joydev snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic iTCO_wdt iTCO_vendor_support ppdev dcdbas serio_raw pcspkr i2c_i801 snd_hda_intel snd_hda_controller snd_hda_codec snd_hwdep snd_pcm lpc_ich snd_timer mfd_core snd soundcore parport_pc parport tpm_tis tpm acpi_cpufreq i915 video button drm_kms_helper drm
>[  174.851527] CPU: 0 PID: 3854 Comm: pm_rpm Tainted: G        W     3.15.0-rc8_kcloud_c63bb6_20140707+ #132
>[  174.851528] Hardware name: Dell Inc. OptiPlex 990/0DXWW6, BIOS A02 02/26/2011
>[  174.851529]  00000000 f24d7d80 c1699f5c f24d7d90 c102cfd4 f81def07 00000009 f5a3bc00
>[  174.851531]  f4d73800 f532b6c0 f24d7d98 c102d010 00000009 f24d7d90 f821c992 f24d7dac
>[  174.851534]  f24d7ddc f81def07 f821a32a 000013a7 f821c992 c2800000 00000000 f4d73a00
>[  174.851537] Call Trace:
>[  174.851539]  [<c1699f5c>] ? dump_stack+0x3e/0x4e
>[  174.851541]  [<c102cfd4>] ? warn_slowpath_common+0x64/0x7a
>[  174.851548]  [<f81def07>] ? intel_modeset_check_state+0xb9/0x52d [i915]
>[  174.851550]  [<c102d010>] ? warn_slowpath_fmt+0x26/0x2a
>[  174.851557]  [<f81def07>] ? intel_modeset_check_state+0xb9/0x52d [i915]
>[  174.851565]  [<f81df3e1>] ? intel_set_mode+0x21/0x2a [i915]
>[  174.851572]  [<f81dfedb>] ? intel_crtc_set_config+0x6b4/0x934 [i915]
>[  174.851574]  [<c1697480>] ? printk+0x17/0x1c
>[  174.851579]  [<f8096826>] ? drm_mode_set_config_internal+0x39/0x8a [drm]
>[  174.851582]  [<f809934d>] ? drm_mode_setcrtc+0x31b/0x3fe [drm]
>[  174.851586]  [<f8099032>] ? drm_mode_setplane+0x13b/0x13b [drm]
>[  174.851590]  [<f808ea98>] ? drm_ioctl+0x38f/0x40a [drm]
>[  174.851593]  [<f8099032>] ? drm_mode_setplane+0x13b/0x13b [drm]
>[  174.851595]  [<c10644c4>] ? ktime_get+0x58/0xc8
>[  174.851598]  [<f808e709>] ? drm_copy_field+0x47/0x47 [drm]
>[  174.851600]  [<c10c7eef>] ? do_vfs_ioctl+0x35f/0x40f
>[  174.851602]  [<c106b1cf>] ? tick_program_event+0x1f/0x25
>[  174.851603]  [<c1041e78>] ? hrtimer_interrupt+0x12e/0x1de
>[  174.851605]  [<c10c7fdd>] ? SyS_ioctl+0x3e/0x61
>[  174.851606]  [<c16a2eac>] ? sysenter_do_call+0x12/0x22
>[  174.851608] ---[ end trace c7babcea469cea09 ]---
>[  174.851608] ------------[ cut here ]------------
>[  174.851616] WARNING: CPU: 0 PID: 3854 at drivers/gpu/drm/i915/intel_display.c:5034 intel_modeset_check_state+0xdc/0x52d [i915]()
>[  174.851617] encoder not enabled
>[  174.851617] Modules linked in: dm_mod joydev snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic iTCO_wdt iTCO_vendor_support ppdev dcdbas serio_raw pcspkr i2c_i801 snd_hda_intel snd_hda_controller snd_hda_codec snd_hwdep snd_pcm lpc_ich snd_timer mfd_core snd soundcore parport_pc parport tpm_tis tpm acpi_cpufreq i915 video button drm_kms_helper drm
>[  174.851628] CPU: 0 PID: 3854 Comm: pm_rpm Tainted: G        W     3.15.0-rc8_kcloud_c63bb6_20140707+ #132
>[  174.851629] Hardware name: Dell Inc. OptiPlex 990/0DXWW6, BIOS A02 02/26/2011
>[  174.851629]  00000000 f24d7d80 c1699f5c f24d7d90 c102cfd4 f81def2a 00000009 f5a3bc00
>[  174.851632]  f4d73800 f532b6c0 f24d7d98 c102d010 00000009 f24d7d90 f821c9b6 f24d7dac
>[  174.851635]  f24d7ddc f81def2a f821a32a 000013aa f821c9b6 c2800000 00000000 f4d73a00
>[  174.851638] Call Trace:
>[  174.851639]  [<c1699f5c>] ? dump_stack+0x3e/0x4e
>[  174.851641]  [<c102cfd4>] ? warn_slowpath_common+0x64/0x7a
>[  174.851649]  [<f81def2a>] ? intel_modeset_check_state+0xdc/0x52d [i915]
>[  174.851656]  [<c102d010>] ? warn_slowpath_fmt+0x26/0x2a
>[  174.851664]  [<f81def2a>] ? intel_modeset_check_state+0xdc/0x52d [i915]
>[  174.851671]  [<f81df3e1>] ? intel_set_mode+0x21/0x2a [i915]
>[  174.851679]  [<f81dfedb>] ? intel_crtc_set_config+0x6b4/0x934 [i915]
>[  174.851681]  [<c1697480>] ? printk+0x17/0x1c
>[  174.851685]  [<f8096826>] ? drm_mode_set_config_internal+0x39/0x8a [drm]
>[  174.851696]  [<f809934d>] ? drm_mode_setcrtc+0x31b/0x3fe [drm]
>[  174.851704]  [<f8099032>] ? drm_mode_setplane+0x13b/0x13b [drm]
>[  174.851712]  [<f808ea98>] ? drm_ioctl+0x38f/0x40a [drm]
>[  174.851720]  [<f8099032>] ? drm_mode_setplane+0x13b/0x13b [drm]
>[  174.851727]  [<c10644c4>] ? ktime_get+0x58/0xc8
>[  174.851736]  [<f808e709>] ? drm_copy_field+0x47/0x47 [drm]
>[  174.851742]  [<c10c7eef>] ? do_vfs_ioctl+0x35f/0x40f
>[  174.851748]  [<c106b1cf>] ? tick_program_event+0x1f/0x25
>[  174.851755]  [<c1041e78>] ? hrtimer_interrupt+0x12e/0x1de
>[  174.851761]  [<c10c7fdd>] ? SyS_ioctl+0x3e/0x61
>[  174.851767]  [<c16a2eac>] ? sysenter_do_call+0x12/0x22
>[  174.851771] ---[ end trace c7babcea469cea0a ]---
>[  174.851772] ------------[ cut here ]------------
>[  174.851779] WARNING: CPU: 0 PID: 3854 at drivers/gpu/drm/i915/intel_display.c:5035 intel_modeset_check_state+0xf5/0x52d [i915]()
>[  174.851780] Modules linked in: dm_mod joydev snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic iTCO_wdt iTCO_vendor_support ppdev dcdbas serio_raw pcspkr i2c_i801 snd_hda_intel snd_hda_controller snd_hda_codec snd_hwdep snd_pcm lpc_ich snd_timer mfd_core snd soundcore parport_pc parport tpm_tis tpm acpi_cpufreq i915 video button drm_kms_helper drm
>[  174.851796] CPU: 0 PID: 3854 Comm: pm_rpm Tainted: G        W     3.15.0-rc8_kcloud_c63bb6_20140707+ #132
>[  174.851797] Hardware name: Dell Inc. OptiPlex 990/0DXWW6, BIOS A02 02/26/2011
>[  174.851798]  00000000 f24d7d94 c1699f5c 00000000 c102cfd4 f81def43 00000009 f5a3bc00
>[  174.851802]  f4d73800 00000000 f24d7da4 c102d04e 00000009 00000000 f24d7ddc f81def43
>[  174.851807]  c2800000 00000000 f4d73a00 00000000 f4d739cc 00000000 00000000 f5a78000
>[  174.851811] Call Trace:
>[  174.851814]  [<c1699f5c>] ? dump_stack+0x3e/0x4e
>[  174.851817]  [<c102cfd4>] ? warn_slowpath_common+0x64/0x7a
>[  174.851829]  [<f81def43>] ? intel_modeset_check_state+0xf5/0x52d [i915]
>[  174.851832]  [<c102d04e>] ? warn_slowpath_null+0xf/0x13
>[  174.851844]  [<f81def43>] ? intel_modeset_check_state+0xf5/0x52d [i915]
>[  174.851857]  [<f81df3e1>] ? intel_set_mode+0x21/0x2a [i915]
>[  174.851869]  [<f81dfedb>] ? intel_crtc_set_config+0x6b4/0x934 [i915]
>[  174.851873]  [<c1697480>] ? printk+0x17/0x1c
>[  174.851880]  [<f8096826>] ? drm_mode_set_config_internal+0x39/0x8a [drm]
>[  174.851886]  [<f809934d>] ? drm_mode_setcrtc+0x31b/0x3fe [drm]
>[  174.851893]  [<f8099032>] ? drm_mode_setplane+0x13b/0x13b [drm]
>[  174.851898]  [<f808ea98>] ? drm_ioctl+0x38f/0x40a [drm]
>[  174.851904]  [<f8099032>] ? drm_mode_setplane+0x13b/0x13b [drm]
>[  174.851907]  [<c10644c4>] ? ktime_get+0x58/0xc8
>[  174.851913]  [<f808e709>] ? drm_copy_field+0x47/0x47 [drm]
>[  174.851916]  [<c10c7eef>] ? do_vfs_ioctl+0x35f/0x40f
>[  174.851918]  [<c106b1cf>] ? tick_program_event+0x1f/0x25
>[  174.851920]  [<c1041e78>] ? hrtimer_interrupt+0x12e/0x1de
>[  174.851923]  [<c10c7fdd>] ? SyS_ioctl+0x3e/0x61
>[  174.851926]  [<c16a2eac>] ? sysenter_do_call+0x12/0x22
>[  174.851927] ---[ end trace c7babcea469cea0b ]---
>[  174.851930] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.851931] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.851933] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.851935] [drm:check_crtc_state] [CRTC:6]
>[  174.851936] [drm:check_crtc_state] [CRTC:10]
>[  174.851938] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.851939] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.851944] [drm:drm_mode_setcrtc] [CRTC:10]
>[  174.851946] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  174.851948] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  174.851951] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.851954] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  174.851956] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  174.851958] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  174.851960] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.851962] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.851964] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  174.851965] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.851967] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  174.851969] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  174.851971] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  174.851974] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  174.851976] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  174.851977] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  174.851980] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  174.851981] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  174.851984] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  174.851986] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  174.851988] [drm:intel_dump_pipe_config] requested mode:
>[  174.851991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.851992] [drm:intel_dump_pipe_config] adjusted mode:
>[  174.851995] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.851998] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  174.852000] [drm:intel_dump_pipe_config] port clock: 65000
>[  174.852002] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  174.852004] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  174.852005] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  174.852007] [drm:intel_dump_pipe_config] ips: 0
>[  174.852008] [drm:intel_dump_pipe_config] double wide: 0
>[  174.872701] [drm:intel_runtime_resume] Resuming device
>[  174.872705] [drm:ironlake_init_pch_refclk] has_panel 0 has_lvds 0 has_ck505 0
>[  174.894723] [drm:intel_runtime_resume] Device resumed
>[  174.894729] [drm:intel_display_power_get] enabling always-on
>[  174.894759] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  174.894760] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  174.894761] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  174.894768] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  174.896113] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  174.896115] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  174.896770] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  174.896772] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  174.896773] [drm:gen6_fdi_link_train] FDI train done.
>[  174.896776] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  174.896777] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  174.898649] [drm:intel_update_fbc] disabled per chip default
>[  174.898652] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.898656] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.898658] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.898660] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.898662] [drm:check_crtc_state] [CRTC:6]
>[  174.898674] [drm:check_crtc_state] [CRTC:10]
>[  174.898675] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.898679] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.898685] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.898686] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  174.898688] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.898689] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  174.898690] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.898691] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.898692] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  174.898694] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  174.932715] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  174.932722] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  174.933133] [drm:intel_update_fbc] no output, disabling
>[  174.933136] [drm:intel_display_power_put] disabling always-on
>[  174.933141] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.933143] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.933145] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.933147] [drm:check_crtc_state] [CRTC:6]
>[  174.933148] [drm:check_crtc_state] [CRTC:10]
>[  174.933149] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.933153] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.933160] [drm:drm_mode_setcrtc] [CRTC:10]
>[  174.933161] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  174.933162] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  174.933164] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.933166] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  174.933168] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  174.933169] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  174.933170] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.933171] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.933172] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  174.933173] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.933175] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  174.933176] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  174.933177] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  174.933179] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  174.933180] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  174.933181] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  174.933182] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  174.933183] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  174.933185] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  174.933186] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  174.933187] [drm:intel_dump_pipe_config] requested mode:
>[  174.933189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.933190] [drm:intel_dump_pipe_config] adjusted mode:
>[  174.933192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.933193] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  174.933194] [drm:intel_dump_pipe_config] port clock: 65000
>[  174.933195] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  174.933196] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  174.933197] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  174.933198] [drm:intel_dump_pipe_config] ips: 0
>[  174.933199] [drm:intel_dump_pipe_config] double wide: 0
>[  174.933201] [drm:intel_display_power_get] enabling always-on
>[  174.933213] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  174.933214] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  174.933215] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  174.933223] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  174.934567] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  174.934569] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  174.935224] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  174.935226] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  174.935227] [drm:gen6_fdi_link_train] FDI train done.
>[  174.935230] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  174.935230] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  174.937102] [drm:intel_update_fbc] disabled per chip default
>[  174.937105] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.937109] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.937111] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.937113] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.937115] [drm:check_crtc_state] [CRTC:6]
>[  174.937124] [drm:check_crtc_state] [CRTC:10]
>[  174.937125] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.937129] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.937133] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.937134] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  174.937136] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.937137] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  174.937138] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.937139] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.937140] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  174.937141] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  174.970748] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  174.970755] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  174.971166] [drm:intel_update_fbc] no output, disabling
>[  174.971169] [drm:intel_display_power_put] disabling always-on
>[  174.971173] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.971176] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.971177] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.971179] [drm:check_crtc_state] [CRTC:6]
>[  174.971180] [drm:check_crtc_state] [CRTC:10]
>[  174.971181] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.971186] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.971192] [drm:drm_mode_setcrtc] [CRTC:10]
>[  174.971193] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  174.971195] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  174.971197] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.971199] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  174.971201] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  174.971202] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  174.971203] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.971204] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.971205] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  174.971206] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.971207] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  174.971209] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  174.971210] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  174.971212] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  174.971213] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  174.971214] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  174.971215] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  174.971216] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  174.971218] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  174.971219] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  174.971220] [drm:intel_dump_pipe_config] requested mode:
>[  174.971222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.971223] [drm:intel_dump_pipe_config] adjusted mode:
>[  174.971224] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  174.971226] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  174.971227] [drm:intel_dump_pipe_config] port clock: 65000
>[  174.971228] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  174.971229] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  174.971230] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  174.971231] [drm:intel_dump_pipe_config] ips: 0
>[  174.971232] [drm:intel_dump_pipe_config] double wide: 0
>[  174.971234] [drm:intel_display_power_get] enabling always-on
>[  174.971246] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  174.971247] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  174.971248] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  174.971256] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  174.972599] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  174.972601] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  174.973256] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  174.973258] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  174.973259] [drm:gen6_fdi_link_train] FDI train done.
>[  174.973262] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  174.973262] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  174.975134] [drm:intel_update_fbc] disabled per chip default
>[  174.975137] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  174.975141] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  174.975143] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  174.975145] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  174.975147] [drm:check_crtc_state] [CRTC:6]
>[  174.975156] [drm:check_crtc_state] [CRTC:10]
>[  174.975157] [drm:check_shared_dpll_state] PCH DPLL A
>[  174.975161] [drm:check_shared_dpll_state] PCH DPLL B
>[  174.975165] [drm:drm_mode_setcrtc] [CRTC:6]
>[  174.975166] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  174.975168] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  174.975169] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  174.975170] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  174.975171] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  174.975172] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  174.975173] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  175.008751] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  175.008759] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  175.009170] [drm:intel_update_fbc] no output, disabling
>[  175.009173] [drm:intel_display_power_put] disabling always-on
>[  175.009177] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  175.009179] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  175.009181] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  175.009183] [drm:check_crtc_state] [CRTC:6]
>[  175.009184] [drm:check_crtc_state] [CRTC:10]
>[  175.009185] [drm:check_shared_dpll_state] PCH DPLL A
>[  175.009189] [drm:check_shared_dpll_state] PCH DPLL B
>[  175.009195] [drm:drm_mode_setcrtc] [CRTC:10]
>[  175.009196] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  175.009198] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  175.009200] [drm:drm_mode_setcrtc] [CRTC:6]
>[  175.009202] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  175.009203] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  175.009205] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  175.009206] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  175.009207] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  175.009208] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  175.009209] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  175.009210] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  175.009212] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  175.009213] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  175.009215] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  175.009216] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  175.009217] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  175.009218] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  175.009219] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  175.009221] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  175.009222] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  175.009223] [drm:intel_dump_pipe_config] requested mode:
>[  175.009225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  175.009226] [drm:intel_dump_pipe_config] adjusted mode:
>[  175.009227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  175.009229] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  175.009230] [drm:intel_dump_pipe_config] port clock: 65000
>[  175.009231] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  175.009232] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  175.009233] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  175.009234] [drm:intel_dump_pipe_config] ips: 0
>[  175.009235] [drm:intel_dump_pipe_config] double wide: 0
>[  175.009237] [drm:intel_display_power_get] enabling always-on
>[  175.009249] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  175.009250] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  175.009251] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  175.009259] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  175.010602] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  175.010604] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  175.011260] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  175.011262] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  175.011262] [drm:gen6_fdi_link_train] FDI train done.
>[  175.011265] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  175.011266] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  175.013138] [drm:intel_update_fbc] disabled per chip default
>[  175.013140] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  175.013144] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  175.013146] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  175.013148] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  175.013150] [drm:check_crtc_state] [CRTC:6]
>[  175.013159] [drm:check_crtc_state] [CRTC:10]
>[  175.013160] [drm:check_shared_dpll_state] PCH DPLL A
>[  175.013164] [drm:check_shared_dpll_state] PCH DPLL B
>[  175.013168] [drm:drm_mode_setcrtc] [CRTC:6]
>[  175.013169] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  175.013171] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  175.013172] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  175.013173] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  175.013174] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  175.013175] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  175.013176] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  175.046786] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  175.046793] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  175.047204] [drm:intel_update_fbc] no output, disabling
>[  175.047207] [drm:intel_display_power_put] disabling always-on
>[  175.047211] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  175.047213] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  175.047215] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  175.047218] [drm:check_crtc_state] [CRTC:6]
>[  175.047219] [drm:check_crtc_state] [CRTC:10]
>[  175.047220] [drm:check_shared_dpll_state] PCH DPLL A
>[  175.047224] [drm:check_shared_dpll_state] PCH DPLL B
>[  175.047231] [drm:drm_mode_setcrtc] [CRTC:10]
>[  175.047232] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  175.047233] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  175.047236] [drm:drm_mode_setcrtc] [CRTC:6]
>[  175.047237] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  175.047239] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  175.047240] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  175.047241] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  175.047242] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  175.047244] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  175.047245] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  175.047246] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  175.047247] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  175.047248] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  175.047250] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  175.047251] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  175.047252] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  175.047253] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  175.047254] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  175.047256] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  175.047257] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  175.047258] [drm:intel_dump_pipe_config] requested mode:
>[  175.047260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  175.047261] [drm:intel_dump_pipe_config] adjusted mode:
>[  175.047263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  175.047264] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  175.047265] [drm:intel_dump_pipe_config] port clock: 65000
>[  175.047266] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  175.047267] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  175.047269] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  175.047270] [drm:intel_dump_pipe_config] ips: 0
>[  175.047270] [drm:intel_dump_pipe_config] double wide: 0
>[  175.047272] [drm:intel_display_power_get] enabling always-on
>[  175.047284] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  175.047285] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  175.047286] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  175.047294] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  175.048638] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  175.048640] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  175.049295] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  175.049297] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  175.049298] [drm:gen6_fdi_link_train] FDI train done.
>[  175.049301] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  175.049302] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  175.051173] [drm:intel_update_fbc] disabled per chip default
>[  175.051176] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  175.051180] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  175.051182] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  175.051184] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  175.051186] [drm:check_crtc_state] [CRTC:6]
>[  175.051195] [drm:check_crtc_state] [CRTC:10]
>[  175.051196] [drm:check_shared_dpll_state] PCH DPLL A
>[  175.051200] [drm:check_shared_dpll_state] PCH DPLL B
>[  175.051204] [drm:drm_mode_setcrtc] [CRTC:6]
>[  175.051205] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  175.051207] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  175.051208] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  175.051209] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  175.051210] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  175.051211] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  175.051212] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  175.084784] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  175.084792] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  175.085203] [drm:intel_update_fbc] no output, disabling
>[  175.085206] [drm:intel_display_power_put] disabling always-on
>[  175.085210] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  175.085212] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  175.085214] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  175.085216] [drm:check_crtc_state] [CRTC:6]
>[  175.085217] [drm:check_crtc_state] [CRTC:10]
>[  175.085218] [drm:check_shared_dpll_state] PCH DPLL A
>[  175.085223] [drm:check_shared_dpll_state] PCH DPLL B
>[  175.085229] [drm:drm_mode_setcrtc] [CRTC:10]
>[  175.085230] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  175.085232] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  175.085234] [drm:drm_mode_setcrtc] [CRTC:6]
>[  175.085236] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  175.085237] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  175.085239] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  175.085240] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  175.085241] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  175.085242] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  175.085243] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  175.085244] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  175.085246] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  175.085247] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  175.085249] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  175.085250] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  175.085251] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  175.085252] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  175.085253] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  175.085255] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  175.085256] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  175.085257] [drm:intel_dump_pipe_config] requested mode:
>[  175.085259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  175.085260] [drm:intel_dump_pipe_config] adjusted mode:
>[  175.085261] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  175.085263] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  175.085264] [drm:intel_dump_pipe_config] port clock: 65000
>[  175.085265] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  175.085266] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  175.085267] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  175.085268] [drm:intel_dump_pipe_config] ips: 0
>[  175.085269] [drm:intel_dump_pipe_config] double wide: 0
>[  175.085271] [drm:intel_display_power_get] enabling always-on
>[  175.085283] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  175.085284] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  175.085285] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  175.085293] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  175.086637] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  175.086639] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  175.087294] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  175.087296] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  175.087297] [drm:gen6_fdi_link_train] FDI train done.
>[  175.087300] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  175.087300] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  175.089172] [drm:intel_update_fbc] disabled per chip default
>[  175.089175] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  175.089178] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  175.089181] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  175.089183] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  175.089185] [drm:check_crtc_state] [CRTC:6]
>[  175.089194] [drm:check_crtc_state] [CRTC:10]
>[  175.089195] [drm:check_shared_dpll_state] PCH DPLL A
>[  175.089198] [drm:check_shared_dpll_state] PCH DPLL B
>[  175.089203] [drm:drm_mode_setcrtc] [CRTC:6]
>[  175.089204] [drm:intel_crtc_set_config] [CRTC:6] [NOFB]
>[  175.089205] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  175.089207] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [NOCRTC]
>[  175.089208] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  175.089208] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  175.089210] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  175.089211] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  175.122817] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 6
>[  175.122825] [drm:intel_disable_shared_dpll] disabling PCH DPLL A
>[  175.123235] [drm:intel_update_fbc] no output, disabling
>[  175.123238] [drm:intel_display_power_put] disabling always-on
>[  175.123243] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  175.123245] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  175.123247] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  175.123249] [drm:check_crtc_state] [CRTC:6]
>[  175.123250] [drm:check_crtc_state] [CRTC:10]
>[  175.123251] [drm:check_shared_dpll_state] PCH DPLL A
>[  175.123256] [drm:check_shared_dpll_state] PCH DPLL B
>[  175.123261] [drm:drm_mode_setcrtc] [CRTC:10]
>[  175.123262] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  175.123264] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  175.123266] [drm:drm_mode_setcrtc] [CRTC:6]
>[  175.123268] [drm:drm_mode_setcrtc] [CONNECTOR:12:VGA-1]
>[  175.123269] [drm:intel_crtc_set_config] [CRTC:6] [FB:28] #connectors=1 (x y) (0 0)
>[  175.123271] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  175.123272] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=1, fb_changed=0
>[  175.123273] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  175.123274] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  175.123275] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  175.123276] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  175.123278] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  175.123279] [drm:connected_sink_compute_bpp] [CONNECTOR:12:VGA-1] checking for sink bpp constrains
>[  175.123281] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1
>[  175.123282] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  175.123283] [drm:intel_dump_pipe_config] [CRTC:6][modeset] config for pipe A
>[  175.123284] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  175.123285] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  175.123287] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64
>[  175.123288] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  175.123289] [drm:intel_dump_pipe_config] requested mode:
>[  175.123291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  175.123292] [drm:intel_dump_pipe_config] adjusted mode:
>[  175.123293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  175.123295] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  175.123296] [drm:intel_dump_pipe_config] port clock: 65000
>[  175.123297] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  175.123298] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  175.123299] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  175.123300] [drm:intel_dump_pipe_config] ips: 0
>[  175.123301] [drm:intel_dump_pipe_config] double wide: 0
>[  175.123303] [drm:intel_display_power_get] enabling always-on
>[  175.123315] [drm:intel_get_shared_dpll] CRTC:6 allocated PCH DPLL A
>[  175.123316] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A
>[  175.123317] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A
>[  175.123325] [drm:ironlake_update_primary_plane] Writing base 004B2000 00000000 0 0 4096
>[  175.124668] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x100
>[  175.124670] [drm:gen6_fdi_link_train] FDI train 1 done.
>[  175.125326] [drm:gen6_fdi_link_train] FDI_RX_IIR 0x600
>[  175.125328] [drm:gen6_fdi_link_train] FDI train 2 done.
>[  175.125328] [drm:gen6_fdi_link_train] FDI train done.
>[  175.125331] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 6
>[  175.125332] [drm:intel_enable_shared_dpll] enabling PCH DPLL A
>[  175.127204] [drm:intel_update_fbc] disabled per chip default
>[  175.127207] [drm:intel_connector_check_state] [CONNECTOR:12:VGA-1]
>[  175.127210] [drm:check_encoder_state] [ENCODER:13:DAC-13]
>[  175.127212] [drm:check_encoder_state] [ENCODER:14:TMDS-14]
>[  175.127214] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[  175.127216] [drm:check_crtc_state] [CRTC:6]
>[  175.127226] [drm:check_crtc_state] [CRTC:10]
>[  175.127226] [drm:check_shared_dpll_state] PCH DPLL A
>[  175.127230] [drm:check_shared_dpll_state] PCH DPLL B
>[  175.127289] [drm:intel_crtc_set_config] [CRTC:6] [FB:27] #connectors=1 (x y) (0 0)
>[  175.127290] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=0, fb_changed=1
>[  175.127291] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  175.127293] [drm:ironlake_update_primary_plane] Writing base 001A6000 00000000 0 0 4096
>[  175.144807] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  175.144810] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  175.144812] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  175.147611] [drm:intel_crtc_set_config] [CRTC:6] [FB:27] #connectors=1 (x y) (0 0)
>[  175.147614] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:6], mode_changed=0, fb_changed=0
>[  175.147615] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  175.147616] [drm:intel_crtc_set_config] [CRTC:10] [NOFB]
>[  175.147618] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:10], mode_changed=0, fb_changed=0
>[  175.147619] [drm:intel_modeset_stage_output_state] [CONNECTOR:12:VGA-1] to [CRTC:6]
>[  176.802807] [drm] Enabling RC6 states: RC6 on, RC6p off, RC6pp off
>[  176.806564] [drm:gen6_enable_rps] Overclocking supported. Max: 1350MHz, Overclock max: 1350MHz

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Attachments on bug 80463: 101656 | 101820 | 102162 | 102343 | 102498

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