Attachment 102461 Details for Bug 81082 – dmesg after s3

dmesg after s3

dmesg-after-s3.log (text/plain), 123.51 KB, created by liulei on 2014-07-09 07:00:37 UTC

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Description:

Filename:

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Creator: liulei

Created: 2014-07-09 07:00:37 UTC

Size: 123.51 KB

patch

obsolete

>[  147.757523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  147.758040] [drm:intel_dp_start_link_train] clock recovery OK
>[  147.772508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  147.786509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  147.800506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  147.814372] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  147.828507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  147.842510] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  147.843327] [drm:intel_dp_link_down] 
>[  147.907523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  147.921520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  147.922039] [drm:intel_dp_start_link_train] clock recovery OK
>[  147.936693] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  147.951522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  147.965521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  147.979523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  147.993523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  148.007524] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  148.008342] [drm:intel_dp_link_down] 
>[  148.072525] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  148.086523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  148.087042] [drm:intel_dp_start_link_train] clock recovery OK
>[  148.087208] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  148.559787] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[  148.559816] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0007
>[  148.564253] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  148.564259] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  148.605520] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[  148.605525] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  148.605530] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0007
>[  148.605533] [drm:wait_panel_status] Wait complete
>[  148.605538] [drm:_edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd000f
>[  148.605541] [drm:_edp_panel_vdd_on] eDP was not running
>[  148.630192] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  148.630200] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  148.807404] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  148.807564] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  148.807857] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  148.821507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  148.835509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  148.836027] [drm:intel_dp_start_link_train] clock recovery OK
>[  148.850521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  148.864521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  148.878518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  148.892520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  148.906518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  148.920521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  148.921339] [drm:intel_dp_link_down] 
>[  148.985523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  148.999521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.000040] [drm:intel_dp_start_link_train] clock recovery OK
>[  149.014507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.028513] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.042507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.056509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.070767] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.085529] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.086275] [drm:intel_dp_link_down] 
>[  149.150511] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.164509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.165037] [drm:intel_dp_start_link_train] clock recovery OK
>[  149.179518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.193521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.207519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.221522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.235521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.249523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.250340] [drm:intel_dp_link_down] 
>[  149.314370] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.328522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.329040] [drm:intel_dp_start_link_train] clock recovery OK
>[  149.343507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.357509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.371506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.385771] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.400523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.414523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.415344] [drm:intel_dp_link_down] 
>[  149.479524] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.493519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.494037] [drm:intel_dp_start_link_train] clock recovery OK
>[  149.508507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.522509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.536506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.550509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.564506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.578509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.579337] [drm:intel_dp_link_down] 
>[  149.643526] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.657523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.658041] [drm:intel_dp_start_link_train] clock recovery OK
>[  149.672506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.686509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.700506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.715524] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.729517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.743520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.744338] [drm:intel_dp_link_down] 
>[  149.808522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.822523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.823041] [drm:intel_dp_start_link_train] clock recovery OK
>[  149.823208] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  149.825850] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  149.826006] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  149.826299] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  149.840527] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.854519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.855037] [drm:intel_dp_start_link_train] clock recovery OK
>[  149.869510] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.883506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.897510] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.911506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.925509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.939506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.940324] [drm:intel_dp_link_down] 
>[  150.004523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.018523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.019040] [drm:intel_dp_start_link_train] clock recovery OK
>[  150.033507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.047509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.061507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.075509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.089506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.103509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.104328] [drm:intel_dp_link_down] 
>[  150.168523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.182526] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.183044] [drm:intel_dp_start_link_train] clock recovery OK
>[  150.197507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.211372] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.225517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.239520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.253517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.267788] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.268579] [drm:intel_dp_link_down] 
>[  150.333521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.347520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.348038] [drm:intel_dp_start_link_train] clock recovery OK
>[  150.362521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.376522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.390519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.404523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.418519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.432523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.433342] [drm:intel_dp_link_down] 
>[  150.497523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.511519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.512038] [drm:intel_dp_start_link_train] clock recovery OK
>[  150.526369] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.540520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.554518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.568520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.582795] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.597372] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.598117] [drm:intel_dp_link_down] 
>[  150.662527] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.676523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.677041] [drm:intel_dp_start_link_train] clock recovery OK
>[  150.691518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.705520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.719517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.733545] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.748517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.762519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.763337] [drm:intel_dp_link_down] 
>[  150.827521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.841520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.842038] [drm:intel_dp_start_link_train] clock recovery OK
>[  150.842204] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  151.311509] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[  151.311519] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0007
>[  151.315958] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  151.315964] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  151.359521] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[  151.359526] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  151.359531] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0007
>[  151.359534] [drm:wait_panel_status] Wait complete
>[  151.359539] [drm:_edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd000f
>[  151.359542] [drm:_edp_panel_vdd_on] eDP was not running
>[  151.384143] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  151.384149] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  151.561432] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  151.561592] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  151.561885] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  151.575520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.589523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.590040] [drm:intel_dp_start_link_train] clock recovery OK
>[  151.604516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.618519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.632516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.646519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.660516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.674519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.675337] [drm:intel_dp_link_down] 
>[  151.739524] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.753520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.754038] [drm:intel_dp_start_link_train] clock recovery OK
>[  151.768517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.782518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.796519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.810526] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.824520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.838518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.839337] [drm:intel_dp_link_down] 
>[  151.903578] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.917574] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.918092] [drm:intel_dp_start_link_train] clock recovery OK
>[  151.932520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.946520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.960519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.975574] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  151.990519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.004521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.005339] [drm:intel_dp_link_down] 
>[  152.069567] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.083565] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.084083] [drm:intel_dp_start_link_train] clock recovery OK
>[  152.098519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.112522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.126519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.140521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.154521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.168525] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.169376] [drm:intel_dp_link_down] 
>[  152.235524] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.249522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.250040] [drm:intel_dp_start_link_train] clock recovery OK
>[  152.264549] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.278369] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.292546] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.307373] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.321521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.335524] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.336342] [drm:intel_dp_link_down] 
>[  152.400542] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.414538] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.415056] [drm:intel_dp_start_link_train] clock recovery OK
>[  152.429521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.443529] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.458532] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.472530] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.487520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.501412] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.502240] [drm:intel_dp_link_down] 
>[  152.566524] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.580521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.581042] [drm:intel_dp_start_link_train] clock recovery OK
>[  152.581208] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  152.583823] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  152.583980] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  152.584272] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  152.598521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.599067] [drm:intel_dp_start_link_train] clock recovery OK
>[  152.613521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.627522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.641518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.655523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.669517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.683521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.684338] [drm:intel_dp_link_down] 
>[  152.748523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.762521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.763039] [drm:intel_dp_start_link_train] clock recovery OK
>[  152.777565] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.792545] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.806369] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.820521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.834519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.848520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.849338] [drm:intel_dp_link_down] 
>[  152.913531] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.914072] [drm:intel_dp_start_link_train] clock recovery OK
>[  152.928522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.942506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.956509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.970506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.984532] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.998507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  152.999324] [drm:intel_dp_link_down] 
>[  153.063540] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.077557] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.078075] [drm:intel_dp_start_link_train] clock recovery OK
>[  153.092507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.106372] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.120506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.134510] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.148506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.162509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.163327] [drm:intel_dp_link_down] 
>[  153.227511] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.241509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.242026] [drm:intel_dp_start_link_train] clock recovery OK
>[  153.256519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.270548] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.285506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.299509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.313517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.327510] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.328329] [drm:intel_dp_link_down] 
>[  153.392543] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.406539] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.407057] [drm:intel_dp_start_link_train] clock recovery OK
>[  153.421507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.435509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.449506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.463509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.477506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.491509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.492327] [drm:intel_dp_link_down] 
>[  153.556530] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.570526] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  153.571045] [drm:intel_dp_start_link_train] clock recovery OK
>[  153.571211] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  154.063754] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[  154.063782] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0007
>[  154.068215] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  154.068221] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  154.109519] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[  154.109524] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  154.109529] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0007
>[  154.109533] [drm:wait_panel_status] Wait complete
>[  154.109537] [drm:_edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd000f
>[  154.109540] [drm:_edp_panel_vdd_on] eDP was not running
>[  154.134325] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  154.134348] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  154.311399] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  154.311559] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  154.311852] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  154.325507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.339509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.340027] [drm:intel_dp_start_link_train] clock recovery OK
>[  154.354520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.368521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.382518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.396521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.411506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.425509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.426431] [drm:intel_dp_link_down] 
>[  154.491521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.505520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.506051] [drm:intel_dp_start_link_train] clock recovery OK
>[  154.520506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.534509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.548506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.562509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.576506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.590371] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.591245] [drm:intel_dp_link_down] 
>[  154.655602] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.669599] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.670117] [drm:intel_dp_start_link_train] clock recovery OK
>[  154.684507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.698509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.712506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.726510] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.740509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.755593] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.756432] [drm:intel_dp_link_down] 
>[  154.821589] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.835586] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.836104] [drm:intel_dp_start_link_train] clock recovery OK
>[  154.850507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.864509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.878506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.892509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.906506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.920509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.921325] [drm:intel_dp_link_down] 
>[  154.985587] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  154.999582] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.000101] [drm:intel_dp_start_link_train] clock recovery OK
>[  155.014507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.028509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.042506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.056522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.070506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.084509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.085326] [drm:intel_dp_link_down] 
>[  155.149571] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.163570] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.164088] [drm:intel_dp_start_link_train] clock recovery OK
>[  155.178507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.192509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.206506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.220509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.234506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.248509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.249326] [drm:intel_dp_link_down] 
>[  155.313568] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.327556] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.328075] [drm:intel_dp_start_link_train] clock recovery OK
>[  155.328241] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  155.330752] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  155.330908] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  155.331201] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  155.345556] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.359552] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.360070] [drm:intel_dp_start_link_train] clock recovery OK
>[  155.374509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.388506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.402509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.416506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.430509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.444506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.445324] [drm:intel_dp_link_down] 
>[  155.509543] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.523541] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.524059] [drm:intel_dp_start_link_train] clock recovery OK
>[  155.538507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.552509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.566506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.580509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.594506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.608509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.609326] [drm:intel_dp_link_down] 
>[  155.673531] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.687529] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.688047] [drm:intel_dp_start_link_train] clock recovery OK
>[  155.702507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.716509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.730506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.744368] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.758506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.772509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.773328] [drm:intel_dp_link_down] 
>[  155.837526] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.851522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.852040] [drm:intel_dp_start_link_train] clock recovery OK
>[  155.866507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.880509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.894506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.908509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.922506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.936509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.937326] [drm:intel_dp_link_down] 
>[  156.001523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  156.002121] [drm:intel_dp_start_link_train] clock recovery OK
>[  156.016513] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  156.030506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  156.044509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  156.058506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  156.072509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  156.086506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  156.087323] [drm:intel_dp_link_down] 
>[  156.151522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  156.165522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  156.166040] [drm:intel_dp_start_link_train] clock recovery OK
>[  156.180507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  156.194509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  156.208506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  156.222509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  156.236506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  156.250509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  156.251326] [drm:intel_dp_link_down] 
>[  156.315522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  156.329520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  156.330038] [drm:intel_dp_start_link_train] clock recovery OK
>[  156.330205] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  156.815814] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[  156.815842] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0007
>[  156.820275] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  156.820280] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  156.863522] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[  156.863527] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  156.863532] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0007
>[  156.863535] [drm:wait_panel_status] Wait complete
>[  156.863540] [drm:_edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd000f
>[  156.863543] [drm:_edp_panel_vdd_on] eDP was not running
>[  156.888474] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  156.888498] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  157.065280] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  157.065488] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  157.065789] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  157.079505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.093508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.094025] [drm:intel_dp_start_link_train] clock recovery OK
>[  157.108520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.122521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.136517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.151509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.165505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.179509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.180326] [drm:intel_dp_link_down] 
>[  157.244522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.258523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.259041] [drm:intel_dp_start_link_train] clock recovery OK
>[  157.273506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.287508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.301505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.315508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.329505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.343508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.344325] [drm:intel_dp_link_down] 
>[  157.408522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.422520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.423038] [drm:intel_dp_start_link_train] clock recovery OK
>[  157.437506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.451508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.465506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.479508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.493506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.507508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.508325] [drm:intel_dp_link_down] 
>[  157.572522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.586371] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.586946] [drm:intel_dp_start_link_train] clock recovery OK
>[  157.601506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.615509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.629505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.643508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.657505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.671508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.672325] [drm:intel_dp_link_down] 
>[  157.736522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.750521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.751039] [drm:intel_dp_start_link_train] clock recovery OK
>[  157.765506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.779508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.793505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.807508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.821506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.835508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.836325] [drm:intel_dp_link_down] 
>[  157.900523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.914368] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.914918] [drm:intel_dp_start_link_train] clock recovery OK
>[  157.929506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.943508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.957505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.971508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.985506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  157.999508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.000325] [drm:intel_dp_link_down] 
>[  158.064522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.078520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.079038] [drm:intel_dp_start_link_train] clock recovery OK
>[  158.079205] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  158.081870] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  158.082027] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  158.082319] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  158.096521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.110518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.111038] [drm:intel_dp_start_link_train] clock recovery OK
>[  158.125510] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.139505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.153508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.167508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.181509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.195505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.196323] [drm:intel_dp_link_down] 
>[  158.260522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.274520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.275038] [drm:intel_dp_start_link_train] clock recovery OK
>[  158.289505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.303508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.317505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.331508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.345506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.359508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.360325] [drm:intel_dp_link_down] 
>[  158.424522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.438522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.439042] [drm:intel_dp_start_link_train] clock recovery OK
>[  158.453506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.467508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.481506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.495508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.509506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.523508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.524326] [drm:intel_dp_link_down] 
>[  158.588370] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.602523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.603041] [drm:intel_dp_start_link_train] clock recovery OK
>[  158.617506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.631508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.645505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.659508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.673505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.687508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.688325] [drm:intel_dp_link_down] 
>[  158.752521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.766519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.767036] [drm:intel_dp_start_link_train] clock recovery OK
>[  158.781505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.795508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.809505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.823508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.837505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.851508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.852326] [drm:intel_dp_link_down] 
>[  158.916509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.930508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.931026] [drm:intel_dp_start_link_train] clock recovery OK
>[  158.945520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.959521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.973517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  158.987519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  159.001517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  159.015518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  159.016337] [drm:intel_dp_link_down] 
>[  159.080521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  159.094522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  159.095040] [drm:intel_dp_start_link_train] clock recovery OK
>[  159.095206] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  159.567774] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[  159.567802] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0007
>[  159.572241] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  159.572246] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  159.613516] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[  159.613521] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  159.613526] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0007
>[  159.613529] [drm:wait_panel_status] Wait complete
>[  159.613534] [drm:_edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd000f
>[  159.613537] [drm:_edp_panel_vdd_on] eDP was not running
>[  159.637978] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  159.637983] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  159.815400] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  159.815559] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  159.815852] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  159.829505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  159.843508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  159.844025] [drm:intel_dp_start_link_train] clock recovery OK
>[  159.858516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  159.872518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  159.886517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  159.900520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  159.914365] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  159.928521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  159.929340] [drm:intel_dp_link_down] 
>[  159.993522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.007370] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.007945] [drm:intel_dp_start_link_train] clock recovery OK
>[  160.022506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.036508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.050505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.064508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.078505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.092508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.093324] [drm:intel_dp_link_down] 
>[  160.157523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.171522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.172040] [drm:intel_dp_start_link_train] clock recovery OK
>[  160.186506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.200508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.214505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.228508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.242505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.256368] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.257204] [drm:intel_dp_link_down] 
>[  160.321524] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.335521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.336039] [drm:intel_dp_start_link_train] clock recovery OK
>[  160.350505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.364509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.378505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.392370] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.406505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.420508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.421325] [drm:intel_dp_link_down] 
>[  160.485520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.499518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.500036] [drm:intel_dp_start_link_train] clock recovery OK
>[  160.514365] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.528508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.542505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.556508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.570505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.584508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.585324] [drm:intel_dp_link_down] 
>[  160.649522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.663519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.664138] [drm:intel_dp_start_link_train] clock recovery OK
>[  160.678506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.692508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.706505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.720370] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.734505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.748508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.749324] [drm:intel_dp_link_down] 
>[  160.813523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.827519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.828037] [drm:intel_dp_start_link_train] clock recovery OK
>[  160.828204] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  160.830616] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  160.830773] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  160.831065] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  160.845519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.859516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.860034] [drm:intel_dp_start_link_train] clock recovery OK
>[  160.874509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.888505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.902508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.916570] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.931522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.945517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  160.946336] [drm:intel_dp_link_down] 
>[  161.010520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.024370] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.024945] [drm:intel_dp_start_link_train] clock recovery OK
>[  161.039506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.053508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.067505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.081370] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.095505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.109508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.110326] [drm:intel_dp_link_down] 
>[  161.174522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.188519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.189038] [drm:intel_dp_start_link_train] clock recovery OK
>[  161.203506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.217508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.231608] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.246518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.260515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.274519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.275338] [drm:intel_dp_link_down] 
>[  161.339509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.353508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.354025] [drm:intel_dp_start_link_train] clock recovery OK
>[  161.368519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.382518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.396516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.410519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.424515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.438518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.439336] [drm:intel_dp_link_down] 
>[  161.503521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.517524] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.518042] [drm:intel_dp_start_link_train] clock recovery OK
>[  161.532506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.546614] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.561517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.575552] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.590505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.604508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.605335] [drm:intel_dp_link_down] 
>[  161.669522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.683520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.684038] [drm:intel_dp_start_link_train] clock recovery OK
>[  161.698506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.712508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.726505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.740368] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.754505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.768370] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.769244] [drm:intel_dp_link_down] 
>[  161.833525] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.847520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.848039] [drm:intel_dp_start_link_train] clock recovery OK
>[  161.848205] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  162.319826] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[  162.319854] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0007
>[  162.324301] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  162.324307] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  162.365655] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[  162.365661] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  162.365666] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0007
>[  162.365669] [drm:wait_panel_status] Wait complete
>[  162.365674] [drm:_edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd000f
>[  162.365677] [drm:_edp_panel_vdd_on] eDP was not running
>[  162.390434] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  162.390457] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  162.567383] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  162.567542] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  162.567836] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  162.581505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.595508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.596026] [drm:intel_dp_start_link_train] clock recovery OK
>[  162.610517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.624521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.638519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.652522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.666517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.680385] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.681188] [drm:intel_dp_link_down] 
>[  162.745523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.759519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.760038] [drm:intel_dp_start_link_train] clock recovery OK
>[  162.774522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.788518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.802515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.816519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.830516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.844518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.845336] [drm:intel_dp_link_down] 
>[  162.909523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.923522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.924041] [drm:intel_dp_start_link_train] clock recovery OK
>[  162.938516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.952518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.966516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.980518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  162.994516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.009519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.010336] [drm:intel_dp_link_down] 
>[  163.074521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.088518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.089036] [drm:intel_dp_start_link_train] clock recovery OK
>[  163.103517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.117521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.131521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.145523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.159517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.173521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.174338] [drm:intel_dp_link_down] 
>[  163.238522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.252522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.253042] [drm:intel_dp_start_link_train] clock recovery OK
>[  163.267517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.281522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.296517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.310422] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.324515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.338520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.339338] [drm:intel_dp_link_down] 
>[  163.403510] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.417508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.418026] [drm:intel_dp_start_link_train] clock recovery OK
>[  163.432520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.446520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.460516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.474519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.488516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.502520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.503338] [drm:intel_dp_link_down] 
>[  163.567509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.581508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.582026] [drm:intel_dp_start_link_train] clock recovery OK
>[  163.582192] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  163.584556] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  163.584713] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  163.585005] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  163.598520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.612516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.613033] [drm:intel_dp_start_link_train] clock recovery OK
>[  163.627509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.641516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.655518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.669516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.683519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.697515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.698335] [drm:intel_dp_link_down] 
>[  163.762522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.776520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.777038] [drm:intel_dp_start_link_train] clock recovery OK
>[  163.791516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.805519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.819515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.833519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.847515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.861518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.862336] [drm:intel_dp_link_down] 
>[  163.926520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.940444] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.940963] [drm:intel_dp_start_link_train] clock recovery OK
>[  163.955517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.969521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.983516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  163.997522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.011518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.025521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.026339] [drm:intel_dp_link_down] 
>[  164.090523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.104521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.105039] [drm:intel_dp_start_link_train] clock recovery OK
>[  164.119516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.133518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.147516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.161518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.175515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.189518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.190336] [drm:intel_dp_link_down] 
>[  164.254521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.268519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.269037] [drm:intel_dp_start_link_train] clock recovery OK
>[  164.283517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.297526] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.311517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.325520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.339519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.353370] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.354218] [drm:intel_dp_link_down] 
>[  164.418576] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.432572] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.433090] [drm:intel_dp_start_link_train] clock recovery OK
>[  164.447518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.461519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.475517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.489520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.503515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.517518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.518337] [drm:intel_dp_link_down] 
>[  164.582567] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.596564] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  164.597084] [drm:intel_dp_start_link_train] clock recovery OK
>[  164.597251] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  165.071649] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[  165.071678] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0007
>[  165.076037] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  165.076042] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  165.117519] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[  165.117524] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  165.117529] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0007
>[  165.117532] [drm:wait_panel_status] Wait complete
>[  165.117537] [drm:_edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd000f
>[  165.117540] [drm:_edp_panel_vdd_on] eDP was not running
>[  165.142302] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  165.142325] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  165.319478] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  165.319638] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  165.319931] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  165.333511] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.347513] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.348030] [drm:intel_dp_start_link_train] clock recovery OK
>[  165.362517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.376523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.390517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.404520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.418517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.432520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.433338] [drm:intel_dp_link_down] 
>[  165.497520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.511520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.512049] [drm:intel_dp_start_link_train] clock recovery OK
>[  165.526508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.540507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.554504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.568507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.582504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.596507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.597324] [drm:intel_dp_link_down] 
>[  165.661555] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.675555] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.676073] [drm:intel_dp_start_link_train] clock recovery OK
>[  165.690505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.704508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.718505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.732507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.746505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.760507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.761324] [drm:intel_dp_link_down] 
>[  165.825542] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.839540] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.840057] [drm:intel_dp_start_link_train] clock recovery OK
>[  165.854505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.868507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.882504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.896507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.910505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.924507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  165.925324] [drm:intel_dp_link_down] 
>[  165.989535] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.003531] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.004049] [drm:intel_dp_start_link_train] clock recovery OK
>[  166.018505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.033529] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.047525] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.061527] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.075523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.089371] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.090261] [drm:intel_dp_link_down] 
>[  166.154524] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.168525] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.169048] [drm:intel_dp_start_link_train] clock recovery OK
>[  166.183504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.197507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.211504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.225507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.239504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.253507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.254323] [drm:intel_dp_link_down] 
>[  166.318520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.332519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.333036] [drm:intel_dp_start_link_train] clock recovery OK
>[  166.333203] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  166.335700] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  166.335857] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  166.336149] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  166.350525] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.364523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.365042] [drm:intel_dp_start_link_train] clock recovery OK
>[  166.379507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.393504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.407508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.421505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.435507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.449505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.450322] [drm:intel_dp_link_down] 
>[  166.514368] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.528519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.529037] [drm:intel_dp_start_link_train] clock recovery OK
>[  166.543504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.557507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.571366] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.585507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.600518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.614520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.615338] [drm:intel_dp_link_down] 
>[  166.679522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.693520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.694037] [drm:intel_dp_start_link_train] clock recovery OK
>[  166.708505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.722507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.736504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.750507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.764505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.778367] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.779217] [drm:intel_dp_link_down] 
>[  166.843519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.857519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.858038] [drm:intel_dp_start_link_train] clock recovery OK
>[  166.872505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.886507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.900504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.915518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.929516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.943520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  166.944338] [drm:intel_dp_link_down] 
>[  167.008521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.022520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.023053] [drm:intel_dp_start_link_train] clock recovery OK
>[  167.037505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.051508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.065504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.079507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.093365] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.107507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.108324] [drm:intel_dp_link_down] 
>[  167.172601] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.186598] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.187116] [drm:intel_dp_start_link_train] clock recovery OK
>[  167.201505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.215507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.230593] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.245508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.259504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.273507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.274324] [drm:intel_dp_link_down] 
>[  167.338509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.352507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.353024] [drm:intel_dp_start_link_train] clock recovery OK
>[  167.353190] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  167.823787] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[  167.823815] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0007
>[  167.828250] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  167.828256] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  167.869550] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[  167.869555] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  167.869560] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0007
>[  167.869563] [drm:wait_panel_status] Wait complete
>[  167.869568] [drm:_edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd000f
>[  167.869571] [drm:_edp_panel_vdd_on] eDP was not running
>[  167.894319] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  167.894342] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  168.071270] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  168.071518] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  168.071813] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  168.085504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.099519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.100037] [drm:intel_dp_start_link_train] clock recovery OK
>[  168.114366] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.128533] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.142530] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.156531] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.170526] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.184528] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.185347] [drm:intel_dp_link_down] 
>[  168.249525] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.263521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.264039] [drm:intel_dp_start_link_train] clock recovery OK
>[  168.278364] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.292507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.306505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.320507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.334511] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.348507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.349325] [drm:intel_dp_link_down] 
>[  168.413671] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.427522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.428040] [drm:intel_dp_start_link_train] clock recovery OK
>[  168.442505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.456507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.470504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.484507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.498504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.512370] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.513243] [drm:intel_dp_link_down] 
>[  168.577520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.591519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.592039] [drm:intel_dp_start_link_train] clock recovery OK
>[  168.606506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.620507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.634504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.648507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.662504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.676507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.677325] [drm:intel_dp_link_down] 
>[  168.741520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.755518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.756037] [drm:intel_dp_start_link_train] clock recovery OK
>[  168.770505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.784507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.798505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.812507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.826504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.840507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.841324] [drm:intel_dp_link_down] 
>[  168.905519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.919516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.920034] [drm:intel_dp_start_link_train] clock recovery OK
>[  168.934505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.948507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.962504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.976507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  168.990504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.004507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.005324] [drm:intel_dp_link_down] 
>[  169.069370] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.083518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.084036] [drm:intel_dp_start_link_train] clock recovery OK
>[  169.084202] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  169.086426] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  169.086583] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  169.086875] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  169.100508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.114365] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.114904] [drm:intel_dp_start_link_train] clock recovery OK
>[  169.129370] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.143514] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.157517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.171514] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.185516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.199514] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.200334] [drm:intel_dp_link_down] 
>[  169.264521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.278368] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.278917] [drm:intel_dp_start_link_train] clock recovery OK
>[  169.293505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.307507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.321504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.335507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.349504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.363507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.364324] [drm:intel_dp_link_down] 
>[  169.428522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.442521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.443040] [drm:intel_dp_start_link_train] clock recovery OK
>[  169.457505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.471507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.485522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.499507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.513515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.527507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.528324] [drm:intel_dp_link_down] 
>[  169.592522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.606516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.607054] [drm:intel_dp_start_link_train] clock recovery OK
>[  169.621504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.635507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.649504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.663507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.677504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.691507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.692325] [drm:intel_dp_link_down] 
>[  169.756512] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.770504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.771023] [drm:intel_dp_start_link_train] clock recovery OK
>[  169.785521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.799758] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.814531] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.828504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.842508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.856504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.857322] [drm:intel_dp_link_down] 
>[  169.921521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.935520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.936038] [drm:intel_dp_start_link_train] clock recovery OK
>[  169.950505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.964507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.978504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  169.992370] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  170.006527] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  170.020507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  170.021324] [drm:intel_dp_link_down] 
>[  170.085521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  170.099520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  170.100038] [drm:intel_dp_start_link_train] clock recovery OK
>[  170.100204] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  170.575770] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[  170.575798] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0007
>[  170.580235] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  170.580241] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  170.621518] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[  170.621523] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  170.621528] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0007
>[  170.621531] [drm:wait_panel_status] Wait complete
>[  170.621536] [drm:_edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd000f
>[  170.621539] [drm:_edp_panel_vdd_on] eDP was not running
>[  170.646349] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  170.646372] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  170.823395] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  170.823554] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  170.823847] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  170.837504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  170.851507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  170.852024] [drm:intel_dp_start_link_train] clock recovery OK
>[  170.866517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  170.880521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  170.894517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  170.908519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  170.922516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  170.936520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  170.937339] [drm:intel_dp_link_down] 
>[  171.001522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.015521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.016040] [drm:intel_dp_start_link_train] clock recovery OK
>[  171.030505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.044507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.058504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.072507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.086504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.100507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.101324] [drm:intel_dp_link_down] 
>[  171.165523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.179520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.180038] [drm:intel_dp_start_link_train] clock recovery OK
>[  171.194504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.208507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.222504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.236507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.250504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.264510] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.265327] [drm:intel_dp_link_down] 
>[  171.329512] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.343504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.344021] [drm:intel_dp_start_link_train] clock recovery OK
>[  171.358521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.372518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.386520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.400517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.414522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.428517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.429336] [drm:intel_dp_link_down] 
>[  171.493522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.507518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.508036] [drm:intel_dp_start_link_train] clock recovery OK
>[  171.522505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.536507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.550504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.564370] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.578504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.592507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.593324] [drm:intel_dp_link_down] 
>[  171.657522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.671519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.672039] [drm:intel_dp_start_link_train] clock recovery OK
>[  171.686505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.700507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.714364] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.728507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.742504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.756507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.757324] [drm:intel_dp_link_down] 
>[  171.821521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.835370] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.835944] [drm:intel_dp_start_link_train] clock recovery OK
>[  171.836110] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  171.838030] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  171.838187] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  171.838484] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  171.852507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.866503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.867020] [drm:intel_dp_start_link_train] clock recovery OK
>[  171.881521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.895515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.909521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.923517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.937520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.951517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  171.952335] [drm:intel_dp_link_down] 
>[  172.016522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.030520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.031038] [drm:intel_dp_start_link_train] clock recovery OK
>[  172.045505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.059512] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.073504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.087506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.101504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.115506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.116323] [drm:intel_dp_link_down] 
>[  172.180519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.194520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.195038] [drm:intel_dp_start_link_train] clock recovery OK
>[  172.209504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.223506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.237503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.251507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.265503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.279510] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.280328] [drm:intel_dp_link_down] 
>[  172.344518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.358519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.359037] [drm:intel_dp_start_link_train] clock recovery OK
>[  172.373504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.387506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.401504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.415506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.429503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.443506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.444323] [drm:intel_dp_link_down] 
>[  172.508710] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.522519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.523037] [drm:intel_dp_start_link_train] clock recovery OK
>[  172.537374] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.551368] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.565363] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.579517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.593516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.607519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.608337] [drm:intel_dp_link_down] 
>[  172.672521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.686521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.687039] [drm:intel_dp_start_link_train] clock recovery OK
>[  172.701504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.715507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.729504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.743506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.757503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.771506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.772323] [drm:intel_dp_link_down] 
>[  172.836369] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.850520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  172.851039] [drm:intel_dp_start_link_train] clock recovery OK
>[  172.851205] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  173.328225] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[  173.328235] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0007
>[  173.332701] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  173.332707] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  173.375517] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[  173.375523] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  173.375528] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0007
>[  173.375531] [drm:wait_panel_status] Wait complete
>[  173.375536] [drm:_edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd000f
>[  173.375539] [drm:_edp_panel_vdd_on] eDP was not running
>[  173.400392] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  173.400416] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  173.577369] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  173.577528] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  173.577822] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  173.591503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.605506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.606023] [drm:intel_dp_start_link_train] clock recovery OK
>[  173.620518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.634520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.648516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.662519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.676514] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.690517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.691335] [drm:intel_dp_link_down] 
>[  173.755522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.769515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.770036] [drm:intel_dp_start_link_train] clock recovery OK
>[  173.784506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.798503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.812506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.826503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.840506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.854504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.855321] [drm:intel_dp_link_down] 
>[  173.919519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.933517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.934035] [drm:intel_dp_start_link_train] clock recovery OK
>[  173.948503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.962506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.976503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.990506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.004509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.018506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.019323] [drm:intel_dp_link_down] 
>[  174.083713] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.097519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.098037] [drm:intel_dp_start_link_train] clock recovery OK
>[  174.112504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.126506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.140503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.154506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.168507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.182506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.183333] [drm:intel_dp_link_down] 
>[  174.247520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.261526] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.262044] [drm:intel_dp_start_link_train] clock recovery OK
>[  174.276504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.290506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.304503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.318506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.332503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.346507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.347337] [drm:intel_dp_link_down] 
>[  174.411520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.425520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.426039] [drm:intel_dp_start_link_train] clock recovery OK
>[  174.440504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.454506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.468503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.482506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.496507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.510506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.511335] [drm:intel_dp_link_down] 
>[  174.575508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.589506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.590033] [drm:intel_dp_start_link_train] clock recovery OK
>[  174.590200] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  174.592118] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  174.592283] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  174.592622] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  174.606520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.620517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.621036] [drm:intel_dp_start_link_train] clock recovery OK
>[  174.635507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.649503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.663506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.677503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.691364] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.705503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.706331] [drm:intel_dp_link_down] 
>[  174.770369] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.784366] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.784913] [drm:intel_dp_start_link_train] clock recovery OK
>[  174.799504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.813506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.827503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.841506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.855503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.869506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.870324] [drm:intel_dp_link_down] 
>[  174.934519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.948517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.949035] [drm:intel_dp_start_link_train] clock recovery OK
>[  174.963504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.977506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  174.991503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.005506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.019503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.033506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.034326] [drm:intel_dp_link_down] 
>[  175.098520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.112519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.113037] [drm:intel_dp_start_link_train] clock recovery OK
>[  175.127504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.141506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.155503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.169506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.183504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.197507] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.198326] [drm:intel_dp_link_down] 
>[  175.262521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.276520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.277037] [drm:intel_dp_start_link_train] clock recovery OK
>[  175.291515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.305516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.319514] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.333368] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.347514] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.361517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.362335] [drm:intel_dp_link_down] 
>[  175.426521] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.440520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.441037] [drm:intel_dp_start_link_train] clock recovery OK
>[  175.455514] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.469517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.484519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.498518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.512520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.526520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.527340] [drm:intel_dp_link_down] 
>[  175.591519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.605518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  175.606036] [drm:intel_dp_start_link_train] clock recovery OK
>[  175.606202] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  176.079668] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[  176.079695] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0007
>[  176.084056] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  176.084061] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  176.125514] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[  176.125519] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  176.125524] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0007
>[  176.125527] [drm:wait_panel_status] Wait complete
>[  176.125532] [drm:_edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd000f
>[  176.125535] [drm:_edp_panel_vdd_on] eDP was not running
>[  176.149953] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  176.149959] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  176.327475] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  176.327635] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  176.327928] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  176.341516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.355520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.356039] [drm:intel_dp_start_link_train] clock recovery OK
>[  176.370515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.384517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.398514] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.412517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.426514] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.440516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.441334] [drm:intel_dp_link_down] 
>[  176.505519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.519516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.520034] [drm:intel_dp_start_link_train] clock recovery OK
>[  176.534517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.548520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.562517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.576520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.590517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.604518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.605336] [drm:intel_dp_link_down] 
>[  176.669518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.683516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.684035] [drm:intel_dp_start_link_train] clock recovery OK
>[  176.698518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.712517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.726515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.740519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.754513] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.768515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.769333] [drm:intel_dp_link_down] 
>[  176.833519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.847519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.848088] [drm:intel_dp_start_link_train] clock recovery OK
>[  176.862518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.876520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.890519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.904516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.918516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.933573] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  176.934428] [drm:intel_dp_link_down] 
>[  176.999572] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.013571] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.014121] [drm:intel_dp_start_link_train] clock recovery OK
>[  177.028366] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.042517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.056515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.070517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.084514] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.098518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.099337] [drm:intel_dp_link_down] 
>[  177.163560] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.177557] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.178075] [drm:intel_dp_start_link_train] clock recovery OK
>[  177.192515] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.206519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.220516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.234519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.248516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.262520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.263340] [drm:intel_dp_link_down] 
>[  177.327547] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.341544] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.342062] [drm:intel_dp_start_link_train] clock recovery OK
>[  177.342228] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  177.344361] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  177.344520] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  177.344812] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  177.358368] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.372517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.373037] [drm:intel_dp_start_link_train] clock recovery OK
>[  177.387540] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.402518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.416520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.430516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.444519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.458517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.459335] [drm:intel_dp_link_down] 
>[  177.523531] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.537528] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.538046] [drm:intel_dp_start_link_train] clock recovery OK
>[  177.552519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.566517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.580513] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.594517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.608514] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.622519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.623340] [drm:intel_dp_link_down] 
>[  177.687519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.701518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.702057] [drm:intel_dp_start_link_train] clock recovery OK
>[  177.716516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.730528] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.744362] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.758522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.772517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.786519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.787337] [drm:intel_dp_link_down] 
>[  177.851518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.865518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.866035] [drm:intel_dp_start_link_train] clock recovery OK
>[  177.880509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.894517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.908503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.922506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.936503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.950514] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  177.951333] [drm:intel_dp_link_down] 
>[  178.015518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.029518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.030047] [drm:intel_dp_start_link_train] clock recovery OK
>[  178.044508] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.058506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.072503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.086522] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.100503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.114365] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.115215] [drm:intel_dp_link_down] 
>[  178.179554] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.193553] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.194071] [drm:intel_dp_start_link_train] clock recovery OK
>[  178.208504] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.222505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.236502] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.250506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.264365] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.278365] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.279216] [drm:intel_dp_link_down] 
>[  178.343540] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.357561] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  178.358079] [drm:intel_dp_start_link_train] clock recovery OK
>[  178.358246] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  178.831791] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[  178.831819] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0007
>[  178.836185] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  178.836191] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  178.877521] [drm:_edp_panel_vdd_on] Turning eDP VDD on
>[  178.877526] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  178.877531] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0007
>[  178.877534] [drm:wait_panel_status] Wait complete
>[  178.877539] [drm:_edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd000f
>[  178.877542] [drm:_edp_panel_vdd_on] eDP was not running
>[  178.902274] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  178.902297] [drm:intel_hpd_irq_handler] digital hpd port 2 0
>[  179.079386] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  179.079545] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  179.079839] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  179.093503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.107506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.108022] [drm:intel_dp_start_link_train] clock recovery OK
>[  179.122516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.136519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.150516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.164519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.178516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.192520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.193341] [drm:intel_dp_link_down] 
>[  179.257520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.271518] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.272036] [drm:intel_dp_start_link_train] clock recovery OK
>[  179.286502] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.300506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.314363] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.328505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.342502] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.356505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.357322] [drm:intel_dp_link_down] 
>[  179.421519] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.435517] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.436035] [drm:intel_dp_start_link_train] clock recovery OK
>[  179.450503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.464506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.478503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.492506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.506502] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.520506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.521325] [drm:intel_dp_link_down] 
>[  179.585539] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.599539] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.600113] [drm:intel_dp_start_link_train] clock recovery OK
>[  179.614503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.628520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.642502] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.656506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.670502] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.684505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.685322] [drm:intel_dp_link_down] 
>[  179.749520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.763595] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.764114] [drm:intel_dp_start_link_train] clock recovery OK
>[  179.778364] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.792506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.806502] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.820505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.834503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.848506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.849323] [drm:intel_dp_link_down] 
>[  179.913595] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.927578] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.928096] [drm:intel_dp_start_link_train] clock recovery OK
>[  179.942503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.956505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.970502] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.984506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.998503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.012505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.013322] [drm:intel_dp_link_down] 
>[  180.077577] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.091579] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.092098] [drm:intel_dp_start_link_train] clock recovery OK
>[  180.092264] [drm:intel_dp_complete_link_train] *ERROR* failed to train DP, aborting
>[  180.094591] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  180.094749] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  180.095042] [drm:intel_dp_check_link_status] TMDS-24: channel EQ not ok, retraining
>[  180.108509] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.122503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.123020] [drm:intel_dp_start_link_train] clock recovery OK
>[  180.137572] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.151567] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.166505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.180502] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.194506] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.208502] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.209319] [drm:intel_dp_link_down] 
>[  180.273562] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.287559] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.288077] [drm:intel_dp_start_link_train] clock recovery OK
>[  180.302503] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.316505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.330502] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.344505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.358365] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.372505] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.373323] [drm:intel_dp_link_down] 
>[  180.437576] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.451368] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  180.451827] [drm:intel_dp_start_link_train] clock recovery OK
>[  180.466366] [drm:intel_dp_set_signal_levels] Using signal levels 00000000

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Attachments on bug 81082: 102460 | 102461

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