Attachment 102498 Details for Bug 80463 – Correct patch

[patch] Correct patch

0001-drm-i915-squash-the-5-SNB-runtime-PM-fixes.patch (text/plain), 8.40 KB, created by Paulo Zanoni on 2014-07-09 20:12:22 UTC

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Creator: Paulo Zanoni

Created: 2014-07-09 20:12:22 UTC

Size: 8.40 KB

patch

obsolete

>From 179c534bebd77ecc65cedfa55006fe9b3b18cfd7 Mon Sep 17 00:00:00 2001
>From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>Date: Thu, 3 Jul 2014 17:53:28 -0300
>Subject: [PATCH] drm/i915: squash the 5 SNB runtime PM fixes
>
>- This is a combination of 5 commits.
>- The first commit's message is:
>drm/i915: add POWER_DOMAIN_PLLS
>
>And get/put it when needed. The special thing about this commit is
>that it will now return false in ibx_pch_dpll_get_hw_state() in case
>the power domain is not enabled. This will fix some WARNs we have when
>we run pm_rpm on SNB.
>
>Testcase: igt/pm_rpm
>Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=80463
>Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
>- This is the 2nd commit message:
>
>drm/i915: check the power domains in ironlake_get_pipe_config()
>
>Just like we already do in haswell_get_pipe_config(). This should
>prevent some WARNs when we run pm_rpm on SNB.
>
>Testcase: igt/pm_rpm
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80463
>Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
>- This is the 3rd commit message:
>
>drm/i915: check the power domains in intel_lvds_get_hw_state()
>
>Just like we do for the other encoders. This should fix some WARNs
>when running pm_rpm on SNB.
>
>Testcase: igt/pm_rpm
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80463
>Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
>- This is the 4th commit message:
>
>drm/i915: don't read LVDS regs at compute_config time
>
>We may reach this point while the machine is still runtime suspended,
>so we'll hit a WARN. The other encoders also don't touch registers at
>this point, so instead of waking the machine up, write some code to
>keep the register always at the same state, including after we runtime
>suspend/resume.
>
>Testcase: igt/pm_rpm
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80463
>Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
>- This is the 5th commit message:
>
>drm/i915: get/put runtime PM at i915_semaphore_status
>
>Otherwise we will print some WARNs when we read registers and the
>machine is suspended.
>
>Testcase: igt/pm_rpm/debugfs-read
>Cc: Ben Widawsky <ben@bwidawsk.net>
>Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>---
> drivers/gpu/drm/i915/i915_debugfs.c  |  4 ++++
> drivers/gpu/drm/i915/i915_drv.h      |  1 +
> drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++++++
> drivers/gpu/drm/i915/intel_lvds.c    | 18 ++++++++++++++----
> drivers/gpu/drm/i915/intel_pm.c      |  1 +
> 5 files changed, 34 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>index 3945191..1ff56ec 100644
>--- a/drivers/gpu/drm/i915/i915_debugfs.c
>+++ b/drivers/gpu/drm/i915/i915_debugfs.c
>@@ -2043,6 +2043,8 @@ static const char *power_domain_str(enum intel_display_power_domain domain)
> 		return "VGA";
> 	case POWER_DOMAIN_AUDIO:
> 		return "AUDIO";
>+	case POWER_DOMAIN_PLLS:
>+		return "PLLS";
> 	case POWER_DOMAIN_INIT:
> 		return "INIT";
> 	default:
>@@ -2314,6 +2316,7 @@ static int i915_semaphore_status(struct seq_file *m, void *unused)
> 	ret = mutex_lock_interruptible(&dev->struct_mutex);
> 	if (ret)
> 		return ret;
>+	intel_runtime_pm_get(dev_priv);
> 
> 	if (IS_BROADWELL(dev)) {
> 		struct page *page;
>@@ -2363,6 +2366,7 @@ static int i915_semaphore_status(struct seq_file *m, void *unused)
> 	}
> 	seq_putc(m, '\n');
> 
>+	intel_runtime_pm_put(dev_priv);
> 	mutex_unlock(&dev->struct_mutex);
> 	return 0;
> }
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 90216bb..2a28d3b 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -129,6 +129,7 @@ enum intel_display_power_domain {
> 	POWER_DOMAIN_PORT_OTHER,
> 	POWER_DOMAIN_VGA,
> 	POWER_DOMAIN_AUDIO,
>+	POWER_DOMAIN_PLLS,
> 	POWER_DOMAIN_INIT,
> 
> 	POWER_DOMAIN_NUM,
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 5a50ff9..40b99e0 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -1814,6 +1814,8 @@ static void intel_enable_shared_dpll(struct intel_crtc *crtc)
> 	}
> 	WARN_ON(pll->on);
> 
>+	intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
>+
> 	DRM_DEBUG_KMS("enabling %s\n", pll->name);
> 	pll->enable(dev_priv, pll);
> 	pll->on = true;
>@@ -1850,6 +1852,8 @@ static void intel_disable_shared_dpll(struct intel_crtc *crtc)
> 	DRM_DEBUG_KMS("disabling %s\n", pll->name);
> 	pll->disable(dev_priv, pll);
> 	pll->on = false;
>+
>+	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
> }
> 
> static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
>@@ -7234,6 +7238,10 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> 	struct drm_i915_private *dev_priv = dev->dev_private;
> 	uint32_t tmp;
> 
>+	if (!intel_display_power_enabled(dev_priv,
>+					 POWER_DOMAIN_PIPE(crtc->pipe)))
>+		return false;
>+
> 	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
> 	pipe_config->shared_dpll = DPLL_ID_PRIVATE;
> 
>@@ -11269,6 +11277,9 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
> {
> 	uint32_t val;
> 
>+	if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
>+		return false;
>+
> 	val = I915_READ(PCH_DPLL(pll->id));
> 	hw_state->dpll = val;
> 	hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
>@@ -12834,6 +12845,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> 
> 		DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
> 			      pll->name, pll->refcount, pll->on);
>+
>+		if (pll->refcount)
>+			intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
> 	}
> 
> 	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
>diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
>index 4d29a83..c511287 100644
>--- a/drivers/gpu/drm/i915/intel_lvds.c
>+++ b/drivers/gpu/drm/i915/intel_lvds.c
>@@ -51,6 +51,7 @@ struct intel_lvds_encoder {
> 
> 	bool is_dual_link;
> 	u32 reg;
>+	u32 a3_power;
> 
> 	struct intel_lvds_connector *attached_connector;
> };
>@@ -71,8 +72,13 @@ static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
> 	struct drm_device *dev = encoder->base.dev;
> 	struct drm_i915_private *dev_priv = dev->dev_private;
> 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
>+	enum intel_display_power_domain power_domain;
> 	u32 tmp;
> 
>+	power_domain = intel_display_port_power_domain(encoder);
>+	if (!intel_display_power_enabled(dev_priv, power_domain))
>+		return false;
>+
> 	tmp = I915_READ(lvds_encoder->reg);
> 
> 	if (!(tmp & LVDS_PORT_EN))
>@@ -165,8 +171,11 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder)
> 
> 	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
> 	 * appropriately here, but we need to look more thoroughly into how
>-	 * panels behave in the two modes.
>+	 * panels behave in the two modes. For now, let's just maintain the
>+	 * value we got from the BIOS.
> 	 */
>+	 temp &= ~LVDS_A3_POWER_MASK;
>+	 temp |= lvds_encoder->a3_power;
> 
> 	/* Set the dithering flag on LVDS as needed, note that there is no
> 	 * special lvds dither control bit on pch-split platforms, dithering is
>@@ -264,7 +273,6 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
> 				      struct intel_crtc_config *pipe_config)
> {
> 	struct drm_device *dev = intel_encoder->base.dev;
>-	struct drm_i915_private *dev_priv = dev->dev_private;
> 	struct intel_lvds_encoder *lvds_encoder =
> 		to_lvds_encoder(&intel_encoder->base);
> 	struct intel_connector *intel_connector =
>@@ -279,8 +287,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
> 		return false;
> 	}
> 
>-	if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) ==
>-	    LVDS_A3_POWER_UP)
>+	if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
> 		lvds_bpp = 8*3;
> 	else
> 		lvds_bpp = 6*3;
>@@ -1081,6 +1088,9 @@ out:
> 	DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
> 		      lvds_encoder->is_dual_link ? "dual" : "single");
> 
>+	lvds_encoder->a3_power = I915_READ(lvds_encoder->reg) &
>+				 LVDS_A3_POWER_MASK;
>+
> 	/*
> 	 * Unlock registers and just
> 	 * leave them unlocked
>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>index 19c5c26..55228df 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -6346,6 +6346,7 @@ EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
> 	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |		\
> 	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |		\
> 	BIT(POWER_DOMAIN_PORT_CRT) |			\
>+	BIT(POWER_DOMAIN_PLLS) |			\
> 	BIT(POWER_DOMAIN_INIT))
> #define HSW_DISPLAY_POWER_DOMAINS (				\
> 	(POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |	\
>-- 
>2.0.0
>

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