Attachment 104462 Details for Bug 79575 – r600_debug_ps.log

r600_debug_ps.log

r600_debug_ps.log (text/plain), 133.39 KB, created by Andrei Slavoiu on 2014-08-12 00:10:10 UTC

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Creator: Andrei Slavoiu

Created: 2014-08-12 00:10:10 UTC

Size: 133.39 KB

patch

obsolete

>make[1]: Entering directory '/home/andrei/x/wine/dlls/advapi32/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/advapi32/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/advpack/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/advpack/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/amstream/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/amstream/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/apphelp/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/apphelp/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/atl/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/atl/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/atl100/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/atl100/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/atl80/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/atl80/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/avifil32/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/avifil32/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/bcrypt/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/bcrypt/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/browseui/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/browseui/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/cabinet/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/cabinet/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/comcat/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/comcat/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/comctl32/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/comctl32/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/comdlg32/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/comdlg32/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/credui/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/credui/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/crypt32/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/crypt32/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/cryptnet/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/cryptnet/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/cryptui/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/cryptui/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/d3d10/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/d3d10/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/d3d10core/tests'
>make[1]: Nothing to be done for 'test'.
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/d3d10core/tests'
>make[1]: Entering directory '/home/andrei/x/wine/dlls/d3d8/tests'
>../../../tools/runtest -q -P wine -T ../../.. -M d3d8.dll -p d3d8_test.exe.so device && touch device.ok
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>
>Shader Disassembly:
>
>	V_MOV_B32_e32 v0, 0               ; 7E000280
>	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
>	S_ENDPGM                          ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
>	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
>	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
>	S_ENDPGM                            ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
>	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
>	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
>	S_ENDPGM                            ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	V_MOV_B32_e32 v0, 0               ; 7E000280
>	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
>	S_ENDPGM                          ; BF810000
>
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>
>Shader Disassembly:
>
>	V_MOV_B32_e32 v0, 0               ; 7E000280
>	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
>	S_ENDPGM                          ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
>	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
>	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
>	S_ENDPGM                            ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
>	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
>	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
>	S_ENDPGM                            ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	V_MOV_B32_e32 v0, 0               ; 7E000280
>	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
>	S_ENDPGM                          ; BF810000
>
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>
>Shader Disassembly:
>
>	V_MOV_B32_e32 v0, 0               ; 7E000280
>	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
>	S_ENDPGM                          ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
>	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
>	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
>	S_ENDPGM                            ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
>	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
>	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
>	S_ENDPGM                            ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	V_MOV_B32_e32 v0, 0               ; 7E000280
>	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
>	S_ENDPGM                          ; BF810000
>
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>
>Shader Disassembly:
>
>	V_MOV_B32_e32 v0, 0               ; 7E000280
>	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
>	S_ENDPGM                          ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
>	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
>	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
>	S_ENDPGM                            ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
>	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
>	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
>	S_ENDPGM                            ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	V_MOV_B32_e32 v0, 0               ; 7E000280
>	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
>	S_ENDPGM                          ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
>  %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
>  %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
>  %25 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                     ; BEFE0A7E
>	S_MOV_B32 m0, s9                         ; BEFC0309
>	V_INTERP_P1_F32 v2, v0, 3, 0, [m0]       ; C8080300
>	V_INTERP_P2_F32 v2, [v2], v1, 3, 0, [m0] ; C8090301
>	V_INTERP_P1_F32 v3, v0, 2, 0, [m0]       ; C80C0200
>	V_INTERP_P2_F32 v3, [v3], v1, 2, 0, [m0] ; C80D0201
>	V_INTERP_P1_F32 v4, v0, 1, 0, [m0]       ; C8100100
>	V_INTERP_P2_F32 v4, [v4], v1, 1, 0, [m0] ; C8110101
>	V_INTERP_P1_F32 v5, v0, 0, 0, [m0]       ; C8140000
>	V_INTERP_P2_F32 v5, [v5], v1, 0, 0, [m0] ; C8150001
>	EXP 15, 0, 0, 1, 1, v5, v4, v3, v2       ; F800180F 02030405
>	S_ENDPGM                                 ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  %28 = call i32 @llvm.SI.packf16(float %24, float %25)
>  %29 = bitcast i32 %28 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0  ; 5E000101
>	V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102
>	V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002
>	V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1  ; 5E020302
>	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0  ; F8001C0F 00010001
>	S_ENDPGM                            ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0
>  %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0
>  %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0
>  %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11)
>  %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11)
>  %28 = bitcast float %26 to i32
>  %29 = bitcast float %27 to i32
>  %30 = insertelement <2 x i32> undef, i32 %28, i32 0
>  %31 = insertelement <2 x i32> %30, i32 %29, i32 1
>  %32 = bitcast <8 x i32> %23 to <32 x i8>
>  %33 = bitcast <4 x i32> %25 to <16 x i8>
>  %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %32, <16 x i8> %33, i32 2)
>  %35 = extractelement <4 x float> %34, i32 0
>  %36 = extractelement <4 x float> %34, i32 1
>  %37 = extractelement <4 x float> %34, i32 2
>  %38 = extractelement <4 x float> %34, i32 3
>  %39 = call i32 @llvm.SI.packf16(float %35, float %36)
>  %40 = bitcast i32 %39 to float
>  %41 = call i32 @llvm.SI.packf16(float %37, float %38)
>  %42 = bitcast i32 %41 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %40, float %42, float %40, float %42)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
>	S_MOV_B32 m0, s9                                                      ; BEFC0309
>	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                    ; C80C0100
>	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                              ; C80D0101
>	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                    ; C8080000
>	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                              ; C8090001
>	S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0                                    ; C0800300
>	S_LOAD_DWORDX8 s[4:11], s[4:5], 0x0                                   ; C0C20500
>	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
>	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002
>	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
>	V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3                                    ; 5E080702
>	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1                                    ; 5E000300
>	EXP 15, 0, 1, 1, 1, v0, v4, v0, v4                                    ; F8001C0F 04000400
>	S_ENDPGM                                                              ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0
>  %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0
>  %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0
>  %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11)
>  %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11)
>  %28 = bitcast float %26 to i32
>  %29 = bitcast float %27 to i32
>  %30 = insertelement <2 x i32> undef, i32 %28, i32 0
>  %31 = insertelement <2 x i32> %30, i32 %29, i32 1
>  %32 = bitcast <8 x i32> %23 to <32 x i8>
>  %33 = bitcast <4 x i32> %25 to <16 x i8>
>  %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %32, <16 x i8> %33, i32 2)
>  %35 = extractelement <4 x float> %34, i32 0
>  %36 = extractelement <4 x float> %34, i32 1
>  %37 = extractelement <4 x float> %34, i32 2
>  %38 = extractelement <4 x float> %34, i32 3
>  %39 = call i32 @llvm.SI.packf16(float %35, float %36)
>  %40 = bitcast i32 %39 to float
>  %41 = call i32 @llvm.SI.packf16(float %37, float %38)
>  %42 = bitcast i32 %41 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %40, float %42, float %40, float %42)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
>	S_MOV_B32 m0, s9                                                      ; BEFC0309
>	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                    ; C80C0100
>	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                              ; C80D0101
>	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                    ; C8080000
>	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                              ; C8090001
>	S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0                                    ; C0800300
>	S_LOAD_DWORDX8 s[4:11], s[4:5], 0x0                                   ; C0C20500
>	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
>	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002
>	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
>	V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3                                    ; 5E080702
>	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1                                    ; 5E000300
>	EXP 15, 0, 1, 1, 1, v0, v4, v0, v4                                    ; F8001C0F 04000400
>	S_ENDPGM                                                              ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], FOG, PERSPECTIVE
>DCL OUT[0], COLOR
>DCL CONST[1..2]
>DCL TEMP[0..1]
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV_SAT TEMP[0], IMM[0].xyyy
>  1: MAD_SAT TEMP[1].x, IN[0].xxxx, CONST[1].xxxx, CONST[1].yyyy
>  2: LRP OUT[0].xyz, TEMP[1].xxxx, TEMP[0], CONST[2]
>  3: MOV OUT[0].w, TEMP[0]
>  4: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 16)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 20)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 32)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 36)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %23, i32 40)
>  %29 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
>  %30 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  %31 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  %32 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  %33 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  %34 = fmul float %29, %24
>  %35 = fadd float %34, %25
>  %36 = call float @llvm.AMDIL.clamp.(float %35, float 0.000000e+00, float 1.000000e+00)
>  %37 = call float @llvm.AMDGPU.lrp(float %36, float %30, float %26)
>  %38 = call float @llvm.AMDGPU.lrp(float %36, float %31, float %27)
>  %39 = call float @llvm.AMDGPU.lrp(float %36, float %32, float %28)
>  %40 = call i32 @llvm.SI.packf16(float %37, float %38)
>  %41 = bitcast i32 %40 to float
>  %42 = call i32 @llvm.SI.packf16(float %39, float %33)
>  %43 = bitcast i32 %42 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %41, float %43, float %41, float %43)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.lrp(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                     ; BEFE0A7E
>	S_MOV_B32 m0, s9                         ; BEFC0309
>	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]       ; C8080000
>	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001
>	S_LOAD_DWORDX4 s[0:3], s[0:1], 0x0       ; C0800100
>	S_WAITCNT lgkmcnt(0)                     ; BF8C007F
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x4      ; C2020104
>	S_BUFFER_LOAD_DWORD s5, s[0:3], 0x5      ; C2028105
>	S_WAITCNT lgkmcnt(0)                     ; BF8C007F
>	V_MOV_B32_e32 v0, s5                     ; 7E000205
>	V_MAD_F32 v0, v2, s4, v0, 0, 0           ; D2820000 04000902
>	V_ADD_F32_e64 v0, v0, 0, 1, 0            ; D2060800 00010100
>	V_SUB_F32_e32 v1, 1.000000e+00, v0       ; 080200F2
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x9      ; C2020109
>	S_WAITCNT lgkmcnt(0)                     ; BF8C007F
>	V_MUL_F32_e64 v2, v1, s4, 0, 0           ; D2100002 00000901
>	V_ADD_F32_e64 v3, 0.000000e+00, 0, 1, 0  ; D2060803 00010080
>	V_MAD_F32 v2, v0, v3, v2, 0, 0           ; D2820002 040A0700
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x8      ; C2020108
>	S_WAITCNT lgkmcnt(0)                     ; BF8C007F
>	V_MUL_F32_e64 v4, v1, s4, 0, 0           ; D2100004 00000901
>	V_ADD_F32_e64 v5, 1.000000e+00, 0, 1, 0  ; D2060805 000100F2
>	V_MAD_F32 v4, v0, v5, v4, 0, 0           ; D2820004 04120B00
>	V_CVT_PKRTZ_F16_F32_e32 v2, v4, v2       ; 5E040504
>	S_BUFFER_LOAD_DWORD s0, s[0:3], 0xa      ; C200010A
>	S_WAITCNT lgkmcnt(0)                     ; BF8C007F
>	V_MUL_F32_e64 v1, v1, s0, 0, 0           ; D2100001 00000101
>	V_MAD_F32 v0, v0, v3, v1, 0, 0           ; D2820000 04060700
>	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v3       ; 5E000700
>	EXP 15, 0, 1, 1, 1, v2, v0, v2, v0       ; F8001C0F 00020002
>	S_ENDPGM                                 ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL OUT[0], COLOR
>DCL CONST[0..3]
>  0: MOV OUT[0], CONST[3]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 48)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 52)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 56)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 60)
>  %28 = call i32 @llvm.SI.packf16(float %24, float %25)
>  %29 = bitcast i32 %28 to float
>  %30 = call i32 @llvm.SI.packf16(float %26, float %27)
>  %31 = bitcast i32 %30 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %29, float %31, float %29, float %31)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>
>Shader Disassembly:
>
>	S_LOAD_DWORDX4 s[0:3], s[0:1], 0x0  ; C0800100
>	S_WAITCNT lgkmcnt(0)                ; BF8C007F
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0xe ; C202010E
>	S_BUFFER_LOAD_DWORD s5, s[0:3], 0xf ; C202810F
>	S_WAITCNT lgkmcnt(0)                ; BF8C007F
>	V_MOV_B32_e32 v0, s5                ; 7E000205
>	V_CVT_PKRTZ_F16_F32_e32 v0, s4, v0  ; 5E000004
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0xc ; C202010C
>	S_BUFFER_LOAD_DWORD s0, s[0:3], 0xd ; C200010D
>	S_WAITCNT lgkmcnt(0)                ; BF8C007F
>	V_MOV_B32_e32 v1, s0                ; 7E020200
>	V_CVT_PKRTZ_F16_F32_e32 v1, s4, v1  ; 5E020204
>	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0  ; F8001C0F 00010001
>	S_ENDPGM                            ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
>	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
>	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
>	S_ENDPGM                            ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
>  %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
>  %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
>  %25 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                     ; BEFE0A7E
>	S_MOV_B32 m0, s9                         ; BEFC0309
>	V_INTERP_P1_F32 v2, v0, 3, 0, [m0]       ; C8080300
>	V_INTERP_P2_F32 v2, [v2], v1, 3, 0, [m0] ; C8090301
>	V_INTERP_P1_F32 v3, v0, 2, 0, [m0]       ; C80C0200
>	V_INTERP_P2_F32 v3, [v3], v1, 2, 0, [m0] ; C80D0201
>	V_INTERP_P1_F32 v4, v0, 1, 0, [m0]       ; C8100100
>	V_INTERP_P2_F32 v4, [v4], v1, 1, 0, [m0] ; C8110101
>	V_INTERP_P1_F32 v5, v0, 0, 0, [m0]       ; C8140000
>	V_INTERP_P2_F32 v5, [v5], v1, 0, 0, [m0] ; C8150001
>	EXP 15, 0, 0, 1, 1, v5, v4, v3, v2       ; F800180F 02030405
>	S_ENDPGM                                 ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
>  %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
>  %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
>  %25 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7)
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  %28 = call i32 @llvm.SI.packf16(float %24, float %25)
>  %29 = bitcast i32 %28 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                     ; BEFE0A7E
>	S_MOV_B32 m0, s9                         ; BEFC0309
>	V_INTERP_P1_F32 v2, v0, 3, 0, [m0]       ; C8080300
>	V_INTERP_P2_F32 v2, [v2], v1, 3, 0, [m0] ; C8090301
>	V_INTERP_P1_F32 v3, v0, 2, 0, [m0]       ; C80C0200
>	V_INTERP_P2_F32 v3, [v3], v1, 2, 0, [m0] ; C80D0201
>	V_CVT_PKRTZ_F16_F32_e32 v2, v3, v2       ; 5E040503
>	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]       ; C80C0100
>	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101
>	V_INTERP_P1_F32 v4, v0, 0, 0, [m0]       ; C8100000
>	V_INTERP_P2_F32 v4, [v4], v1, 0, 0, [m0] ; C8110001
>	V_CVT_PKRTZ_F16_F32_e32 v0, v4, v3       ; 5E000704
>	EXP 15, 0, 1, 1, 1, v0, v2, v0, v2       ; F8001C0F 02000200
>	S_ENDPGM                                 ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..9]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, CONST[9].xyyy
>  1: MOV TEMP[0].w, CONST[9].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0].xyz, TEMP[0], IN[0]
>  4: MOV TEMP[0].xyz, TEMP[0].xyzx
>  5: MOV TEMP[0].w, IN[0].wwww
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 144)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 148)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 156)
>  %27 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0
>  %28 = load <8 x i32> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0
>  %30 = load <4 x i32> addrspace(2)* %29, !tbaa !0
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
>  %33 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7)
>  %35 = fdiv float %24, %26
>  %36 = fdiv float %25, %26
>  %37 = bitcast float %35 to i32
>  %38 = bitcast float %36 to i32
>  %39 = insertelement <2 x i32> undef, i32 %37, i32 0
>  %40 = insertelement <2 x i32> %39, i32 %38, i32 1
>  %41 = bitcast <8 x i32> %28 to <32 x i8>
>  %42 = bitcast <4 x i32> %30 to <16 x i8>
>  %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %40, <32 x i8> %41, <16 x i8> %42, i32 2)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = fmul float %44, %31
>  %48 = fmul float %45, %32
>  %49 = fmul float %46, %33
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %47, float %48, float %49, float %34)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
>	S_MOV_B32 m0, s9                                                      ; BEFC0309
>	V_INTERP_P1_F32 v2, v0, 2, 0, [m0]                                    ; C8080200
>	V_INTERP_P2_F32 v2, [v2], v1, 2, 0, [m0]                              ; C8090201
>	S_LOAD_DWORDX4 s[12:15], s[0:1], 0x0                                  ; C0860100
>	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
>	S_BUFFER_LOAD_DWORD s0, s[12:15], 0x25                                ; C2000D25
>	S_BUFFER_LOAD_DWORD s1, s[12:15], 0x27                                ; C2008D27
>	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
>	V_RCP_F32_e32 v3, s1                                                  ; 7E065401
>	V_MUL_F32_e32 v5, s0, v3                                              ; 100A0600
>	S_BUFFER_LOAD_DWORD s0, s[12:15], 0x24                                ; C2000D24
>	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
>	V_MUL_F32_e32 v4, s0, v3                                              ; 10080600
>	S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0                                    ; C0800300
>	S_LOAD_DWORDX8 s[12:19], s[4:5], 0x0                                  ; C0C60500
>	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
>	IMAGE_SAMPLE v[3:5], 7, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[12:19], s[0:3] ; F0800700 00030304
>	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
>	V_MUL_F32_e32 v2, v2, v5                                              ; 10040B02
>	V_INTERP_P1_F32 v6, v0, 1, 0, [m0]                                    ; C8180100
>	V_INTERP_P2_F32 v6, [v6], v1, 1, 0, [m0]                              ; C8190101
>	V_MUL_F32_e32 v6, v6, v4                                              ; 100C0906
>	V_INTERP_P1_F32 v7, v0, 0, 0, [m0]                                    ; C81C0000
>	V_INTERP_P2_F32 v7, [v7], v1, 0, 0, [m0]                              ; C81D0001
>	V_MUL_F32_e32 v3, v7, v3                                              ; 10060707
>	V_INTERP_P1_F32 v4, v0, 3, 0, [m0]                                    ; C8100300
>	V_INTERP_P2_F32 v4, [v4], v1, 3, 0, [m0]                              ; C8110301
>	EXP 15, 0, 0, 1, 1, v3, v6, v2, v4                                    ; F800180F 04020603
>	S_ENDPGM                                                              ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..4]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: MOV TEMP[0].w, IN[0].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0].xyz, TEMP[0], CONST[4]
>  4: MOV TEMP[0].xyz, TEMP[0].xyzx
>  5: MOV TEMP[0].w, CONST[4].wwww
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 64)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 68)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 72)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 76)
>  %28 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0
>  %29 = load <8 x i32> addrspace(2)* %28, !tbaa !0
>  %30 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0
>  %31 = load <4 x i32> addrspace(2)* %30, !tbaa !0
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7)
>  %35 = fdiv float %32, %34
>  %36 = fdiv float %33, %34
>  %37 = bitcast float %35 to i32
>  %38 = bitcast float %36 to i32
>  %39 = insertelement <2 x i32> undef, i32 %37, i32 0
>  %40 = insertelement <2 x i32> %39, i32 %38, i32 1
>  %41 = bitcast <8 x i32> %29 to <32 x i8>
>  %42 = bitcast <4 x i32> %31 to <16 x i8>
>  %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %40, <32 x i8> %41, <16 x i8> %42, i32 2)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = fmul float %44, %24
>  %48 = fmul float %45, %25
>  %49 = fmul float %46, %26
>  %50 = call i32 @llvm.SI.packf16(float %47, float %48)
>  %51 = bitcast i32 %50 to float
>  %52 = call i32 @llvm.SI.packf16(float %49, float %27)
>  %53 = bitcast i32 %52 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %51, float %53, float %51, float %53)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                                                   ; BEFE0A7E
>	S_MOV_B32 m0, s9                                                       ; BEFC0309
>	V_INTERP_P1_F32 v2, v0, 1, 0, [m0]                                     ; C8080100
>	V_INTERP_P2_F32 v2, [v2], v1, 1, 0, [m0]                               ; C8090101
>	V_INTERP_P1_F32 v3, v0, 3, 0, [m0]                                     ; C80C0300
>	V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0]                               ; C80D0301
>	V_RCP_F32_e32 v3, v3                                                   ; 7E065503
>	V_MUL_F32_e32 v5, v3, v2                                               ; 100A0503
>	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                     ; C8080000
>	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                               ; C8090001
>	V_MUL_F32_e32 v4, v3, v2                                               ; 10080503
>	S_LOAD_DWORDX4 s[8:11], s[2:3], 0x0                                    ; C0840300
>	S_LOAD_DWORDX8 s[12:19], s[4:5], 0x0                                   ; C0C60500
>	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
>	IMAGE_SAMPLE v[0:2], 7, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[12:19], s[8:11] ; F0800700 00430004
>	S_LOAD_DWORDX4 s[0:3], s[0:1], 0x0                                     ; C0800100
>	S_WAITCNT vmcnt(0) lgkmcnt(0)                                          ; BF8C0070
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x11                                   ; C2020111
>	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
>	V_MOV_B32_e32 v3, s4                                                   ; 7E060204
>	V_MUL_F32_e32 v3, v3, v1                                               ; 10060303
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x10                                   ; C2020110
>	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
>	V_MOV_B32_e32 v4, s4                                                   ; 7E080204
>	V_MUL_F32_e32 v4, v4, v0                                               ; 10080104
>	V_CVT_PKRTZ_F16_F32_e32 v3, v4, v3                                     ; 5E060704
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x12                                   ; C2020112
>	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
>	V_MOV_B32_e32 v4, s4                                                   ; 7E080204
>	V_MUL_F32_e32 v0, v4, v2                                               ; 10000504
>	S_BUFFER_LOAD_DWORD s0, s[0:3], 0x13                                   ; C2000113
>	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
>	V_CVT_PKRTZ_F16_F32_e64 v0, v0, s0, 0, 0                               ; D25E0000 00000100
>	EXP 15, 0, 1, 1, 1, v3, v0, v3, v0                                     ; F8001C0F 00030003
>	S_ENDPGM                                                               ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..4]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: MOV TEMP[0].w, IN[0].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], CONST[4]
>  4: MOV OUT[0], TEMP[0]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 64)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 68)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 72)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 76)
>  %28 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0
>  %29 = load <8 x i32> addrspace(2)* %28, !tbaa !0
>  %30 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0
>  %31 = load <4 x i32> addrspace(2)* %30, !tbaa !0
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7)
>  %35 = fdiv float %32, %34
>  %36 = fdiv float %33, %34
>  %37 = bitcast float %35 to i32
>  %38 = bitcast float %36 to i32
>  %39 = insertelement <2 x i32> undef, i32 %37, i32 0
>  %40 = insertelement <2 x i32> %39, i32 %38, i32 1
>  %41 = bitcast <8 x i32> %29 to <32 x i8>
>  %42 = bitcast <4 x i32> %31 to <16 x i8>
>  %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %40, <32 x i8> %41, <16 x i8> %42, i32 2)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %44, %24
>  %49 = fmul float %45, %25
>  %50 = fmul float %46, %26
>  %51 = fmul float %47, %27
>  %52 = call i32 @llvm.SI.packf16(float %48, float %49)
>  %53 = bitcast i32 %52 to float
>  %54 = call i32 @llvm.SI.packf16(float %50, float %51)
>  %55 = bitcast i32 %54 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %53, float %55, float %53, float %55)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                                                    ; BEFE0A7E
>	S_MOV_B32 m0, s9                                                        ; BEFC0309
>	V_INTERP_P1_F32 v2, v0, 1, 0, [m0]                                      ; C8080100
>	V_INTERP_P2_F32 v2, [v2], v1, 1, 0, [m0]                                ; C8090101
>	V_INTERP_P1_F32 v3, v0, 3, 0, [m0]                                      ; C80C0300
>	V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0]                                ; C80D0301
>	V_RCP_F32_e32 v3, v3                                                    ; 7E065503
>	V_MUL_F32_e32 v5, v3, v2                                                ; 100A0503
>	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                      ; C8080000
>	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                                ; C8090001
>	V_MUL_F32_e32 v4, v3, v2                                                ; 10080503
>	S_LOAD_DWORDX4 s[8:11], s[2:3], 0x0                                     ; C0840300
>	S_LOAD_DWORDX8 s[12:19], s[4:5], 0x0                                    ; C0C60500
>	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
>	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[12:19], s[8:11] ; F0800F00 00430004
>	S_LOAD_DWORDX4 s[0:3], s[0:1], 0x0                                      ; C0800100
>	S_WAITCNT vmcnt(0) lgkmcnt(0)                                           ; BF8C0070
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x13                                    ; C2020113
>	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
>	V_MOV_B32_e32 v4, s4                                                    ; 7E080204
>	V_MUL_F32_e32 v4, v4, v3                                                ; 10080704
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x12                                    ; C2020112
>	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
>	V_MOV_B32_e32 v5, s4                                                    ; 7E0A0204
>	V_MUL_F32_e32 v5, v5, v2                                                ; 100A0505
>	V_CVT_PKRTZ_F16_F32_e32 v4, v5, v4                                      ; 5E080905
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x11                                    ; C2020111
>	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
>	V_MOV_B32_e32 v5, s4                                                    ; 7E0A0204
>	V_MUL_F32_e32 v5, v5, v1                                                ; 100A0305
>	S_BUFFER_LOAD_DWORD s0, s[0:3], 0x10                                    ; C2000110
>	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
>	V_MOV_B32_e32 v6, s0                                                    ; 7E0C0200
>	V_MUL_F32_e32 v0, v6, v0                                                ; 10000106
>	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v5                                      ; 5E000B00
>	EXP 15, 0, 1, 1, 1, v0, v4, v0, v4                                      ; F8001C0F 04000400
>	S_ENDPGM                                                                ; BF810000
>
>fixme:win:EnumDisplayDevicesW ((null),0,0x32f6a8,0x00000000), stub!
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>
>Shader Disassembly:
>
>	V_MOV_B32_e32 v0, 0               ; 7E000280
>	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
>	S_ENDPGM                          ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
>	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
>	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
>	S_ENDPGM                            ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
>	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
>	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
>	S_ENDPGM                            ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	V_MOV_B32_e32 v0, 0               ; 7E000280
>	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
>	S_ENDPGM                          ; BF810000
>
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>
>Shader Disassembly:
>
>	V_MOV_B32_e32 v0, 0               ; 7E000280
>	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
>	S_ENDPGM                          ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
>	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
>	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
>	S_ENDPGM                            ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
>	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
>	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
>	S_ENDPGM                            ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	V_MOV_B32_e32 v0, 0               ; 7E000280
>	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
>	S_ENDPGM                          ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
>  %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
>  %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
>  %25 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                     ; BEFE0A7E
>	S_MOV_B32 m0, s9                         ; BEFC0309
>	V_INTERP_P1_F32 v2, v0, 3, 0, [m0]       ; C8080300
>	V_INTERP_P2_F32 v2, [v2], v1, 3, 0, [m0] ; C8090301
>	V_INTERP_P1_F32 v3, v0, 2, 0, [m0]       ; C80C0200
>	V_INTERP_P2_F32 v3, [v3], v1, 2, 0, [m0] ; C80D0201
>	V_INTERP_P1_F32 v4, v0, 1, 0, [m0]       ; C8100100
>	V_INTERP_P2_F32 v4, [v4], v1, 1, 0, [m0] ; C8110101
>	V_INTERP_P1_F32 v5, v0, 0, 0, [m0]       ; C8140000
>	V_INTERP_P2_F32 v5, [v5], v1, 0, 0, [m0] ; C8150001
>	EXP 15, 0, 0, 1, 1, v5, v4, v3, v2       ; F800180F 02030405
>	S_ENDPGM                                 ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  %28 = call i32 @llvm.SI.packf16(float %24, float %25)
>  %29 = bitcast i32 %28 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0  ; 5E000101
>	V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102
>	V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002
>	V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1  ; 5E020302
>	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0  ; F8001C0F 00010001
>	S_ENDPGM                            ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0
>  %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0
>  %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0
>  %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11)
>  %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11)
>  %28 = bitcast float %26 to i32
>  %29 = bitcast float %27 to i32
>  %30 = insertelement <2 x i32> undef, i32 %28, i32 0
>  %31 = insertelement <2 x i32> %30, i32 %29, i32 1
>  %32 = bitcast <8 x i32> %23 to <32 x i8>
>  %33 = bitcast <4 x i32> %25 to <16 x i8>
>  %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %32, <16 x i8> %33, i32 2)
>  %35 = extractelement <4 x float> %34, i32 0
>  %36 = extractelement <4 x float> %34, i32 1
>  %37 = extractelement <4 x float> %34, i32 2
>  %38 = extractelement <4 x float> %34, i32 3
>  %39 = call i32 @llvm.SI.packf16(float %35, float %36)
>  %40 = bitcast i32 %39 to float
>  %41 = call i32 @llvm.SI.packf16(float %37, float %38)
>  %42 = bitcast i32 %41 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %40, float %42, float %40, float %42)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
>	S_MOV_B32 m0, s9                                                      ; BEFC0309
>	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                    ; C80C0100
>	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                              ; C80D0101
>	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                    ; C8080000
>	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                              ; C8090001
>	S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0                                    ; C0800300
>	S_LOAD_DWORDX8 s[4:11], s[4:5], 0x0                                   ; C0C20500
>	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
>	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002
>	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
>	V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3                                    ; 5E080702
>	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1                                    ; 5E000300
>	EXP 15, 0, 1, 1, 1, v0, v4, v0, v4                                    ; F8001C0F 04000400
>	S_ENDPGM                                                              ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0
>  %23 = load <8 x i32> addrspace(2)* %22, !tbaa !0
>  %24 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0
>  %25 = load <4 x i32> addrspace(2)* %24, !tbaa !0
>  %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11)
>  %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11)
>  %28 = bitcast float %26 to i32
>  %29 = bitcast float %27 to i32
>  %30 = insertelement <2 x i32> undef, i32 %28, i32 0
>  %31 = insertelement <2 x i32> %30, i32 %29, i32 1
>  %32 = bitcast <8 x i32> %23 to <32 x i8>
>  %33 = bitcast <4 x i32> %25 to <16 x i8>
>  %34 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %32, <16 x i8> %33, i32 2)
>  %35 = extractelement <4 x float> %34, i32 0
>  %36 = extractelement <4 x float> %34, i32 1
>  %37 = extractelement <4 x float> %34, i32 2
>  %38 = extractelement <4 x float> %34, i32 3
>  %39 = call i32 @llvm.SI.packf16(float %35, float %36)
>  %40 = bitcast i32 %39 to float
>  %41 = call i32 @llvm.SI.packf16(float %37, float %38)
>  %42 = bitcast i32 %41 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %40, float %42, float %40, float %42)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
>	S_MOV_B32 m0, s9                                                      ; BEFC0309
>	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                    ; C80C0100
>	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                              ; C80D0101
>	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                    ; C8080000
>	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                              ; C8090001
>	S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0                                    ; C0800300
>	S_LOAD_DWORDX8 s[4:11], s[4:5], 0x0                                   ; C0C20500
>	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
>	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002
>	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
>	V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3                                    ; 5E080702
>	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1                                    ; 5E000300
>	EXP 15, 0, 1, 1, 1, v0, v4, v0, v4                                    ; F8001C0F 04000400
>	S_ENDPGM                                                              ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], FOG, PERSPECTIVE
>DCL OUT[0], COLOR
>DCL CONST[1..2]
>DCL TEMP[0..1]
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV_SAT TEMP[0], IMM[0].xyyy
>  1: MAD_SAT TEMP[1].x, IN[0].xxxx, CONST[1].xxxx, CONST[1].yyyy
>  2: LRP OUT[0].xyz, TEMP[1].xxxx, TEMP[0], CONST[2]
>  3: MOV OUT[0].w, TEMP[0]
>  4: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 16)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 20)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 32)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 36)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %23, i32 40)
>  %29 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
>  %30 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  %31 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  %32 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  %33 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
>  %34 = fmul float %29, %24
>  %35 = fadd float %34, %25
>  %36 = call float @llvm.AMDIL.clamp.(float %35, float 0.000000e+00, float 1.000000e+00)
>  %37 = call float @llvm.AMDGPU.lrp(float %36, float %30, float %26)
>  %38 = call float @llvm.AMDGPU.lrp(float %36, float %31, float %27)
>  %39 = call float @llvm.AMDGPU.lrp(float %36, float %32, float %28)
>  %40 = call i32 @llvm.SI.packf16(float %37, float %38)
>  %41 = bitcast i32 %40 to float
>  %42 = call i32 @llvm.SI.packf16(float %39, float %33)
>  %43 = bitcast i32 %42 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %41, float %43, float %41, float %43)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDIL.clamp.(float, float, float) #2
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.lrp(float, float, float) #2
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                     ; BEFE0A7E
>	S_MOV_B32 m0, s9                         ; BEFC0309
>	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]       ; C8080000
>	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001
>	S_LOAD_DWORDX4 s[0:3], s[0:1], 0x0       ; C0800100
>	S_WAITCNT lgkmcnt(0)                     ; BF8C007F
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x4      ; C2020104
>	S_BUFFER_LOAD_DWORD s5, s[0:3], 0x5      ; C2028105
>	S_WAITCNT lgkmcnt(0)                     ; BF8C007F
>	V_MOV_B32_e32 v0, s5                     ; 7E000205
>	V_MAD_F32 v0, v2, s4, v0, 0, 0           ; D2820000 04000902
>	V_ADD_F32_e64 v0, v0, 0, 1, 0            ; D2060800 00010100
>	V_SUB_F32_e32 v1, 1.000000e+00, v0       ; 080200F2
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x9      ; C2020109
>	S_WAITCNT lgkmcnt(0)                     ; BF8C007F
>	V_MUL_F32_e64 v2, v1, s4, 0, 0           ; D2100002 00000901
>	V_ADD_F32_e64 v3, 0.000000e+00, 0, 1, 0  ; D2060803 00010080
>	V_MAD_F32 v2, v0, v3, v2, 0, 0           ; D2820002 040A0700
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x8      ; C2020108
>	S_WAITCNT lgkmcnt(0)                     ; BF8C007F
>	V_MUL_F32_e64 v4, v1, s4, 0, 0           ; D2100004 00000901
>	V_ADD_F32_e64 v5, 1.000000e+00, 0, 1, 0  ; D2060805 000100F2
>	V_MAD_F32 v4, v0, v5, v4, 0, 0           ; D2820004 04120B00
>	V_CVT_PKRTZ_F16_F32_e32 v2, v4, v2       ; 5E040504
>	S_BUFFER_LOAD_DWORD s0, s[0:3], 0xa      ; C200010A
>	S_WAITCNT lgkmcnt(0)                     ; BF8C007F
>	V_MUL_F32_e64 v1, v1, s0, 0, 0           ; D2100001 00000101
>	V_MAD_F32 v0, v0, v3, v1, 0, 0           ; D2820000 04060700
>	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v3       ; 5E000700
>	EXP 15, 0, 1, 1, 1, v2, v0, v2, v0       ; F8001C0F 00020002
>	S_ENDPGM                                 ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL OUT[0], COLOR
>DCL CONST[0..3]
>  0: MOV OUT[0], CONST[3]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 48)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 52)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 56)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 60)
>  %28 = call i32 @llvm.SI.packf16(float %24, float %25)
>  %29 = bitcast i32 %28 to float
>  %30 = call i32 @llvm.SI.packf16(float %26, float %27)
>  %31 = bitcast i32 %30 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %29, float %31, float %29, float %31)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>
>Shader Disassembly:
>
>	S_LOAD_DWORDX4 s[0:3], s[0:1], 0x0  ; C0800100
>	S_WAITCNT lgkmcnt(0)                ; BF8C007F
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0xe ; C202010E
>	S_BUFFER_LOAD_DWORD s5, s[0:3], 0xf ; C202810F
>	S_WAITCNT lgkmcnt(0)                ; BF8C007F
>	V_MOV_B32_e32 v0, s5                ; 7E000205
>	V_CVT_PKRTZ_F16_F32_e32 v0, s4, v0  ; 5E000004
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0xc ; C202010C
>	S_BUFFER_LOAD_DWORD s0, s[0:3], 0xd ; C200010D
>	S_WAITCNT lgkmcnt(0)                ; BF8C007F
>	V_MOV_B32_e32 v1, s0                ; 7E020200
>	V_CVT_PKRTZ_F16_F32_e32 v1, s4, v1  ; 5E020204
>	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0  ; F8001C0F 00010001
>	S_ENDPGM                            ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
>	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
>	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
>	S_ENDPGM                            ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
>  %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
>  %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
>  %25 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                     ; BEFE0A7E
>	S_MOV_B32 m0, s9                         ; BEFC0309
>	V_INTERP_P1_F32 v2, v0, 3, 0, [m0]       ; C8080300
>	V_INTERP_P2_F32 v2, [v2], v1, 3, 0, [m0] ; C8090301
>	V_INTERP_P1_F32 v3, v0, 2, 0, [m0]       ; C80C0200
>	V_INTERP_P2_F32 v3, [v3], v1, 2, 0, [m0] ; C80D0201
>	V_INTERP_P1_F32 v4, v0, 1, 0, [m0]       ; C8100100
>	V_INTERP_P2_F32 v4, [v4], v1, 1, 0, [m0] ; C8110101
>	V_INTERP_P1_F32 v5, v0, 0, 0, [m0]       ; C8140000
>	V_INTERP_P2_F32 v5, [v5], v1, 0, 0, [m0] ; C8150001
>	EXP 15, 0, 0, 1, 1, v5, v4, v3, v2       ; F800180F 02030405
>	S_ENDPGM                                 ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
>  %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
>  %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
>  %25 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7)
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  %28 = call i32 @llvm.SI.packf16(float %24, float %25)
>  %29 = bitcast i32 %28 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                     ; BEFE0A7E
>	S_MOV_B32 m0, s9                         ; BEFC0309
>	V_INTERP_P1_F32 v2, v0, 3, 0, [m0]       ; C8080300
>	V_INTERP_P2_F32 v2, [v2], v1, 3, 0, [m0] ; C8090301
>	V_INTERP_P1_F32 v3, v0, 2, 0, [m0]       ; C80C0200
>	V_INTERP_P2_F32 v3, [v3], v1, 2, 0, [m0] ; C80D0201
>	V_CVT_PKRTZ_F16_F32_e32 v2, v3, v2       ; 5E040503
>	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]       ; C80C0100
>	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101
>	V_INTERP_P1_F32 v4, v0, 0, 0, [m0]       ; C8100000
>	V_INTERP_P2_F32 v4, [v4], v1, 0, 0, [m0] ; C8110001
>	V_CVT_PKRTZ_F16_F32_e32 v0, v4, v3       ; 5E000704
>	EXP 15, 0, 1, 1, 1, v0, v2, v0, v2       ; F8001C0F 02000200
>	S_ENDPGM                                 ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..9]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, CONST[9].xyyy
>  1: MOV TEMP[0].w, CONST[9].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0].xyz, TEMP[0], IN[0]
>  4: MOV TEMP[0].xyz, TEMP[0].xyzx
>  5: MOV TEMP[0].w, IN[0].wwww
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 144)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 148)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 156)
>  %27 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0
>  %28 = load <8 x i32> addrspace(2)* %27, !tbaa !0
>  %29 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0
>  %30 = load <4 x i32> addrspace(2)* %29, !tbaa !0
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
>  %33 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7)
>  %35 = fdiv float %24, %26
>  %36 = fdiv float %25, %26
>  %37 = bitcast float %35 to i32
>  %38 = bitcast float %36 to i32
>  %39 = insertelement <2 x i32> undef, i32 %37, i32 0
>  %40 = insertelement <2 x i32> %39, i32 %38, i32 1
>  %41 = bitcast <8 x i32> %28 to <32 x i8>
>  %42 = bitcast <4 x i32> %30 to <16 x i8>
>  %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %40, <32 x i8> %41, <16 x i8> %42, i32 2)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = fmul float %44, %31
>  %48 = fmul float %45, %32
>  %49 = fmul float %46, %33
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %47, float %48, float %49, float %34)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
>	S_MOV_B32 m0, s9                                                      ; BEFC0309
>	V_INTERP_P1_F32 v2, v0, 2, 0, [m0]                                    ; C8080200
>	V_INTERP_P2_F32 v2, [v2], v1, 2, 0, [m0]                              ; C8090201
>	S_LOAD_DWORDX4 s[12:15], s[0:1], 0x0                                  ; C0860100
>	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
>	S_BUFFER_LOAD_DWORD s0, s[12:15], 0x25                                ; C2000D25
>	S_BUFFER_LOAD_DWORD s1, s[12:15], 0x27                                ; C2008D27
>	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
>	V_RCP_F32_e32 v3, s1                                                  ; 7E065401
>	V_MUL_F32_e32 v5, s0, v3                                              ; 100A0600
>	S_BUFFER_LOAD_DWORD s0, s[12:15], 0x24                                ; C2000D24
>	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
>	V_MUL_F32_e32 v4, s0, v3                                              ; 10080600
>	S_LOAD_DWORDX4 s[0:3], s[2:3], 0x0                                    ; C0800300
>	S_LOAD_DWORDX8 s[12:19], s[4:5], 0x0                                  ; C0C60500
>	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
>	IMAGE_SAMPLE v[3:5], 7, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[12:19], s[0:3] ; F0800700 00030304
>	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
>	V_MUL_F32_e32 v2, v2, v5                                              ; 10040B02
>	V_INTERP_P1_F32 v6, v0, 1, 0, [m0]                                    ; C8180100
>	V_INTERP_P2_F32 v6, [v6], v1, 1, 0, [m0]                              ; C8190101
>	V_MUL_F32_e32 v6, v6, v4                                              ; 100C0906
>	V_INTERP_P1_F32 v7, v0, 0, 0, [m0]                                    ; C81C0000
>	V_INTERP_P2_F32 v7, [v7], v1, 0, 0, [m0]                              ; C81D0001
>	V_MUL_F32_e32 v3, v7, v3                                              ; 10060707
>	V_INTERP_P1_F32 v4, v0, 3, 0, [m0]                                    ; C8100300
>	V_INTERP_P2_F32 v4, [v4], v1, 3, 0, [m0]                              ; C8110301
>	EXP 15, 0, 0, 1, 1, v3, v6, v2, v4                                    ; F800180F 04020603
>	S_ENDPGM                                                              ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..4]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: MOV TEMP[0].w, IN[0].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0].xyz, TEMP[0], CONST[4]
>  4: MOV TEMP[0].xyz, TEMP[0].xyzx
>  5: MOV TEMP[0].w, CONST[4].wwww
>  6: MOV OUT[0], TEMP[0]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 64)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 68)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 72)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 76)
>  %28 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0
>  %29 = load <8 x i32> addrspace(2)* %28, !tbaa !0
>  %30 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0
>  %31 = load <4 x i32> addrspace(2)* %30, !tbaa !0
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7)
>  %35 = fdiv float %32, %34
>  %36 = fdiv float %33, %34
>  %37 = bitcast float %35 to i32
>  %38 = bitcast float %36 to i32
>  %39 = insertelement <2 x i32> undef, i32 %37, i32 0
>  %40 = insertelement <2 x i32> %39, i32 %38, i32 1
>  %41 = bitcast <8 x i32> %29 to <32 x i8>
>  %42 = bitcast <4 x i32> %31 to <16 x i8>
>  %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %40, <32 x i8> %41, <16 x i8> %42, i32 2)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = fmul float %44, %24
>  %48 = fmul float %45, %25
>  %49 = fmul float %46, %26
>  %50 = call i32 @llvm.SI.packf16(float %47, float %48)
>  %51 = bitcast i32 %50 to float
>  %52 = call i32 @llvm.SI.packf16(float %49, float %27)
>  %53 = bitcast i32 %52 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %51, float %53, float %51, float %53)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                                                   ; BEFE0A7E
>	S_MOV_B32 m0, s9                                                       ; BEFC0309
>	V_INTERP_P1_F32 v2, v0, 1, 0, [m0]                                     ; C8080100
>	V_INTERP_P2_F32 v2, [v2], v1, 1, 0, [m0]                               ; C8090101
>	V_INTERP_P1_F32 v3, v0, 3, 0, [m0]                                     ; C80C0300
>	V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0]                               ; C80D0301
>	V_RCP_F32_e32 v3, v3                                                   ; 7E065503
>	V_MUL_F32_e32 v5, v3, v2                                               ; 100A0503
>	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                     ; C8080000
>	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                               ; C8090001
>	V_MUL_F32_e32 v4, v3, v2                                               ; 10080503
>	S_LOAD_DWORDX4 s[8:11], s[2:3], 0x0                                    ; C0840300
>	S_LOAD_DWORDX8 s[12:19], s[4:5], 0x0                                   ; C0C60500
>	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
>	IMAGE_SAMPLE v[0:2], 7, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[12:19], s[8:11] ; F0800700 00430004
>	S_LOAD_DWORDX4 s[0:3], s[0:1], 0x0                                     ; C0800100
>	S_WAITCNT vmcnt(0) lgkmcnt(0)                                          ; BF8C0070
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x11                                   ; C2020111
>	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
>	V_MOV_B32_e32 v3, s4                                                   ; 7E060204
>	V_MUL_F32_e32 v3, v3, v1                                               ; 10060303
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x10                                   ; C2020110
>	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
>	V_MOV_B32_e32 v4, s4                                                   ; 7E080204
>	V_MUL_F32_e32 v4, v4, v0                                               ; 10080104
>	V_CVT_PKRTZ_F16_F32_e32 v3, v4, v3                                     ; 5E060704
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x12                                   ; C2020112
>	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
>	V_MOV_B32_e32 v4, s4                                                   ; 7E080204
>	V_MUL_F32_e32 v0, v4, v2                                               ; 10000504
>	S_BUFFER_LOAD_DWORD s0, s[0:3], 0x13                                   ; C2000113
>	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
>	V_CVT_PKRTZ_F16_F32_e64 v0, v0, s0, 0, 0                               ; D25E0000 00000100
>	EXP 15, 0, 1, 1, 1, v3, v0, v3, v0                                     ; F8001C0F 00030003
>	S_ENDPGM                                                               ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[1..4]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: MOV TEMP[0].w, IN[0].wwww
>  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
>  3: MUL TEMP[0], TEMP[0], CONST[4]
>  4: MOV OUT[0], TEMP[0]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
>  %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0
>  %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 64)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 68)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 72)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 76)
>  %28 = getelementptr [32 x <8 x i32>] addrspace(2)* %2, i64 0, i32 0
>  %29 = load <8 x i32> addrspace(2)* %28, !tbaa !0
>  %30 = getelementptr [16 x <4 x i32>] addrspace(2)* %1, i64 0, i32 0
>  %31 = load <4 x i32> addrspace(2)* %30, !tbaa !0
>  %32 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
>  %33 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
>  %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7)
>  %35 = fdiv float %32, %34
>  %36 = fdiv float %33, %34
>  %37 = bitcast float %35 to i32
>  %38 = bitcast float %36 to i32
>  %39 = insertelement <2 x i32> undef, i32 %37, i32 0
>  %40 = insertelement <2 x i32> %39, i32 %38, i32 1
>  %41 = bitcast <8 x i32> %29 to <32 x i8>
>  %42 = bitcast <4 x i32> %31 to <16 x i8>
>  %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %40, <32 x i8> %41, <16 x i8> %42, i32 2)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = fmul float %44, %24
>  %49 = fmul float %45, %25
>  %50 = fmul float %46, %26
>  %51 = fmul float %47, %27
>  %52 = call i32 @llvm.SI.packf16(float %48, float %49)
>  %53 = bitcast i32 %52 to float
>  %54 = call i32 @llvm.SI.packf16(float %50, float %51)
>  %55 = bitcast i32 %54 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %53, float %55, float %53, float %55)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>!0 = metadata !{metadata !"const", null, i32 1}
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                                                    ; BEFE0A7E
>	S_MOV_B32 m0, s9                                                        ; BEFC0309
>	V_INTERP_P1_F32 v2, v0, 1, 0, [m0]                                      ; C8080100
>	V_INTERP_P2_F32 v2, [v2], v1, 1, 0, [m0]                                ; C8090101
>	V_INTERP_P1_F32 v3, v0, 3, 0, [m0]                                      ; C80C0300
>	V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0]                                ; C80D0301
>	V_RCP_F32_e32 v3, v3                                                    ; 7E065503
>	V_MUL_F32_e32 v5, v3, v2                                                ; 100A0503
>	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                      ; C8080000
>	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                                ; C8090001
>	V_MUL_F32_e32 v4, v3, v2                                                ; 10080503
>	S_LOAD_DWORDX4 s[8:11], s[2:3], 0x0                                     ; C0840300
>	S_LOAD_DWORDX8 s[12:19], s[4:5], 0x0                                    ; C0C60500
>	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
>	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[12:19], s[8:11] ; F0800F00 00430004
>	S_LOAD_DWORDX4 s[0:3], s[0:1], 0x0                                      ; C0800100
>	S_WAITCNT vmcnt(0) lgkmcnt(0)                                           ; BF8C0070
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x13                                    ; C2020113
>	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
>	V_MOV_B32_e32 v4, s4                                                    ; 7E080204
>	V_MUL_F32_e32 v4, v4, v3                                                ; 10080704
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x12                                    ; C2020112
>	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
>	V_MOV_B32_e32 v5, s4                                                    ; 7E0A0204
>	V_MUL_F32_e32 v5, v5, v2                                                ; 100A0505
>	V_CVT_PKRTZ_F16_F32_e32 v4, v5, v4                                      ; 5E080905
>	S_BUFFER_LOAD_DWORD s4, s[0:3], 0x11                                    ; C2020111
>	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
>	V_MOV_B32_e32 v5, s4                                                    ; 7E0A0204
>	V_MUL_F32_e32 v5, v5, v1                                                ; 100A0305
>	S_BUFFER_LOAD_DWORD s0, s[0:3], 0x10                                    ; C2000110
>	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
>	V_MOV_B32_e32 v6, s0                                                    ; 7E0C0200
>	V_MUL_F32_e32 v0, v6, v0                                                ; 10000106
>	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v5                                      ; 5E000B00
>	EXP 15, 0, 1, 1, 1, v0, v4, v0, v4                                      ; F8001C0F 04000400
>	S_ENDPGM                                                                ; BF810000
>
>fixme:win:EnumDisplayDevicesW ((null),0,0x32f6a8,0x00000000), stub!
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>
>Shader Disassembly:
>
>	V_MOV_B32_e32 v0, 0               ; 7E000280
>	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
>	S_ENDPGM                          ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
>	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
>	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
>	S_ENDPGM                            ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
>	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
>	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
>	S_ENDPGM                            ; BF810000
>
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	V_MOV_B32_e32 v0, 0               ; 7E000280
>	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
>	S_ENDPGM                          ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
>  %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
>  %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
>  %25 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7)
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                     ; BEFE0A7E
>	S_MOV_B32 m0, s9                         ; BEFC0309
>	V_INTERP_P1_F32 v2, v0, 3, 0, [m0]       ; C8080300
>	V_INTERP_P2_F32 v2, [v2], v1, 3, 0, [m0] ; C8090301
>	V_INTERP_P1_F32 v3, v0, 2, 0, [m0]       ; C80C0200
>	V_INTERP_P2_F32 v3, [v3], v1, 2, 0, [m0] ; C80D0201
>	V_INTERP_P1_F32 v4, v0, 1, 0, [m0]       ; C8100100
>	V_INTERP_P2_F32 v4, [v4], v1, 1, 0, [m0] ; C8110101
>	V_INTERP_P1_F32 v5, v0, 0, 0, [m0]       ; C8140000
>	V_INTERP_P2_F32 v5, [v5], v1, 0, 0, [m0] ; C8150001
>	EXP 15, 0, 0, 1, 1, v5, v4, v3, v2       ; F800180F 02030405
>	S_ENDPGM                                 ; BF810000
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5)
>  %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5)
>  %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5)
>  %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5)
>  %26 = call i32 @llvm.SI.packf16(float %22, float %23)
>  %27 = bitcast i32 %26 to float
>  %28 = call i32 @llvm.SI.packf16(float %24, float %25)
>  %29 = bitcast i32 %28 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>
>Shader Disassembly:
>
>	S_WQM_B64 exec, exec                ; BEFE0A7E
>	S_MOV_B32 m0, s9                    ; BEFC0309
>	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
>	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
>	V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0  ; 5E000101
>	V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102
>	V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002
>	V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1  ; 5E020302
>	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0  ; F8001C0F 00010001
>	S_ENDPGM                            ; BF810000
>
>FRAG
>  0: END
>; ModuleID = 'tgsi'
>
>define void @main([17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [6 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
>main_body:
>  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)
>
>attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" }
>wine: Unhandled exception 0xc000008d in thread 9 at address 0x7aad3e3a (thread 0009), starting debugger...
>Unhandled exception: denormal float operand in 32-bit code (0x7aad3d1f).
>Register dump:
> CS:0023 SS:002b DS:002b ES:002b FS:0063 GS:006b
> EIP:7aad3d1f ESP:00329950 EBP:003299d8 EFLAGS:00210287(  R- --  I S - -P-C)
> EAX:00329b2c EBX:7b7ec000 ECX:00000001 EDX:7b36860e
> ESI:7ccb4f0c EDI:00329b18
>Stack dump:
>0x00329950:  7ccb4ee4 00000af7 00000040 7cc6cfb8
>0x00329960:  7cc6cfbc 00329d80 ffffffff 00000000
>0x00329970:  7b36860e 7ccb4f34 ffffffff 00000000
>0x00329980:  ffffffff 00329b01 00329b00 00329b40
>0x00329990:  00329b01 000000ad 00000000 7b7ec000
>0x003299a0:  7cde3268 7ccaacd8 7cde3218 7b09b94c
>Backtrace:
>=>0 0x7aad3d1f _ZNK4llvm17AMDGPUMCInstLower5lowerEPKNS_12MachineInstrERNS_6MCInstE+0xef() in libllvm-3.6svn.so (0x003299d8)
>  1 0x7aad415e _ZN4llvm16AMDGPUAsmPrinter15EmitInstructionEPKNS_12MachineInstrE+0xbd() in libllvm-3.6svn.so (0x7ccb4ee4)
>  2 0x7abdb978 _ZN4llvm10AsmPrinter16EmitFunctionBodyEv+0x8d7() in libllvm-3.6svn.so (0x00329d68)
>  3 0x7aabc050 _ZN4llvm16AMDGPUAsmPrinter20runOnMachineFunctionERNS_15MachineFunctionE+0x2cf() in libllvm-3.6svn.so (0x00329e38)
>  4 0x7b0a4114 _ZN4llvm19MachineFunctionPass13runOnFunctionERNS_8FunctionE+0x73() in libllvm-3.6svn.so (0x7cbe48e8)
>  5 0x7ad22e3b _ZN4llvm13FPPassManager13runOnFunctionERNS_8FunctionE+0x20a() in libllvm-3.6svn.so (0x00329ee8)
>  6 0x7ad23188 _ZN4llvm13FPPassManager11runOnModuleERNS_6ModuleE+0x37() in libllvm-3.6svn.so (0x7de62b38)
>  7 0x7ad23494 _ZN4llvm6legacy15PassManagerImpl3runERNS_6ModuleE+0x2f3() in libllvm-3.6svn.so (0x7dea6a20)
>  8 0x7ad23656 _ZN4llvm6legacy11PassManager3runERNS_6ModuleE+0x25() in libllvm-3.6svn.so (0x7cc6c390)
>  9 0x7b27aeca _ZL21LLVMTargetMachineEmitP23LLVMOpaqueTargetMachineP16LLVMOpaqueModuleRN4llvm21formatted_raw_ostreamE19LLVMCodeGenFileTypePPc+0xc9() in libllvm-3.6svn.so (0x7cc6c390)
>  10 0x7b27b0f0 LLVMTargetMachineEmitToMemoryBuffer+0x14f() in libllvm-3.6svn.so (0x0032a040)
>  11 0x7d99bd6e radeon_llvm_compile+0x205() in radeonsi_dri.so (0x7b7f50a0)
>  12 0x7da4de9d si_compile_llvm+0x94() in radeonsi_dri.so (0x7cd76018)
>  13 0x7da4e84d si_pipe_shader_create+0x63c() in radeonsi_dri.so (0x0032dc9c)
>  14 0x7da5458c si_shader_select+0x2eb() in radeonsi_dri.so (0x7de68938)
>  15 0x7da546b3 si_create_shader_state+0x8a() in radeonsi_dri.so (0x7cc634a8)
>  16 0x7d8abff1 ureg_create_shader+0x50() in radeonsi_dri.so (0x7cbf61c0)
>  17 0x7d8d2a7a util_make_empty_fragment_shader+0xb1() in radeonsi_dri.so (0x0032f018)
>  18 0x7d8b9ad7 util_blitter_create+0x386() in radeonsi_dri.so (0x7cd65600)
>  19 0x7da477e0 si_create_context+0x16f() in radeonsi_dri.so (0x7de75410)
>  20 0x7d7a2997 st_api_create_context+0x76() in radeonsi_dri.so (0x7de74cd4)
>  21 0x7d861d4f dri_create_context+0x1ee() in radeonsi_dri.so (0x7de74cd4)
>  22 0x7d85e555 driCreateContextAttribs+0x31c() in radeonsi_dri.so (0x00000001)
>  23 0x7e1307b3 dri2_create_context_attribs+0x1a2() in libgl.so.1 (0x7cc5c0e0)
>  24 0x7e10487d glXCreateContextAttribsARB+0x1ac() in libgl.so.1 (0x0032f658)
>  25 0x7e4251c3 create_glxcontext.isra+0x52() in winex11 (0x0032f688)
>  26 0x7e4254f8 X11DRV_wglCreateContextAttribsARB+0x187(hdc=<is not available>, hShareContext=<is not available>, attribList=<is not available>) [/home/andrei/x/wine/dlls/winex11.drv/opengl.c:2081] in winex11 (0x0032f6d8)
>  27 0x7e9e46da wglCreateContextAttribsARB+0x99(hdc=<couldn't compute location>, share=<couldn't compute location>, attribs=<couldn't compute location>) [/home/andrei/x/wine/dlls/opengl32/wgl.c:268] in opengl32 (0x0032f718)
>  28 0x7ea99829 context_create+0x388(swapchain=0x11fdd8, target=0x11cdb0, ds_format=0x131c10) [/home/andrei/x/wine/dlls/wined3d/context.c:1543] in wined3d (0x0032f7a8)
>  29 0x7eb2f5b7 wined3d_swapchain_create+0x8d6(device=<couldn't compute location>, desc=<couldn't compute location>, parent=<couldn't compute location>, parent_ops=<couldn't compute location>, swapchain=<couldn't compute location>) [/home/andrei/x/wine/dlls/wined3d/swapchain.c:923] in wined3d (0x0032f878)
>  30 0x7efe7ed0 d3d8_swapchain_create+0x7f(device=0x127388, desc=0x32fa24, swapchain=0x32f8fc) [/home/andrei/x/wine/dlls/d3d8/swapchain.c:167] in d3d8 (0x0032f8c8)
>  31 0x7efdceda device_parent_create_swapchain+0x49(device_parent=<couldn't compute location>, desc=<couldn't compute location>, swapchain=<couldn't compute location>) [/home/andrei/x/wine/dlls/d3d8/device.c:3034] in d3d8 (0x0032f918)
>  32 0x7eaadc8c wined3d_device_init_3d+0xeb(device=<couldn't compute location>, swapchain_desc=<couldn't compute location>) [/home/andrei/x/wine/dlls/wined3d/device.c:896] in wined3d (0x0032f9d8)
>  33 0x7efe4ca2 device_init+0x141(device=0x127388, parent=0x127370, wined3d=0x127688, adapter=0, device_type=D3DDEVTYPE_HAL, focus_window=0x20048, flags=0x42, parameters=0x32fc4c) [/home/andrei/x/wine/dlls/d3d8/device.c:3134] in d3d8 (0x0032fa78)
>  34 0x7efe50e6 d3d8_CreateDevice+0xb5(iface=<couldn't compute location>, adapter=<couldn't compute location>, device_type=<couldn't compute location>, focus_window=<couldn't compute location>, flags=<couldn't compute location>, parameters=<couldn't compute location>, device=<couldn't compute location>) [/home/andrei/x/wine/dlls/d3d8/directx.c:369] in d3d8 (0x0032fae8)
>  35 0x7ebc414b func_device+0x48a() [/home/andrei/x/wine/dlls/d3d8/tests/device.c:2602] in d3d8_test (0x0032fd38)
>  36 0x7ebaa284 main+0x383(argc=<is not available>, argv=<is not available>) [/home/andrei/x/wine/dlls/d3d8/tests/../../../include/wine/test.h:584] in d3d8_test (0x0032fe18)
>  37 0x7ebe7ce0 __wine_spec_exe_entry+0x7f(peb=<couldn't compute location>) [/home/andrei/x/wine/dlls/winecrt0/exe_entry.c:36] in d3d8_test (0x0032fe58)
>  38 0x7b85f4fc call_process_entry+0xb() in kernel32 (0x0032fe78)
>  39 0x7b860593 start_process+0x62(peb=<couldn't compute location>) [/home/andrei/x/wine/dlls/kernel32/process.c:1097] in kernel32 (0x0032feb8)
>  40 0x7bc7fd90 call_thread_func_wrapper+0xb() in ntdll (0x0032fed8)
>  41 0x7bc82d1d call_thread_func+0x7c(entry=0x7b860530, arg=0x7ffdf000, frame=0x32ffc8) [/home/andrei/x/wine/dlls/ntdll/signal_i386.c:2637] in ntdll (0x0032ffa8)
>  42 0x7bc7fd6e call_thread_entry_point+0x11() in ntdll (0x0032ffc8)
>  43 0x7bc53dee start_process+0x1d(kernel_start=0x7b860530) [/home/andrei/x/wine/dlls/ntdll/loader.c:2856] in ntdll (0x0032ffe8)
>  44 0xf752969d wine_call_on_stack+0x1c() in libwine.so.1 (0x00000000)
>  45 0xf752975b wine_switch_to_stack+0x2a(func=0x7bc53dd0, arg=0x7b860530, stack=0x330000) [/home/andrei/x/wine/libs/wine/port.c:59] in libwine.so.1 (0xff80a198)
>  46 0x7bc59939 LdrInitializeThunk+0x238(kernel_start=<couldn't compute location>, unknown2=<couldn't compute location>, unknown3=<couldn't compute location>, unknown4=<couldn't compute location>) [/home/andrei/x/wine/dlls/ntdll/loader.c:2910] in ntdll (0xff80a1d8)
>  47 0x7b866db3 __wine_kernel_init+0xa12() [/home/andrei/x/wine/dlls/kernel32/process.c:1269] in kernel32 (0xff80b2f8)
>  48 0x7bc5a863 __wine_process_init+0x192() [/home/andrei/x/wine/dlls/ntdll/loader.c:3119] in ntdll (0xff80b388)
>  49 0xf7526e18 wine_init+0x2c7(argc=0x3, argv=0xff80b8d4, error="", error_size=0x400) [/home/andrei/x/wine/libs/wine/loader.c:958] in libwine.so.1 (0xff80b3e8)
>  50 0x7bf00d5c main+0x8b(argc=<is not available>, argv=<is not available>) [/home/andrei/x/wine/loader/main.c:237] in <wine-loader> (0xff80b838)
>  51 0xf7331443 __libc_start_main+0xf2() in libc.so.6 (0x00000000)
>0x7aad3d1f _ZNK4llvm17AMDGPUMCInstLower5lowerEPKNS_12MachineInstrERNS_6MCInstE+0xef in libllvm-3.6svn.so: fstpl	0xffffffb0(%ebp)
>Modules:
>Module	Address			Debug info	Name (76 modules)
>ELF	7a3d0000-7b7ff000	Dwarf           libllvm-3.6svn.so
>ELF	7b800000-7ba5f000	Dwarf           kernel32<elf>
>  \-PE	7b810000-7ba5f000	\               kernel32
>ELF	7bc00000-7bce4000	Dwarf           ntdll<elf>
>  \-PE	7bc10000-7bce4000	\               ntdll
>ELF	7bf00000-7bf04000	Dwarf           <wine-loader>
>ELF	7cb20000-7cb45000	Deferred        imm32<elf>
>  \-PE	7cb30000-7cb45000	\               imm32
>ELF	7d5f0000-7de0f000	Dwarf           radeonsi_dri.so
>ELF	7dee0000-7dee6000	Deferred        libtxc_dxtn.so
>ELF	7dee8000-7df36000	Deferred        libncurses.so.5
>ELF	7df38000-7df40000	Deferred        libffi.so.6
>ELF	7df40000-7df5b000	Deferred        libgcc_s.so.1
>ELF	7e050000-7e05f000	Deferred        libdrm_radeon.so.1
>ELF	7e060000-7e079000	Deferred        libelf.so.1
>ELF	7e080000-7e089000	Deferred        librt.so.1
>ELF	7e090000-7e0a6000	Deferred        libudev.so.1
>ELF	7e0a8000-7e0b5000	Deferred        libdrm.so.2
>ELF	7e0b8000-7e0bb000	Deferred        libxshmfence.so.1
>ELF	7e0c0000-7e0c6000	Deferred        libxcb-sync.so.1
>ELF	7e0c8000-7e0cb000	Deferred        libxcb-present.so.0
>ELF	7e0d0000-7e0d3000	Deferred        libxcb-dri3.so.0
>ELF	7e0d8000-7e0ef000	Deferred        libxcb-glx.so.0
>ELF	7e0f0000-7e182000	Dwarf           libgl.so.1
>ELF	7e1c8000-7e1ce000	Deferred        libxfixes.so.3
>ELF	7e1d0000-7e1db000	Deferred        libxcursor.so.1
>ELF	7e1e0000-7e1f1000	Deferred        libxi.so.6
>ELF	7e1f8000-7e1fc000	Deferred        libxcomposite.so.1
>ELF	7e200000-7e20b000	Deferred        libxrandr.so.2
>ELF	7e210000-7e21b000	Deferred        libxrender.so.1
>ELF	7e220000-7e227000	Deferred        libxxf86vm.so.1
>ELF	7e228000-7e22c000	Deferred        libxinerama.so.1
>ELF	7e230000-7e251000	Deferred        libxcb.so.1
>ELF	7e258000-7e390000	Deferred        libx11.so.6
>ELF	7e390000-7e3a3000	Deferred        libxext.so.6
>ELF	7e3a8000-7e3ad000	Deferred        libxcb-dri2.so.0
>ELF	7e3b0000-7e3b2000	Deferred        libx11-xcb.so.1
>ELF	7e3b8000-7e3bc000	Deferred        libxdamage.so.1
>ELF	7e3c0000-7e3d9000	Deferred        libglapi.so.0
>ELF	7e3e8000-7e47c000	Dwarf           winex11<elf>
>  \-PE	7e3f0000-7e47c000	\               winex11
>ELF	7e480000-7e4a8000	Deferred        libexpat.so.1
>ELF	7e4a8000-7e4e3000	Deferred        libfontconfig.so.1
>ELF	7e4e8000-7e520000	Deferred        libpng16.so.16
>ELF	7e520000-7e531000	Deferred        libbz2.so.1
>ELF	7e538000-7e54e000	Deferred        libz.so.1
>ELF	7e550000-7e5f1000	Deferred        libfreetype.so.6
>ELF	7e5f8000-7e5ff000	Deferred        libxdmcp.so.6
>ELF	7e600000-7e604000	Deferred        libxau.so.6
>ELF	7e638000-7e652000	Deferred        version<elf>
>  \-PE	7e640000-7e652000	\               version
>ELF	7e658000-7e7b4000	Deferred        user32<elf>
>  \-PE	7e670000-7e7b4000	\               user32
>ELF	7e7b8000-7e82b000	Deferred        advapi32<elf>
>  \-PE	7e7c0000-7e82b000	\               advapi32
>ELF	7e830000-7e948000	Deferred        gdi32<elf>
>  \-PE	7e840000-7e948000	\               gdi32
>ELF	7e948000-7ea57000	Dwarf           opengl32<elf>
>  \-PE	7e960000-7ea57000	\               opengl32
>ELF	7ea58000-7eb98000	Dwarf           wined3d<elf>
>  \-PE	7ea70000-7eb98000	\               wined3d
>ELF	7eb98000-7ebfa000	Dwarf           d3d8_test<elf>
>  \-PE	7eba0000-7ebfa000	\               d3d8_test
>ELF	7ef70000-7ef7d000	Deferred        libnss_files.so.2
>ELF	7ef80000-7ef8c000	Deferred        libnss_nis.so.2
>ELF	7ef90000-7efa9000	Deferred        libnsl.so.1
>ELF	7efb0000-7efb9000	Deferred        libnss_compat.so.2
>ELF	7efc8000-7effc000	Dwarf           d3d8<elf>
>  \-PE	7efd0000-7effc000	\               d3d8
>ELF	f72c8000-f730d000	Deferred        libm.so.6
>ELF	f7310000-f7314000	Deferred        libdl.so.2
>ELF	f7318000-f74bb000	Dwarf           libc.so.6
>ELF	f74c0000-f74db000	Deferred        libpthread.so.0
>ELF	f7520000-f76d6000	Dwarf           libwine.so.1
>ELF	f76d8000-f76fa000	Deferred        ld-linux.so.2
>ELF	f7701000-f7702000	Deferred        [vdso].so
>Threads:
>process  tid      prio (all id:s are in hex)
>00000008 (D) Z:\home\andrei\x\wine\dlls\d3d8\tests\d3d8_test.exe
>	00000009    0 <==
>0000000e services.exe
>	0000001f    0
>	0000001e    0
>	00000016    0
>	00000014    0
>	00000010    0
>	0000000f    0
>00000012 winedevice.exe
>	0000001b    0
>	00000018    0
>	00000017    0
>	00000013    0
>00000019 plugplay.exe
>	00000021    0
>	00000020    0
>	0000001a    0
>0000001c explorer.exe
>	0000001d    0
>Makefile:159: recipe for target 'device.ok' failed
>make[1]: *** [device.ok] Error 141
>make[1]: Leaving directory '/home/andrei/x/wine/dlls/d3d8/tests'
>Makefile:3648: recipe for target 'dlls/d3d8/tests/test' failed
>make: *** [dlls/d3d8/tests/test] Error 2

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