Attachment 106831 Details for Bug 84310 – dmesg

dmesg

xrandr_rotation_left.dmesg (text/plain), 123.82 KB, created by Guo Jinxian on 2014-09-25 06:48:19 UTC

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Creator: Guo Jinxian

Created: 2014-09-25 06:48:19 UTC

Size: 123.82 KB

patch

obsolete

>[   60.188327] [drm:drm_mode_debug_printmodeline] Modeline 44:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[   60.188329] [drm:drm_mode_debug_printmodeline] Modeline 47:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   60.188332] [drm:drm_mode_debug_printmodeline] Modeline 42:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   60.188334] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   60.188336] [drm:drm_mode_debug_printmodeline] Modeline 70:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[   60.188339] [drm:drm_mode_debug_printmodeline] Modeline 55:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   60.188341] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   60.188344] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   60.188346] [drm:drm_mode_debug_printmodeline] Modeline 50:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   60.188348] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[   60.188351] [drm:drm_mode_debug_printmodeline] Modeline 76:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[   60.188353] [drm:drm_mode_debug_printmodeline] Modeline 43:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[   60.188355] [drm:drm_mode_debug_printmodeline] Modeline 51:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   60.188357] [drm:drm_mode_debug_printmodeline] Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   60.188360] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   60.188362] [drm:drm_mode_debug_printmodeline] Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   60.188366] [drm:drm_mode_getconnector] [CONNECTOR:28:?]
>[   60.188390] [drm:add_framebuffer_internal] [FB:99]
>[   60.241547] [drm:drm_mode_setcrtc] [CRTC:12]
>[   60.241554] [drm:drm_mode_setcrtc] [CONNECTOR:28:DP-1]
>[   60.241557] [drm:intel_crtc_set_config] [CRTC:12] [FB:99] #connectors=1 (x y) (0 0)
>[   60.241562] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   60.241565] [drm:drm_mode_debug_printmodeline] Modeline 96:"3840x2160" 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
>[   60.241569] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 59 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x0
>[   60.241571] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=1, fb_changed=1
>[   60.241574] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[   60.241576] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[   60.241578] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[   60.241582] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   60.241586] [drm:connected_sink_compute_bpp] [CONNECTOR:28:DP-1] checking for sink bpp constrains
>[   60.241589] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 0a pixel clock 63500KHz
>[   60.241597] [drm:intel_dp_compute_config] DP link bw 06 lane count 2 clock 162000 bpp 24
>[   60.241599] [drm:intel_dp_compute_config] DP link bw required 152400 available 259200
>[   60.241601] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   60.241604] [drm:intel_dump_pipe_config] [CRTC:12][modeset] config for pipe B
>[   60.241605] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   60.241607] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   60.241609] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   60.241612] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2466095, gmch_n: 4194304, link_m: 102753, link_n: 262144, tu: 64
>[   60.241614] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   60.241615] [drm:intel_dump_pipe_config] requested mode:
>[   60.241619] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 59 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x0
>[   60.241620] [drm:intel_dump_pipe_config] adjusted mode:
>[   60.241623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 59 63500 1024 1072 1176 1328 768 771 775 798 0x0 0xa
>[   60.241626] [drm:intel_dump_crtc_timings] crtc timings: 63500 1024 1072 1176 1328 768 771 775 798, type: 0x0 flags: 0xa
>[   60.241627] [drm:intel_dump_pipe_config] port clock: 162000
>[   60.241629] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[   60.241631] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   60.241633] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   60.241635] [drm:intel_dump_pipe_config] ips: 0
>[   60.241636] [drm:intel_dump_pipe_config] double wide: 0
>[   60.264167] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.270946] [drm:drm_dp_dpcd_access] too many retries, giving up
>[   60.270947] [drm:intel_dp_start_link_train] *ERROR* failed to enable link training
>[   60.275600] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.282323] [drm:drm_dp_dpcd_access] too many retries, giving up
>[   60.282324] [drm:intel_dp_complete_link_train] *ERROR* failed to update link training
>[   60.284470] [drm:ironlake_update_primary_plane] Writing base 00312000 00000000 0 0 4096
>[   60.301210] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1]
>[   60.301213] [drm:intel_connector_check_state] [CONNECTOR:28:DP-1]
>[   60.301217] [drm:intel_connector_check_state] [CONNECTOR:35:HDMI-A-2]
>[   60.301219] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[   60.301225] [drm:check_encoder_state] [ENCODER:27:TMDS-27]
>[   60.301229] [drm:check_encoder_state] [ENCODER:29:DP MST-29]
>[   60.301230] [drm:check_encoder_state] [ENCODER:30:DP MST-30]
>[   60.301232] [drm:check_encoder_state] [ENCODER:31:DP MST-31]
>[   60.301236] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[   60.301241] [drm:check_crtc_state] [CRTC:8]
>[   60.301248] [drm:check_crtc_state] [CRTC:12]
>[   60.301255] [drm:check_crtc_state] [CRTC:16]
>[   60.301261] [drm:check_shared_dpll_state] WRPLL 1
>[   60.301263] [drm:check_shared_dpll_state] WRPLL 2
>[   60.301272] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[   60.301277] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[   60.301280] [drm:drm_mode_getconnector] [CONNECTOR:32:?]
>[   60.301283] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1]
>[   60.301284] [drm:intel_hdmi_detect] [CONNECTOR:32:HDMI-A-1]
>[   60.301442] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[   60.301444] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[   60.301446] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] disconnected
>[   60.301449] [drm:drm_mode_getconnector] [CONNECTOR:32:?]
>[   60.301450] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1]
>[   60.301452] [drm:intel_hdmi_detect] [CONNECTOR:32:HDMI-A-1]
>[   60.301609] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[   60.301610] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[   60.301612] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] disconnected
>[   60.301616] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[   60.301619] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[   60.301621] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   60.301623] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2]
>[   60.301627] [drm:intel_hdmi_detect] [CONNECTOR:35:HDMI-A-2]
>[   60.326531] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[   60.326607] [drm:drm_edid_to_eld] ELD monitor ASUS PA238
>[   60.326610] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0
>[   60.326611] [drm:drm_edid_to_eld] ELD size 9, SAD count 1
>[   60.326674] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] probed modes :
>[   60.326677] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   60.326679] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   60.326682] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   60.326685] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   60.326687] [drm:drm_mode_debug_printmodeline] Modeline 107:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   60.326689] [drm:drm_mode_debug_printmodeline] Modeline 101:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[   60.326692] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   60.326694] [drm:drm_mode_debug_printmodeline] Modeline 125:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   60.326696] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   60.326699] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   60.326701] [drm:drm_mode_debug_printmodeline] Modeline 124:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   60.326704] [drm:drm_mode_debug_printmodeline] Modeline 66:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   60.326706] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   60.326708] [drm:drm_mode_debug_printmodeline] Modeline 69:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   60.326711] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   60.326713] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[   60.326715] [drm:drm_mode_debug_printmodeline] Modeline 79:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   60.326718] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   60.326720] [drm:drm_mode_debug_printmodeline] Modeline 114:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   60.326722] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[   60.326725] [drm:drm_mode_debug_printmodeline] Modeline 105:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[   60.326727] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   60.326730] [drm:drm_mode_debug_printmodeline] Modeline 89:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   60.326732] [drm:drm_mode_debug_printmodeline] Modeline 90:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   60.326734] [drm:drm_mode_debug_printmodeline] Modeline 121:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[   60.326737] [drm:drm_mode_debug_printmodeline] Modeline 103:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[   60.326739] [drm:drm_mode_debug_printmodeline] Modeline 91:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[   60.326741] [drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   60.326744] [drm:drm_mode_debug_printmodeline] Modeline 93:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   60.326746] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   60.326748] [drm:drm_mode_debug_printmodeline] Modeline 81:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[   60.326751] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[   60.326753] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[   60.326755] [drm:drm_mode_debug_printmodeline] Modeline 61:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[   60.326757] [drm:drm_mode_debug_printmodeline] Modeline 82:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   60.326760] [drm:drm_mode_debug_printmodeline] Modeline 83:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[   60.326762] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   60.326764] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   60.326767] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   60.326771] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   60.326796] [drm:add_framebuffer_internal] [FB:100]
>[   60.388119] [drm:drm_mode_setcrtc] [CRTC:16]
>[   60.388125] [drm:drm_mode_setcrtc] [CONNECTOR:35:HDMI-A-2]
>[   60.388129] [drm:intel_crtc_set_config] [CRTC:16] [FB:100] #connectors=1 (x y) (0 0)
>[   60.388132] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   60.388136] [drm:drm_mode_debug_printmodeline] Modeline 97:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   60.388139] [drm:drm_mode_debug_printmodeline] Modeline 104:"1024x768" 59 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x0
>[   60.388141] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=1, fb_changed=1
>[   60.388144] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[   60.388146] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[   60.388148] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[   60.388151] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[   60.388154] [drm:connected_sink_compute_bpp] [CONNECTOR:35:HDMI-A-2] checking for sink bpp constrains
>[   60.388160] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[   60.388162] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[   60.388164] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   60.388166] [drm:intel_dump_pipe_config] [CRTC:16][modeset] config for pipe C
>[   60.388168] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   60.388170] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   60.388172] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   60.388174] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   60.388176] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   60.388178] [drm:intel_dump_pipe_config] requested mode:
>[   60.388181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 59 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x0
>[   60.388183] [drm:intel_dump_pipe_config] adjusted mode:
>[   60.388186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 59 63500 1024 1072 1176 1328 768 771 775 798 0x0 0xa
>[   60.388189] [drm:intel_dump_crtc_timings] crtc timings: 63500 1024 1072 1176 1328 768 771 775 798, type: 0x0 flags: 0xa
>[   60.388190] [drm:intel_dump_pipe_config] port clock: 63500
>[   60.388192] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[   60.388194] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   60.388196] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   60.388198] [drm:intel_dump_pipe_config] ips: 0
>[   60.388199] [drm:intel_dump_pipe_config] double wide: 0
>[   60.391283] [drm:intel_disable_shared_dpll] disable WRPLL 1 (active 1, on? 1) for crtc 16
>[   60.391286] [drm:intel_disable_shared_dpll] disabling WRPLL 1
>[   60.394209] [drm:intel_get_shared_dpll] CRTC:16 allocated WRPLL 1
>[   60.394211] [drm:intel_get_shared_dpll] using WRPLL 1 for pipe C
>[   60.394213] [drm:intel_enable_shared_dpll] enable WRPLL 1 (active 0, on? 0) for crtc 16
>[   60.394215] [drm:intel_enable_shared_dpll] enabling WRPLL 1
>[   60.394246] [drm:intel_ddi_pre_enable] Audio on pipe C on DDI
>[   60.394247] [drm:intel_ddi_pre_enable] DDI audio: write eld information
>[   60.394249] [drm:intel_write_eld] ELD on [CONNECTOR:35:HDMI-A-2], [ENCODER:34:TMDS-34]
>[   60.394251] [drm:haswell_write_eld] HDMI audio: enable codec
>[   60.394254] [drm:haswell_write_eld] HDMI audio: pin eld vld status=0x00000400
>[   60.394256] [drm:haswell_write_eld] HDMI audio: eld vld status=0x00000500
>[   60.394257] [drm:haswell_write_eld] HDMI audio: audio conf: 0x0079fa60
>[   60.394259] [drm:haswell_write_eld] ELD on pipe C
>[   60.394261] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 63500 not found, falling back to defaults
>[   60.394262] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[   60.394376] [drm:ironlake_update_primary_plane] Writing base 02825000 00000000 0 0 4096
>[   60.411088] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1]
>[   60.411091] [drm:intel_connector_check_state] [CONNECTOR:28:DP-1]
>[   60.411095] [drm:intel_connector_check_state] [CONNECTOR:35:HDMI-A-2]
>[   60.411097] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[   60.411100] [drm:check_encoder_state] [ENCODER:27:TMDS-27]
>[   60.411102] [drm:check_encoder_state] [ENCODER:29:DP MST-29]
>[   60.411104] [drm:check_encoder_state] [ENCODER:30:DP MST-30]
>[   60.411105] [drm:check_encoder_state] [ENCODER:31:DP MST-31]
>[   60.411106] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[   60.411108] [drm:check_crtc_state] [CRTC:8]
>[   60.411115] [drm:check_crtc_state] [CRTC:12]
>[   60.411122] [drm:check_crtc_state] [CRTC:16]
>[   60.411128] [drm:check_shared_dpll_state] WRPLL 1
>[   60.411129] [drm:check_shared_dpll_state] WRPLL 2
>[   62.230224] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[   62.230231] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[   76.818078] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[   76.818080] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   76.818083] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 59 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x0
>[   76.818085] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   76.818086] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=1
>[   76.818088] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[   76.818089] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[   76.818090] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[   76.818092] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[   76.818094] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains
>[   76.818096] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   76.818101] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   76.818102] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   76.818104] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   76.818105] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
>[   76.818105] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   76.818106] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   76.818108] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   76.818109] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   76.818110] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   76.818111] [drm:intel_dump_pipe_config] requested mode:
>[   76.818113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   76.818114] [drm:intel_dump_pipe_config] adjusted mode:
>[   76.818115] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   76.818117] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   76.818118] [drm:intel_dump_pipe_config] port clock: 270000
>[   76.818119] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   76.818120] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   76.818121] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   76.818121] [drm:intel_dump_pipe_config] ips: 1
>[   76.818122] [drm:intel_dump_pipe_config] double wide: 0
>[   76.832262] [drm:intel_edp_backlight_off] 
>[   77.032852] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   77.050862] [drm:edp_panel_vdd_on] Turning eDP VDD on
>[   77.050868] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   77.051018] [drm:intel_edp_panel_off] Turn eDP power off
>[   77.051021] [drm:wait_panel_off] Wait for panel power off time
>[   77.051023] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   77.105885] [drm:wait_panel_status] Wait complete
>[   77.105909] [drm:intel_edp_panel_on] Turn eDP power on
>[   77.105912] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   77.652172] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000
>[   77.685184] [drm:wait_panel_status] Wait complete
>[   77.685187] [drm:wait_panel_on] Wait for panel power on
>[   77.685189] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   77.894291] [drm:wait_panel_status] Wait complete
>[   77.894294] [drm:edp_panel_vdd_on] Turning eDP VDD on
>[   77.894299] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   77.895355] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   77.895803] [drm:intel_dp_start_link_train] clock recovery OK
>[   77.896549] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   77.896783] [drm:intel_edp_backlight_on] 
>[   77.896784] [drm:intel_panel_enable_backlight] pipe A
>[   77.896790] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   77.896794] [drm:intel_edp_psr_enable] PSR not supported by this panel
>[   77.896798] [drm:ironlake_update_primary_plane] Writing base 00881000 00000000 0 0 15360
>[   77.931312] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1]
>[   77.931314] [drm:intel_connector_check_state] [CONNECTOR:28:DP-1]
>[   77.931318] [drm:intel_connector_check_state] [CONNECTOR:35:HDMI-A-2]
>[   77.931319] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[   77.931321] [drm:check_encoder_state] [ENCODER:27:TMDS-27]
>[   77.931322] [drm:check_encoder_state] [ENCODER:29:DP MST-29]
>[   77.931323] [drm:check_encoder_state] [ENCODER:30:DP MST-30]
>[   77.931324] [drm:check_encoder_state] [ENCODER:31:DP MST-31]
>[   77.931324] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[   77.931326] [drm:check_crtc_state] [CRTC:8]
>[   77.931332] [drm:check_crtc_state] [CRTC:12]
>[   77.931337] [drm:check_crtc_state] [CRTC:16]
>[   77.931343] [drm:check_shared_dpll_state] WRPLL 1
>[   77.931344] [drm:check_shared_dpll_state] WRPLL 2
>[   77.931347] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[   77.931348] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   77.931350] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 59 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x0
>[   77.931353] [drm:drm_mode_debug_printmodeline] Modeline 96:"3840x2160" 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
>[   77.931354] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=1, fb_changed=1
>[   77.931355] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[   77.931356] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[   77.931357] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[   77.931359] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   77.931360] [drm:connected_sink_compute_bpp] [CONNECTOR:28:DP-1] checking for sink bpp constrains
>[   77.931362] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 0a pixel clock 262750KHz
>[   77.931366] [drm:intel_dp_compute_config] DP link bw 0a lane count 4 clock 270000 bpp 24
>[   77.931367] [drm:intel_dp_compute_config] DP link bw required 630600 available 864000
>[   77.931368] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   77.931369] [drm:intel_dump_pipe_config] [CRTC:12][modeset] config for pipe B
>[   77.931370] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   77.931371] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   77.931372] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   77.931374] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6122518, gmch_n: 8388608, link_m: 510209, link_n: 524288, tu: 64
>[   77.931375] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   77.931376] [drm:intel_dump_pipe_config] requested mode:
>[   77.931378] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
>[   77.931379] [drm:intel_dump_pipe_config] adjusted mode:
>[   77.931381] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
>[   77.931383] [drm:intel_dump_crtc_timings] crtc timings: 262750 3840 3888 3920 4000 2160 2163 2168 2191, type: 0x48 flags: 0x9
>[   77.931383] [drm:intel_dump_pipe_config] port clock: 270000
>[   77.931384] [drm:intel_dump_pipe_config] pipe src size: 3840x2160
>[   77.931385] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   77.931386] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   77.931387] [drm:intel_dump_pipe_config] ips: 0
>[   77.931388] [drm:intel_dump_pipe_config] double wide: 0
>[   77.936597] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   77.943492] [drm:drm_dp_dpcd_access] too many retries, giving up
>[   77.943493] [drm:intel_dp_start_link_train] *ERROR* failed to enable link training
>[   77.946257] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   77.954321] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   77.954573] [drm:ironlake_update_primary_plane] Writing base 00881000 00000000 0 0 15360
>[   77.987981] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1]
>[   77.987982] [drm:intel_connector_check_state] [CONNECTOR:28:DP-1]
>[   77.987986] [drm:intel_connector_check_state] [CONNECTOR:35:HDMI-A-2]
>[   77.987987] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[   77.987988] [drm:check_encoder_state] [ENCODER:27:TMDS-27]
>[   77.987990] [drm:check_encoder_state] [ENCODER:29:DP MST-29]
>[   77.987991] [drm:check_encoder_state] [ENCODER:30:DP MST-30]
>[   77.987992] [drm:check_encoder_state] [ENCODER:31:DP MST-31]
>[   77.987992] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[   77.987994] [drm:check_crtc_state] [CRTC:8]
>[   77.987999] [drm:check_crtc_state] [CRTC:12]
>[   77.988005] [drm:check_crtc_state] [CRTC:16]
>[   77.988010] [drm:check_shared_dpll_state] WRPLL 1
>[   77.988010] [drm:check_shared_dpll_state] WRPLL 2
>[   77.988013] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[   77.988014] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   77.988016] [drm:drm_mode_debug_printmodeline] Modeline 104:"1024x768" 59 63500 1024 1072 1176 1328 768 771 775 798 0x0 0x0
>[   77.988018] [drm:drm_mode_debug_printmodeline] Modeline 97:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   77.988019] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=1, fb_changed=1
>[   77.988020] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[   77.988021] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[   77.988022] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[   77.988023] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[   77.988025] [drm:connected_sink_compute_bpp] [CONNECTOR:35:HDMI-A-2] checking for sink bpp constrains
>[   77.988027] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[   77.988027] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[   77.988029] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   77.988029] [drm:intel_dump_pipe_config] [CRTC:16][modeset] config for pipe C
>[   77.988030] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   77.988031] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   77.988032] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   77.988033] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   77.988035] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   77.988035] [drm:intel_dump_pipe_config] requested mode:
>[   77.988037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   77.988037] [drm:intel_dump_pipe_config] adjusted mode:
>[   77.988039] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   77.988041] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   77.988041] [drm:intel_dump_pipe_config] port clock: 148500
>[   77.988042] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   77.988043] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   77.988044] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   77.988045] [drm:intel_dump_pipe_config] ips: 0
>[   77.988045] [drm:intel_dump_pipe_config] double wide: 0
>[   78.003355] [drm:intel_disable_shared_dpll] disable WRPLL 1 (active 1, on? 1) for crtc 16
>[   78.003355] [drm:intel_disable_shared_dpll] disabling WRPLL 1
>[   78.004638] [drm:intel_get_shared_dpll] CRTC:16 allocated WRPLL 1
>[   78.004638] [drm:intel_get_shared_dpll] using WRPLL 1 for pipe C
>[   78.004640] [drm:intel_enable_shared_dpll] enable WRPLL 1 (active 0, on? 0) for crtc 16
>[   78.004641] [drm:intel_enable_shared_dpll] enabling WRPLL 1
>[   78.004670] [drm:intel_ddi_pre_enable] Audio on pipe C on DDI
>[   78.004671] [drm:intel_ddi_pre_enable] DDI audio: write eld information
>[   78.004672] [drm:intel_write_eld] ELD on [CONNECTOR:35:HDMI-A-2], [ENCODER:34:TMDS-34]
>[   78.004673] [drm:haswell_write_eld] HDMI audio: enable codec
>[   78.004675] [drm:haswell_write_eld] HDMI audio: pin eld vld status=0x00000400
>[   78.004676] [drm:haswell_write_eld] HDMI audio: eld vld status=0x00000500
>[   78.004677] [drm:haswell_write_eld] HDMI audio: audio conf: 0x0071fa60
>[   78.004679] [drm:haswell_write_eld] ELD on pipe C
>[   78.004680] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[   78.004790] [drm:ironlake_update_primary_plane] Writing base 00881000 00000000 0 0 15360
>[   78.021487] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1]
>[   78.021489] [drm:intel_connector_check_state] [CONNECTOR:28:DP-1]
>[   78.021492] [drm:intel_connector_check_state] [CONNECTOR:35:HDMI-A-2]
>[   78.021494] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[   78.021495] [drm:check_encoder_state] [ENCODER:27:TMDS-27]
>[   78.021498] [drm:check_encoder_state] [ENCODER:29:DP MST-29]
>[   78.021498] [drm:check_encoder_state] [ENCODER:30:DP MST-30]
>[   78.021499] [drm:check_encoder_state] [ENCODER:31:DP MST-31]
>[   78.021500] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[   78.021501] [drm:check_crtc_state] [CRTC:8]
>[   78.021506] [drm:check_crtc_state] [CRTC:12]
>[   78.021511] [drm:check_crtc_state] [CRTC:16]
>[   78.021516] [drm:check_shared_dpll_state] WRPLL 1
>[   78.021516] [drm:check_shared_dpll_state] WRPLL 2
>[   78.030571] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[   78.030576] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[   78.030578] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[   78.030580] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[   78.030581] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[   78.030584] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[   78.030586] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
>[   78.030588] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[   78.030589] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[   78.030591] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[   78.030593] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[   78.030595] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0
>[   78.030596] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[   78.030598] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[   78.030599] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[   80.063413] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[   80.063420] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[   88.172216] [drm:i915_gem_open] 
>[   88.172435] [drm:i915_gem_open] 
>[   88.172599] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[   88.172605] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[   88.172611] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[   88.172614] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[   88.172617] [drm:drm_mode_getconnector] [CONNECTOR:19:?]
>[   88.172620] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:19:eDP-1]
>[   88.172622] [drm:intel_dp_detect] [CONNECTOR:19:eDP-1]
>[   88.172633] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   88.172637] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:19:eDP-1] probed modes :
>[   88.172640] [drm:drm_mode_debug_printmodeline] Modeline 20:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   88.172642] [drm:drm_mode_debug_printmodeline] Modeline 21:"1920x1080" 40 92520 1920 1966 1996 2080 1080 1082 1086 1112 0x40 0xa
>[   88.172645] [drm:drm_mode_getconnector] [CONNECTOR:19:?]
>[   88.172660] [drm:add_framebuffer_internal] [FB:59]
>[   88.195115] [drm:drm_mode_setcrtc] [CRTC:8]
>[   88.195121] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1]
>[   88.195124] [drm:intel_crtc_set_config] [CRTC:8] [FB:59] #connectors=1 (x y) (0 0)
>[   88.195127] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   88.195130] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   88.195133] [drm:drm_mode_debug_printmodeline] Modeline 99:"800x600" 59 38250 800 832 912 1024 600 603 607 624 0x0 0x0
>[   88.195135] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=1
>[   88.195138] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[   88.195139] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[   88.195141] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[   88.195144] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[   88.195146] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains
>[   88.195150] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   88.195156] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   88.195157] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   88.195160] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   88.195162] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
>[   88.195163] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   88.195165] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   88.195167] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   88.195169] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   88.195171] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   88.195172] [drm:intel_dump_pipe_config] requested mode:
>[   88.195175] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 59 38250 800 832 912 1024 600 603 607 624 0x0 0x0
>[   88.195176] [drm:intel_dump_pipe_config] adjusted mode:
>[   88.195179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   88.195181] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   88.195183] [drm:intel_dump_pipe_config] port clock: 270000
>[   88.195184] [drm:intel_dump_pipe_config] pipe src size: 800x600
>[   88.195186] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   88.195188] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00f00000, size: 0x05a00438, enabled
>[   88.195189] [drm:intel_dump_pipe_config] ips: 1
>[   88.195190] [drm:intel_dump_pipe_config] double wide: 0
>[   88.201888] [drm:intel_edp_backlight_off] 
>[   88.402706] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   88.418719] [drm:edp_panel_vdd_on] Turning eDP VDD on
>[   88.418726] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   88.418879] [drm:intel_edp_panel_off] Turn eDP power off
>[   88.418884] [drm:wait_panel_off] Wait for panel power off time
>[   88.418887] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   88.473742] [drm:wait_panel_status] Wait complete
>[   88.474565] [drm:intel_edp_panel_on] Turn eDP power on
>[   88.474569] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   89.020034] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[   89.020038] [drm:wait_panel_status] Wait complete
>[   89.020047] [drm:wait_panel_on] Wait for panel power on
>[   89.020050] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control abcd0003
>[   89.229132] [drm:wait_panel_status] Wait complete
>[   89.229139] [drm:edp_panel_vdd_on] Turning eDP VDD on
>[   89.229146] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   89.230207] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   89.230655] [drm:intel_dp_start_link_train] clock recovery OK
>[   89.231406] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   89.231643] [drm:intel_edp_backlight_on] 
>[   89.231644] [drm:intel_panel_enable_backlight] pipe A
>[   89.231651] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   89.231657] [drm:intel_edp_psr_enable] PSR not supported by this panel
>[   89.231662] [drm:ironlake_update_primary_plane] Writing base 02838000 00000000 0 0 3200
>[   89.266153] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1]
>[   89.266156] [drm:intel_connector_check_state] [CONNECTOR:28:DP-1]
>[   89.266160] [drm:intel_connector_check_state] [CONNECTOR:35:HDMI-A-2]
>[   89.266163] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[   89.266164] [drm:check_encoder_state] [ENCODER:27:TMDS-27]
>[   89.266166] [drm:check_encoder_state] [ENCODER:29:DP MST-29]
>[   89.266168] [drm:check_encoder_state] [ENCODER:30:DP MST-30]
>[   89.266169] [drm:check_encoder_state] [ENCODER:31:DP MST-31]
>[   89.266170] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[   89.266173] [drm:check_crtc_state] [CRTC:8]
>[   89.266180] [drm:check_crtc_state] [CRTC:12]
>[   89.266186] [drm:check_crtc_state] [CRTC:16]
>[   89.266192] [drm:check_shared_dpll_state] WRPLL 1
>[   89.266194] [drm:check_shared_dpll_state] WRPLL 2
>[   89.266204] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[   89.266207] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[   89.266210] [drm:drm_mode_getconnector] [CONNECTOR:28:?]
>[   89.266213] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1]
>[   89.266216] [drm:intel_dp_detect] [CONNECTOR:28:DP-1]
>[   89.266491] [drm:intel_dp_get_dpcd] DPCD: 11 0a a4 01 01 00 01 81 00 00 00 00 00 00 00
>[   89.266668] [drm:intel_dp_probe_oui] Sink OUI: 0080e1
>[   89.266843] [drm:intel_dp_probe_oui] Branch OUI: 0080e1
>[   89.329275] [drm:drm_edid_to_eld] ELD monitor DELL UP3214Q
>[   89.329277] [drm:drm_edid_to_eld] ELD size 8, SAD count 0
>[   89.329312] [drm:drm_mode_debug_printmodeline] Modeline 139:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[   89.329314] [drm:drm_mode_prune_invalid] Not using 720x480i mode 3
>[   89.329317] [drm:drm_mode_debug_printmodeline] Modeline 140:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[   89.329318] [drm:drm_mode_prune_invalid] Not using 720x576i mode 3
>[   89.329320] [drm:drm_mode_debug_printmodeline] Modeline 159:"720x480i" 60 13513 720 739 801 858 480 488 494 525 0x40 0x101a
>[   89.329322] [drm:drm_mode_prune_invalid] Not using 720x480i mode 3
>[   89.329326] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1] probed modes :
>[   89.329329] [drm:drm_mode_debug_printmodeline] Modeline 38:"3840x2160" 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
>[   89.329331] [drm:drm_mode_debug_printmodeline] Modeline 39:"3840x2160" 30 300000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[   89.329333] [drm:drm_mode_debug_printmodeline] Modeline 46:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[   89.329336] [drm:drm_mode_debug_printmodeline] Modeline 40:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[   89.329338] [drm:drm_mode_debug_printmodeline] Modeline 58:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   89.329340] [drm:drm_mode_debug_printmodeline] Modeline 78:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   89.329343] [drm:drm_mode_debug_printmodeline] Modeline 41:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   89.329345] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   89.329348] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   89.329350] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[   89.329352] [drm:drm_mode_debug_printmodeline] Modeline 73:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   89.329355] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   89.329357] [drm:drm_mode_debug_printmodeline] Modeline 48:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   89.329360] [drm:drm_mode_debug_printmodeline] Modeline 45:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[   89.329362] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   89.329364] [drm:drm_mode_debug_printmodeline] Modeline 49:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   89.329366] [drm:drm_mode_debug_printmodeline] Modeline 44:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[   89.329369] [drm:drm_mode_debug_printmodeline] Modeline 47:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   89.329371] [drm:drm_mode_debug_printmodeline] Modeline 42:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   89.329374] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   89.329376] [drm:drm_mode_debug_printmodeline] Modeline 70:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[   89.329378] [drm:drm_mode_debug_printmodeline] Modeline 55:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   89.329381] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   89.329383] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   89.329385] [drm:drm_mode_debug_printmodeline] Modeline 50:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   89.329388] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[   89.329390] [drm:drm_mode_debug_printmodeline] Modeline 76:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[   89.329392] [drm:drm_mode_debug_printmodeline] Modeline 43:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[   89.329395] [drm:drm_mode_debug_printmodeline] Modeline 51:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   89.329397] [drm:drm_mode_debug_printmodeline] Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   89.329399] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   89.329402] [drm:drm_mode_debug_printmodeline] Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   89.329406] [drm:drm_mode_getconnector] [CONNECTOR:28:?]
>[   89.329430] [drm:add_framebuffer_internal] [FB:99]
>[   89.378916] [drm:drm_mode_setcrtc] [CRTC:12]
>[   89.378923] [drm:drm_mode_setcrtc] [CONNECTOR:28:DP-1]
>[   89.378926] [drm:intel_crtc_set_config] [CRTC:12] [FB:99] #connectors=1 (x y) (0 0)
>[   89.378929] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   89.378933] [drm:drm_mode_debug_printmodeline] Modeline 96:"3840x2160" 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
>[   89.378936] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 59 38250 800 832 912 1024 600 603 607 624 0x0 0x0
>[   89.378938] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=1, fb_changed=1
>[   89.378941] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[   89.378943] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[   89.378945] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[   89.378948] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   89.378950] [drm:connected_sink_compute_bpp] [CONNECTOR:28:DP-1] checking for sink bpp constrains
>[   89.378954] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 0a pixel clock 38250KHz
>[   89.378960] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 24
>[   89.378962] [drm:intel_dp_compute_config] DP link bw required 91800 available 129600
>[   89.378965] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   89.378967] [drm:intel_dump_pipe_config] [CRTC:12][modeset] config for pipe B
>[   89.378969] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   89.378971] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   89.378973] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   89.378975] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1485482, gmch_n: 2097152, link_m: 61895, link_n: 262144, tu: 64
>[   89.378978] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   89.378979] [drm:intel_dump_pipe_config] requested mode:
>[   89.378982] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 59 38250 800 832 912 1024 600 603 607 624 0x0 0x0
>[   89.378984] [drm:intel_dump_pipe_config] adjusted mode:
>[   89.378987] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 59 38250 800 832 912 1024 600 603 607 624 0x0 0xa
>[   89.378990] [drm:intel_dump_crtc_timings] crtc timings: 38250 800 832 912 1024 600 603 607 624, type: 0x0 flags: 0xa
>[   89.378991] [drm:intel_dump_pipe_config] port clock: 162000
>[   89.378993] [drm:intel_dump_pipe_config] pipe src size: 800x600
>[   89.378995] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   89.378997] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   89.378998] [drm:intel_dump_pipe_config] ips: 0
>[   89.379000] [drm:intel_dump_pipe_config] double wide: 0
>[   89.404567] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   89.405999] [drm:intel_dp_start_link_train] clock recovery OK
>[   89.408223] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   89.408476] [drm:ironlake_update_primary_plane] Writing base 02A0D000 00000000 0 0 3200
>[   89.425243] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1]
>[   89.425245] [drm:intel_connector_check_state] [CONNECTOR:28:DP-1]
>[   89.425249] [drm:intel_connector_check_state] [CONNECTOR:35:HDMI-A-2]
>[   89.425252] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[   89.425254] [drm:check_encoder_state] [ENCODER:27:TMDS-27]
>[   89.425256] [drm:check_encoder_state] [ENCODER:29:DP MST-29]
>[   89.425257] [drm:check_encoder_state] [ENCODER:30:DP MST-30]
>[   89.425259] [drm:check_encoder_state] [ENCODER:31:DP MST-31]
>[   89.425260] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[   89.425263] [drm:check_crtc_state] [CRTC:8]
>[   89.425270] [drm:check_crtc_state] [CRTC:12]
>[   89.425276] [drm:check_crtc_state] [CRTC:16]
>[   89.425283] [drm:check_shared_dpll_state] WRPLL 1
>[   89.425284] [drm:check_shared_dpll_state] WRPLL 2
>[   89.425292] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[   89.425295] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[   89.425299] [drm:drm_mode_getconnector] [CONNECTOR:32:?]
>[   89.425301] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1]
>[   89.425303] [drm:intel_hdmi_detect] [CONNECTOR:32:HDMI-A-1]
>[   89.425456] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[   89.425458] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[   89.425460] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] disconnected
>[   89.425462] [drm:drm_mode_getconnector] [CONNECTOR:32:?]
>[   89.425463] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1]
>[   89.425465] [drm:intel_hdmi_detect] [CONNECTOR:32:HDMI-A-1]
>[   89.425620] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[   89.425622] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[   89.425623] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] disconnected
>[   89.425627] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[   89.425630] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[   89.425633] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   89.425634] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2]
>[   89.425638] [drm:intel_hdmi_detect] [CONNECTOR:35:HDMI-A-2]
>[   89.450544] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[   89.450615] [drm:drm_edid_to_eld] ELD monitor ASUS PA238
>[   89.450618] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0
>[   89.450620] [drm:drm_edid_to_eld] ELD size 9, SAD count 1
>[   89.450681] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] probed modes :
>[   89.450684] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   89.450687] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   89.450689] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   89.450692] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   89.450694] [drm:drm_mode_debug_printmodeline] Modeline 107:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   89.450697] [drm:drm_mode_debug_printmodeline] Modeline 101:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[   89.450699] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   89.450701] [drm:drm_mode_debug_printmodeline] Modeline 125:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   89.450704] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   89.450706] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   89.450708] [drm:drm_mode_debug_printmodeline] Modeline 124:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   89.450711] [drm:drm_mode_debug_printmodeline] Modeline 66:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   89.450713] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   89.450715] [drm:drm_mode_debug_printmodeline] Modeline 69:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   89.450718] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   89.450720] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[   89.450723] [drm:drm_mode_debug_printmodeline] Modeline 79:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   89.450725] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   89.450727] [drm:drm_mode_debug_printmodeline] Modeline 114:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   89.450730] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[   89.450732] [drm:drm_mode_debug_printmodeline] Modeline 105:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[   89.450734] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   89.450737] [drm:drm_mode_debug_printmodeline] Modeline 89:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   89.450739] [drm:drm_mode_debug_printmodeline] Modeline 90:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   89.450741] [drm:drm_mode_debug_printmodeline] Modeline 121:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[   89.450744] [drm:drm_mode_debug_printmodeline] Modeline 103:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[   89.450746] [drm:drm_mode_debug_printmodeline] Modeline 91:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[   89.450749] [drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   89.450751] [drm:drm_mode_debug_printmodeline] Modeline 93:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   89.450753] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   89.450755] [drm:drm_mode_debug_printmodeline] Modeline 81:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[   89.450758] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[   89.450760] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[   89.450762] [drm:drm_mode_debug_printmodeline] Modeline 61:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[   89.450764] [drm:drm_mode_debug_printmodeline] Modeline 82:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   89.450767] [drm:drm_mode_debug_printmodeline] Modeline 83:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[   89.450769] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   89.450771] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   89.450774] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   89.450778] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[   89.450802] [drm:add_framebuffer_internal] [FB:100]
>[   89.502841] [drm:drm_mode_setcrtc] [CRTC:16]
>[   89.502846] [drm:drm_mode_setcrtc] [CONNECTOR:35:HDMI-A-2]
>[   89.502850] [drm:intel_crtc_set_config] [CRTC:16] [FB:100] #connectors=1 (x y) (0 0)
>[   89.502852] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   89.502856] [drm:drm_mode_debug_printmodeline] Modeline 97:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   89.502859] [drm:drm_mode_debug_printmodeline] Modeline 104:"800x600" 59 38250 800 832 912 1024 600 603 607 624 0x0 0x0
>[   89.502861] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=1, fb_changed=1
>[   89.502864] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[   89.502866] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[   89.502868] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[   89.502871] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[   89.502874] [drm:connected_sink_compute_bpp] [CONNECTOR:35:HDMI-A-2] checking for sink bpp constrains
>[   89.502879] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[   89.502881] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[   89.502883] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   89.502885] [drm:intel_dump_pipe_config] [CRTC:16][modeset] config for pipe C
>[   89.502887] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   89.502889] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   89.502891] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   89.502893] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   89.502895] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   89.502897] [drm:intel_dump_pipe_config] requested mode:
>[   89.502900] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 59 38250 800 832 912 1024 600 603 607 624 0x0 0x0
>[   89.502901] [drm:intel_dump_pipe_config] adjusted mode:
>[   89.502905] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 59 38250 800 832 912 1024 600 603 607 624 0x0 0xa
>[   89.502907] [drm:intel_dump_crtc_timings] crtc timings: 38250 800 832 912 1024 600 603 607 624, type: 0x0 flags: 0xa
>[   89.502909] [drm:intel_dump_pipe_config] port clock: 38250
>[   89.502911] [drm:intel_dump_pipe_config] pipe src size: 800x600
>[   89.502913] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   89.502915] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   89.502916] [drm:intel_dump_pipe_config] ips: 0
>[   89.502918] [drm:intel_dump_pipe_config] double wide: 0
>[   89.512286] [drm:intel_disable_shared_dpll] disable WRPLL 1 (active 1, on? 1) for crtc 16
>[   89.512289] [drm:intel_disable_shared_dpll] disabling WRPLL 1
>[   89.514632] [drm:intel_get_shared_dpll] CRTC:16 allocated WRPLL 1
>[   89.514634] [drm:intel_get_shared_dpll] using WRPLL 1 for pipe C
>[   89.514636] [drm:intel_enable_shared_dpll] enable WRPLL 1 (active 0, on? 0) for crtc 16
>[   89.514637] [drm:intel_enable_shared_dpll] enabling WRPLL 1
>[   89.514668] [drm:intel_ddi_pre_enable] Audio on pipe C on DDI
>[   89.514669] [drm:intel_ddi_pre_enable] DDI audio: write eld information
>[   89.514672] [drm:intel_write_eld] ELD on [CONNECTOR:35:HDMI-A-2], [ENCODER:34:TMDS-34]
>[   89.514673] [drm:haswell_write_eld] HDMI audio: enable codec
>[   89.514676] [drm:haswell_write_eld] HDMI audio: pin eld vld status=0x00000400
>[   89.514678] [drm:haswell_write_eld] HDMI audio: eld vld status=0x00000500
>[   89.514679] [drm:haswell_write_eld] HDMI audio: audio conf: 0x0079fa60
>[   89.514681] [drm:haswell_write_eld] ELD on pipe C
>[   89.514683] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 38250 not found, falling back to defaults
>[   89.514685] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[   89.514793] [drm:ironlake_update_primary_plane] Writing base 02BE2000 00000000 0 0 3200
>[   89.531530] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1]
>[   89.531533] [drm:intel_connector_check_state] [CONNECTOR:28:DP-1]
>[   89.531537] [drm:intel_connector_check_state] [CONNECTOR:35:HDMI-A-2]
>[   89.531539] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[   89.531541] [drm:check_encoder_state] [ENCODER:27:TMDS-27]
>[   89.531543] [drm:check_encoder_state] [ENCODER:29:DP MST-29]
>[   89.531544] [drm:check_encoder_state] [ENCODER:30:DP MST-30]
>[   89.531546] [drm:check_encoder_state] [ENCODER:31:DP MST-31]
>[   89.531547] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[   89.531550] [drm:check_crtc_state] [CRTC:8]
>[   89.531558] [drm:check_crtc_state] [CRTC:12]
>[   89.531564] [drm:check_crtc_state] [CRTC:16]
>[   89.531569] [drm:check_shared_dpll_state] WRPLL 1
>[   89.531571] [drm:check_shared_dpll_state] WRPLL 2
>[   91.429274] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[   91.429280] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[   93.983110] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[   93.983111] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   93.983114] [drm:drm_mode_debug_printmodeline] Modeline 99:"800x600" 59 38250 800 832 912 1024 600 603 607 624 0x0 0x0
>[   93.983116] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   93.983117] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=1
>[   93.983118] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[   93.983119] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[   93.983120] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[   93.983122] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[   93.983124] [drm:connected_sink_compute_bpp] [CONNECTOR:19:eDP-1] checking for sink bpp constrains
>[   93.983126] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[   93.983130] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[   93.983131] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[   93.983132] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   93.983133] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
>[   93.983134] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   93.983135] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   93.983136] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   93.983138] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   93.983139] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   93.983139] [drm:intel_dump_pipe_config] requested mode:
>[   93.983141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   93.983142] [drm:intel_dump_pipe_config] adjusted mode:
>[   93.983144] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   93.983145] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   93.983146] [drm:intel_dump_pipe_config] port clock: 270000
>[   93.983147] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   93.983148] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   93.983149] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   93.983150] [drm:intel_dump_pipe_config] ips: 1
>[   93.983150] [drm:intel_dump_pipe_config] double wide: 0
>[   93.983969] [drm:intel_edp_backlight_off] 
>[   94.184699] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   94.202701] [drm:edp_panel_vdd_on] Turning eDP VDD on
>[   94.202707] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   94.202863] [drm:intel_edp_panel_off] Turn eDP power off
>[   94.202866] [drm:wait_panel_off] Wait for panel power off time
>[   94.202869] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   94.257723] [drm:wait_panel_status] Wait complete
>[   94.257747] [drm:intel_edp_panel_on] Turn eDP power on
>[   94.257748] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   94.804009] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[   94.804010] [drm:wait_panel_status] Wait complete
>[   94.804013] [drm:wait_panel_on] Wait for panel power on
>[   94.804016] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   95.013112] [drm:wait_panel_status] Wait complete
>[   95.013114] [drm:edp_panel_vdd_on] Turning eDP VDD on
>[   95.013120] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   95.014174] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   95.014621] [drm:intel_dp_start_link_train] clock recovery OK
>[   95.015368] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   95.015601] [drm:intel_edp_backlight_on] 
>[   95.015602] [drm:intel_panel_enable_backlight] pipe A
>[   95.015608] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[   95.015613] [drm:intel_edp_psr_enable] PSR not supported by this panel
>[   95.015617] [drm:ironlake_update_primary_plane] Writing base 00881000 00000000 0 0 15360
>[   95.050132] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1]
>[   95.050134] [drm:intel_connector_check_state] [CONNECTOR:28:DP-1]
>[   95.050137] [drm:intel_connector_check_state] [CONNECTOR:35:HDMI-A-2]
>[   95.050139] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[   95.050140] [drm:check_encoder_state] [ENCODER:27:TMDS-27]
>[   95.050141] [drm:check_encoder_state] [ENCODER:29:DP MST-29]
>[   95.050142] [drm:check_encoder_state] [ENCODER:30:DP MST-30]
>[   95.050143] [drm:check_encoder_state] [ENCODER:31:DP MST-31]
>[   95.050143] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[   95.050146] [drm:check_crtc_state] [CRTC:8]
>[   95.050151] [drm:check_crtc_state] [CRTC:12]
>[   95.050157] [drm:check_crtc_state] [CRTC:16]
>[   95.050162] [drm:check_shared_dpll_state] WRPLL 1
>[   95.050163] [drm:check_shared_dpll_state] WRPLL 2
>[   95.050166] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[   95.050167] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   95.050169] [drm:drm_mode_debug_printmodeline] Modeline 100:"800x600" 59 38250 800 832 912 1024 600 603 607 624 0x0 0x0
>[   95.050171] [drm:drm_mode_debug_printmodeline] Modeline 96:"3840x2160" 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
>[   95.050172] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=1, fb_changed=1
>[   95.050173] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[   95.050174] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[   95.050175] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[   95.050176] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[   95.050178] [drm:connected_sink_compute_bpp] [CONNECTOR:28:DP-1] checking for sink bpp constrains
>[   95.050179] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 0a pixel clock 262750KHz
>[   95.050183] [drm:intel_dp_compute_config] DP link bw 0a lane count 4 clock 270000 bpp 24
>[   95.050184] [drm:intel_dp_compute_config] DP link bw required 630600 available 864000
>[   95.050185] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   95.050186] [drm:intel_dump_pipe_config] [CRTC:12][modeset] config for pipe B
>[   95.050186] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[   95.050187] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   95.050189] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   95.050190] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6122518, gmch_n: 8388608, link_m: 510209, link_n: 524288, tu: 64
>[   95.050191] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   95.050192] [drm:intel_dump_pipe_config] requested mode:
>[   95.050193] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
>[   95.050194] [drm:intel_dump_pipe_config] adjusted mode:
>[   95.050196] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
>[   95.050197] [drm:intel_dump_crtc_timings] crtc timings: 262750 3840 3888 3920 4000 2160 2163 2168 2191, type: 0x48 flags: 0x9
>[   95.050198] [drm:intel_dump_pipe_config] port clock: 270000
>[   95.050199] [drm:intel_dump_pipe_config] pipe src size: 3840x2160
>[   95.050200] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   95.050201] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   95.050201] [drm:intel_dump_pipe_config] ips: 0
>[   95.050202] [drm:intel_dump_pipe_config] double wide: 0
>[   95.059416] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   95.066312] [drm:drm_dp_dpcd_access] too many retries, giving up
>[   95.066313] [drm:intel_dp_start_link_train] *ERROR* failed to enable link training
>[   95.067308] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   95.074140] [drm:drm_dp_dpcd_access] too many retries, giving up
>[   95.074141] [drm:intel_dp_complete_link_train] *ERROR* failed to update link training
>[   95.076392] [drm:ironlake_update_primary_plane] Writing base 00881000 00000000 0 0 15360
>[   95.109800] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1]
>[   95.109802] [drm:intel_connector_check_state] [CONNECTOR:28:DP-1]
>[   95.109805] [drm:intel_connector_check_state] [CONNECTOR:35:HDMI-A-2]
>[   95.109807] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[   95.109808] [drm:check_encoder_state] [ENCODER:27:TMDS-27]
>[   95.109811] [drm:check_encoder_state] [ENCODER:29:DP MST-29]
>[   95.109811] [drm:check_encoder_state] [ENCODER:30:DP MST-30]
>[   95.109812] [drm:check_encoder_state] [ENCODER:31:DP MST-31]
>[   95.109813] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[   95.109814] [drm:check_crtc_state] [CRTC:8]
>[   95.109819] [drm:check_crtc_state] [CRTC:12]
>[   95.109824] [drm:check_crtc_state] [CRTC:16]
>[   95.109829] [drm:check_shared_dpll_state] WRPLL 1
>[   95.109830] [drm:check_shared_dpll_state] WRPLL 2
>[   95.109832] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[   95.109833] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   95.109835] [drm:drm_mode_debug_printmodeline] Modeline 104:"800x600" 59 38250 800 832 912 1024 600 603 607 624 0x0 0x0
>[   95.109836] [drm:drm_mode_debug_printmodeline] Modeline 97:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   95.109837] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=1, fb_changed=1
>[   95.109838] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[   95.109839] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[   95.109840] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[   95.109842] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[   95.109843] [drm:connected_sink_compute_bpp] [CONNECTOR:35:HDMI-A-2] checking for sink bpp constrains
>[   95.109845] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[   95.109846] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[   95.109847] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[   95.109847] [drm:intel_dump_pipe_config] [CRTC:16][modeset] config for pipe C
>[   95.109848] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[   95.109849] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   95.109850] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   95.109851] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   95.109852] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   95.109853] [drm:intel_dump_pipe_config] requested mode:
>[   95.109855] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   95.109855] [drm:intel_dump_pipe_config] adjusted mode:
>[   95.109857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   95.109858] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   95.109859] [drm:intel_dump_pipe_config] port clock: 148500
>[   95.109860] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   95.109861] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   95.109861] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   95.109862] [drm:intel_dump_pipe_config] ips: 0
>[   95.109863] [drm:intel_dump_pipe_config] double wide: 0
>[   95.115174] [drm:intel_disable_shared_dpll] disable WRPLL 1 (active 1, on? 1) for crtc 16
>[   95.115175] [drm:intel_disable_shared_dpll] disabling WRPLL 1
>[   95.116457] [drm:intel_get_shared_dpll] CRTC:16 allocated WRPLL 1
>[   95.116458] [drm:intel_get_shared_dpll] using WRPLL 1 for pipe C
>[   95.116459] [drm:intel_enable_shared_dpll] enable WRPLL 1 (active 0, on? 0) for crtc 16
>[   95.116460] [drm:intel_enable_shared_dpll] enabling WRPLL 1
>[   95.116489] [drm:intel_ddi_pre_enable] Audio on pipe C on DDI
>[   95.116490] [drm:intel_ddi_pre_enable] DDI audio: write eld information
>[   95.116491] [drm:intel_write_eld] ELD on [CONNECTOR:35:HDMI-A-2], [ENCODER:34:TMDS-34]
>[   95.116492] [drm:haswell_write_eld] HDMI audio: enable codec
>[   95.116494] [drm:haswell_write_eld] HDMI audio: pin eld vld status=0x00000400
>[   95.116495] [drm:haswell_write_eld] HDMI audio: eld vld status=0x00000500
>[   95.116496] [drm:haswell_write_eld] HDMI audio: audio conf: 0x0071fa60
>[   95.116497] [drm:haswell_write_eld] ELD on pipe C
>[   95.116498] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[   95.116609] [drm:ironlake_update_primary_plane] Writing base 00881000 00000000 0 0 15360
>[   95.133305] [drm:intel_connector_check_state] [CONNECTOR:19:eDP-1]
>[   95.133307] [drm:intel_connector_check_state] [CONNECTOR:28:DP-1]
>[   95.133310] [drm:intel_connector_check_state] [CONNECTOR:35:HDMI-A-2]
>[   95.133312] [drm:check_encoder_state] [ENCODER:18:TMDS-18]
>[   95.133313] [drm:check_encoder_state] [ENCODER:27:TMDS-27]
>[   95.133315] [drm:check_encoder_state] [ENCODER:29:DP MST-29]
>[   95.133316] [drm:check_encoder_state] [ENCODER:30:DP MST-30]
>[   95.133316] [drm:check_encoder_state] [ENCODER:31:DP MST-31]
>[   95.133317] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[   95.133318] [drm:check_crtc_state] [CRTC:8]
>[   95.133325] [drm:check_crtc_state] [CRTC:12]
>[   95.133330] [drm:check_crtc_state] [CRTC:16]
>[   95.133335] [drm:check_shared_dpll_state] WRPLL 1
>[   95.133336] [drm:check_shared_dpll_state] WRPLL 2
>[   95.142212] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[   95.142216] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[   95.142219] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[   95.142220] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[   95.142222] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[   95.142225] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[   95.142227] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
>[   95.142228] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[   95.142230] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[   95.142232] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[   95.142234] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[   95.142235] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0
>[   95.142237] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[   95.142239] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[   95.142240] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[   97.208246] [drm:edp_panel_vdd_off_sync] Turning eDP VDD off
>[   97.208253] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  122.705965] [drm:i915_gem_open] 
>[  122.706015] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[  122.706021] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  122.706025] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  122.706027] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  122.706030] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  122.706034] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[  122.706036] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
>[  122.706038] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  122.706039] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  122.706041] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  122.706043] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[  122.706045] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0
>[  122.706047] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  122.706048] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  122.706050] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  122.721482] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[  122.721485] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  122.721487] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  122.721488] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  122.721489] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  122.721491] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[  122.721493] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
>[  122.721494] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  122.721495] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  122.721496] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  122.721497] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[  122.721499] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0
>[  122.721500] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  122.721500] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  122.721501] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  122.729834] [drm:i915_gem_open] 
>[  122.729850] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[  122.731863] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[  122.731874] [drm:drm_mode_addfb] [FB:59]
>[  122.732019] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[  122.732023] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[  122.732096] [drm:drm_mode_getconnector] [CONNECTOR:19:?]
>[  122.732108] [drm:drm_mode_getconnector] [CONNECTOR:19:?]
>[  122.732259] [drm:drm_mode_getconnector] [CONNECTOR:28:?]
>[  122.732266] [drm:drm_mode_getconnector] [CONNECTOR:28:?]
>[  122.732290] [drm:drm_mode_getconnector] [CONNECTOR:32:?]
>[  122.732293] [drm:drm_mode_getconnector] [CONNECTOR:32:?]
>[  122.732319] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[  122.732325] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[  122.775734] [drm:drm_mode_addfb] [FB:59]
>[  122.775945] [drm:drm_mode_setcrtc] [CRTC:8]
>[  122.775949] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1]
>[  122.775952] [drm:intel_crtc_set_config] [CRTC:8] [FB:59] #connectors=1 (x y) (0 0)
>[  122.775955] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=1
>[  122.775958] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  122.775959] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  122.775961] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  122.782400] [drm:ironlake_update_primary_plane] Writing base 02DCA000 00000000 0 0 15360
>[  122.796192] [drm:drm_mode_setcrtc] [CRTC:12]
>[  122.796195] [drm:drm_mode_setcrtc] [CONNECTOR:28:DP-1]
>[  122.796197] [drm:intel_crtc_set_config] [CRTC:12] [FB:59] #connectors=1 (x y) (0 0)
>[  122.796199] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=1
>[  122.796201] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  122.796202] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  122.796204] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  122.796208] [drm:ironlake_update_primary_plane] Writing base 02DCA000 00000000 0 0 15360
>[  122.808804] [drm:drm_mode_setcrtc] [CRTC:16]
>[  122.808807] [drm:drm_mode_setcrtc] [CONNECTOR:35:HDMI-A-2]
>[  122.808809] [drm:intel_crtc_set_config] [CRTC:16] [FB:59] #connectors=1 (x y) (0 0)
>[  122.808811] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=1
>[  122.808812] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  122.808814] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  122.808815] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  122.808819] [drm:ironlake_update_primary_plane] Writing base 02DCA000 00000000 0 0 15360
>[  184.427821] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[  184.427823] [drm:intel_set_config_compute_mode_changes] crtc has no fb, will flip
>[  184.427825] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=1
>[  184.427826] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  184.427827] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  184.427828] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  184.427834] [drm:intel_update_fbc] no output, disabling
>[  184.427838] [drm:ironlake_update_primary_plane] Writing base 00881000 00000000 0 0 15360
>[  184.443487] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[  184.443491] [drm:intel_set_config_compute_mode_changes] crtc has no fb, will flip
>[  184.443492] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=1
>[  184.443494] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  184.443495] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  184.443496] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  184.443501] [drm:intel_update_fbc] disabled per chip default
>[  184.443504] [drm:ironlake_update_primary_plane] Writing base 00881000 00000000 0 0 15360
>[  184.447101] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[  184.447103] [drm:intel_set_config_compute_mode_changes] crtc has no fb, will flip
>[  184.447104] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=1
>[  184.447105] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  184.447106] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  184.447107] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  184.447114] [drm:intel_update_fbc] more than one pipe active, disabling compression
>[  184.447116] [drm:ironlake_update_primary_plane] Writing base 00881000 00000000 0 0 15360
>[  184.462713] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[  184.462715] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  184.462716] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  184.462717] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  184.462717] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  184.462719] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[  184.462720] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
>[  184.462721] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  184.462722] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  184.462723] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  184.462724] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[  184.462726] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0
>[  184.462726] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  184.462727] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  184.462728] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  184.462737] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[  184.462738] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  184.462739] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  184.462740] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  184.462741] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  184.462742] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[  184.462743] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
>[  184.462744] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  184.462745] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  184.462746] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  184.462747] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[  184.462748] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0
>[  184.462749] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  184.462750] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  184.462751] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  184.471182] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[  184.471184] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  184.471185] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  184.471186] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  184.471186] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  184.471188] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[  184.471189] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
>[  184.471190] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  184.471191] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  184.471192] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  184.471193] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[  184.471194] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0
>[  184.471195] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  184.471196] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  184.471196] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  184.484519] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[  184.484525] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  184.484528] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  184.484531] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  184.484533] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  184.484536] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[  184.484538] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
>[  184.484540] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  184.484541] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  184.484543] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  184.484545] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[  184.484547] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0
>[  184.484549] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  184.484550] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  184.484552] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  189.385980] [drm:i915_gem_open] 
>[  189.386025] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[  189.386029] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  189.386031] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  189.386033] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  189.386035] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  189.386038] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[  189.386040] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
>[  189.386042] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  189.386044] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  189.386045] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  189.386047] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[  189.386049] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0
>[  189.386051] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  189.386052] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  189.386054] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  189.389177] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[  189.389180] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  189.389181] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  189.389183] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  189.389184] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  189.389186] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[  189.389187] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
>[  189.389188] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  189.389189] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  189.389190] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  189.389191] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[  189.389193] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0
>[  189.389194] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  189.389194] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  189.389195] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  189.397448] [drm:i915_gem_open] 
>[  189.397465] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[  189.398106] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[  189.398118] [drm:drm_mode_addfb] [FB:59]
>[  189.398298] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[  189.398302] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[  189.398382] [drm:drm_mode_getconnector] [CONNECTOR:19:?]
>[  189.398394] [drm:drm_mode_getconnector] [CONNECTOR:19:?]
>[  189.398550] [drm:drm_mode_getconnector] [CONNECTOR:28:?]
>[  189.398558] [drm:drm_mode_getconnector] [CONNECTOR:28:?]
>[  189.398588] [drm:drm_mode_getconnector] [CONNECTOR:32:?]
>[  189.398592] [drm:drm_mode_getconnector] [CONNECTOR:32:?]
>[  189.398618] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[  189.398625] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[  189.430880] [drm:drm_mode_addfb] [FB:59]
>[  189.431137] [drm:drm_mode_setcrtc] [CRTC:8]
>[  189.431142] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1]
>[  189.431145] [drm:intel_crtc_set_config] [CRTC:8] [FB:59] #connectors=1 (x y) (0 0)
>[  189.431149] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=1
>[  189.431151] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  189.431152] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  189.431154] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  189.437650] [drm:ironlake_update_primary_plane] Writing base 02DCA000 00000000 0 0 15360
>[  189.446105] [drm:drm_mode_setcrtc] [CRTC:12]
>[  189.446110] [drm:drm_mode_setcrtc] [CONNECTOR:28:DP-1]
>[  189.446113] [drm:intel_crtc_set_config] [CRTC:12] [FB:59] #connectors=1 (x y) (0 0)
>[  189.446116] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=1
>[  189.446118] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  189.446119] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  189.446121] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  189.446126] [drm:ironlake_update_primary_plane] Writing base 02DCA000 00000000 0 0 15360
>[  189.453044] [drm:drm_mode_setcrtc] [CRTC:16]
>[  189.453048] [drm:drm_mode_setcrtc] [CONNECTOR:35:HDMI-A-2]
>[  189.453050] [drm:intel_crtc_set_config] [CRTC:16] [FB:59] #connectors=1 (x y) (0 0)
>[  189.453052] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=1
>[  189.453054] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  189.453056] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  189.453057] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  189.453062] [drm:ironlake_update_primary_plane] Writing base 02DCA000 00000000 0 0 15360
>[  255.692514] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[  255.692517] [drm:intel_set_config_compute_mode_changes] crtc has no fb, will flip
>[  255.692519] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=1
>[  255.692520] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  255.692522] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  255.692523] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  255.692528] [drm:intel_update_fbc] no output, disabling
>[  255.692531] [drm:ironlake_update_primary_plane] Writing base 00881000 00000000 0 0 15360
>[  255.695685] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[  255.695687] [drm:intel_set_config_compute_mode_changes] crtc has no fb, will flip
>[  255.695688] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=1
>[  255.695690] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  255.695691] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  255.695692] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  255.695697] [drm:intel_update_fbc] disabled per chip default
>[  255.695700] [drm:ironlake_update_primary_plane] Writing base 00881000 00000000 0 0 15360
>[  255.696684] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[  255.696686] [drm:intel_set_config_compute_mode_changes] crtc has no fb, will flip
>[  255.696687] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=1
>[  255.696688] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  255.696689] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  255.696690] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  255.696692] [drm:intel_update_fbc] more than one pipe active, disabling compression
>[  255.696695] [drm:ironlake_update_primary_plane] Writing base 00881000 00000000 0 0 15360
>[  255.699455] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[  255.699456] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  255.699457] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  255.699458] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  255.699459] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  255.699460] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[  255.699461] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
>[  255.699462] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  255.699463] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  255.699464] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  255.699465] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[  255.699466] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0
>[  255.699467] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  255.699468] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  255.699469] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  255.699479] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[  255.699480] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  255.699480] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  255.699481] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  255.699482] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  255.699483] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[  255.699484] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
>[  255.699485] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  255.699486] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  255.699487] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  255.699488] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[  255.699489] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0
>[  255.699490] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  255.699491] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  255.699492] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  255.707926] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[  255.707927] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  255.707928] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  255.707929] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  255.707930] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  255.707931] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[  255.707932] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
>[  255.707933] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  255.707934] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  255.707935] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  255.707936] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[  255.707937] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0
>[  255.707938] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  255.707939] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  255.707939] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  255.719976] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[  255.719982] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  255.719984] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  255.719987] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  255.719989] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  255.719992] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[  255.719994] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
>[  255.719995] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  255.719997] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  255.719998] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  255.720001] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[  255.720003] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0
>[  255.720004] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  255.720006] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  255.720007] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  260.653799] [drm:i915_gem_open] 
>[  260.653848] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[  260.653852] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  260.653854] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  260.653856] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  260.653858] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  260.653861] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[  260.653863] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
>[  260.653865] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  260.653866] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  260.653868] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  260.653870] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[  260.653872] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0
>[  260.653874] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  260.653876] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  260.653877] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  260.657067] [drm:intel_crtc_set_config] [CRTC:8] [FB:98] #connectors=1 (x y) (0 0)
>[  260.657070] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  260.657072] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  260.657073] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  260.657074] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  260.657077] [drm:intel_crtc_set_config] [CRTC:12] [FB:98] #connectors=1 (x y) (0 0)
>[  260.657078] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=0
>[  260.657079] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  260.657080] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  260.657081] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  260.657083] [drm:intel_crtc_set_config] [CRTC:16] [FB:98] #connectors=1 (x y) (0 0)
>[  260.657084] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=0
>[  260.657085] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  260.657086] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  260.657087] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  260.665488] [drm:i915_gem_open] 
>[  260.665509] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[  260.666119] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[  260.666129] [drm:drm_mode_addfb] [FB:59]
>[  260.666281] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[  260.666285] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[4] ENCODERS[6]
>[  260.666357] [drm:drm_mode_getconnector] [CONNECTOR:19:?]
>[  260.666368] [drm:drm_mode_getconnector] [CONNECTOR:19:?]
>[  260.666552] [drm:drm_mode_getconnector] [CONNECTOR:28:?]
>[  260.666563] [drm:drm_mode_getconnector] [CONNECTOR:28:?]
>[  260.666596] [drm:drm_mode_getconnector] [CONNECTOR:32:?]
>[  260.666600] [drm:drm_mode_getconnector] [CONNECTOR:32:?]
>[  260.666627] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[  260.666633] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[  260.696780] [drm:drm_mode_addfb] [FB:59]
>[  260.697003] [drm:drm_mode_setcrtc] [CRTC:8]
>[  260.697007] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1]
>[  260.697011] [drm:intel_crtc_set_config] [CRTC:8] [FB:59] #connectors=1 (x y) (0 0)
>[  260.697014] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=1
>[  260.697016] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  260.697018] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  260.697020] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  260.703424] [drm:ironlake_update_primary_plane] Writing base 02DCA000 00000000 0 0 15360
>[  260.714960] [drm:drm_mode_setcrtc] [CRTC:12]
>[  260.714963] [drm:drm_mode_setcrtc] [CONNECTOR:28:DP-1]
>[  260.714965] [drm:intel_crtc_set_config] [CRTC:12] [FB:59] #connectors=1 (x y) (0 0)
>[  260.714968] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:12], mode_changed=0, fb_changed=1
>[  260.714969] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  260.714971] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  260.714973] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  260.714977] [drm:ironlake_update_primary_plane] Writing base 02DCA000 00000000 0 0 15360
>[  260.735981] [drm:drm_mode_setcrtc] [CRTC:16]
>[  260.735983] [drm:drm_mode_setcrtc] [CONNECTOR:35:HDMI-A-2]
>[  260.735985] [drm:intel_crtc_set_config] [CRTC:16] [FB:59] #connectors=1 (x y) (0 0)
>[  260.735987] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:16], mode_changed=0, fb_changed=1
>[  260.735989] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  260.735990] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  260.735992] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  260.735996] [drm:ironlake_update_primary_plane] Writing base 02DCA000 00000000 0 0 15360
>[  260.825802] [drm:drm_fb_get_bpp_depth] unsupported pixel format YUYV little-endian (0x56595559)
>[  260.825806] [drm:add_framebuffer_internal] [FB:99]
>[  260.826606] [drm:drm_fb_get_bpp_depth] unsupported pixel format YUYV little-endian (0x56595559)
>[  260.826610] [drm:add_framebuffer_internal] [FB:100]
>[  260.827519] [drm:drm_fb_get_bpp_depth] unsupported pixel format YUYV little-endian (0x56595559)
>[  260.827524] [drm:add_framebuffer_internal] [FB:104]
>[  332.802720] [drm:drm_mode_getconnector] [CONNECTOR:19:?]
>[  332.802725] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:19:eDP-1]
>[  332.802727] [drm:intel_dp_detect] [CONNECTOR:19:eDP-1]
>[  332.802738] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  332.802742] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:19:eDP-1] probed modes :
>[  332.802745] [drm:drm_mode_debug_printmodeline] Modeline 20:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  332.802748] [drm:drm_mode_debug_printmodeline] Modeline 21:"1920x1080" 40 92520 1920 1966 1996 2080 1080 1082 1086 1112 0x40 0xa
>[  332.802751] [drm:drm_mode_getconnector] [CONNECTOR:19:?]
>[  332.802855] [drm:drm_mode_getconnector] [CONNECTOR:28:?]
>[  332.802857] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1]
>[  332.802861] [drm:intel_dp_detect] [CONNECTOR:28:DP-1]
>[  332.803147] [drm:intel_dp_get_dpcd] DPCD: 11 0a a4 01 01 00 01 81 00 00 00 00 00 00 00
>[  332.803323] [drm:intel_dp_probe_oui] Sink OUI: 0080e1
>[  332.803500] [drm:intel_dp_probe_oui] Branch OUI: 0080e1
>[  332.865803] [drm:drm_edid_to_eld] ELD monitor DELL UP3214Q
>[  332.865805] [drm:drm_edid_to_eld] ELD size 8, SAD count 0
>[  332.865852] [drm:drm_mode_debug_printmodeline] Modeline 142:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  332.865853] [drm:drm_mode_prune_invalid] Not using 720x480i mode 3
>[  332.865856] [drm:drm_mode_debug_printmodeline] Modeline 143:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  332.865857] [drm:drm_mode_prune_invalid] Not using 720x576i mode 3
>[  332.865860] [drm:drm_mode_debug_printmodeline] Modeline 162:"720x480i" 60 13513 720 739 801 858 480 488 494 525 0x40 0x101a
>[  332.865861] [drm:drm_mode_prune_invalid] Not using 720x480i mode 3
>[  332.865865] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:28:DP-1] probed modes :
>[  332.865868] [drm:drm_mode_debug_printmodeline] Modeline 38:"3840x2160" 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
>[  332.865870] [drm:drm_mode_debug_printmodeline] Modeline 39:"3840x2160" 30 300000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[  332.865872] [drm:drm_mode_debug_printmodeline] Modeline 46:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  332.865875] [drm:drm_mode_debug_printmodeline] Modeline 40:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  332.865877] [drm:drm_mode_debug_printmodeline] Modeline 58:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  332.865879] [drm:drm_mode_debug_printmodeline] Modeline 78:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  332.865882] [drm:drm_mode_debug_printmodeline] Modeline 41:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  332.865885] [drm:drm_mode_debug_printmodeline] Modeline 74:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  332.865887] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  332.865889] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  332.865892] [drm:drm_mode_debug_printmodeline] Modeline 73:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  332.865894] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  332.865896] [drm:drm_mode_debug_printmodeline] Modeline 48:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  332.865899] [drm:drm_mode_debug_printmodeline] Modeline 45:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  332.865901] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  332.865903] [drm:drm_mode_debug_printmodeline] Modeline 49:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  332.865906] [drm:drm_mode_debug_printmodeline] Modeline 44:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[  332.865908] [drm:drm_mode_debug_printmodeline] Modeline 47:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  332.865910] [drm:drm_mode_debug_printmodeline] Modeline 42:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  332.865913] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  332.865915] [drm:drm_mode_debug_printmodeline] Modeline 70:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  332.865917] [drm:drm_mode_debug_printmodeline] Modeline 55:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  332.865920] [drm:drm_mode_debug_printmodeline] Modeline 56:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  332.865922] [drm:drm_mode_debug_printmodeline] Modeline 57:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  332.865924] [drm:drm_mode_debug_printmodeline] Modeline 50:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  332.865927] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  332.865929] [drm:drm_mode_debug_printmodeline] Modeline 76:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  332.865931] [drm:drm_mode_debug_printmodeline] Modeline 43:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  332.865934] [drm:drm_mode_debug_printmodeline] Modeline 51:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  332.865936] [drm:drm_mode_debug_printmodeline] Modeline 52:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  332.865938] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  332.865940] [drm:drm_mode_debug_printmodeline] Modeline 53:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  332.865951] [drm:drm_mode_getconnector] [CONNECTOR:28:?]
>[  332.865987] [drm:drm_mode_getconnector] [CONNECTOR:32:?]
>[  332.865989] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1]
>[  332.865991] [drm:intel_hdmi_detect] [CONNECTOR:32:HDMI-A-1]
>[  332.866145] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  332.866147] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  332.866148] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:32:HDMI-A-1] disconnected
>[  332.866153] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[  332.866156] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2]
>[  332.866159] [drm:intel_hdmi_detect] [CONNECTOR:35:HDMI-A-2]
>[  332.891064] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  332.891133] [drm:drm_edid_to_eld] ELD monitor ASUS PA238
>[  332.891136] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0
>[  332.891137] [drm:drm_edid_to_eld] ELD size 9, SAD count 1
>[  332.891187] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] probed modes :
>[  332.891189] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  332.891192] [drm:drm_mode_debug_printmodeline] Modeline 112:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  332.891194] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  332.891196] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  332.891199] [drm:drm_mode_debug_printmodeline] Modeline 107:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  332.891201] [drm:drm_mode_debug_printmodeline] Modeline 101:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  332.891203] [drm:drm_mode_debug_printmodeline] Modeline 111:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  332.891206] [drm:drm_mode_debug_printmodeline] Modeline 125:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  332.891208] [drm:drm_mode_debug_printmodeline] Modeline 110:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  332.891211] [drm:drm_mode_debug_printmodeline] Modeline 109:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  332.891213] [drm:drm_mode_debug_printmodeline] Modeline 124:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  332.891215] [drm:drm_mode_debug_printmodeline] Modeline 66:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  332.891217] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  332.891220] [drm:drm_mode_debug_printmodeline] Modeline 69:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  332.891222] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  332.891225] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  332.891227] [drm:drm_mode_debug_printmodeline] Modeline 79:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  332.891229] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  332.891232] [drm:drm_mode_debug_printmodeline] Modeline 114:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  332.891234] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  332.891236] [drm:drm_mode_debug_printmodeline] Modeline 105:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[  332.891239] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  332.891241] [drm:drm_mode_debug_printmodeline] Modeline 89:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  332.891243] [drm:drm_mode_debug_printmodeline] Modeline 90:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  332.891246] [drm:drm_mode_debug_printmodeline] Modeline 121:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  332.891248] [drm:drm_mode_debug_printmodeline] Modeline 103:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  332.891250] [drm:drm_mode_debug_printmodeline] Modeline 91:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  332.891253] [drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  332.891255] [drm:drm_mode_debug_printmodeline] Modeline 93:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  332.891257] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  332.891260] [drm:drm_mode_debug_printmodeline] Modeline 81:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  332.891262] [drm:drm_mode_debug_printmodeline] Modeline 64:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  332.891264] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  332.891266] [drm:drm_mode_debug_printmodeline] Modeline 61:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  332.891269] [drm:drm_mode_debug_printmodeline] Modeline 82:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  332.891271] [drm:drm_mode_debug_printmodeline] Modeline 83:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  332.891273] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  332.891276] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  332.891278] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  332.891284] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[  332.895012] [drm:drm_mode_addfb] [FB:106]
>[  332.895019] [drm:drm_mode_setcrtc] [CRTC:8]
>[  332.895023] [drm:drm_mode_setcrtc] [CONNECTOR:19:eDP-1]
>[  332.895026] [drm:intel_crtc_set_config] [CRTC:8] [FB:106] #connectors=1 (x y) (0 0)
>[  332.895030] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=1
>[  332.895032] [drm:intel_modeset_stage_output_state] [CONNECTOR:19:eDP-1] to [CRTC:8]
>[  332.895034] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:DP-1] to [CRTC:12]
>[  332.895036] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:HDMI-A-2] to [CRTC:16]
>[  332.895042] [drm:ironlake_update_primary_plane] Writing base 04F76000 00000000 0 0 7680

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Attachments on bug 84310: 106831 | 107765 | 107766

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