Attachment 107113 Details for Bug 83792 – Kernel messages, round 1

Kernel messages, round 1

kernelmessages-1.txt (text/plain), 3.48 KB, created by Tim Nelson on 2014-09-30 10:49:42 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Tim Nelson

Created: 2014-09-30 10:49:42 UTC

Size: 3.48 KB

patch

obsolete

>Sep 30 20:51:56 annwn [  400.948902] [drm] Initialized drm 1.1.0 20060810 
>Sep 30 20:51:56 annwn [  401.029363] [drm] radeon kernel modesetting enabled. 
>Sep 30 20:51:56 annwn [  401.030531] [drm] initializing kernel modesetting (RV380 0x1002:0x3151 0x1002:0x3151). 
>Sep 30 20:51:56 annwn [  401.030700] [drm] register mmio base: 0xFBEE0000 
>Sep 30 20:51:56 annwn [  401.030795] [drm] register mmio size: 65536 
>Sep 30 20:51:56 annwn [  401.031050] [drm] Generation 2 PCI interface, using max accessible memory 
>Sep 30 20:51:56 annwn [  401.031157] radeon 0000:0b:00.0: VRAM: 256M 0x00000000D0000000 - 0x00000000DFFFFFFF (128M used) 
>Sep 30 20:51:56 annwn [  401.031304] radeon 0000:0b:00.0: GTT: 512M 0x00000000B0000000 - 0x00000000CFFFFFFF 
>Sep 30 20:51:56 annwn [  401.031456] [drm] Detected VRAM RAM=256M, BAR=256M 
>Sep 30 20:51:56 annwn [  401.031552] [drm] RAM width 128bits DDR 
>Sep 30 20:51:56 annwn [  401.031775] [TTM] Zone  kernel: Available graphics memory: 3051254 kiB 
>Sep 30 20:51:56 annwn [  401.031885] [TTM] Zone   dma32: Available graphics memory: 2097152 kiB 
>Sep 30 20:51:56 annwn [  401.031987] [TTM] Initializing pool allocator 
>Sep 30 20:51:56 annwn [  401.032086] [TTM] Initializing DMA pool allocator 
>Sep 30 20:51:56 annwn [  401.032294] [drm] radeon: 128M of VRAM memory ready 
>Sep 30 20:51:56 annwn [  401.032391] [drm] radeon: 512M of GTT memory ready. 
>Sep 30 20:51:56 annwn [  401.032505] [drm] GART: num cpu pages 131072, num gpu pages 131072 
>Sep 30 20:51:56 annwn [  401.033389] [drm] Possible lm63 thermal controller at 0x26 
>Sep 30 20:51:56 annwn [  401.033545] [drm] radeon: 1 quad pipes, 1 Z pipes initialized. 
>Sep 30 20:51:56 annwn [  401.036563] [drm] PCIE GART of 512M enabled (table at 0x00000000D0040000). 
>Sep 30 20:51:56 annwn [  401.036711] radeon 0000:0b:00.0: WB enabled 
>Sep 30 20:51:56 annwn [  401.036870] radeon 0000:0b:00.0: fence driver on ring 0 use gpu addr 0x00000000b0000000 and cpu addr 0xffff8801bb083000 
>Sep 30 20:51:56 annwn [  401.037026] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). 
>Sep 30 20:51:56 annwn [  401.037128] [drm] Driver supports precise vblank timestamp query. 
>Sep 30 20:51:56 annwn [  401.037279] radeon 0000:0b:00.0: radeon: using MSI. 
>Sep 30 20:51:56 annwn [  401.037432] [drm] radeon: irq initialized. 
>Sep 30 20:51:56 annwn [  401.037573] [drm] Loading R300 Microcode 
>Sep 30 20:51:56 annwn [  401.054839] [drm] radeon: ring at 0x00000000B0001000 
>Sep 30 20:51:56 annwn [  401.054962] [drm] ring test succeeded in 2 usecs 
>Sep 30 20:51:56 annwn [  401.055452] [drm] ib test succeeded in 0 usecs 
>Sep 30 20:51:56 annwn [  401.055963] [drm] Radeon Display Connectors 
>Sep 30 20:51:56 annwn [  401.056064] [drm] Connector 0: 
>Sep 30 20:51:56 annwn [  401.056161] [drm]   DVI-I-1 
>Sep 30 20:51:56 annwn [  401.056257] [drm]   HPD1 
>Sep 30 20:51:56 annwn [  401.056353] [drm]   DDC: 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 
>Sep 30 20:51:56 annwn [  401.056453] [drm]   Encoders: 
>Sep 30 20:51:56 annwn [  401.056548] [drm]     CRT1: INTERNAL_DAC1 
>Sep 30 20:51:56 annwn [  401.056646] [drm]     DFP1: INTERNAL_TMDS1 
>Sep 30 20:51:56 annwn [  401.056750] [drm] Connector 1: 
>Sep 30 20:51:56 annwn [  401.056963] [drm]   DVI-I-2 
>Sep 30 20:51:56 annwn [  401.057058] [drm]   HPD2 
>Sep 30 20:51:56 annwn [  401.057173] [drm]   DDC: 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 
>Sep 30 20:51:56 annwn [  401.057274] [drm]   Encoders: 
>Sep 30 20:51:56 annwn [  401.057379] [drm]     CRT2: INTERNAL_DAC2 
>Sep 30 20:51:56 annwn [  401.057486] [drm]     DFP2: INTERNAL_DVO1

Actions: View

Attachments on bug 83792: 107113 | 107982

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.