Attachment 107188 Details for Bug 84444 – drm/i915/bdw: Enable single subspan dispatch

[patch] drm/i915/bdw: Enable single subspan dispatch

0001-drm-i915-bdw-Enable-single-subspan-dispatch.patch (text/plain), 2.06 KB, created by Mika Kuoppala on 2014-10-01 13:21:01 UTC

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Creator: Mika Kuoppala

Created: 2014-10-01 13:21:01 UTC

Size: 2.06 KB

patch

obsolete

>From ad99378966528b4cb5bd5cab946d3ede7708c475 Mon Sep 17 00:00:00 2001
>From: Mika Kuoppala <mika.kuoppala@intel.com>
>Date: Wed, 1 Oct 2014 16:14:46 +0300
>Subject: [PATCH] drm/i915/bdw: Enable single subspan dispatch
>
>What we are doing here is limiting the hardware's ability to
>dispatch on multiple EUs simultaneously. However for some
>weird reason, this seems to help on some simpler workloads.
>
>As the dwords emitted would be odd in this case, always
>emit 4 dwords per workaround so that we end up in even.
>
>Reference: https://bugs.freedesktop.org/show_bug.cgi?id=84444
>Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
>---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>index 816a692..d90c4d1 100644
>--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>@@ -677,6 +677,7 @@ static inline void intel_ring_emit_wa(struct intel_engine_cs *ring,
> 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> 	intel_ring_emit(ring, addr);
> 	intel_ring_emit(ring, value);
>+	intel_ring_emit(ring, MI_NOOP);
> 
> 	dev_priv->intel_wa_regs[dev_priv->num_wa_regs].addr = addr;
> 	dev_priv->intel_wa_regs[dev_priv->num_wa_regs].mask = value & 0xFFFF;
>@@ -707,7 +708,7 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
> 	 * update the number of dwords required based on the
> 	 * actual number of workarounds applied
> 	 */
>-	ret = intel_ring_begin(ring, 18);
>+	ret = intel_ring_begin(ring, 7 * 4);
> 	if (ret)
> 		return ret;
> 
>@@ -725,6 +726,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
> 	intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
> 			   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
> 
>+	intel_ring_emit_wa(ring, GEN7_HALF_SLICE_CHICKEN1,
>+			   _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
>+
> 	/* Use Force Non-Coherent whenever executing a 3D context. This is a
> 	 * workaround for for a possible hang in the unlikely event a TLB
> 	 * invalidation occurs during a PSD flush.
>-- 
>1.9.1
>

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Attachments on bug 84444: 107034 | 107188

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