Attachment 108938 Details for Bug 85908 – dmesg

dmesg

dmesg_bsw01_kms_render_1105.txt (text/plain), 93.69 KB, created by lu hua on 2014-11-05 08:50:48 UTC

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Creator: lu hua

Created: 2014-11-05 08:50:48 UTC

Size: 93.69 KB

patch

obsolete

>[  449.804143] kms_render: executing
>[  449.804480] [drm:i915_gem_open] 
>[  449.804847] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 624 MHz (60)
>[  449.807056] [drm:intel_set_cpu_fifo_underrun_reporting [i915]] *ERROR* pipe B underrun
>[  449.807112] [drm:i915_gem_open] 
>[  449.807235] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
>[  449.807473] kms_render: starting subtest direct-render
>[  449.807523] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  449.807547] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  449.807571] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  449.807580] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  449.807591] [drm:drm_mode_getconnector] [CONNECTOR:29:?]
>[  449.807598] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:29:eDP-1]
>[  449.807603] [drm:intel_dp_detect] [CONNECTOR:29:eDP-1]
>[  449.843671] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  449.843685] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  449.879793] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[  449.915933] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 208 MHz (20)
>[  449.929678] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[  449.941697] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  449.941709] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:29:eDP-1] probed modes :
>[  449.941718] [drm:drm_mode_debug_printmodeline] Modeline 30:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  449.941738] [drm:drm_mode_getconnector] [CONNECTOR:29:?]
>[  449.941862] [drm:add_framebuffer_internal] [FB:40]
>[  449.941879] [drm:add_framebuffer_internal] [FB:41]
>[  449.941890] [drm:drm_mode_setcrtc] [CRTC:8]
>[  449.941899] [drm:drm_mode_setcrtc] [CONNECTOR:29:eDP-1]
>[  449.941905] [drm:intel_crtc_set_config] [CRTC:8] [FB:40] #connectors=1 (x y) (0 0)
>[  449.941912] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  449.941917] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
>[  449.941923] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:8]
>[  449.941928] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  449.941932] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  449.941936] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  449.941943] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[  449.941950] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  449.941957] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  449.941962] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[  449.941967] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[  449.941974] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  449.941979] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
>[  449.941982] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  449.941986] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  449.941992] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  449.941998] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  449.942003] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  449.942006] [drm:intel_dump_pipe_config] requested mode:
>[  449.942013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  449.942017] [drm:intel_dump_pipe_config] adjusted mode:
>[  449.942024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  449.942031] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  449.942035] [drm:intel_dump_pipe_config] port clock: 270000
>[  449.942039] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  449.942044] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  449.942049] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  449.942052] [drm:intel_dump_pipe_config] ips: 0
>[  449.942056] [drm:intel_dump_pipe_config] double wide: 0
>[  449.943931] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  449.982681] [drm:intel_edp_backlight_off] 
>[  450.207750] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  450.243694] [drm:edp_panel_off] Turn eDP port C panel power off
>[  450.243704] [drm:wait_panel_off] Wait for panel power off time
>[  450.243712] [drm:wait_panel_status] mask b0000000 value 00000000 status e0000003 control abcd0000
>[  450.287713] [drm:wait_panel_status] Wait complete
>[  450.313697] [drm:intel_dp_link_down] 
>[  450.388805] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  450.388815] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=2, cursor=2, C: plane=2, cursor=2, SR: plane=0, cursor=0
>[  450.523714] [drm:vlv_detach_power_sequencer] detaching pipe B power sequencer from port C
>[  450.523726] [drm:vlv_init_panel_power_sequencer] initializing pipe A power sequencer for port C
>[  450.523736] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06
>[  450.535778] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  450.535787] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  450.844910] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[  450.844920] [drm:wait_panel_status] Wait complete
>[  450.844931] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  450.844936] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled
>[  451.045748] [drm:edp_panel_on] Turn eDP port C panel power on
>[  451.045761] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  451.045770] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008
>[  451.045775] [drm:wait_panel_status] Wait complete
>[  451.045782] [drm:wait_panel_on] Wait for panel power on
>[  451.045789] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b
>[  451.199736] [drm:wait_panel_status] Wait complete
>[  451.199746] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  451.199756] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  451.247857] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  451.247870] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  451.383745] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  451.455750] [drm:intel_dp_start_link_train] clock recovery OK
>[  451.527878] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  451.551812] [drm:g4x_check_srwm] SR watermark: display plane 54, cursor 2
>[  451.551821] [drm:g4x_check_srwm] SR watermark: display plane 106, cursor 2
>[  451.551828] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=39, cursor=2, B: plane=2, cursor=2, C: plane=2, cursor=2, SR: plane=54, cursor=2
>[  451.551836] [drm:intel_set_memory_cxsr] memory self-refresh is enabled
>[  451.551847] [drm:intel_edp_backlight_on] 
>[  451.551852] [drm:intel_panel_enable_backlight] pipe A
>[  451.551859] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3906
>[  451.575819] [drm:i9xx_update_primary_plane] Writing base 0089C000 00000000 0 0 3840
>[  451.575842] [drm:intel_connector_check_state] [CONNECTOR:29:eDP-1]
>[  451.575857] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  451.575862] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  451.575868] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  451.575874] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  451.575879] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  451.575885] [drm:check_crtc_state] [CRTC:8]
>[  451.583759] [drm:check_crtc_state] [CRTC:13]
>[  451.583768] [drm:check_crtc_state] [CRTC:18]
>[  452.861817] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  452.861833] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  459.365361] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  459.365375] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
>[  459.365381] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [NOCRTC]
>[  459.365385] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  459.365390] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  459.365395] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  459.365402] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  459.367064] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  459.393114] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  459.393127] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  459.405226] [drm:intel_edp_backlight_off] 
>[  459.630122] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  459.666145] [drm:edp_panel_off] Turn eDP port C panel power off
>[  459.666154] [drm:wait_panel_off] Wait for panel power off time
>[  459.666162] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[  459.710120] [drm:wait_panel_status] Wait complete
>[  459.736139] [drm:intel_dp_link_down] 
>[  459.811162] [drm:intel_set_cpu_fifo_underrun_reporting [i915]] *ERROR* pipe A underrun
>[  459.811174] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  459.811182] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=2, cursor=2, C: plane=2, cursor=2, SR: plane=0, cursor=0
>[  459.821128] [drm:intel_display_power_put] disabling dpio-common-d
>[  459.833121] [drm:intel_display_power_put] disabling dpio-common-bc
>[  459.845125] [drm:intel_display_power_put] disabling pipe-a
>[  459.857180] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  459.857187] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  459.857192] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  459.857196] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  459.857201] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  459.857205] [drm:check_crtc_state] [CRTC:8]
>[  459.857210] [drm:check_crtc_state] [CRTC:13]
>[  459.857215] [drm:check_crtc_state] [CRTC:18]
>[  459.858179] [drm:add_framebuffer_internal] [FB:40]
>[  459.858197] [drm:add_framebuffer_internal] [FB:41]
>[  459.858207] [drm:drm_mode_setcrtc] [CRTC:8]
>[  459.858216] [drm:drm_mode_setcrtc] [CONNECTOR:29:eDP-1]
>[  459.858223] [drm:intel_crtc_set_config] [CRTC:8] [FB:40] #connectors=1 (x y) (0 0)
>[  459.858228] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  459.858234] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
>[  459.858238] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  459.858243] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:8]
>[  459.858247] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  459.858253] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  459.858260] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  459.858266] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  459.858274] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  459.858290] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  459.858295] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  459.858301] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  459.858306] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
>[  459.858310] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  459.858314] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  459.858320] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  459.858325] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  459.858331] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  459.858334] [drm:intel_dump_pipe_config] requested mode:
>[  459.858350] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  459.858372] [drm:intel_dump_pipe_config] adjusted mode:
>[  459.858390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  459.858410] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  459.858426] [drm:intel_dump_pipe_config] port clock: 270000
>[  459.858442] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  459.858459] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  459.858476] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  459.858487] [drm:intel_dump_pipe_config] ips: 0
>[  459.858491] [drm:intel_dump_pipe_config] double wide: 0
>[  459.862079] [drm:intel_display_power_get] enabling pipe-a
>[  459.882168] [drm:intel_display_power_get] enabling dpio-common-bc
>[  459.894128] [drm:intel_display_power_get] enabling dpio-common-d
>[  460.002140] [drm:vlv_init_panel_power_sequencer] initializing pipe A power sequencer for port C
>[  460.002156] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06
>[  460.014135] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  460.014144] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  460.267302] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000
>[  460.432156] [drm:wait_panel_status] Wait complete
>[  460.432174] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  460.432180] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled
>[  460.633384] [drm:edp_panel_on] Turn eDP port C panel power on
>[  460.633398] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  460.633407] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008
>[  460.633412] [drm:wait_panel_status] Wait complete
>[  460.633419] [drm:wait_panel_on] Wait for panel power on
>[  460.633426] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b
>[  460.787172] [drm:wait_panel_status] Wait complete
>[  460.787185] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  460.787196] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  460.835172] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  460.835185] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  460.971191] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  461.043180] [drm:intel_dp_start_link_train] clock recovery OK
>[  461.115141] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  461.139270] [drm:g4x_check_srwm] SR watermark: display plane 107, cursor 2
>[  461.139277] [drm:g4x_check_srwm] SR watermark: display plane 211, cursor 2
>[  461.139284] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=61, cursor=2, B: plane=2, cursor=2, C: plane=2, cursor=2, SR: plane=107, cursor=2
>[  461.139292] [drm:intel_set_memory_cxsr] memory self-refresh is enabled
>[  461.139303] [drm:intel_edp_backlight_on] 
>[  461.139307] [drm:intel_panel_enable_backlight] pipe A
>[  461.139314] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3906
>[  461.163193] [drm:i9xx_update_primary_plane] Writing base 0089C000 00000000 0 0 7680
>[  461.163215] [drm:intel_connector_check_state] [CONNECTOR:29:eDP-1]
>[  461.163230] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  461.163236] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  461.163242] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  461.163247] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  461.163253] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  461.163259] [drm:check_crtc_state] [CRTC:8]
>[  461.171245] [drm:check_crtc_state] [CRTC:13]
>[  461.171254] [drm:check_crtc_state] [CRTC:18]
>[  463.854313] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  463.854328] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  468.332643] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  468.332656] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
>[  468.332662] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [NOCRTC]
>[  468.332666] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  468.332671] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  468.332675] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  468.332683] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  468.334468] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  468.363509] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  468.363524] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  468.375506] [drm:intel_edp_backlight_off] 
>[  468.600674] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  468.636522] [drm:edp_panel_off] Turn eDP port C panel power off
>[  468.636532] [drm:wait_panel_off] Wait for panel power off time
>[  468.636540] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[  468.680524] [drm:wait_panel_status] Wait complete
>[  468.704672] [drm:intel_dp_link_down] 
>[  468.779569] [drm:intel_set_cpu_fifo_underrun_reporting [i915]] *ERROR* pipe A underrun
>[  468.779584] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  468.779592] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=2, cursor=2, C: plane=2, cursor=2, SR: plane=0, cursor=0
>[  468.789531] [drm:intel_display_power_put] disabling dpio-common-d
>[  468.801525] [drm:intel_display_power_put] disabling dpio-common-bc
>[  468.813540] [drm:intel_display_power_put] disabling pipe-a
>[  468.825558] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  468.825566] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  468.825571] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  468.825575] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  468.825579] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  468.825584] [drm:check_crtc_state] [CRTC:8]
>[  468.825589] [drm:check_crtc_state] [CRTC:13]
>[  468.825593] [drm:check_crtc_state] [CRTC:18]
>[  468.828648] [drm:add_framebuffer_internal] [FB:40]
>[  468.828666] [drm:add_framebuffer_internal] [FB:41]
>[  468.828677] [drm:drm_mode_setcrtc] [CRTC:8]
>[  468.828687] [drm:drm_mode_setcrtc] [CONNECTOR:29:eDP-1]
>[  468.828694] [drm:intel_crtc_set_config] [CRTC:8] [FB:40] #connectors=1 (x y) (0 0)
>[  468.828701] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  468.828706] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
>[  468.828710] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  468.828716] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:8]
>[  468.828721] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  468.828725] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  468.828732] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  468.828739] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  468.828743] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24
>[  468.828751] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  468.828767] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  468.828772] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  468.828778] [drm:intel_modeset_pipe_config] plane bpp: 30, pipe bpp: 24, dithering: 1
>[  468.828783] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
>[  468.828787] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  468.828791] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  468.828796] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  468.828802] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  468.828807] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  468.828811] [drm:intel_dump_pipe_config] requested mode:
>[  468.828819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  468.828822] [drm:intel_dump_pipe_config] adjusted mode:
>[  468.828829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  468.828836] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  468.828840] [drm:intel_dump_pipe_config] port clock: 270000
>[  468.828844] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  468.828849] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  468.828854] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  468.828857] [drm:intel_dump_pipe_config] ips: 0
>[  468.828861] [drm:intel_dump_pipe_config] double wide: 0
>[  468.832490] [drm:intel_display_power_get] enabling pipe-a
>[  468.852528] [drm:intel_display_power_get] enabling dpio-common-bc
>[  468.864551] [drm:intel_display_power_get] enabling dpio-common-d
>[  468.972560] [drm:vlv_init_panel_power_sequencer] initializing pipe A power sequencer for port C
>[  468.972576] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06
>[  468.984652] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  468.984661] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  469.237699] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000
>[  469.402560] [drm:wait_panel_status] Wait complete
>[  469.402577] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  469.402583] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled
>[  469.603594] [drm:edp_panel_on] Turn eDP port C panel power on
>[  469.603607] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  469.603616] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008
>[  469.603621] [drm:wait_panel_status] Wait complete
>[  469.603629] [drm:wait_panel_on] Wait for panel power on
>[  469.603635] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b
>[  469.757690] [drm:wait_panel_status] Wait complete
>[  469.757703] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  469.757714] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  469.805622] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  469.805635] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  469.941580] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  470.013583] [drm:intel_dp_start_link_train] clock recovery OK
>[  470.085641] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  470.109646] [drm:g4x_check_srwm] SR watermark: display plane 107, cursor 2
>[  470.109653] [drm:g4x_check_srwm] SR watermark: display plane 211, cursor 2
>[  470.109660] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=61, cursor=2, B: plane=2, cursor=2, C: plane=2, cursor=2, SR: plane=107, cursor=2
>[  470.109668] [drm:intel_set_memory_cxsr] memory self-refresh is enabled
>[  470.109679] [drm:intel_edp_backlight_on] 
>[  470.109683] [drm:intel_panel_enable_backlight] pipe A
>[  470.109690] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3906
>[  470.133686] [drm:i9xx_update_primary_plane] Writing base 0089C000 00000000 0 0 7680
>[  470.133708] [drm:intel_connector_check_state] [CONNECTOR:29:eDP-1]
>[  470.133723] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  470.133729] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  470.133735] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  470.133741] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  470.133746] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  470.133752] [drm:check_crtc_state] [CRTC:8]
>[  470.141608] [drm:check_crtc_state] [CRTC:13]
>[  470.141617] [drm:check_crtc_state] [CRTC:18]
>[  472.822715] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  472.822730] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  478.741236] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  478.741251] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
>[  478.741257] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [NOCRTC]
>[  478.741261] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  478.741266] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  478.741270] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  478.741278] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  478.742937] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  478.767009] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  478.767022] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  478.778980] [drm:intel_edp_backlight_off] 
>[  479.003993] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  479.039990] [drm:edp_panel_off] Turn eDP port C panel power off
>[  479.040002] [drm:wait_panel_off] Wait for panel power off time
>[  479.040011] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[  479.084136] [drm:wait_panel_status] Wait complete
>[  479.109995] [drm:intel_dp_link_down] 
>[  479.185122] [drm:intel_set_cpu_fifo_underrun_reporting [i915]] *ERROR* pipe A underrun
>[  479.185135] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  479.185143] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=2, cursor=2, C: plane=2, cursor=2, SR: plane=0, cursor=0
>[  479.194994] [drm:intel_display_power_put] disabling dpio-common-d
>[  479.207046] [drm:intel_display_power_put] disabling dpio-common-bc
>[  479.218994] [drm:intel_display_power_put] disabling pipe-a
>[  479.231003] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  479.231010] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  479.231015] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  479.231020] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  479.231024] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  479.231029] [drm:check_crtc_state] [CRTC:8]
>[  479.231033] [drm:check_crtc_state] [CRTC:13]
>[  479.231038] [drm:check_crtc_state] [CRTC:18]
>[  479.232782] [drm:add_framebuffer_internal] [FB:40]
>[  479.232801] [drm:add_framebuffer_internal] [FB:41]
>[  479.232812] [drm:drm_mode_setcrtc] [CRTC:8]
>[  479.232822] [drm:drm_mode_setcrtc] [CONNECTOR:29:eDP-1]
>[  479.232828] [drm:intel_crtc_set_config] [CRTC:8] [FB:40] #connectors=1 (x y) (0 0)
>[  479.232837] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  479.232842] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
>[  479.232847] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  479.232852] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:8]
>[  479.232857] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  479.232861] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  479.232868] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  479.232875] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  479.232883] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  479.232903] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  479.232907] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  479.232913] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  479.232918] [drm:intel_dump_pipe_config] [CRTC:8][modeset] config for pipe A
>[  479.232922] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  479.232926] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  479.232932] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  479.232967] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  479.232972] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  479.232976] [drm:intel_dump_pipe_config] requested mode:
>[  479.232984] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  479.232994] [drm:intel_dump_pipe_config] adjusted mode:
>[  479.233014] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  479.233033] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  479.233049] [drm:intel_dump_pipe_config] port clock: 270000
>[  479.233065] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  479.233082] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  479.233097] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  479.233101] [drm:intel_dump_pipe_config] ips: 0
>[  479.233130] [drm:intel_dump_pipe_config] double wide: 0
>[  479.236960] [drm:intel_display_power_get] enabling pipe-a
>[  479.256997] [drm:intel_display_power_get] enabling dpio-common-bc
>[  479.268997] [drm:intel_display_power_get] enabling dpio-common-d
>[  479.377012] [drm:vlv_init_panel_power_sequencer] initializing pipe A power sequencer for port C
>[  479.377027] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06
>[  479.389003] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  479.389012] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  479.641168] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000
>[  479.806025] [drm:wait_panel_status] Wait complete
>[  479.806038] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  479.806044] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled
>[  480.007039] [drm:edp_panel_on] Turn eDP port C panel power on
>[  480.007052] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  480.007061] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008
>[  480.007066] [drm:wait_panel_status] Wait complete
>[  480.007074] [drm:wait_panel_on] Wait for panel power on
>[  480.007080] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b
>[  480.161152] [drm:wait_panel_status] Wait complete
>[  480.161164] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  480.161176] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  480.209095] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  480.209108] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  480.345054] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  480.417050] [drm:intel_dp_start_link_train] clock recovery OK
>[  480.489098] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  480.513114] [drm:g4x_check_srwm] SR watermark: display plane 107, cursor 2
>[  480.513122] [drm:g4x_check_srwm] SR watermark: display plane 211, cursor 2
>[  480.513129] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=61, cursor=2, B: plane=2, cursor=2, C: plane=2, cursor=2, SR: plane=107, cursor=2
>[  480.513137] [drm:intel_set_memory_cxsr] memory self-refresh is enabled
>[  480.513148] [drm:intel_edp_backlight_on] 
>[  480.513153] [drm:intel_panel_enable_backlight] pipe A
>[  480.513159] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3906
>[  480.537161] [drm:i9xx_update_primary_plane] Writing base 0089C000 00000000 0 0 7680
>[  480.537184] [drm:intel_connector_check_state] [CONNECTOR:29:eDP-1]
>[  480.537199] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  480.537204] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  480.537210] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  480.537216] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  480.537222] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  480.537228] [drm:check_crtc_state] [CRTC:8]
>[  480.545066] [drm:check_crtc_state] [CRTC:13]
>[  480.545075] [drm:check_crtc_state] [CRTC:18]
>[  483.231295] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  483.231310] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  487.706450] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  487.706464] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=1, fb_changed=0
>[  487.706469] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [NOCRTC]
>[  487.706473] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  487.706478] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  487.706483] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  487.706490] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  487.708340] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  487.737382] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  487.737397] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  487.749425] [drm:intel_edp_backlight_off] 
>[  487.974398] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  488.010460] [drm:edp_panel_off] Turn eDP port C panel power off
>[  488.010469] [drm:wait_panel_off] Wait for panel power off time
>[  488.010478] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[  488.054411] [drm:wait_panel_status] Wait complete
>[  488.078405] [drm:intel_dp_link_down] 
>[  488.153517] [drm:intel_set_cpu_fifo_underrun_reporting [i915]] *ERROR* pipe A underrun
>[  488.153530] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  488.153537] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=2, cursor=2, C: plane=2, cursor=2, SR: plane=0, cursor=0
>[  488.163359] [drm:intel_display_power_put] disabling dpio-common-d
>[  488.175430] [drm:intel_display_power_put] disabling dpio-common-bc
>[  488.187400] [drm:intel_display_power_put] disabling pipe-a
>[  488.199407] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  488.199415] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  488.199420] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  488.199424] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  488.199428] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  488.199433] [drm:check_crtc_state] [CRTC:8]
>[  488.199438] [drm:check_crtc_state] [CRTC:13]
>[  488.199442] [drm:check_crtc_state] [CRTC:18]
>[  488.202393] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  488.202407] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  488.202418] [drm:drm_mode_getconnector] [CONNECTOR:29:?]
>[  488.202425] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:29:eDP-1]
>[  488.202430] [drm:intel_dp_detect] [CONNECTOR:29:eDP-1]
>[  488.202437] [drm:intel_display_power_get] enabling pipe-a
>[  488.214354] [drm:intel_display_power_get] enabling dpio-common-bc
>[  488.226465] [drm:intel_display_power_get] enabling dpio-common-d
>[  488.262403] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  488.262410] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  488.611618] [drm:vlv_power_sequencer_pipe] picked pipe A power sequencer for port C
>[  488.611635] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06
>[  488.611642] [drm:vlv_power_sequencer_kick] kicking pipe A power sequencer for port C
>[  488.641423] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[  488.641431] [drm:wait_panel_status] Wait complete
>[  488.641441] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  488.641447] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled
>[  488.876437] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[  488.924438] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[  488.936473] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  488.936485] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:29:eDP-1] probed modes :
>[  488.936494] [drm:drm_mode_debug_printmodeline] Modeline 30:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  488.936513] [drm:drm_mode_getconnector] [CONNECTOR:29:?]
>[  488.936629] [drm:add_framebuffer_internal] [FB:40]
>[  488.936646] [drm:add_framebuffer_internal] [FB:41]
>[  488.936655] [drm:drm_mode_setcrtc] [CRTC:13]
>[  488.936663] [drm:drm_mode_setcrtc] [CONNECTOR:29:eDP-1]
>[  488.936670] [drm:intel_crtc_set_config] [CRTC:13] [FB:40] #connectors=1 (x y) (0 0)
>[  488.936678] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  488.936683] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=1, fb_changed=0
>[  488.936687] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  488.936692] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  488.936697] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  488.936701] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  488.936708] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  488.936714] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  488.936721] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  488.936727] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[  488.936731] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[  488.936738] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  488.936743] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  488.936746] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  488.936750] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  488.936756] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  488.936762] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  488.936767] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  488.936770] [drm:intel_dump_pipe_config] requested mode:
>[  488.936777] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  488.936781] [drm:intel_dump_pipe_config] adjusted mode:
>[  488.936788] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  488.936794] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  488.936798] [drm:intel_dump_pipe_config] port clock: 270000
>[  488.936802] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  488.936828] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  488.936833] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  488.936836] [drm:intel_dump_pipe_config] ips: 0
>[  488.936840] [drm:intel_dump_pipe_config] double wide: 0
>[  489.054449] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  489.054464] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0000
>[  489.066502] [drm:vlv_detach_power_sequencer] detaching pipe A power sequencer from port C
>[  489.066513] [drm:vlv_init_panel_power_sequencer] initializing pipe B power sequencer for port C
>[  489.066524] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06
>[  489.078441] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  489.078450] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  489.655661] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[  489.655671] [drm:wait_panel_status] Wait complete
>[  489.655681] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  489.655687] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled
>[  489.856642] [drm:edp_panel_on] Turn eDP port C panel power on
>[  489.856656] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  489.856665] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008
>[  489.856670] [drm:wait_panel_status] Wait complete
>[  489.856677] [drm:wait_panel_on] Wait for panel power on
>[  489.856684] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b
>[  490.010489] [drm:wait_panel_status] Wait complete
>[  490.010502] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  490.010513] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  490.058526] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  490.058538] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  490.194493] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  490.266496] [drm:intel_dp_start_link_train] clock recovery OK
>[  490.338556] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  490.362564] [drm:g4x_check_srwm] SR watermark: display plane 54, cursor 2
>[  490.362571] [drm:g4x_check_srwm] SR watermark: display plane 106, cursor 2
>[  490.362578] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=39, cursor=2, C: plane=2, cursor=2, SR: plane=54, cursor=2
>[  490.362586] [drm:intel_set_memory_cxsr] memory self-refresh is enabled
>[  490.362597] [drm:intel_edp_backlight_on] 
>[  490.362602] [drm:intel_panel_enable_backlight] pipe B
>[  490.362608] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3906
>[  490.386553] [drm:i9xx_update_primary_plane] Writing base 0089C000 00000000 0 0 3840
>[  490.386576] [drm:intel_connector_check_state] [CONNECTOR:29:eDP-1]
>[  490.386591] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  490.386596] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  490.386602] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  490.386608] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  490.386614] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  490.386620] [drm:check_crtc_state] [CRTC:8]
>[  490.386626] [drm:check_crtc_state] [CRTC:13]
>[  490.394511] [drm:check_crtc_state] [CRTC:18]
>[  491.855575] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  491.855590] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  498.149727] [drm:intel_crtc_set_config] [CRTC:13] [NOFB]
>[  498.149741] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=1, fb_changed=0
>[  498.149747] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [NOCRTC]
>[  498.149751] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  498.149756] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  498.149761] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  498.149768] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[  498.150844] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  498.163350] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
>[  498.184954] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  498.184967] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  498.196950] [drm:intel_edp_backlight_off] 
>[  498.421866] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  498.457888] [drm:edp_panel_off] Turn eDP port C panel power off
>[  498.457897] [drm:wait_panel_off] Wait for panel power off time
>[  498.457906] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[  498.501867] [drm:wait_panel_status] Wait complete
>[  498.527896] [drm:intel_dp_link_down] 
>[  498.602878] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  498.602888] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=2, cursor=2, C: plane=2, cursor=2, SR: plane=0, cursor=0
>[  498.612870] [drm:intel_display_power_put] disabling dpio-common-d
>[  498.624870] [drm:intel_display_power_put] disabling dpio-common-bc
>[  498.636892] [drm:intel_display_power_put] disabling pipe-a
>[  498.648903] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  498.648910] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  498.648915] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  498.648920] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  498.648924] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  498.648928] [drm:check_crtc_state] [CRTC:8]
>[  498.648933] [drm:check_crtc_state] [CRTC:13]
>[  498.648937] [drm:check_crtc_state] [CRTC:18]
>[  498.650208] [drm:add_framebuffer_internal] [FB:40]
>[  498.650226] [drm:add_framebuffer_internal] [FB:41]
>[  498.650237] [drm:drm_mode_setcrtc] [CRTC:13]
>[  498.650246] [drm:drm_mode_setcrtc] [CONNECTOR:29:eDP-1]
>[  498.650253] [drm:intel_crtc_set_config] [CRTC:13] [FB:40] #connectors=1 (x y) (0 0)
>[  498.650259] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  498.650264] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=1, fb_changed=0
>[  498.650268] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  498.650274] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  498.650278] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  498.650283] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  498.650290] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  498.650296] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  498.650304] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  498.650320] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  498.650324] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  498.650330] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  498.650335] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  498.650339] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  498.650343] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  498.650348] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  498.650354] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  498.650359] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  498.650363] [drm:intel_dump_pipe_config] requested mode:
>[  498.650370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  498.650374] [drm:intel_dump_pipe_config] adjusted mode:
>[  498.650381] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  498.650388] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  498.650401] [drm:intel_dump_pipe_config] port clock: 270000
>[  498.650416] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  498.650433] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  498.650450] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  498.650466] [drm:intel_dump_pipe_config] ips: 0
>[  498.650482] [drm:intel_dump_pipe_config] double wide: 0
>[  498.653886] [drm:intel_display_power_get] enabling pipe-a
>[  498.673927] [drm:intel_display_power_get] enabling dpio-common-bc
>[  498.685874] [drm:intel_display_power_get] enabling dpio-common-d
>[  498.793888] [drm:vlv_init_panel_power_sequencer] initializing pipe B power sequencer for port C
>[  498.793904] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06
>[  498.805878] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  498.805887] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  499.059046] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000
>[  499.223904] [drm:wait_panel_status] Wait complete
>[  499.223922] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  499.223928] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled
>[  499.425087] [drm:edp_panel_on] Turn eDP port C panel power on
>[  499.425101] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  499.425110] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008
>[  499.425115] [drm:wait_panel_status] Wait complete
>[  499.425122] [drm:wait_panel_on] Wait for panel power on
>[  499.425129] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b
>[  499.578920] [drm:wait_panel_status] Wait complete
>[  499.578934] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  499.578945] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  499.626922] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  499.626934] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  499.762948] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  499.834925] [drm:intel_dp_start_link_train] clock recovery OK
>[  499.906928] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  499.931018] [drm:g4x_check_srwm] SR watermark: display plane 107, cursor 2
>[  499.931025] [drm:g4x_check_srwm] SR watermark: display plane 211, cursor 2
>[  499.931032] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=61, cursor=2, C: plane=2, cursor=2, SR: plane=107, cursor=2
>[  499.931040] [drm:intel_set_memory_cxsr] memory self-refresh is enabled
>[  499.931051] [drm:intel_edp_backlight_on] 
>[  499.931056] [drm:intel_panel_enable_backlight] pipe B
>[  499.931062] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3906
>[  499.954943] [drm:i9xx_update_primary_plane] Writing base 0089C000 00000000 0 0 7680
>[  499.954966] [drm:intel_connector_check_state] [CONNECTOR:29:eDP-1]
>[  499.954980] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  499.954986] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  499.954992] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  499.954998] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  499.955004] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  499.955010] [drm:check_crtc_state] [CRTC:8]
>[  499.955016] [drm:check_crtc_state] [CRTC:13]
>[  499.962999] [drm:check_crtc_state] [CRTC:18]
>[  499.964961] [drm:intel_set_cpu_fifo_underrun_reporting [i915]] *ERROR* pipe B underrun
>[  499.964998] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
>[  502.640061] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  502.640076] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  507.124521] [drm:intel_crtc_set_config] [CRTC:13] [NOFB]
>[  507.124535] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=1, fb_changed=0
>[  507.124541] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [NOCRTC]
>[  507.124545] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  507.124550] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  507.124555] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  507.124562] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[  507.126249] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  507.155256] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  507.155272] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  507.167254] [drm:intel_edp_backlight_off] 
>[  507.392323] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  507.428267] [drm:edp_panel_off] Turn eDP port C panel power off
>[  507.428276] [drm:wait_panel_off] Wait for panel power off time
>[  507.428285] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[  507.472271] [drm:wait_panel_status] Wait complete
>[  507.498275] [drm:intel_dp_link_down] 
>[  507.573357] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  507.573367] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=2, cursor=2, C: plane=2, cursor=2, SR: plane=0, cursor=0
>[  507.583274] [drm:intel_display_power_put] disabling dpio-common-d
>[  507.595325] [drm:intel_display_power_put] disabling dpio-common-bc
>[  507.607274] [drm:intel_display_power_put] disabling pipe-a
>[  507.619281] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  507.619288] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  507.619293] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  507.619298] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  507.619302] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  507.619307] [drm:check_crtc_state] [CRTC:8]
>[  507.619312] [drm:check_crtc_state] [CRTC:13]
>[  507.619316] [drm:check_crtc_state] [CRTC:18]
>[  507.622394] [drm:add_framebuffer_internal] [FB:40]
>[  507.622412] [drm:add_framebuffer_internal] [FB:41]
>[  507.622423] [drm:drm_mode_setcrtc] [CRTC:13]
>[  507.622432] [drm:drm_mode_setcrtc] [CONNECTOR:29:eDP-1]
>[  507.622439] [drm:intel_crtc_set_config] [CRTC:13] [FB:40] #connectors=1 (x y) (0 0)
>[  507.622446] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  507.622451] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=1, fb_changed=0
>[  507.622455] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  507.622461] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  507.622465] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  507.622470] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  507.622476] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  507.622483] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  507.622488] [drm:connected_sink_compute_bpp] clamping display bpp (was 30) to EDID reported max of 24
>[  507.622496] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  507.622512] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  507.622517] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  507.622524] [drm:intel_modeset_pipe_config] plane bpp: 30, pipe bpp: 24, dithering: 1
>[  507.622528] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  507.622532] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  507.622536] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  507.622542] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  507.622547] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  507.622552] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  507.622556] [drm:intel_dump_pipe_config] requested mode:
>[  507.622564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  507.622567] [drm:intel_dump_pipe_config] adjusted mode:
>[  507.622574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  507.622581] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  507.622585] [drm:intel_dump_pipe_config] port clock: 270000
>[  507.622589] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  507.622594] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  507.622599] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  507.622603] [drm:intel_dump_pipe_config] ips: 0
>[  507.622606] [drm:intel_dump_pipe_config] double wide: 0
>[  507.626235] [drm:intel_display_power_get] enabling pipe-a
>[  507.646327] [drm:intel_display_power_get] enabling dpio-common-bc
>[  507.658277] [drm:intel_display_power_get] enabling dpio-common-d
>[  507.766292] [drm:vlv_init_panel_power_sequencer] initializing pipe B power sequencer for port C
>[  507.766308] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06
>[  507.778288] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  507.778297] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  508.029448] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000
>[  508.194308] [drm:wait_panel_status] Wait complete
>[  508.194325] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  508.194331] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled
>[  508.395332] [drm:edp_panel_on] Turn eDP port C panel power on
>[  508.395346] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  508.395355] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008
>[  508.395360] [drm:wait_panel_status] Wait complete
>[  508.395367] [drm:wait_panel_on] Wait for panel power on
>[  508.395374] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b
>[  508.549378] [drm:wait_panel_status] Wait complete
>[  508.549388] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  508.549398] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  508.597349] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  508.597362] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  508.733329] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  508.805329] [drm:intel_dp_start_link_train] clock recovery OK
>[  508.877371] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  508.901394] [drm:g4x_check_srwm] SR watermark: display plane 107, cursor 2
>[  508.901401] [drm:g4x_check_srwm] SR watermark: display plane 211, cursor 2
>[  508.901408] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=61, cursor=2, C: plane=2, cursor=2, SR: plane=107, cursor=2
>[  508.901416] [drm:intel_set_memory_cxsr] memory self-refresh is enabled
>[  508.901427] [drm:intel_edp_backlight_on] 
>[  508.901431] [drm:intel_panel_enable_backlight] pipe B
>[  508.901438] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3906
>[  508.925400] [drm:i9xx_update_primary_plane] Writing base 0089C000 00000000 0 0 7680
>[  508.925422] [drm:intel_connector_check_state] [CONNECTOR:29:eDP-1]
>[  508.925437] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  508.925443] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  508.925449] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  508.925455] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  508.925460] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  508.925466] [drm:check_crtc_state] [CRTC:8]
>[  508.925472] [drm:check_crtc_state] [CRTC:13]
>[  508.933344] [drm:check_crtc_state] [CRTC:18]
>[  511.616536] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  511.616551] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  517.533104] [drm:intel_crtc_set_config] [CRTC:13] [NOFB]
>[  517.533119] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=1, fb_changed=0
>[  517.533125] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [NOCRTC]
>[  517.533129] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  517.533133] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  517.533138] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  517.533146] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[  517.534683] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  517.535526] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
>[  517.558731] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  517.558744] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  517.570724] [drm:intel_edp_backlight_off] 
>[  517.795776] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  517.831739] [drm:edp_panel_off] Turn eDP port C panel power off
>[  517.831751] [drm:wait_panel_off] Wait for panel power off time
>[  517.831760] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[  517.875741] [drm:wait_panel_status] Wait complete
>[  517.901739] [drm:intel_dp_link_down] 
>[  517.976837] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  517.976847] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=2, cursor=2, C: plane=2, cursor=2, SR: plane=0, cursor=0
>[  517.986743] [drm:intel_display_power_put] disabling dpio-common-d
>[  517.998790] [drm:intel_display_power_put] disabling dpio-common-bc
>[  518.010743] [drm:intel_display_power_put] disabling pipe-a
>[  518.022750] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  518.022757] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  518.022762] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  518.022767] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  518.022771] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  518.022775] [drm:check_crtc_state] [CRTC:8]
>[  518.022780] [drm:check_crtc_state] [CRTC:13]
>[  518.022784] [drm:check_crtc_state] [CRTC:18]
>[  518.024577] [drm:add_framebuffer_internal] [FB:40]
>[  518.024595] [drm:add_framebuffer_internal] [FB:41]
>[  518.024606] [drm:drm_mode_setcrtc] [CRTC:13]
>[  518.024614] [drm:drm_mode_setcrtc] [CONNECTOR:29:eDP-1]
>[  518.024621] [drm:intel_crtc_set_config] [CRTC:13] [FB:40] #connectors=1 (x y) (0 0)
>[  518.024629] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  518.024634] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=1, fb_changed=0
>[  518.024638] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  518.024644] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  518.024648] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  518.024653] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  518.024660] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  518.024666] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  518.024674] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  518.024721] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  518.024726] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  518.024733] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  518.024738] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  518.024753] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  518.024769] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  518.024787] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  518.024804] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  518.024817] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  518.024821] [drm:intel_dump_pipe_config] requested mode:
>[  518.024829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  518.024832] [drm:intel_dump_pipe_config] adjusted mode:
>[  518.024839] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  518.024846] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  518.024850] [drm:intel_dump_pipe_config] port clock: 270000
>[  518.024854] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  518.024858] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  518.024863] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  518.024867] [drm:intel_dump_pipe_config] ips: 0
>[  518.024870] [drm:intel_dump_pipe_config] double wide: 0
>[  518.028707] [drm:intel_display_power_get] enabling pipe-a
>[  518.048755] [drm:intel_display_power_get] enabling dpio-common-bc
>[  518.060745] [drm:intel_display_power_get] enabling dpio-common-d
>[  518.168763] [drm:vlv_init_panel_power_sequencer] initializing pipe B power sequencer for port C
>[  518.168779] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06
>[  518.180751] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  518.180760] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  518.432919] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000
>[  518.597777] [drm:wait_panel_status] Wait complete
>[  518.597794] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  518.597800] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled
>[  518.798947] [drm:edp_panel_on] Turn eDP port C panel power on
>[  518.798961] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  518.798970] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008
>[  518.798975] [drm:wait_panel_status] Wait complete
>[  518.798982] [drm:wait_panel_on] Wait for panel power on
>[  518.798989] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b
>[  518.952858] [drm:wait_panel_status] Wait complete
>[  518.952871] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  518.952881] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  519.000820] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  519.000833] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  519.136798] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  519.208802] [drm:intel_dp_start_link_train] clock recovery OK
>[  519.280830] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  519.302956] [drm:g4x_check_srwm] SR watermark: display plane 107, cursor 2
>[  519.302964] [drm:g4x_check_srwm] SR watermark: display plane 211, cursor 2
>[  519.302971] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=61, cursor=2, C: plane=2, cursor=2, SR: plane=107, cursor=2
>[  519.302979] [drm:intel_set_memory_cxsr] memory self-refresh is enabled
>[  519.302989] [drm:intel_edp_backlight_on] 
>[  519.302994] [drm:intel_panel_enable_backlight] pipe B
>[  519.303001] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3906
>[  519.326819] [drm:i9xx_update_primary_plane] Writing base 0089C000 00000000 0 0 7680
>[  519.326841] [drm:intel_connector_check_state] [CONNECTOR:29:eDP-1]
>[  519.326856] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  519.326862] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  519.326868] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  519.326874] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  519.326879] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  519.326885] [drm:check_crtc_state] [CRTC:8]
>[  519.326891] [drm:check_crtc_state] [CRTC:13]
>[  519.334845] [drm:check_crtc_state] [CRTC:18]
>[  522.016981] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  522.016996] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  526.496246] [drm:intel_crtc_set_config] [CRTC:13] [NOFB]
>[  526.496260] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=1, fb_changed=0
>[  526.496266] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [NOCRTC]
>[  526.496270] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  526.496275] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  526.496280] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  526.496287] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[  526.498089] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  526.503783] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
>[  526.528151] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  526.528164] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  526.540130] [drm:intel_edp_backlight_off] 
>[  526.765286] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  526.801139] [drm:edp_panel_off] Turn eDP port C panel power off
>[  526.801149] [drm:wait_panel_off] Wait for panel power off time
>[  526.801157] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[  526.845145] [drm:wait_panel_status] Wait complete
>[  526.871147] [drm:intel_dp_link_down] 
>[  526.946155] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  526.946165] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=2, cursor=2, C: plane=2, cursor=2, SR: plane=0, cursor=0
>[  526.956151] [drm:intel_display_power_put] disabling dpio-common-d
>[  526.968146] [drm:intel_display_power_put] disabling dpio-common-bc
>[  526.980198] [drm:intel_display_power_put] disabling pipe-a
>[  526.992154] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  526.992161] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  526.992166] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  526.992171] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  526.992175] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  526.992179] [drm:check_crtc_state] [CRTC:8]
>[  526.992184] [drm:check_crtc_state] [CRTC:13]
>[  526.992189] [drm:check_crtc_state] [CRTC:18]
>[  526.995179] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  526.995193] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  526.995204] [drm:drm_mode_getconnector] [CONNECTOR:29:?]
>[  526.995211] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:29:eDP-1]
>[  526.995216] [drm:intel_dp_detect] [CONNECTOR:29:eDP-1]
>[  526.995223] [drm:intel_display_power_get] enabling pipe-a
>[  527.007155] [drm:intel_display_power_get] enabling dpio-common-bc
>[  527.019150] [drm:intel_display_power_get] enabling dpio-common-d
>[  527.055155] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  527.055163] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  527.402176] [drm:vlv_power_sequencer_pipe] picked pipe A power sequencer for port C
>[  527.402190] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06
>[  527.402197] [drm:vlv_power_sequencer_kick] kicking pipe A power sequencer for port C
>[  527.432236] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[  527.432244] [drm:wait_panel_status] Wait complete
>[  527.432253] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  527.432259] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled
>[  527.667205] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[  527.715235] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[  527.727202] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  527.727214] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:29:eDP-1] probed modes :
>[  527.727223] [drm:drm_mode_debug_printmodeline] Modeline 30:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  527.727242] [drm:drm_mode_getconnector] [CONNECTOR:29:?]
>[  527.727273] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  527.727282] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  527.727291] [drm:drm_mode_getconnector] [CONNECTOR:22:?]
>[  527.727297] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:22:HDMI-A-1]
>[  527.727302] [drm:intel_hdmi_detect] [CONNECTOR:22:HDMI-A-1]
>[  527.740140] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  527.740148] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  527.752185] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:22:HDMI-A-1] disconnected
>[  527.752200] [drm:drm_mode_getconnector] [CONNECTOR:22:?]
>[  527.752206] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:22:HDMI-A-1]
>[  527.752210] [drm:intel_hdmi_detect] [CONNECTOR:22:HDMI-A-1]
>[  527.765142] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  527.765149] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  527.777187] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:22:HDMI-A-1] disconnected
>[  527.777211] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  527.777221] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  527.777230] [drm:drm_mode_getconnector] [CONNECTOR:22:?]
>[  527.777235] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:22:HDMI-A-1]
>[  527.777240] [drm:intel_hdmi_detect] [CONNECTOR:22:HDMI-A-1]
>[  527.790143] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  527.790150] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  527.802187] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:22:HDMI-A-1] disconnected
>[  527.802201] [drm:drm_mode_getconnector] [CONNECTOR:22:?]
>[  527.802207] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:22:HDMI-A-1]
>[  527.802212] [drm:intel_hdmi_detect] [CONNECTOR:22:HDMI-A-1]
>[  527.815144] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  527.815152] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  527.827188] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:22:HDMI-A-1] disconnected
>[  527.827211] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  527.827221] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  527.827230] [drm:drm_mode_getconnector] [CONNECTOR:22:?]
>[  527.827235] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:22:HDMI-A-1]
>[  527.827240] [drm:intel_hdmi_detect] [CONNECTOR:22:HDMI-A-1]
>[  527.840145] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  527.840152] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  527.852286] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:22:HDMI-A-1] disconnected
>[  527.852299] [drm:drm_mode_getconnector] [CONNECTOR:22:?]
>[  527.852305] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:22:HDMI-A-1]
>[  527.852310] [drm:intel_hdmi_detect] [CONNECTOR:22:HDMI-A-1]
>[  527.865146] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  527.865154] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  527.877225] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:22:HDMI-A-1] disconnected
>[  527.877248] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  527.877259] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  527.877268] [drm:drm_mode_getconnector] [CONNECTOR:27:?]
>[  527.877273] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:27:DP-1]
>[  527.877278] [drm:intel_dp_detect] [CONNECTOR:27:DP-1]
>[  527.901191] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:27:DP-1] disconnected
>[  527.901204] [drm:drm_mode_getconnector] [CONNECTOR:27:?]
>[  527.901210] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:27:DP-1]
>[  527.901214] [drm:intel_dp_detect] [CONNECTOR:27:DP-1]
>[  527.925253] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:27:DP-1] disconnected
>[  527.925273] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  527.925283] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  527.925292] [drm:drm_mode_getconnector] [CONNECTOR:27:?]
>[  527.925297] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:27:DP-1]
>[  527.925301] [drm:intel_dp_detect] [CONNECTOR:27:DP-1]
>[  527.949193] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:27:DP-1] disconnected
>[  527.949207] [drm:drm_mode_getconnector] [CONNECTOR:27:?]
>[  527.949213] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:27:DP-1]
>[  527.949217] [drm:intel_dp_detect] [CONNECTOR:27:DP-1]
>[  527.973307] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:27:DP-1] disconnected
>[  527.973327] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  527.973338] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  527.973352] [drm:drm_mode_getconnector] [CONNECTOR:27:?]
>[  527.973357] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:27:DP-1]
>[  527.973361] [drm:intel_dp_detect] [CONNECTOR:27:DP-1]
>[  527.997195] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:27:DP-1] disconnected
>[  527.997209] [drm:drm_mode_getconnector] [CONNECTOR:27:?]
>[  527.997215] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:27:DP-1]
>[  527.997219] [drm:intel_dp_detect] [CONNECTOR:27:DP-1]
>[  528.021196] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:27:DP-1] disconnected
>[  528.021218] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  528.021228] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  528.021236] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[  528.021242] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2]
>[  528.021246] [drm:intel_hdmi_detect] [CONNECTOR:35:HDMI-A-2]
>[  528.034153] [drm:gmbus_xfer] GMBUS [i915 gmbus panel] NAK for addr: 0050 r(1)
>[  528.034161] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus panel
>[  528.046266] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] disconnected
>[  528.046279] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[  528.046285] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2]
>[  528.046290] [drm:intel_hdmi_detect] [CONNECTOR:35:HDMI-A-2]
>[  528.059155] [drm:gmbus_xfer] GMBUS [i915 gmbus panel] NAK for addr: 0050 r(1)
>[  528.059163] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus panel
>[  528.071224] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] disconnected
>[  528.071247] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  528.071257] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  528.071266] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[  528.071271] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2]
>[  528.071275] [drm:intel_hdmi_detect] [CONNECTOR:35:HDMI-A-2]
>[  528.084156] [drm:gmbus_xfer] GMBUS [i915 gmbus panel] NAK for addr: 0050 r(1)
>[  528.084163] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus panel
>[  528.096200] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] disconnected
>[  528.096213] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[  528.096219] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2]
>[  528.096223] [drm:intel_hdmi_detect] [CONNECTOR:35:HDMI-A-2]
>[  528.109157] [drm:gmbus_xfer] GMBUS [i915 gmbus panel] NAK for addr: 0050 r(1)
>[  528.109165] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus panel
>[  528.121201] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] disconnected
>[  528.121225] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  528.121236] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  528.121244] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[  528.121250] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2]
>[  528.121254] [drm:intel_hdmi_detect] [CONNECTOR:35:HDMI-A-2]
>[  528.134158] [drm:gmbus_xfer] GMBUS [i915 gmbus panel] NAK for addr: 0050 r(1)
>[  528.134166] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus panel
>[  528.146202] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] disconnected
>[  528.146216] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[  528.146222] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2]
>[  528.146226] [drm:intel_hdmi_detect] [CONNECTOR:35:HDMI-A-2]
>[  528.159159] [drm:gmbus_xfer] GMBUS [i915 gmbus panel] NAK for addr: 0050 r(1)
>[  528.159167] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus panel
>[  528.171204] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:HDMI-A-2] disconnected
>[  528.171226] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  528.171237] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  528.171245] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[  528.171250] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-2]
>[  528.171255] [drm:intel_dp_detect] [CONNECTOR:37:DP-2]
>[  528.195228] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-2] disconnected
>[  528.195241] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[  528.195246] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-2]
>[  528.195251] [drm:intel_dp_detect] [CONNECTOR:37:DP-2]
>[  528.219206] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-2] disconnected
>[  528.219229] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  528.219239] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  528.219248] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[  528.219253] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-2]
>[  528.219257] [drm:intel_dp_detect] [CONNECTOR:37:DP-2]
>[  528.243251] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-2] disconnected
>[  528.243265] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[  528.243270] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-2]
>[  528.243275] [drm:intel_dp_detect] [CONNECTOR:37:DP-2]
>[  528.267208] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-2] disconnected
>[  528.267227] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  528.267237] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  528.267245] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[  528.267250] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-2]
>[  528.267255] [drm:intel_dp_detect] [CONNECTOR:37:DP-2]
>[  528.291302] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-2] disconnected
>[  528.291316] [drm:drm_mode_getconnector] [CONNECTOR:37:?]
>[  528.291322] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-2]
>[  528.291327] [drm:intel_dp_detect] [CONNECTOR:37:DP-2]
>[  528.315210] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:37:DP-2] disconnected
>[  528.315464] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  528.315470] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  528.315477] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  528.315480] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  528.315484] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=1, fb_changed=0
>[  528.315485] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  528.315488] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  528.315490] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  528.315493] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  528.315497] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  528.315501] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  528.315507] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  528.315520] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  528.315522] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  528.315526] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  528.315528] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  528.315530] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  528.315532] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  528.315535] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  528.315539] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  528.315542] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  528.315543] [drm:intel_dump_pipe_config] requested mode:
>[  528.315549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  528.315550] [drm:intel_dump_pipe_config] adjusted mode:
>[  528.315555] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  528.315559] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  528.315561] [drm:intel_dump_pipe_config] port clock: 270000
>[  528.315563] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  528.315565] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  528.315568] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  528.315569] [drm:intel_dump_pipe_config] ips: 0
>[  528.315571] [drm:intel_dump_pipe_config] double wide: 0
>[  528.429222] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  528.429231] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0000
>[  528.441217] [drm:vlv_detach_power_sequencer] detaching pipe A power sequencer from port C
>[  528.441222] [drm:vlv_init_panel_power_sequencer] initializing pipe B power sequencer for port C
>[  528.441230] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06
>[  528.453271] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  528.453275] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  529.030392] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[  529.030396] [drm:wait_panel_status] Wait complete
>[  529.030403] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  529.030407] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled
>[  529.231393] [drm:edp_panel_on] Turn eDP port C panel power on
>[  529.231399] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  529.231406] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008
>[  529.231409] [drm:wait_panel_status] Wait complete
>[  529.231415] [drm:wait_panel_on] Wait for panel power on
>[  529.231420] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b
>[  529.385304] [drm:wait_panel_status] Wait complete
>[  529.385310] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  529.385319] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  529.433353] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  529.433361] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  529.569271] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  529.639276] [drm:intel_dp_start_link_train] clock recovery OK
>[  529.711271] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  529.735400] [drm:g4x_check_srwm] SR watermark: display plane 107, cursor 2
>[  529.735403] [drm:g4x_check_srwm] SR watermark: display plane 211, cursor 2
>[  529.735408] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=61, cursor=2, C: plane=2, cursor=2, SR: plane=107, cursor=2
>[  529.735414] [drm:intel_set_memory_cxsr] memory self-refresh is enabled
>[  529.735422] [drm:intel_edp_backlight_on] 
>[  529.735424] [drm:intel_panel_enable_backlight] pipe B
>[  529.735429] [drm:intel_panel_actually_set_backlight] set backlight PWM = 3906
>[  529.759286] [drm:i9xx_update_primary_plane] Writing base 000A0000 00000000 0 0 7680
>[  529.759305] [drm:intel_connector_check_state] [CONNECTOR:29:eDP-1]
>[  529.759317] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  529.759321] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  529.759324] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  529.759328] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  529.759331] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  529.759335] [drm:check_crtc_state] [CRTC:8]
>[  529.759339] [drm:check_crtc_state] [CRTC:13]
>[  529.767346] [drm:check_crtc_state] [CRTC:18]
>[  529.767356] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  529.767362] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  529.767366] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  529.767380] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  529.767385] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  529.767388] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  529.767412] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  529.767416] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  529.767418] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  529.790423] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 624 MHz (60)
>[  529.793110] [drm:intel_set_cpu_fifo_underrun_reporting [i915]] *ERROR* pipe B underrun
>[  529.793166] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  529.793173] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  529.793177] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  529.793183] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  529.793187] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  529.793190] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  529.793193] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  529.793197] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  529.793199] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  529.793307] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
>[  529.892246] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 208 MHz (20)
>[  530.649323] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  530.649338] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007

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Attachments on bug 85908: 108938

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