Attachment 109327 Details for Bug 86189 – dmesg

dmesg

dmesg_bsw_missed_1112.txt (text/plain), 127.75 KB, created by lu hua on 2014-11-12 07:34:44 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: lu hua

Created: 2014-11-12 07:34:44 UTC

Size: 127.75 KB

patch

obsolete

>[  432.107707] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  432.107715] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  432.107731] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  432.107736] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  432.107742] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  432.107747] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  432.107751] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  432.107789] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  432.107796] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  432.107802] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  432.107807] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  432.107811] [drm:intel_dump_pipe_config] requested mode:
>[  432.107818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  432.107822] [drm:intel_dump_pipe_config] adjusted mode:
>[  432.107829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  432.107836] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  432.107840] [drm:intel_dump_pipe_config] port clock: 270000
>[  432.107844] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  432.107848] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  432.107853] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  432.107857] [drm:intel_dump_pipe_config] ips: 0
>[  432.107860] [drm:intel_dump_pipe_config] double wide: 0
>[  432.107866] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  432.108798] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  432.108806] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  432.108814] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  432.116611] gem_exec_blt: executing
>[  432.116922] [drm:i915_gem_open] 
>[  432.118011] [drm:i915_gem_open] 
>[  432.341994] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  432.421663] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 437 MHz (42)
>[  432.506329] [drm:valleyview_set_rps] GPU freq request from 437 MHz (42) to 478 MHz (46)
>[  432.590863] [drm:valleyview_set_rps] GPU freq request from 478 MHz (46) to 562 MHz (54)
>[  432.675120] [drm:valleyview_set_rps] GPU freq request from 562 MHz (54) to 624 MHz (60)
>[  433.000965] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  433.002076] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  433.002086] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  433.002093] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  433.002100] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  433.002108] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  433.002118] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  433.002124] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  433.002129] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  433.002136] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  433.002144] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  433.002160] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  433.002165] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  433.002171] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  433.002176] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  433.002180] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  433.002184] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  433.002189] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  433.002195] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  433.002200] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  433.002204] [drm:intel_dump_pipe_config] requested mode:
>[  433.002212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  433.002220] [drm:intel_dump_pipe_config] adjusted mode:
>[  433.002227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  433.002233] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  433.002237] [drm:intel_dump_pipe_config] port clock: 270000
>[  433.002241] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  433.002245] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  433.002250] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  433.002254] [drm:intel_dump_pipe_config] ips: 0
>[  433.002257] [drm:intel_dump_pipe_config] double wide: 0
>[  433.002263] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  433.002269] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  433.002274] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  433.002279] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  433.003089] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  433.006953] [drm:i915_ring_test_irq_set] Masking interrupts on rings 0x00000000
>[  433.015753] gem_exec_blt: executing
>[  433.016046] [drm:i915_gem_open] 
>[  433.016299] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 624 MHz (60)
>[  433.018129] [drm:i915_gem_open] 
>[  433.018473] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  433.092919] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  433.092931] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  433.092938] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  433.092945] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  433.092952] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  433.092959] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  433.092964] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  433.092970] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  433.092977] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  433.092985] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  433.093001] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  433.093006] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  433.093012] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  433.093017] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  433.093021] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  433.093025] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  433.093031] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  433.093036] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  433.093041] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  433.093045] [drm:intel_dump_pipe_config] requested mode:
>[  433.093053] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  433.093056] [drm:intel_dump_pipe_config] adjusted mode:
>[  433.093063] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  433.093069] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  433.093073] [drm:intel_dump_pipe_config] port clock: 270000
>[  433.093077] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  433.093082] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  433.093087] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  433.093090] [drm:intel_dump_pipe_config] ips: 0
>[  433.093094] [drm:intel_dump_pipe_config] double wide: 0
>[  433.093099] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  433.093105] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  433.093110] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  433.093115] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  433.100649] gem_exec_blt: executing
>[  433.100956] [drm:i915_gem_open] 
>[  433.101213] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  433.102993] [drm:i915_gem_open] 
>[  433.222208] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  433.266930] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 437 MHz (42)
>[  433.340891] [drm:valleyview_set_rps] GPU freq request from 437 MHz (42) to 416 MHz (40)
>[  433.341661] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  433.341673] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  433.341679] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  433.341687] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  433.341694] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  433.341701] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  433.341706] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  433.341712] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  433.341718] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  433.341726] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  433.341743] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  433.341747] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  433.341754] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  433.341759] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  433.341763] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  433.341767] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  433.341772] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  433.341778] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  433.341783] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  433.341787] [drm:intel_dump_pipe_config] requested mode:
>[  433.341794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  433.341798] [drm:intel_dump_pipe_config] adjusted mode:
>[  433.341805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  433.341811] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  433.341850] [drm:intel_dump_pipe_config] port clock: 270000
>[  433.341867] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  433.341883] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  433.341900] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  433.341916] [drm:intel_dump_pipe_config] ips: 0
>[  433.341933] [drm:intel_dump_pipe_config] double wide: 0
>[  433.341949] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  433.341955] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  433.341961] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  433.341966] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  433.342987] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  433.349402] gem_exec_blt: executing
>[  433.349676] [drm:i915_gem_open] 
>[  433.349965] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 624 MHz (60)
>[  433.352126] [drm:i915_gem_open] 
>[  433.353053] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  433.355969] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  433.435864] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  433.520375] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  433.612407] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  433.689367] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 437 MHz (42)
>[  433.773865] [drm:valleyview_set_rps] GPU freq request from 437 MHz (42) to 478 MHz (46)
>[  433.858565] [drm:valleyview_set_rps] GPU freq request from 478 MHz (46) to 562 MHz (54)
>[  433.942837] [drm:valleyview_set_rps] GPU freq request from 562 MHz (54) to 624 MHz (60)
>[  434.279289] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  434.279942] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  434.279955] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  434.279962] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  434.279969] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  434.279977] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  434.279984] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  434.279989] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  434.279994] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  434.280001] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  434.280010] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  434.280029] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  434.280033] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  434.280040] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  434.280045] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  434.280049] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  434.280053] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  434.280058] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  434.280064] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  434.280069] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  434.280073] [drm:intel_dump_pipe_config] requested mode:
>[  434.280080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  434.280084] [drm:intel_dump_pipe_config] adjusted mode:
>[  434.280091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  434.280097] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  434.280101] [drm:intel_dump_pipe_config] port clock: 270000
>[  434.280105] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  434.280110] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  434.280115] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  434.280119] [drm:intel_dump_pipe_config] ips: 0
>[  434.280126] [drm:intel_dump_pipe_config] double wide: 0
>[  434.280132] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  434.280138] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  434.280143] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  434.280148] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  434.280987] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  445.823160] [drm:i915_error_state_write] Resetting error state
>[  445.826553] [drm:i915_ring_test_irq_set] Masking interrupts on rings 0x0000000f
>[  445.835092] gem_exec_blt: executing
>[  445.835366] [drm:i915_gem_open] 
>[  445.836004] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 624 MHz (60)
>[  447.762024] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  447.763636] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  449.761729] [drm] Fake missed irq on bsd ring
>[  449.762460] [drm:i915_gem_open] 
>[  453.762032] [drm] Fake missed irq on blitter ring
>[  453.862968] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  453.881549] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  453.881560] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  453.881567] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  453.881574] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  453.881581] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  453.881588] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  453.881593] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  453.881599] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  453.881606] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  453.881614] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  453.881629] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  453.881633] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  453.881640] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  453.881645] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  453.881648] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  453.881652] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  453.881658] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  453.881663] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  453.881668] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  453.881672] [drm:intel_dump_pipe_config] requested mode:
>[  453.881680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  453.881684] [drm:intel_dump_pipe_config] adjusted mode:
>[  453.881690] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  453.881697] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  453.881701] [drm:intel_dump_pipe_config] port clock: 270000
>[  453.881705] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  453.881710] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  453.881714] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  453.881718] [drm:intel_dump_pipe_config] ips: 0
>[  453.881722] [drm:intel_dump_pipe_config] double wide: 0
>[  453.881727] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  453.881733] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  453.881767] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  453.881774] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  453.889341] gem_exec_blt: executing
>[  453.889611] [drm:i915_gem_open] 
>[  453.889901] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  453.891918] [drm:i915_gem_open] 
>[  454.015917] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  454.017827] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  454.031806] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  454.046346] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 395 MHz (38)
>[  454.047833] [drm:valleyview_set_rps] GPU freq request from 395 MHz (38) to 208 MHz (20)
>[  454.116395] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  454.171650] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  454.171661] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  454.171668] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  454.171675] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  454.171682] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  454.171689] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  454.171694] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  454.171700] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  454.171707] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  454.171715] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  454.171731] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  454.171735] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  454.171742] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  454.171747] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  454.171785] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  454.171790] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  454.171795] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  454.171801] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  454.171806] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  454.171810] [drm:intel_dump_pipe_config] requested mode:
>[  454.171818] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  454.171821] [drm:intel_dump_pipe_config] adjusted mode:
>[  454.171828] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  454.171835] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  454.171839] [drm:intel_dump_pipe_config] port clock: 270000
>[  454.171843] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  454.171848] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  454.171852] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  454.171856] [drm:intel_dump_pipe_config] ips: 0
>[  454.171860] [drm:intel_dump_pipe_config] double wide: 0
>[  454.171865] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  454.171872] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  454.171885] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  454.171902] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  454.179597] gem_exec_blt: executing
>[  454.179910] [drm:i915_gem_open] 
>[  454.180166] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  454.181970] [drm:i915_gem_open] 
>[  454.408071] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  454.409842] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  454.454427] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  454.538954] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  454.650151] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  454.651855] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  454.707965] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  454.792397] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  455.118244] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  455.119249] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  455.119262] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  455.119269] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  455.119276] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  455.119284] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  455.119290] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  455.119295] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  455.119301] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  455.119308] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  455.119316] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  455.119332] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  455.119336] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  455.119343] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  455.119348] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  455.119352] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  455.119356] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  455.119361] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  455.119367] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  455.119372] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  455.119375] [drm:intel_dump_pipe_config] requested mode:
>[  455.119383] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  455.119387] [drm:intel_dump_pipe_config] adjusted mode:
>[  455.119394] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  455.119400] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  455.119404] [drm:intel_dump_pipe_config] port clock: 270000
>[  455.119408] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  455.119413] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  455.119418] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  455.119421] [drm:intel_dump_pipe_config] ips: 0
>[  455.119425] [drm:intel_dump_pipe_config] double wide: 0
>[  455.119430] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  455.119436] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  455.119441] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  455.119447] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  455.132962] gem_exec_blt: executing
>[  455.133237] [drm:i915_gem_open] 
>[  455.133496] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  455.134977] [drm:i915_gem_open] 
>[  455.214378] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  455.214388] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  455.214395] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  455.214402] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  455.214409] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  455.214416] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  455.214421] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  455.214426] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  455.214433] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  455.214441] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  455.214457] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  455.214461] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  455.214467] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  455.214472] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  455.214476] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  455.214480] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  455.214485] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  455.214491] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  455.214496] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  455.214500] [drm:intel_dump_pipe_config] requested mode:
>[  455.214508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  455.214511] [drm:intel_dump_pipe_config] adjusted mode:
>[  455.214518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  455.214525] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  455.214529] [drm:intel_dump_pipe_config] port clock: 270000
>[  455.214532] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  455.214537] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  455.214542] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  455.214546] [drm:intel_dump_pipe_config] ips: 0
>[  455.214549] [drm:intel_dump_pipe_config] double wide: 0
>[  455.214554] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  455.214560] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  455.214565] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  455.214571] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  455.222077] gem_exec_blt: executing
>[  455.222346] [drm:i915_gem_open] 
>[  456.770411] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  456.772087] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  458.770327] [drm] Fake missed irq on render ring
>[  458.771338] [drm:i915_gem_open] 
>[  458.932539] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  458.963164] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  459.017260] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  459.101753] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  459.105151] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  459.106236] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  459.106248] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  459.106255] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  459.106263] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  459.106270] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  459.106277] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  459.106282] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  459.106288] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  459.106298] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  459.106306] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  459.106323] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  459.106327] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  459.106334] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  459.106339] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  459.106343] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  459.106347] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  459.106352] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  459.106358] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  459.106363] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  459.106367] [drm:intel_dump_pipe_config] requested mode:
>[  459.106375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  459.106378] [drm:intel_dump_pipe_config] adjusted mode:
>[  459.106385] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  459.106392] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  459.106396] [drm:intel_dump_pipe_config] port clock: 270000
>[  459.106404] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  459.106408] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  459.106413] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  459.106417] [drm:intel_dump_pipe_config] ips: 0
>[  459.106421] [drm:intel_dump_pipe_config] double wide: 0
>[  459.106426] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  459.106431] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  459.106436] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  459.106442] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  459.108239] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  459.114424] gem_exec_blt: executing
>[  459.114700] [drm:i915_gem_open] 
>[  459.114953] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 624 MHz (60)
>[  459.116292] [drm:i915_gem_open] 
>[  459.117086] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  459.119001] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  459.270700] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  459.299285] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  459.355245] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  459.435219] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  459.439963] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  459.524289] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  459.657655] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  459.693699] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 437 MHz (42)
>[  459.778037] [drm:valleyview_set_rps] GPU freq request from 437 MHz (42) to 478 MHz (46)
>[  459.862576] [drm:valleyview_set_rps] GPU freq request from 478 MHz (46) to 562 MHz (54)
>[  459.946744] [drm:valleyview_set_rps] GPU freq request from 562 MHz (54) to 624 MHz (60)
>[  460.098105] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  460.098118] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  460.098125] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  460.098133] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  460.098140] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  460.098147] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  460.098152] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  460.098158] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  460.098164] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  460.098173] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  460.098188] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  460.098193] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  460.098199] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  460.098204] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  460.098208] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  460.098212] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  460.098217] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  460.098223] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  460.098228] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  460.098232] [drm:intel_dump_pipe_config] requested mode:
>[  460.098239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  460.098243] [drm:intel_dump_pipe_config] adjusted mode:
>[  460.098250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  460.098256] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  460.098260] [drm:intel_dump_pipe_config] port clock: 270000
>[  460.098264] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  460.098269] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  460.098274] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  460.098277] [drm:intel_dump_pipe_config] ips: 0
>[  460.098281] [drm:intel_dump_pipe_config] double wide: 0
>[  460.098286] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  460.098292] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  460.098297] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  460.098302] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  460.103206] [drm:i915_ring_test_irq_set] Masking interrupts on rings 0x00000000
>[  460.111840] gem_exec_blt: executing
>[  460.112147] [drm:i915_gem_open] 
>[  460.112638] [drm:i915_gem_open] 
>[  460.186193] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  460.186204] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  460.186211] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  460.186218] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  460.186226] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  460.186232] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  460.186238] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  460.186243] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  460.186250] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  460.186258] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  460.186275] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  460.186279] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  460.186286] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  460.186291] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  460.186294] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  460.186298] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  460.186304] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  460.186310] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  460.186315] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  460.186318] [drm:intel_dump_pipe_config] requested mode:
>[  460.186326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  460.186330] [drm:intel_dump_pipe_config] adjusted mode:
>[  460.186337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  460.186343] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  460.186347] [drm:intel_dump_pipe_config] port clock: 270000
>[  460.186351] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  460.186356] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  460.186360] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  460.186364] [drm:intel_dump_pipe_config] ips: 0
>[  460.186368] [drm:intel_dump_pipe_config] double wide: 0
>[  460.186373] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  460.186379] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  460.186384] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  460.186389] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  460.193851] gem_exec_blt: executing
>[  460.194167] [drm:i915_gem_open] 
>[  460.194609] [drm:i915_gem_open] 
>[  460.254940] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  460.285021] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 437 MHz (42)
>[  460.314731] [drm:valleyview_set_rps] GPU freq request from 437 MHz (42) to 416 MHz (40)
>[  460.369251] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 437 MHz (42)
>[  460.433920] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  460.433932] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  460.433938] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  460.433945] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  460.433953] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  460.433960] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  460.433965] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  460.433970] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  460.433977] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  460.433985] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  460.434001] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  460.434005] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  460.434012] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  460.434017] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  460.434021] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  460.434024] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  460.434030] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  460.434085] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  460.434103] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  460.434119] [drm:intel_dump_pipe_config] requested mode:
>[  460.434137] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  460.434140] [drm:intel_dump_pipe_config] adjusted mode:
>[  460.434147] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  460.434154] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  460.434162] [drm:intel_dump_pipe_config] port clock: 270000
>[  460.434166] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  460.434171] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  460.434176] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  460.434180] [drm:intel_dump_pipe_config] ips: 0
>[  460.434183] [drm:intel_dump_pipe_config] double wide: 0
>[  460.434189] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  460.434195] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  460.434200] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  460.434206] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  460.441956] gem_exec_blt: executing
>[  460.442247] [drm:i915_gem_open] 
>[  460.442497] [drm:valleyview_set_rps] GPU freq request from 437 MHz (42) to 624 MHz (60)
>[  460.444221] [drm:i915_gem_open] 
>[  460.667303] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  460.707379] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 437 MHz (42)
>[  460.791651] [drm:valleyview_set_rps] GPU freq request from 437 MHz (42) to 478 MHz (46)
>[  460.876151] [drm:valleyview_set_rps] GPU freq request from 478 MHz (46) to 562 MHz (54)
>[  460.888698] [drm:valleyview_set_rps] GPU freq request from 562 MHz (54) to 416 MHz (40)
>[  460.960842] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 437 MHz (42)
>[  461.045144] [drm:valleyview_set_rps] GPU freq request from 437 MHz (42) to 478 MHz (46)
>[  461.129618] [drm:valleyview_set_rps] GPU freq request from 478 MHz (46) to 562 MHz (54)
>[  461.214271] [drm:valleyview_set_rps] GPU freq request from 562 MHz (54) to 624 MHz (60)
>[  461.333655] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  461.334584] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  461.334596] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  461.334603] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  461.334610] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  461.334618] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  461.334624] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  461.334629] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  461.334635] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  461.334641] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  461.334650] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  461.334665] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  461.334669] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  461.334676] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  461.334681] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  461.334685] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  461.334689] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  461.334694] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  461.334700] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  461.334705] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  461.334709] [drm:intel_dump_pipe_config] requested mode:
>[  461.334716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  461.334720] [drm:intel_dump_pipe_config] adjusted mode:
>[  461.334727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  461.334733] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  461.334737] [drm:intel_dump_pipe_config] port clock: 270000
>[  461.334741] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  461.334746] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  461.334751] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  461.334754] [drm:intel_dump_pipe_config] ips: 0
>[  461.334758] [drm:intel_dump_pipe_config] double wide: 0
>[  461.334763] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  461.334769] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  461.334774] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  461.334780] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  461.335231] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  464.809290] [drm:i915_error_state_write] Resetting error state
>[  464.812647] [drm:i915_ring_test_irq_set] Masking interrupts on rings 0x0000000f
>[  464.821203] gem_exec_blt: executing
>[  464.821499] [drm:i915_gem_open] 
>[  464.821754] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 624 MHz (60)
>[  464.823563] [drm:i915_gem_open] 
>[  464.823915] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  464.825416] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  468.770746] [drm] Fake missed irq on blitter ring
>[  468.898246] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  468.898258] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  468.898265] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  468.898272] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  468.898280] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  468.898287] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  468.898292] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  468.898297] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  468.898304] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  468.898312] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  468.898328] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  468.898332] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  468.898339] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  468.898344] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  468.898348] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  468.898352] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  468.898357] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  468.898363] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  468.898368] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  468.898371] [drm:intel_dump_pipe_config] requested mode:
>[  468.898379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  468.898383] [drm:intel_dump_pipe_config] adjusted mode:
>[  468.898390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  468.898396] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  468.898400] [drm:intel_dump_pipe_config] port clock: 270000
>[  468.898404] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  468.898409] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  468.898453] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  468.898470] [drm:intel_dump_pipe_config] ips: 0
>[  468.898485] [drm:intel_dump_pipe_config] double wide: 0
>[  468.898503] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  468.899747] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  468.899758] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  468.899767] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  468.902835] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  468.907399] gem_exec_blt: executing
>[  468.907691] [drm:i915_gem_open] 
>[  468.907949] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  468.909598] [drm:i915_gem_open] 
>[  469.150794] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  469.151649] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  469.151661] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  469.151668] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  469.151675] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  469.151683] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  469.151689] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  469.151695] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  469.151700] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  469.151710] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  469.151719] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  469.151734] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  469.151739] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  469.151745] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  469.151750] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  469.151754] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  469.151758] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  469.151764] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  469.151769] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  469.151774] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  469.151778] [drm:intel_dump_pipe_config] requested mode:
>[  469.151786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  469.151789] [drm:intel_dump_pipe_config] adjusted mode:
>[  469.151796] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  469.151803] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  469.151807] [drm:intel_dump_pipe_config] port clock: 270000
>[  469.151810] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  469.151816] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  469.151824] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  469.151828] [drm:intel_dump_pipe_config] ips: 0
>[  469.151831] [drm:intel_dump_pipe_config] double wide: 0
>[  469.151836] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  469.151842] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  469.151847] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  469.151853] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  469.152600] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  469.159415] gem_exec_blt: executing
>[  469.159713] [drm:i915_gem_open] 
>[  469.159965] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 624 MHz (60)
>[  469.161740] [drm:i915_gem_open] 
>[  469.162674] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  469.164596] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  469.325755] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  469.410146] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  470.120641] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  470.121851] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  470.121863] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  470.121870] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  470.121878] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  470.121885] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  470.121892] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  470.121897] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  470.121903] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  470.121910] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  470.121918] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  470.121934] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  470.121938] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  470.121945] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  470.121950] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  470.121954] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  470.121958] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  470.121963] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  470.121969] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  470.121974] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  470.121978] [drm:intel_dump_pipe_config] requested mode:
>[  470.121986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  470.121989] [drm:intel_dump_pipe_config] adjusted mode:
>[  470.121996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  470.122003] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  470.122007] [drm:intel_dump_pipe_config] port clock: 270000
>[  470.122011] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  470.122016] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  470.122020] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  470.122024] [drm:intel_dump_pipe_config] ips: 0
>[  470.122028] [drm:intel_dump_pipe_config] double wide: 0
>[  470.122033] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  470.122039] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  470.122044] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  470.122049] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  470.122630] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  470.135526] gem_exec_blt: executing
>[  470.135800] [drm:i915_gem_open] 
>[  470.136052] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 624 MHz (60)
>[  470.137822] [drm:i915_gem_open] 
>[  470.138173] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  470.139642] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  470.255243] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  470.262310] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  470.262322] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  470.262330] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  470.262337] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  470.262345] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  470.262351] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  470.262357] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  470.262362] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  470.262369] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  470.262378] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  470.262393] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  470.262398] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  470.262404] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  470.262409] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  470.262413] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  470.262417] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  470.262423] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  470.262428] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  470.262433] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  470.262437] [drm:intel_dump_pipe_config] requested mode:
>[  470.262445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  470.262448] [drm:intel_dump_pipe_config] adjusted mode:
>[  470.262455] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  470.262462] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  470.262466] [drm:intel_dump_pipe_config] port clock: 270000
>[  470.262470] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  470.262507] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  470.262524] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  470.262538] [drm:intel_dump_pipe_config] ips: 0
>[  470.262554] [drm:intel_dump_pipe_config] double wide: 0
>[  470.262572] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  470.262588] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  470.262604] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  470.262616] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  470.270233] gem_exec_blt: executing
>[  470.270551] [drm:i915_gem_open] 
>[  470.270804] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  470.272657] [drm:i915_gem_open] 
>[  470.337790] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  470.339563] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  470.424272] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  470.434801] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  470.509009] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  470.586301] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  470.586312] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  470.586319] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  470.586326] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  470.586334] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  470.586340] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  470.586345] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  470.586351] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  470.586358] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  470.586366] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  470.586381] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  470.586386] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  470.586392] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  470.586397] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  470.586401] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  470.586405] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  470.586410] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  470.586416] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  470.586421] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  470.586425] [drm:intel_dump_pipe_config] requested mode:
>[  470.586432] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  470.586436] [drm:intel_dump_pipe_config] adjusted mode:
>[  470.586443] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  470.586449] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  470.586453] [drm:intel_dump_pipe_config] port clock: 270000
>[  470.586457] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  470.586462] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  470.586467] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  470.586470] [drm:intel_dump_pipe_config] ips: 0
>[  470.586474] [drm:intel_dump_pipe_config] double wide: 0
>[  470.586479] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  470.586485] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  470.586525] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  470.586532] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  470.594187] gem_exec_blt: executing
>[  470.594458] [drm:i915_gem_open] 
>[  470.594766] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  470.596713] [drm:i915_gem_open] 
>[  470.655798] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  470.677870] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 437 MHz (42)
>[  470.711684] [drm:valleyview_set_rps] GPU freq request from 437 MHz (42) to 416 MHz (40)
>[  470.762634] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 437 MHz (42)
>[  470.846862] [drm:valleyview_set_rps] GPU freq request from 437 MHz (42) to 478 MHz (46)
>[  470.931503] [drm:valleyview_set_rps] GPU freq request from 478 MHz (46) to 562 MHz (54)
>[  471.015802] [drm:valleyview_set_rps] GPU freq request from 562 MHz (54) to 624 MHz (60)
>[  471.043911] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  471.045592] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  471.100332] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  471.185058] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  471.511498] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  471.511512] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  471.511519] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  471.511526] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  471.511566] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  471.511574] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  471.511580] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  471.511585] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  471.511592] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  471.511600] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  471.511616] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  471.511620] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  471.511627] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  471.511632] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  471.511635] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  471.511639] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  471.511645] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  471.511651] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  471.511656] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  471.511659] [drm:intel_dump_pipe_config] requested mode:
>[  471.511667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  471.511671] [drm:intel_dump_pipe_config] adjusted mode:
>[  471.511678] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  471.511684] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  471.511688] [drm:intel_dump_pipe_config] port clock: 270000
>[  471.511692] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  471.511697] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  471.511701] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  471.511705] [drm:intel_dump_pipe_config] ips: 0
>[  471.511709] [drm:intel_dump_pipe_config] double wide: 0
>[  471.511715] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  471.511720] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  471.511725] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  471.511731] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  471.517431] [drm:i915_ring_test_irq_set] Masking interrupts on rings 0x00000000
>[  471.526067] gem_exec_blt: executing
>[  471.526342] [drm:i915_gem_open] 
>[  471.526835] [drm:i915_gem_open] 
>[  471.600009] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  471.600021] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  471.600028] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  471.600035] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  471.600042] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  471.600049] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  471.600054] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  471.600060] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  471.600067] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  471.600075] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  471.600091] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  471.600095] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  471.600102] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  471.600107] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  471.600111] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  471.600115] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  471.600121] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  471.600126] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  471.600131] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  471.600135] [drm:intel_dump_pipe_config] requested mode:
>[  471.600143] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  471.600146] [drm:intel_dump_pipe_config] adjusted mode:
>[  471.600153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  471.600160] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  471.600164] [drm:intel_dump_pipe_config] port clock: 270000
>[  471.600168] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  471.600172] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  471.600177] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  471.600181] [drm:intel_dump_pipe_config] ips: 0
>[  471.600184] [drm:intel_dump_pipe_config] double wide: 0
>[  471.600190] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  471.600196] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  471.600200] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  471.600206] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  471.609952] gem_exec_blt: executing
>[  471.610227] [drm:i915_gem_open] 
>[  471.610836] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  471.611052] [drm:i915_gem_open] 
>[  471.612797] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  471.691862] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  471.707997] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  471.776366] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  471.776522] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  471.860896] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  471.945764] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  471.953225] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  471.954347] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  471.954358] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  471.954365] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  471.954372] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  471.954380] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  471.954387] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  471.954392] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  471.954397] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  471.954404] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  471.954412] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  471.954429] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  471.954433] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  471.954440] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  471.954445] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  471.954448] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  471.954452] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  471.954458] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  471.954464] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  471.954469] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  471.954472] [drm:intel_dump_pipe_config] requested mode:
>[  471.954480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  471.954484] [drm:intel_dump_pipe_config] adjusted mode:
>[  471.954490] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  471.954497] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  471.954501] [drm:intel_dump_pipe_config] port clock: 270000
>[  471.954505] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  471.954510] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  471.954514] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  471.954518] [drm:intel_dump_pipe_config] ips: 0
>[  471.954522] [drm:intel_dump_pipe_config] double wide: 0
>[  471.954527] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  471.954533] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  471.954538] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  471.954543] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  471.954735] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  471.962205] gem_exec_blt: executing
>[  471.962479] [drm:i915_gem_open] 
>[  471.962767] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 624 MHz (60)
>[  471.964865] [drm:i915_gem_open] 
>[  471.965612] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  471.967670] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  472.114583] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  472.199093] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  472.920020] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  472.920947] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  472.920959] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  472.920966] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  472.920973] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  472.920981] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  472.920988] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  472.920993] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  472.920998] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  472.921005] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  472.921013] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  472.921029] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  472.921034] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  472.921040] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  472.921045] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  472.921049] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  472.921053] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  472.921058] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  472.921064] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  472.921069] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  472.921073] [drm:intel_dump_pipe_config] requested mode:
>[  472.921081] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  472.921084] [drm:intel_dump_pipe_config] adjusted mode:
>[  472.921091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  472.921098] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  472.921102] [drm:intel_dump_pipe_config] port clock: 270000
>[  472.921106] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  472.921110] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  472.921115] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  472.921119] [drm:intel_dump_pipe_config] ips: 0
>[  472.921122] [drm:intel_dump_pipe_config] double wide: 0
>[  472.921128] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  472.921133] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  472.921138] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  472.921144] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  472.921769] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  601.128558] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  601.164440] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  601.164449] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  601.176488] [drm:intel_edp_backlight_off] 
>[  601.401599] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  601.437509] [drm:edp_panel_off] Turn eDP port C panel power off
>[  601.437514] [drm:wait_panel_off] Wait for panel power off time
>[  601.437521] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[  601.478954] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  601.478957] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[  601.478959] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 5 - cnt: 0
>[  601.478987] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C
>[  601.481555] [drm:wait_panel_status] Wait complete
>[  601.507512] [drm:intel_dp_link_down] 
>[  601.582423] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  601.582429] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=2, cursor=2, C: plane=2, cursor=2, SR: plane=0, cursor=0
>[  601.590479] [drm:intel_display_power_put] disabling dpio-common-d
>[  601.602475] [drm:intel_display_power_put] disabling dpio-common-bc
>[  601.614461] [drm:intel_display_power_put] disabling pipe-a
>[  601.624488] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  601.624491] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  601.624494] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  601.624496] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  601.624498] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  601.624501] [drm:check_crtc_state] [CRTC:8]
>[  601.624504] [drm:check_crtc_state] [CRTC:13]
>[  601.624506] [drm:check_crtc_state] [CRTC:18]
>[  667.922377] [drm:i915_error_state_write] Resetting error state
>[  667.925705] [drm:i915_ring_test_irq_set] Masking interrupts on rings 0x0000000f
>[  667.934302] gem_exec_blt: executing
>[  667.934604] [drm:i915_gem_open] 
>[  667.934864] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 624 MHz (60)
>[  667.936732] [drm:i915_gem_open] 
>[  667.937056] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  669.779826] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  671.779867] [drm] Fake missed irq on blitter ring
>[  671.906378] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  671.906707] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  671.906719] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  671.906726] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  671.906743] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  671.906751] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  671.906758] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=1, fb_changed=0
>[  671.906763] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  671.906772] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  671.906793] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  671.906802] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  671.906817] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  671.906821] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  671.906831] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  671.906846] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  671.906850] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  671.906854] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  671.906860] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  671.906865] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  671.906870] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  671.906874] [drm:intel_dump_pipe_config] requested mode:
>[  671.906882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  671.906899] [drm:intel_dump_pipe_config] adjusted mode:
>[  671.906916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  671.906923] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  671.906927] [drm:intel_dump_pipe_config] port clock: 270000
>[  671.906931] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  671.906936] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  671.906940] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  671.906944] [drm:intel_dump_pipe_config] ips: 0
>[  671.906948] [drm:intel_dump_pipe_config] double wide: 0
>[  671.906960] [drm:intel_display_power_get] enabling pipe-a
>[  671.927625] [drm:intel_display_power_get] enabling dpio-common-bc
>[  671.937626] [drm:intel_display_power_get] enabling dpio-common-d
>[  672.006638] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  672.041589] [drm:vlv_init_panel_power_sequencer] initializing pipe B power sequencer for port C
>[  672.041602] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f06
>[  672.053591] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  672.053600] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  672.053609] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000
>[  672.482782] [drm:wait_panel_status] Wait complete
>[  672.482799] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  672.482806] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled
>[  672.683922] [drm:edp_panel_on] Turn eDP port C panel power on
>[  672.683935] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  672.683944] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008
>[  672.683949] [drm:wait_panel_status] Wait complete
>[  672.683957] [drm:wait_panel_on] Wait for panel power on
>[  672.683964] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b
>[  672.837813] [drm:wait_panel_status] Wait complete
>[  672.837826] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  672.837837] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  672.885669] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  672.885682] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  673.021680] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  673.093704] [drm:intel_dp_start_link_train] clock recovery OK
>[  673.165685] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  673.189764] [drm:g4x_check_srwm] SR watermark: display plane 107, cursor 2
>[  673.189771] [drm:g4x_check_srwm] SR watermark: display plane 211, cursor 2
>[  673.189778] [drm:cherryview_update_wm] Setting FIFO watermarks - A: plane=2, cursor=2, B: plane=61, cursor=2, C: plane=2, cursor=2, SR: plane=107, cursor=2
>[  673.189786] [drm:intel_set_memory_cxsr] memory self-refresh is enabled
>[  673.189798] [drm:intel_edp_backlight_on] 
>[  673.189803] [drm:intel_panel_enable_backlight] pipe B
>[  673.189809] [drm:intel_panel_actually_set_backlight] set backlight PWM = 7812
>[  673.213697] [drm:i9xx_update_primary_plane] Writing base 000A0000 00000000 0 0 7680
>[  673.213718] [drm:intel_connector_check_state] [CONNECTOR:29:eDP-1]
>[  673.213734] [drm:check_encoder_state] [ENCODER:21:TMDS-21]
>[  673.213740] [drm:check_encoder_state] [ENCODER:26:TMDS-26]
>[  673.213745] [drm:check_encoder_state] [ENCODER:28:TMDS-28]
>[  673.213751] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  673.213757] [drm:check_encoder_state] [ENCODER:36:TMDS-36]
>[  673.213762] [drm:check_crtc_state] [CRTC:8]
>[  673.213769] [drm:check_crtc_state] [CRTC:13]
>[  673.221718] [drm:check_crtc_state] [CRTC:18]
>[  673.221731] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  673.221739] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  673.221744] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  673.221752] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  673.229491] gem_exec_blt: executing
>[  673.229808] [drm:i915_gem_open] 
>[  673.230076] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 624 MHz (60)
>[  673.231935] [drm:i915_gem_open] 
>[  673.232605] [drm:intel_set_cpu_fifo_underrun_reporting [i915]] *ERROR* pipe B underrun
>[  673.232783] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun
>[  673.232978] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  673.234831] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  673.342818] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  673.427299] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  673.518444] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  673.518455] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  673.518462] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  673.518469] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  673.518476] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  673.518483] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  673.518488] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  673.518494] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  673.518500] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  673.518509] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  673.518525] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  673.518530] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  673.518536] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  673.518541] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  673.518545] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  673.518548] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  673.518554] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  673.518560] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  673.518565] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  673.518568] [drm:intel_dump_pipe_config] requested mode:
>[  673.518576] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  673.518580] [drm:intel_dump_pipe_config] adjusted mode:
>[  673.518587] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  673.518593] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  673.518597] [drm:intel_dump_pipe_config] port clock: 270000
>[  673.518601] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  673.518606] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  673.518610] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  673.518614] [drm:intel_dump_pipe_config] ips: 0
>[  673.518618] [drm:intel_dump_pipe_config] double wide: 0
>[  673.518623] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  673.518629] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  673.518634] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  673.518684] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  673.526237] gem_exec_blt: executing
>[  673.529069] [drm:i915_gem_open] 
>[  675.779999] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  675.782208] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  675.903768] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  675.903782] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  677.780086] [drm] Fake missed irq on render ring
>[  677.783274] [drm:i915_gem_open] 
>[  677.905498] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  677.989956] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  678.062011] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  678.063948] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  678.074505] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  678.159284] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  678.726206] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  678.727277] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  678.727289] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  678.727296] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  678.727303] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  678.727311] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  678.727317] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  678.727322] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  678.727328] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  678.727335] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  678.727344] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  678.727360] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  678.727364] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  678.727371] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  678.727376] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  678.727380] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  678.727384] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  678.727389] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  678.727395] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  678.727400] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  678.727404] [drm:intel_dump_pipe_config] requested mode:
>[  678.727411] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  678.727415] [drm:intel_dump_pipe_config] adjusted mode:
>[  678.727422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  678.727428] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  678.727432] [drm:intel_dump_pipe_config] port clock: 270000
>[  678.727436] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  678.727441] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  678.727446] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  678.727449] [drm:intel_dump_pipe_config] ips: 0
>[  678.727453] [drm:intel_dump_pipe_config] double wide: 0
>[  678.727458] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  678.727464] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  678.727469] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  678.727474] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  678.728204] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  678.740987] gem_exec_blt: executing
>[  678.743824] [drm:i915_gem_open] 
>[  678.744107] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 624 MHz (60)
>[  678.746175] [drm:i915_gem_open] 
>[  678.746541] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  678.748091] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  678.835446] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  678.859639] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  678.859652] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  678.859659] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  678.859666] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  678.859673] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  678.859680] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  678.859685] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  678.859691] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  678.859697] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  678.859705] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  678.859721] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  678.859726] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  678.859732] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  678.859737] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  678.859741] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  678.859745] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  678.859750] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  678.859756] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  678.859761] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  678.859765] [drm:intel_dump_pipe_config] requested mode:
>[  678.859772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  678.859776] [drm:intel_dump_pipe_config] adjusted mode:
>[  678.859783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  678.859789] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  678.859793] [drm:intel_dump_pipe_config] port clock: 270000
>[  678.859797] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  678.859802] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  678.859807] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  678.859810] [drm:intel_dump_pipe_config] ips: 0
>[  678.859814] [drm:intel_dump_pipe_config] double wide: 0
>[  678.859819] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  678.859825] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  678.859830] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  678.859835] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  678.867330] gem_exec_blt: executing
>[  678.870079] [drm:i915_gem_open] 
>[  678.870338] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  678.872058] [drm:i915_gem_open] 
>[  678.996086] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  678.998001] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  679.004323] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  679.089078] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  679.116521] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  679.117032] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  679.117043] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  679.117050] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  679.117057] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  679.117065] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  679.117072] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  679.117077] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  679.117082] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  679.117090] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  679.117101] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  679.117118] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  679.117123] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  679.117136] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  679.117141] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  679.117145] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  679.117149] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  679.117155] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  679.117160] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  679.117166] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  679.117169] [drm:intel_dump_pipe_config] requested mode:
>[  679.117177] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  679.117181] [drm:intel_dump_pipe_config] adjusted mode:
>[  679.117187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  679.117194] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  679.117198] [drm:intel_dump_pipe_config] port clock: 270000
>[  679.117202] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  679.117207] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  679.117211] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  679.117215] [drm:intel_dump_pipe_config] ips: 0
>[  679.117219] [drm:intel_dump_pipe_config] double wide: 0
>[  679.117224] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  679.117230] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  679.117235] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  679.117241] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  679.118044] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  679.125072] gem_exec_blt: executing
>[  679.127741] [drm:i915_gem_open] 
>[  679.128025] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 624 MHz (60)
>[  679.130185] [drm:i915_gem_open] 
>[  679.131082] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  679.133070] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  679.258202] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  679.342714] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  679.411228] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  679.427221] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 437 MHz (42)
>[  679.511549] [drm:valleyview_set_rps] GPU freq request from 437 MHz (42) to 478 MHz (46)
>[  679.596002] [drm:valleyview_set_rps] GPU freq request from 478 MHz (46) to 562 MHz (54)
>[  679.631050] [drm:valleyview_set_rps] GPU freq request from 562 MHz (54) to 416 MHz (40)
>[  679.632999] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  679.680537] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  679.765276] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  680.092693] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  680.094061] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  683.784265] [drm] Fake missed irq on bsd ring
>[  683.787361] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  683.787371] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  683.787377] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  683.787384] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  683.787392] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  683.787399] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  683.787404] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  683.787409] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  683.787416] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  683.787425] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  683.787440] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  683.787445] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  683.787451] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  683.787456] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  683.787460] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  683.787464] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  683.787469] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  683.787475] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  683.787480] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  683.787483] [drm:intel_dump_pipe_config] requested mode:
>[  683.787491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  683.787495] [drm:intel_dump_pipe_config] adjusted mode:
>[  683.787502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  683.787508] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  683.787512] [drm:intel_dump_pipe_config] port clock: 270000
>[  683.787516] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  683.787521] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  683.787525] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  683.787529] [drm:intel_dump_pipe_config] ips: 0
>[  683.787533] [drm:intel_dump_pipe_config] double wide: 0
>[  683.787538] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  683.787544] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  683.787549] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  683.787554] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  683.794401] [drm:i915_ring_test_irq_set] Masking interrupts on rings 0x00000000
>[  683.803007] gem_exec_blt: executing
>[  683.805644] [drm:i915_gem_open] 
>[  683.805901] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 624 MHz (60)
>[  683.807451] [drm:i915_gem_open] 
>[  683.807952] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  683.845227] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  683.907743] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  683.908986] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  683.908997] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  683.909004] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  683.909011] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  683.909019] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  683.909025] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  683.909031] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  683.909036] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  683.909043] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  683.909051] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  683.909067] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  683.909071] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  683.909078] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  683.909083] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  683.909086] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  683.909090] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  683.909096] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  683.909102] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  683.909136] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  683.909144] [drm:intel_dump_pipe_config] requested mode:
>[  683.909151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  683.909155] [drm:intel_dump_pipe_config] adjusted mode:
>[  683.909162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  683.909169] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  683.909172] [drm:intel_dump_pipe_config] port clock: 270000
>[  683.909176] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  683.909181] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  683.909186] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  683.909190] [drm:intel_dump_pipe_config] ips: 0
>[  683.909193] [drm:intel_dump_pipe_config] double wide: 0
>[  683.909199] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  683.909205] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  683.909210] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  683.909216] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  683.916777] gem_exec_blt: executing
>[  683.919343] [drm:i915_gem_open] 
>[  683.919599] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  683.921365] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  683.921559] [drm:i915_gem_open] 
>[  683.923345] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  684.074250] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  684.107805] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  684.158911] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 416 MHz (40)
>[  684.243353] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 624 MHz (60)
>[  684.248295] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  684.248937] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  684.248947] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  684.248954] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  684.248961] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  684.248969] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  684.248976] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  684.248981] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  684.248987] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  684.248993] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  684.249002] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  684.249017] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  684.249022] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  684.249028] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  684.249033] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  684.249037] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  684.249041] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  684.249047] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  684.249052] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  684.249057] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  684.249061] [drm:intel_dump_pipe_config] requested mode:
>[  684.249069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  684.249072] [drm:intel_dump_pipe_config] adjusted mode:
>[  684.249079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  684.249086] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  684.249090] [drm:intel_dump_pipe_config] port clock: 270000
>[  684.249094] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  684.249098] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  684.249103] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  684.249107] [drm:intel_dump_pipe_config] ips: 0
>[  684.249110] [drm:intel_dump_pipe_config] double wide: 0
>[  684.249116] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  684.249147] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  684.249158] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  684.249175] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  684.250269] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)
>[  684.256891] gem_exec_blt: executing
>[  684.259402] [drm:i915_gem_open] 
>[  684.259655] [drm:valleyview_set_rps] GPU freq request from 208 MHz (20) to 624 MHz (60)
>[  684.261371] [drm:i915_gem_open] 
>[  684.483058] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  684.496941] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 437 MHz (42)
>[  684.581394] [drm:valleyview_set_rps] GPU freq request from 437 MHz (42) to 478 MHz (46)
>[  684.665876] [drm:valleyview_set_rps] GPU freq request from 478 MHz (46) to 562 MHz (54)
>[  684.750664] [drm:valleyview_set_rps] GPU freq request from 562 MHz (54) to 624 MHz (60)
>[  685.145836] [drm:valleyview_set_rps] GPU freq request from 624 MHz (60) to 416 MHz (40)
>[  685.146587] [drm:intel_crtc_set_config] [CRTC:8] [NOFB]
>[  685.146598] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0
>[  685.146605] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  685.146612] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  685.146620] [drm:intel_crtc_set_config] [CRTC:13] [FB:39] #connectors=1 (x y) (0 0)
>[  685.146627] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0
>[  685.146632] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  685.146638] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  685.146644] [drm:connected_sink_compute_bpp] [CONNECTOR:29:eDP-1] checking for sink bpp constrains
>[  685.146653] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
>[  685.146668] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 24
>[  685.146672] [drm:intel_dp_compute_config] DP link bw required 333072 available 432000
>[  685.146679] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  685.146684] [drm:intel_dump_pipe_config] [CRTC:13][modeset] config for pipe B
>[  685.146687] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  685.146691] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  685.146697] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  685.146702] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  685.146708] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  685.146711] [drm:intel_dump_pipe_config] requested mode:
>[  685.146719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  685.146723] [drm:intel_dump_pipe_config] adjusted mode:
>[  685.146729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  685.146736] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  685.146740] [drm:intel_dump_pipe_config] port clock: 270000
>[  685.146744] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  685.146749] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  685.146753] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  685.146757] [drm:intel_dump_pipe_config] ips: 0
>[  685.146761] [drm:intel_dump_pipe_config] double wide: 0
>[  685.146766] [drm:intel_crtc_set_config] [CRTC:18] [NOFB]
>[  685.146772] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:18], mode_changed=0, fb_changed=0
>[  685.146777] [drm:intel_modeset_stage_output_state] [CONNECTOR:29:eDP-1] to [CRTC:13]
>[  685.146782] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  685.147738] [drm:valleyview_set_rps] GPU freq request from 416 MHz (40) to 208 MHz (20)

Actions: View

Attachments on bug 86189: 109327

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.