Attachment 112033 Details for Bug 88246 – Mesa debug output after 2881b12

Mesa debug output after 2881b12

after-2881b12-debug.txt (text/plain), 9.15 KB, created by Mike Mason on 2015-01-09 21:40:10 UTC

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Creator: Mike Mason

Created: 2015-01-09 21:40:10 UTC

Size: 9.15 KB

patch

obsolete

>dEQP Core 2014.x (0xcafebabe) starting..
>  target implementation = 'X11 EGL'
>
>Test case 'dEQP-GLES3.functional.shaders.conversions.scalar_to_scalar.int_to_bool_vertex'..
>GLSL IR for native fragment shader 0:
>(
>(declare (shader_in ) vec4 gl_Color)
>(declare (shader_out ) vec4 gl_FragColor)
>(function main
>  (signature void
>    (parameters
>    )
>    (
>      (assign  (xyzw) (var_ref gl_FragColor)  (var_ref gl_Color) ) 
>    ))
>
>)
>
>
>)
>
>Native code for unnamed fragment shader 0 (SIMD8 dispatch):
>SIMD8 shader: 5 instructions. 0 loops. Compacted 80 to 48 bytes (40%)
>   START B0
>   (declare (shader_in ) vec4 gl_Color)
>pln(8)          g124<1>F        g4<0,1,0>F      g2<8,8,1>F      { align1 1Q compacted };
>pln(8)          g125<1>F        g4.4<0,1,0>F    g2<8,8,1>F      { align1 1Q compacted };
>pln(8)          g126<1>F        g5<0,1,0>F      g2<8,8,1>F      { align1 1Q compacted };
>pln(8)          g127<1>F        g5.4<0,1,0>F    g2<8,8,1>F      { align1 1Q compacted };
>   FB write header
>sendc(8)        null            g124<8,8,1>F
>                            render RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
>   END B0
>
>Native code for unnamed fragment shader 0 (SIMD16 dispatch):
>SIMD16 shader: 5 instructions. 0 loops. Compacted 80 to 48 bytes (40%)
>   START B0
>   (declare (shader_in ) vec4 gl_Color)
>pln(16)         g120<1>F        g6<0,1,0>F      g2<8,8,1>F      { align1 1H compacted };
>pln(16)         g122<1>F        g6.4<0,1,0>F    g2<8,8,1>F      { align1 1H compacted };
>pln(16)         g124<1>F        g7<0,1,0>F      g2<8,8,1>F      { align1 1H compacted };
>pln(16)         g126<1>F        g7.4<0,1,0>F    g2<8,8,1>F      { align1 1H compacted };
>   FB write header
>sendc(16)       null            g120<8,8,1>F
>                            render RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
>   END B0
>
>
>GLSL IR for native fragment shader 3:
>(
>(declare (shader_out ) vec4 gl_FragColor)
>(declare (uniform ) vec4 color)
>(function main
>  (signature void
>    (parameters
>    )
>    (
>      (assign  (xyzw) (var_ref gl_FragColor)  (var_ref color) ) 
>    ))
>
>)
>
>
>)
>
>Native code for meta clear fragment shader 3 (SIMD16 dispatch):
>SIMD16 shader: 2 instructions. 0 loops. Compacted 32 to 32 bytes (0%)
>   START B0
>mov(4)          g115<1>F        g2<4,4,1>F                      { align1 WE_all compacted };
>nop                                                             ;
>sendc(16)       null            g115<8,8,1>F
>                            render RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT };
>   END B0
>
>
>GLSL IR for native vertex shader 3:
>(
>(declare (shader_out ) vec4 gl_Position)
>(declare (shader_out ) int gl_Layer)
>(declare (sys ) int gl_InstanceID)
>(declare (shader_in ) vec4 position)
>(function main
>  (signature void
>    (parameters
>    )
>    (
>      (assign  (x) (var_ref gl_Layer)  (var_ref gl_InstanceID) ) 
>      (assign  (xyzw) (var_ref gl_Position)  (var_ref position) ) 
>    ))
>
>)
>
>
>)
>
>vec4 estimated execution time: 30 cycles
>Native code for meta clear vertex shader 3:
>vec4 shader: 6 instructions. 0 loops. Compacted 96 to 96 bytes (0%)
>   START B0
>   indices, point width, clip flags
>mov(8)          g114<1>UD       0x00000000UD                    { align16 1Q compacted };
>   gl_Position
>mov(8)          g115<1>F        g1<4,4,1>F                      { align16 1Q };
>   indices, point width, clip flags
>mov(8)          g114<1>.yD      g2<4,4,1>.wD                    { align16 1Q };
>   URB write
>mov(8)          g113<1>UD       g0<4,4,1>UD                     { align16 WE_all 1Q };
>or(1)           g113.5<1>UD     g0.5<0,1,0>UD   0x0000ff00UD    { align1 WE_all };
>nop                                                             ;
>send(8)         null            g113<4,4,1>F
>                            urb 0 write HWord interleave complete mlen 3 rlen 0 { align16 1Q EOT };
>   END B0
>
>GLSL IR for native fragment shader 4:
>(
>(declare (shader_in ) vec4 packed:v_out0)
>(declare (shader_out ) vec4 dEQP_FragColor)
>(declare (uniform ) bool ref_out0)
>(function main
>  (signature void
>    (parameters
>    )
>    (
>      (declare (temporary ) bool compiler_temp)
>      (assign  (x) (var_ref compiler_temp)  (expression bool == (expression bool > (swiz x (var_ref packed:v_out0) )(constant float (0.500000)) ) (var_ref ref_out0) ) ) 
>      (assign  (x) (var_ref dEQP_FragColor)  (expression float b2f (var_ref compiler_temp) ) ) 
>      (assign  (y) (var_ref dEQP_FragColor)  (expression float b2f (var_ref compiler_temp) ) ) 
>      (assign  (z) (var_ref dEQP_FragColor)  (expression float b2f (var_ref compiler_temp) ) ) 
>      (assign  (w) (var_ref dEQP_FragColor)  (constant float (1.000000)) ) 
>    ))
>
>)
>
>
>)
>
>Native code for unnamed fragment shader 4 (SIMD8 dispatch):
>SIMD8 shader: 8 instructions. 0 loops. Compacted 128 to 96 bytes (25%)
>   START B0
>   (declare (shader_in ) vec4 packed:v_out0)
>pln(8)          g7<1>F          g5<0,1,0>F      g2<8,8,1>F      { align1 1Q compacted };
>   (assign  (x) (var_ref compiler_temp)  (expression bool == (expression bool > (swiz x (var_ref packed:v_out0) )(constant float (0.500000)) ) (var_ref ref_out0) ) ) 
>cmp.g.f0(8)     g3<1>D          g7<8,8,1>F      0.5F            { align1 1Q };
>cmp.z.f0(8)     g2<1>D          g3<8,8,1>D      g4<0,1,0>D      { align1 1Q compacted };
>   (assign  (x) (var_ref dEQP_FragColor)  (expression float b2f (var_ref compiler_temp) ) ) 
>and(8)          g126<1>D        g2<8,8,1>D      0x3f800000UD    { align1 1Q };
>mov(8)          g124<1>F        g126<8,8,1>F                    { align1 1Q compacted };
>mov(8)          g125<1>F        g126<8,8,1>F                    { align1 1Q compacted };
>mov(8)          g127<1>F        1F                              { align1 1Q };
>   FB write header
>sendc(8)        null            g124<8,8,1>F
>                            render RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
>   END B0
>
>Native code for unnamed fragment shader 4 (SIMD16 dispatch):
>SIMD16 shader: 8 instructions. 0 loops. Compacted 128 to 96 bytes (25%)
>   START B0
>   (declare (shader_in ) vec4 packed:v_out0)
>pln(16)         g10<1>F         g7<0,1,0>F      g2<8,8,1>F      { align1 1H compacted };
>   (assign  (x) (var_ref compiler_temp)  (expression bool == (expression bool > (swiz x (var_ref packed:v_out0) )(constant float (0.500000)) ) (var_ref ref_out0) ) ) 
>cmp.g.f0(16)    g4<1>D          g10<8,8,1>F     0.5F            { align1 1H };
>cmp.z.f0(16)    g2<1>D          g4<8,8,1>D      g6<0,1,0>D      { align1 1H compacted };
>   (assign  (x) (var_ref dEQP_FragColor)  (expression float b2f (var_ref compiler_temp) ) ) 
>and(16)         g124<1>D        g2<8,8,1>D      0x3f800000UD    { align1 1H };
>mov(16)         g120<1>F        g124<8,8,1>F                    { align1 1H compacted };
>mov(16)         g122<1>F        g124<8,8,1>F                    { align1 1H compacted };
>mov(16)         g126<1>F        1F                              { align1 1H };
>   FB write header
>sendc(16)       null            g120<8,8,1>F
>                            render RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
>   END B0
>
>
>GLSL IR for native vertex shader 4:
>(
>(declare (shader_out ) vec4 gl_Position)
>(declare (shader_out ) vec4 packed:v_out0)
>(declare (shader_in ) vec4 dEQP_Position)
>(declare (shader_in ) float a_in0)
>(function main
>  (signature void
>    (parameters
>    )
>    (
>      (assign  (xyzw) (var_ref gl_Position)  (var_ref dEQP_Position) ) 
>      (assign  (x) (var_ref packed:v_out0)  (expression float b2f (expression bool i2b (expression int f2i (var_ref a_in0) ) ) ) ) 
>    ))
>
>)
>
>
>)
>
>vec4 estimated execution time: 58 cycles
>Native code for unnamed vertex shader 4:
>vec4 shader: 9 instructions. 0 loops. Compacted 144 to 128 bytes (11%)
>   START B0
>   (assign  (x) (var_ref packed:v_out0)  (expression float b2f (expression bool i2b (expression int f2i (var_ref a_in0) ) ) ) ) 
>mov(8)          g7<1>.xD        g2<4,4,1>.xF                    { align16 1Q compacted };
>   indices, point width, clip flags
>mov(8)          g114<1>UD       0x00000000UD                    { align16 1Q compacted };
>   gl_Position
>mov(8)          g115<1>F        g1<4,4,1>F                      { align16 1Q };
>   (assign  (x) (var_ref packed:v_out0)  (expression float b2f (expression bool i2b (expression int f2i (var_ref a_in0) ) ) ) ) 
>and(8)          g6<1>.xD        g7<4,4,1>.xD    1D              { align16 1Q compacted };
>and(8)          g4<1>.xD        g6<4,4,1>.xD    0x3f800000UD    { align16 1Q };
>   packed:v_out0
>mov(8)          g116<1>F        g4<4,4,1>F                      { align16 1Q };
>   URB write
>mov(8)          g113<1>UD       g0<4,4,1>UD                     { align16 WE_all 1Q };
>or(1)           g113.5<1>UD     g0.5<0,1,0>UD   0x0000ff00UD    { align1 WE_all };
>nop                                                             ;
>send(8)         null            g113<4,4,1>F
>                            urb 0 write HWord interleave complete mlen 5 rlen 0 { align16 1Q EOT };
>   END B0
>
>Vertex shader compile time = 0.193000 ms
>Fragment shader compile time = 0.231000 ms
>Link time = 2.895000 ms
>  Fail (Image comparison failed)
>Test case duration in microseconds = 9333 us
>
>DONE!
>
>Test run totals:
>  Passed:        0/1 (0.0%)
>  Failed:        1/1 (100.0%)
>  Not supported: 0/1 (0.0%)
>  Warnings:      0/1 (0.0%)

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Attachments on bug 88246: 112031 | 112032 | 112033 | 112035

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