Attachment 113442 Details for Bug 89123 – dmesg

dmesg

dmesg_skly05_pm_rps_2_0213.txt (text/plain), 19.55 KB, created by lu hua on 2015-02-13 05:21:40 UTC

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Description:

Filename:

MIME Type:

Creator: lu hua

Created: 2015-02-13 05:21:40 UTC

Size: 19.55 KB

patch

obsolete

>[  339.878649] pm_rps: executing
>[  339.878776] [drm:i915_gem_open] 
>[  339.881338] [drm:gen8_ppgtt_init] Allocated 4 pages for page directories (0 wasted)
>[  339.881343] [drm:gen8_ppgtt_init] Allocated 2048 pages for page tables (0 wasted)
>[  339.881885] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880143ebf480
>[  339.881891] [drm:drm_atomic_get_plane_state] Added [PLANE:17] ffff880004df20c0 state to ffff880143ebf480
>[  339.881896] [drm:drm_atomic_get_crtc_state] Added [CRTC:20] ffff880004cf7800 state to ffff880143ebf480
>[  339.881900] [drm:drm_atomic_check_only] checking ffff880143ebf480
>[  339.881906] [drm:drm_atomic_commit] commiting ffff880143ebf480
>[  339.881929] [drm:skylake_update_primary_plane] Writing base 016C0000 0,0,3200,1800 pitch=12800
>[  339.881939] [drm:drm_atomic_state_clear] Clearing atomic state ffff880143ebf480
>[  339.881943] [drm:drm_atomic_state_free] Freeing atomic state ffff880143ebf480
>[  339.881947] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880143ebf480
>[  339.881951] [drm:drm_atomic_get_plane_state] Added [PLANE:19] ffff880004df2e40 state to ffff880143ebf480
>[  339.881953] [drm:drm_atomic_check_only] checking ffff880143ebf480
>[  339.881957] [drm:drm_atomic_commit] commiting ffff880143ebf480
>[  339.881962] [drm:drm_atomic_state_clear] Clearing atomic state ffff880143ebf480
>[  339.881966] [drm:drm_atomic_state_free] Freeing atomic state ffff880143ebf480
>[  339.881969] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880143ebf480
>[  339.881975] [drm:drm_atomic_get_plane_state] Added [PLANE:21] ffff880004df23c0 state to ffff880143ebf480
>[  339.881977] [drm:drm_atomic_check_only] checking ffff880143ebf480
>[  339.881981] [drm:drm_atomic_commit] commiting ffff880143ebf480
>[  339.881984] [drm:drm_atomic_state_clear] Clearing atomic state ffff880143ebf480
>[  339.881987] [drm:drm_atomic_state_free] Freeing atomic state ffff880143ebf480
>[  339.881990] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880143ebf480
>[  339.881994] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff880004df2f00 state to ffff880143ebf480
>[  339.881996] [drm:drm_atomic_check_only] checking ffff880143ebf480
>[  339.881999] [drm:drm_atomic_commit] commiting ffff880143ebf480
>[  339.882002] [drm:drm_atomic_state_clear] Clearing atomic state ffff880143ebf480
>[  339.882005] [drm:drm_atomic_state_free] Freeing atomic state ffff880143ebf480
>[  339.882009] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880143ebf480
>[  339.882012] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff880004df2540 state to ffff880143ebf480
>[  339.882014] [drm:drm_atomic_check_only] checking ffff880143ebf480
>[  339.882018] [drm:drm_atomic_commit] commiting ffff880143ebf480
>[  339.882020] [drm:drm_atomic_state_clear] Clearing atomic state ffff880143ebf480
>[  339.882023] [drm:drm_atomic_state_free] Freeing atomic state ffff880143ebf480
>[  339.882027] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880143ebf480
>[  339.882030] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff880004df2180 state to ffff880143ebf480
>[  339.882032] [drm:drm_atomic_check_only] checking ffff880143ebf480
>[  339.882035] [drm:drm_atomic_commit] commiting ffff880143ebf480
>[  339.882038] [drm:drm_atomic_state_clear] Clearing atomic state ffff880143ebf480
>[  339.882041] [drm:drm_atomic_state_free] Freeing atomic state ffff880143ebf480
>[  339.882044] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880143ebf480
>[  339.882047] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff880004df2000 state to ffff880143ebf480
>[  339.882050] [drm:drm_atomic_check_only] checking ffff880143ebf480
>[  339.882053] [drm:drm_atomic_commit] commiting ffff880143ebf480
>[  339.882056] [drm:drm_atomic_state_clear] Clearing atomic state ffff880143ebf480
>[  339.882058] [drm:drm_atomic_state_free] Freeing atomic state ffff880143ebf480
>[  339.882062] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880143ebf480
>[  339.882065] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff880004df26c0 state to ffff880143ebf480
>[  339.882068] [drm:drm_atomic_check_only] checking ffff880143ebf480
>[  339.882070] [drm:drm_atomic_commit] commiting ffff880143ebf480
>[  339.882073] [drm:drm_atomic_state_clear] Clearing atomic state ffff880143ebf480
>[  339.882076] [drm:drm_atomic_state_free] Freeing atomic state ffff880143ebf480
>[  339.882079] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880143ebf480
>[  339.882083] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff880004dfe0c0 state to ffff880143ebf480
>[  339.882086] [drm:drm_atomic_check_only] checking ffff880143ebf480
>[  339.882089] [drm:drm_atomic_commit] commiting ffff880143ebf480
>[  339.882092] [drm:drm_atomic_state_clear] Clearing atomic state ffff880143ebf480
>[  339.882094] [drm:drm_atomic_state_free] Freeing atomic state ffff880143ebf480
>[  339.882098] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880143ebf480
>[  339.882101] [drm:drm_atomic_get_plane_state] Added [PLANE:29] ffff880004dfe3c0 state to ffff880143ebf480
>[  339.882103] [drm:drm_atomic_check_only] checking ffff880143ebf480
>[  339.882106] [drm:drm_atomic_commit] commiting ffff880143ebf480
>[  339.882109] [drm:drm_atomic_state_clear] Clearing atomic state ffff880143ebf480
>[  339.882112] [drm:drm_atomic_state_free] Freeing atomic state ffff880143ebf480
>[  339.882115] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880143ebf480
>[  339.882119] [drm:drm_atomic_get_plane_state] Added [PLANE:31] ffff880004dfec00 state to ffff880143ebf480
>[  339.882121] [drm:drm_atomic_check_only] checking ffff880143ebf480
>[  339.882124] [drm:drm_atomic_commit] commiting ffff880143ebf480
>[  339.882127] [drm:drm_atomic_state_clear] Clearing atomic state ffff880143ebf480
>[  339.882130] [drm:drm_atomic_state_free] Freeing atomic state ffff880143ebf480
>[  339.882133] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880143ebf480
>[  339.882136] [drm:drm_atomic_get_plane_state] Added [PLANE:32] ffff880004dfee40 state to ffff880143ebf480
>[  339.882139] [drm:drm_atomic_check_only] checking ffff880143ebf480
>[  339.882142] [drm:drm_atomic_commit] commiting ffff880143ebf480
>[  339.882145] [drm:drm_atomic_state_clear] Clearing atomic state ffff880143ebf480
>[  339.882148] [drm:drm_atomic_state_free] Freeing atomic state ffff880143ebf480
>[  339.882153] [drm:intel_crtc_set_config] [CRTC:20] [FB:57] #connectors=1 (x y) (0 0)
>[  339.882159] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[  339.882163] [drm:intel_modeset_stage_output_state] [CONNECTOR:34:eDP-1] to [CRTC:20]
>[  339.882169] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  339.882173] [drm:connected_sink_compute_bpp] [CONNECTOR:34:eDP-1] checking for sink bpp constrains
>[  339.882180] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 14 pixel clock 361310KHz
>[  339.882183] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[  339.882187] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 18
>[  339.882191] [drm:intel_dp_compute_config] DP link bw required 650358 available 1728000
>[  339.882195] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[  339.882198] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  339.882201] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[  339.882204] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  339.882208] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  339.882212] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 3157174, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
>[  339.882216] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  339.882219] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  339.882221] [drm:intel_dump_pipe_config] requested mode:
>[  339.882227] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
>[  339.882230] [drm:intel_dump_pipe_config] adjusted mode:
>[  339.882234] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
>[  339.882239] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
>[  339.882242] [drm:intel_dump_pipe_config] port clock: 540000
>[  339.882245] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  339.882248] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  339.882252] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.882254] [drm:intel_dump_pipe_config] ips: 0
>[  339.882257] [drm:intel_dump_pipe_config] double wide: 0
>[  339.882260] [drm:intel_crtc_set_config] [CRTC:25] [NOFB]
>[  339.882264] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[  339.882268] [drm:intel_modeset_stage_output_state] [CONNECTOR:34:eDP-1] to [CRTC:20]
>[  339.882272] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  339.882276] [drm:intel_crtc_set_config] [CRTC:30] [NOFB]
>[  339.882279] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=0, fb_changed=0
>[  339.882282] [drm:intel_modeset_stage_output_state] [CONNECTOR:34:eDP-1] to [CRTC:20]
>[  339.882286] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  339.882317] [drm:i915_gem_open] 
>[  339.885087] [drm:gen8_ppgtt_init] Allocated 4 pages for page directories (0 wasted)
>[  339.885090] [drm:gen8_ppgtt_init] Allocated 2048 pages for page tables (0 wasted)
>[  339.885994] [drm:i915_gem_open] 
>[  339.888552] [drm:gen8_ppgtt_init] Allocated 4 pages for page directories (0 wasted)
>[  339.888555] [drm:gen8_ppgtt_init] Allocated 2048 pages for page tables (0 wasted)
>[  339.888903] pm_rps: starting subtest blocking
>[  339.888930] [drm:i915_gem_open] 
>[  339.891424] [drm:gen8_ppgtt_init] Allocated 4 pages for page directories (0 wasted)
>[  339.891428] [drm:gen8_ppgtt_init] Allocated 2048 pages for page tables (0 wasted)
>[  375.150088] pm_rps: exiting, ret=99
>[  375.153493] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88009a4306c0
>[  375.153503] [drm:drm_atomic_get_plane_state] Added [PLANE:17] ffff880004eb1c00 state to ffff88009a4306c0
>[  375.153515] [drm:drm_atomic_get_crtc_state] Added [CRTC:20] ffff88009a62a000 state to ffff88009a4306c0
>[  375.153519] [drm:drm_atomic_check_only] checking ffff88009a4306c0
>[  375.153526] [drm:drm_atomic_commit] commiting ffff88009a4306c0
>[  375.153546] [drm:skylake_update_primary_plane] Writing base 016C0000 0,0,3200,1800 pitch=12800
>[  375.153556] [drm:drm_atomic_state_clear] Clearing atomic state ffff88009a4306c0
>[  375.153560] [drm:drm_atomic_state_free] Freeing atomic state ffff88009a4306c0
>[  375.153564] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88009a4306c0
>[  375.153568] [drm:drm_atomic_get_plane_state] Added [PLANE:19] ffff880004eb1d80 state to ffff88009a4306c0
>[  375.153570] [drm:drm_atomic_check_only] checking ffff88009a4306c0
>[  375.153574] [drm:drm_atomic_commit] commiting ffff88009a4306c0
>[  375.153577] [drm:drm_atomic_state_clear] Clearing atomic state ffff88009a4306c0
>[  375.153580] [drm:drm_atomic_state_free] Freeing atomic state ffff88009a4306c0
>[  375.153583] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88009a4306c0
>[  375.153587] [drm:drm_atomic_get_plane_state] Added [PLANE:21] ffff880004eb1cc0 state to ffff88009a4306c0
>[  375.153590] [drm:drm_atomic_check_only] checking ffff88009a4306c0
>[  375.153593] [drm:drm_atomic_commit] commiting ffff88009a4306c0
>[  375.153596] [drm:drm_atomic_state_clear] Clearing atomic state ffff88009a4306c0
>[  375.153599] [drm:drm_atomic_state_free] Freeing atomic state ffff88009a4306c0
>[  375.153603] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88009a4306c0
>[  375.153606] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff880004eb1e40 state to ffff88009a4306c0
>[  375.153609] [drm:drm_atomic_check_only] checking ffff88009a4306c0
>[  375.153612] [drm:drm_atomic_commit] commiting ffff88009a4306c0
>[  375.153615] [drm:drm_atomic_state_clear] Clearing atomic state ffff88009a4306c0
>[  375.153618] [drm:drm_atomic_state_free] Freeing atomic state ffff88009a4306c0
>[  375.153621] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88009a4306c0
>[  375.153624] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff880004eb1000 state to ffff88009a4306c0
>[  375.153627] [drm:drm_atomic_check_only] checking ffff88009a4306c0
>[  375.153630] [drm:drm_atomic_commit] commiting ffff88009a4306c0
>[  375.153633] [drm:drm_atomic_state_clear] Clearing atomic state ffff88009a4306c0
>[  375.153636] [drm:drm_atomic_state_free] Freeing atomic state ffff88009a4306c0
>[  375.153639] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88009a4306c0
>[  375.153642] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff880004eb10c0 state to ffff88009a4306c0
>[  375.153645] [drm:drm_atomic_check_only] checking ffff88009a4306c0
>[  375.153648] [drm:drm_atomic_commit] commiting ffff88009a4306c0
>[  375.153651] [drm:drm_atomic_state_clear] Clearing atomic state ffff88009a4306c0
>[  375.153654] [drm:drm_atomic_state_free] Freeing atomic state ffff88009a4306c0
>[  375.153657] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88009a4306c0
>[  375.153660] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff880004eb1180 state to ffff88009a4306c0
>[  375.153663] [drm:drm_atomic_check_only] checking ffff88009a4306c0
>[  375.153665] [drm:drm_atomic_commit] commiting ffff88009a4306c0
>[  375.153668] [drm:drm_atomic_state_clear] Clearing atomic state ffff88009a4306c0
>[  375.153671] [drm:drm_atomic_state_free] Freeing atomic state ffff88009a4306c0
>[  375.153675] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88009a4306c0
>[  375.153678] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff880004eb1480 state to ffff88009a4306c0
>[  375.153680] [drm:drm_atomic_check_only] checking ffff88009a4306c0
>[  375.153683] [drm:drm_atomic_commit] commiting ffff88009a4306c0
>[  375.153686] [drm:drm_atomic_state_clear] Clearing atomic state ffff88009a4306c0
>[  375.153689] [drm:drm_atomic_state_free] Freeing atomic state ffff88009a4306c0
>[  375.153692] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88009a4306c0
>[  375.153696] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff880004eb1b40 state to ffff88009a4306c0
>[  375.153698] [drm:drm_atomic_check_only] checking ffff88009a4306c0
>[  375.153701] [drm:drm_atomic_commit] commiting ffff88009a4306c0
>[  375.153704] [drm:drm_atomic_state_clear] Clearing atomic state ffff88009a4306c0
>[  375.153707] [drm:drm_atomic_state_free] Freeing atomic state ffff88009a4306c0
>[  375.153710] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88009a4306c0
>[  375.153714] [drm:drm_atomic_get_plane_state] Added [PLANE:29] ffff880004eb1900 state to ffff88009a4306c0
>[  375.153716] [drm:drm_atomic_check_only] checking ffff88009a4306c0
>[  375.153719] [drm:drm_atomic_commit] commiting ffff88009a4306c0
>[  375.153722] [drm:drm_atomic_state_clear] Clearing atomic state ffff88009a4306c0
>[  375.153725] [drm:drm_atomic_state_free] Freeing atomic state ffff88009a4306c0
>[  375.153728] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88009a4306c0
>[  375.153731] [drm:drm_atomic_get_plane_state] Added [PLANE:31] ffff880004eb1840 state to ffff88009a4306c0
>[  375.153734] [drm:drm_atomic_check_only] checking ffff88009a4306c0
>[  375.153737] [drm:drm_atomic_commit] commiting ffff88009a4306c0
>[  375.153740] [drm:drm_atomic_state_clear] Clearing atomic state ffff88009a4306c0
>[  375.153742] [drm:drm_atomic_state_free] Freeing atomic state ffff88009a4306c0
>[  375.153746] [drm:drm_atomic_state_alloc] Allocate atomic state ffff88009a4306c0
>[  375.153749] [drm:drm_atomic_get_plane_state] Added [PLANE:32] ffff880004eb1f00 state to ffff88009a4306c0
>[  375.153752] [drm:drm_atomic_check_only] checking ffff88009a4306c0
>[  375.153754] [drm:drm_atomic_commit] commiting ffff88009a4306c0
>[  375.153757] [drm:drm_atomic_state_clear] Clearing atomic state ffff88009a4306c0
>[  375.153760] [drm:drm_atomic_state_free] Freeing atomic state ffff88009a4306c0
>[  375.153765] [drm:intel_crtc_set_config] [CRTC:20] [FB:57] #connectors=1 (x y) (0 0)
>[  375.153772] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[  375.153776] [drm:intel_modeset_stage_output_state] [CONNECTOR:34:eDP-1] to [CRTC:20]
>[  375.153782] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  375.153786] [drm:connected_sink_compute_bpp] [CONNECTOR:34:eDP-1] checking for sink bpp constrains
>[  375.153792] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 14 pixel clock 361310KHz
>[  375.153795] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[  375.153799] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 18
>[  375.153803] [drm:intel_dp_compute_config] DP link bw required 650358 available 1728000
>[  375.153807] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[  375.153810] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  375.153813] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[  375.153816] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  375.153820] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  375.153825] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 3157174, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
>[  375.153828] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  375.153831] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  375.153834] [drm:intel_dump_pipe_config] requested mode:
>[  375.153842] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
>[  375.153844] [drm:intel_dump_pipe_config] adjusted mode:
>[  375.153849] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
>[  375.153854] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
>[  375.153857] [drm:intel_dump_pipe_config] port clock: 540000
>[  375.153859] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  375.153863] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  375.153866] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.153869] [drm:intel_dump_pipe_config] ips: 0
>[  375.153871] [drm:intel_dump_pipe_config] double wide: 0
>[  375.153875] [drm:intel_crtc_set_config] [CRTC:25] [NOFB]
>[  375.153879] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[  375.153882] [drm:intel_modeset_stage_output_state] [CONNECTOR:34:eDP-1] to [CRTC:20]
>[  375.153887] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  375.153890] [drm:intel_crtc_set_config] [CRTC:30] [NOFB]
>[  375.153893] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=0, fb_changed=0
>[  375.153897] [drm:intel_modeset_stage_output_state] [CONNECTOR:34:eDP-1] to [CRTC:20]
>[  375.153900] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0

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