Attachment 114435 Details for Bug 89612 – dmesg DRM debug info when trying an xrandr --auto, as requested

dmesg DRM debug info when trying an xrandr --auto, as requested

dmesg.log (text/plain), 598.15 KB, created by Tim Besard on 2015-03-18 10:03:06 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Tim Besard

Created: 2015-03-18 10:03:06 UTC

Size: 598.15 KB

patch

obsolete

>[  880.804484] xrandr --output DP2-1 --off --output DP2-2 --off
>               --> disable external MST monitors
>[  881.252759] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec60c0
>[  881.252778] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6d80
>[  881.254749] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6e40
>[  881.254767] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec60c0
>[  881.256759] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6d80
>[  881.256778] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6e40
>[  881.258752] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec60c0
>[  881.258773] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6d80
>[  881.260775] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6e40
>[  881.260799] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec60c0
>[  881.262719] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6d80
>[  881.262741] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6e40
>[  881.264746] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec60c0
>[  881.264766] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6d80
>[  881.266750] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6e40
>[  881.266771] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec60c0
>[  881.268747] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6d80
>[  881.268767] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6e40
>[  881.270689] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec60c0
>[  881.270707] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6d80
>[  881.272701] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6e40
>[  881.272722] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec60c0
>[  881.274749] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6d80
>[  881.274769] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6e40
>[  881.276769] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec60c0
>[  881.276791] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6d80
>[  881.278759] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6e40
>[  881.278781] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec60c0
>[  881.280751] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6d80
>[  881.280772] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6e40
>[  881.282698] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec60c0
>[  881.282718] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6d80
>[  881.284745] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6e40
>[  881.284764] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec60c0
>[  881.286739] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6d80
>[  881.286759] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6e40
>[  881.288741] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec60c0
>[  881.288760] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6d80
>[  881.290744] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6e40
>[  881.290764] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec60c0
>[  881.292701] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6d80
>[  881.292797] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6e40
>[  881.294753] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec60c0
>[  881.294776] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6d80
>[  881.296750] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6e40
>[  881.296773] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec60c0
>[  881.298736] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6d80
>[  881.298756] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6e40
>[  881.300739] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec60c0
>[  881.300758] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6d80
>[  881.302692] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6e40
>[  881.302711] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec60c0
>[  881.304732] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6d80
>[  881.304751] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6e40
>[  881.306736] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec60c0
>[  881.306755] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6d80
>[  881.308736] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6e40
>[  881.308756] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec60c0
>[  881.310756] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6d80
>[  881.310780] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6e40
>[  881.312699] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec60c0
>[  881.312722] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6d80
>[  881.314730] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6e40
>[  881.314750] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec60c0
>[  881.316738] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6d80
>[  881.316758] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6e40
>[  881.320733] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec60c0
>[  881.320753] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6d80
>[  881.454681] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6e40
>[  881.454701] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec60c0
>[  881.456683] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6d80
>[  881.456703] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6e40
>[  881.458679] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec60c0
>[  881.458700] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6d80
>[  881.460703] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6e40
>[  881.460727] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec60c0
>[  881.462646] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6d80
>[  881.462668] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6e40
>[  881.464675] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec60c0
>[  881.464695] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6d80
>[  881.466631] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.466652] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.468682] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.468702] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.470687] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.470708] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.472644] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.472664] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.474682] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.474703] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.476700] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.476723] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.478701] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.478724] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.480684] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.480703] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.482642] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.482661] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.484678] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.484698] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.486674] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.486694] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.488676] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.488696] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.490681] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.490703] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.492647] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.492670] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.494685] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.494708] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.496684] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.496705] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.498675] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.498694] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.500677] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.500697] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.502630] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.502649] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.504665] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.504684] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.506672] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.506693] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.508671] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.508690] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.510687] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.510710] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.512646] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.512669] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.514663] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.514685] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.516670] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.516692] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.520662] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.520682] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.526681] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.526703] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.528680] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.528703] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.530662] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.530683] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.532624] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.532643] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.534657] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.534677] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.538659] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.538680] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.540661] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.540683] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.542621] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.542643] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.544671] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.544693] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.546662] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.546683] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.548655] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.548674] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.550661] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.550682] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.552613] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.552632] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.554645] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.554665] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.556657] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.556678] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.558650] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.558670] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.560674] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.560698] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.562626] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.562649] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.592645] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.592666] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.594650] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.594672] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.596652] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.596673] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.598635] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.598655] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.600638] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.600657] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.602601] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.602620] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.604634] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.604653] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.606639] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.606660] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.608632] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.608653] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.612664] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.612686] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.614629] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.614649] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.616630] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.616651] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.618625] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.618644] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.620628] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.620649] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.622589] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.622611] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.624628] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.624649] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.628647] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.628668] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.630627] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.630648] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.634625] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.634646] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.638622] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e9c0
>[  881.638647] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e240
>[  881.640625] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e0c0
>[  881.640646] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e9c0
>[  881.684615] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030d53e240
>[  881.684635] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030d53e0c0
>[  881.910543] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8800c9e76180
>[  881.910565] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76240
>[  881.918514] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8800c9e763c0
>[  881.918532] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76180
>[  882.499432] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  882.499444] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
>[  882.499449] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
>[  882.499465] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  882.499477] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  882.499842] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[  882.500185] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[  882.500210] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  882.500217] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
>[  882.500224] [drm:drm_mode_debug_printmodeline] Modeline 32:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  882.500232] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  882.500434] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[  882.500438] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1]
>[  882.500441] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[  882.500449] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1] disconnected
>[  882.500456] [drm:drm_mode_getconnector] [CONNECTOR:46:?]
>[  882.500459] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2]
>[  882.500462] [drm:intel_dp_detect] [CONNECTOR:46:DP-2]
>[  882.500466] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2] disconnected
>[  882.500475] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  882.500479] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3]
>[  882.501810] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.501822] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.501859] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.502387] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.503493] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.503499] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.505218] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.505225] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.505248] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.505757] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.507511] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.507516] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.508357] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.508362] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.508373] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.508877] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.510613] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.510617] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.511435] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.511441] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.511461] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.511956] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.513035] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  882.513056] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3] probed modes :
>[  882.513064] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  882.513072] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  882.513078] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  882.513085] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  882.513092] [drm:drm_mode_debug_printmodeline] Modeline 61:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  882.513098] [drm:drm_mode_debug_printmodeline] Modeline 69:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  882.513105] [drm:drm_mode_debug_printmodeline] Modeline 70:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  882.513112] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  882.513118] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  882.513125] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  882.513131] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  882.513138] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  882.513157] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  882.513211] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  882.513215] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4]
>[  882.513710] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.513714] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.515018] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.515021] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.515032] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.515530] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.516578] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.516581] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.518322] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.518324] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.518336] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.518841] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.520569] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.520572] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.521433] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.521435] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.521445] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.521944] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.523688] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.523691] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.524534] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.524536] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.524547] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.525045] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.526113] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  882.526128] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4] probed modes :
>[  882.526135] [drm:drm_mode_debug_printmodeline] Modeline 73:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  882.526140] [drm:drm_mode_debug_printmodeline] Modeline 76:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  882.526146] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  882.526151] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  882.526156] [drm:drm_mode_debug_printmodeline] Modeline 74:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  882.526162] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  882.526167] [drm:drm_mode_debug_printmodeline] Modeline 83:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  882.526172] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  882.526177] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  882.526182] [drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  882.526187] [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  882.526193] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  882.526206] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  882.526239] [drm:drm_mode_getconnector] [CONNECTOR:57:?]
>[  882.526242] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5]
>[  882.526246] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5] disconnected
>[  882.526252] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[  882.526255] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[  882.526258] [drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[  882.526826] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.526829] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.538464] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  882.538467] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[  882.538473] [drm:drm_mode_getconnector] [CONNECTOR:50:?]
>[  882.538475] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2]
>[  882.538477] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-2]
>[  882.538691] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  882.538695] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  882.538697] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2] disconnected
>[  882.540579] [drm:drm_mode_setcrtc] [CRTC:24]
>[  882.540584] [drm:intel_crtc_set_config] [CRTC:24] [NOFB]
>[  882.540589] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=1, fb_changed=0
>[  882.540591] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [NOCRTC]
>[  882.540593] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  882.540595] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  882.540597] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[  882.540599] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  882.540601] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  882.540605] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[  882.545115] [drm:intel_mst_disable_dp] 2
>[  882.545120] [drm:drm_dp_destroy_payload_step1] 
>[  882.546588] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.546593] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.546604] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.547105] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.548180] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.548183] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.548723] [drm:drm_dp_update_payload_part1] removing payload 0
>[  882.555194] [drm:intel_mst_post_disable_dp] 2
>[  882.555384] [drm:drm_dp_update_payload_part2] payload 0 2
>[  882.555389] [drm:drm_dp_mst_put_payload_id] putting payload 1
>[  882.555402] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802f9ec6c00
>[  882.555420] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[  882.555426] [drm:intel_connector_check_state] [CONNECTOR:55:DP-4]
>[  882.555428] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  882.555430] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  882.555432] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  882.555434] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  882.555435] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  882.555437] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  882.555439] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  882.555441] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  882.555442] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  882.555444] [drm:check_crtc_state] [CRTC:20]
>[  882.555453] [drm:check_crtc_state] [CRTC:24]
>[  882.555455] [drm:check_crtc_state] [CRTC:28]
>[  882.555462] [drm:check_shared_dpll_state] WRPLL 1
>[  882.555464] [drm:check_shared_dpll_state] WRPLL 2
>[  882.555520] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6240
>[  882.555534] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802f9ec6480
>[  882.555856] [drm:drm_mode_setcrtc] [CRTC:28]
>[  882.555860] [drm:intel_crtc_set_config] [CRTC:28] [NOFB]
>[  882.555866] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:28], mode_changed=1, fb_changed=0
>[  882.555869] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [NOCRTC]
>[  882.555872] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  882.555875] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  882.555878] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  882.555881] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  882.555885] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 4
>[  882.561804] [drm:intel_mst_disable_dp] 1
>[  882.561809] [drm:drm_dp_destroy_payload_step1] 
>[  882.654179] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.654185] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.654222] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.654744] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.655812] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.655815] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.656336] [drm:drm_dp_update_payload_part1] removing payload 0
>[  882.675142] [drm:intel_mst_post_disable_dp] 1
>[  882.675325] [drm:drm_dp_mst_put_payload_id] putting payload 2
>[  882.675677] [drm:intel_fbc_update] disabled per chip default
>[  882.675682] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802f9ec6e40
>[  882.675697] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[  882.675701] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  882.675702] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  882.675704] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  882.675705] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  882.675706] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  882.675707] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  882.675709] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  882.675710] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  882.675711] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  882.675712] [drm:check_crtc_state] [CRTC:20]
>[  882.675720] [drm:check_crtc_state] [CRTC:24]
>[  882.675721] [drm:check_crtc_state] [CRTC:28]
>[  882.675723] [drm:check_shared_dpll_state] WRPLL 1
>[  882.675725] [drm:check_shared_dpll_state] WRPLL 2
>[  882.675744] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802f9ec6d80
>[  882.675756] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9ec6180
>[  882.675988] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802f9ec6240
>[  882.682872] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.682876] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.682904] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.683386] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.694974] [drm:drm_mode_addfb2] [FB:87]
>[  882.695331] [drm:drm_mode_setcrtc] [CRTC:20]
>[  882.695341] [drm:drm_mode_setcrtc] [CONNECTOR:31:eDP-1]
>[  882.695345] [drm:intel_crtc_set_config] [CRTC:20] [FB:87] #connectors=1 (x y) (0 0)
>[  882.695354] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=1
>[  882.695356] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  882.695359] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  882.695363] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[  882.695364] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[  882.695371] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz
>[  882.695373] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[  882.695375] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000
>[  882.695377] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[  882.695379] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  882.695381] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[  882.695382] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  882.695384] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  882.695386] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64
>[  882.695388] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  882.695389] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  882.695390] [drm:intel_dump_pipe_config] requested mode:
>[  882.695393] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 0 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x0 0x9
>[  882.695395] [drm:intel_dump_pipe_config] adjusted mode:
>[  882.695397] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  882.695400] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9
>[  882.695401] [drm:intel_dump_pipe_config] port clock: 270000
>[  882.695402] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  882.695404] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  882.695406] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  882.695407] [drm:intel_dump_pipe_config] ips: 1
>[  882.695408] [drm:intel_dump_pipe_config] double wide: 0
>[  882.695413] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02540
>[  882.697457] [drm:ironlake_update_primary_plane] Writing base 0A67C000 00000000 0 0 7680
>[  882.709290] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  882.725852] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9ec6240
>[  882.788779] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  882.788846] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  882.788897] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  882.788946] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  882.789060] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  882.801364] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  882.801369] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
>[  882.801370] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
>[  882.801691] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[  882.801990] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[  882.801998] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  882.802001] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
>[  882.802003] [drm:drm_mode_debug_printmodeline] Modeline 32:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  882.802006] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  882.802086] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[  882.802088] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1]
>[  882.802088] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[  882.802093] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1] disconnected
>[  882.802096] [drm:drm_mode_getconnector] [CONNECTOR:46:?]
>[  882.802097] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2]
>[  882.802098] [drm:intel_dp_detect] [CONNECTOR:46:DP-2]
>[  882.802099] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2] disconnected
>[  882.802102] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  882.802104] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3]
>[  882.803399] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.803409] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.803432] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.803918] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.804938] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.804940] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.806657] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.806660] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.806667] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.807151] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.808863] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.808864] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.809697] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.809698] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.809715] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.810194] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.811879] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.811881] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.812734] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.812735] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.812740] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.813218] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.814248] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  882.814258] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3] probed modes :
>[  882.814261] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  882.814264] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  882.814266] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  882.814269] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  882.814271] [drm:drm_mode_debug_printmodeline] Modeline 61:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  882.814274] [drm:drm_mode_debug_printmodeline] Modeline 69:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  882.814276] [drm:drm_mode_debug_printmodeline] Modeline 70:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  882.814279] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  882.814281] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  882.814283] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  882.814286] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  882.814288] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  882.814300] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  882.814329] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  882.814331] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4]
>[  882.814886] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.814887] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.816180] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.816181] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.816188] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.816667] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.817668] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.817670] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.819412] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.819414] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.819428] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.819908] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.821583] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.821584] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.822458] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.822460] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.822470] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.822956] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.824641] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.824642] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.825503] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  882.825504] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  882.825517] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  882.826004] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  882.827041] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  882.827049] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4] probed modes :
>[  882.827052] [drm:drm_mode_debug_printmodeline] Modeline 73:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  882.827055] [drm:drm_mode_debug_printmodeline] Modeline 76:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  882.827057] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  882.827060] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  882.827062] [drm:drm_mode_debug_printmodeline] Modeline 74:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  882.827065] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  882.827067] [drm:drm_mode_debug_printmodeline] Modeline 83:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  882.827070] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  882.827072] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  882.827074] [drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  882.827077] [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  882.827079] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  882.827088] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  882.827115] [drm:drm_mode_getconnector] [CONNECTOR:57:?]
>[  882.827117] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5]
>[  882.827118] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5] disconnected
>[  882.827121] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[  882.827123] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[  882.827125] [drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[  882.827731] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  882.827733] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  882.838351] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  882.838353] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[  882.838359] [drm:drm_mode_getconnector] [CONNECTOR:50:?]
>[  882.838360] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2]
>[  882.838361] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-2]
>[  882.838582] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  882.838584] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  882.838585] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2] disconnected
>[  883.013724] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  883.039460] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  883.039582] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  883.643907] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  883.647883] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.649904] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  883.651871] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.653901] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  883.657893] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.659890] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  883.661864] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.663818] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  883.665880] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.667888] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  883.669877] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.671893] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  883.673874] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.675891] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  883.677835] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203000
>[  883.679779] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.681849] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  883.683874] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.685877] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  883.687835] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203c00
>[  883.689869] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.691887] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.693872] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.695867] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.697863] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.699848] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.701846] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.703861] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.705863] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.707861] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.709871] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.711821] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.713870] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.715781] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.717863] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.719858] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.723858] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.725868] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.727852] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.729863] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.731864] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.733853] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.735837] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.737848] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.739851] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  883.741761] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  883.743855] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.745847] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  883.747848] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.749846] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  883.751835] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.753841] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  883.755845] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.757840] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  883.759852] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.761841] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  883.763842] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.765840] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  883.767845] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.769842] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  883.771850] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.773836] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  883.775850] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.777835] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  883.779840] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.781849] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  883.783838] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.785844] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  883.787834] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.789832] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  883.793839] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.795839] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  883.801832] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.805828] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  883.809834] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.815827] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  883.819824] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.825839] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  883.833824] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9840
>[  883.843824] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.907800] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  883.911805] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.915787] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  883.919784] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.921799] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  883.923784] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.925800] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  883.927787] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.929781] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  883.931794] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.935778] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  883.939779] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  883.955803] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  884.112469] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  884.112549] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  884.265716] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  884.267579] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  884.269552] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  884.271563] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9180
>[  884.273593] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  884.275570] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc99c0
>[  884.277589] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  884.279526] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  884.281535] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  884.283521] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  884.285534] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203b40
>[  884.287571] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203c00
>[  884.289536] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203b40
>[  884.291529] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203c00
>[  884.293524] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203b40
>[  884.295528] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9000
>[  884.297532] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  884.299518] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  884.301519] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  884.303518] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  884.305515] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  884.307512] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  884.309519] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  884.311522] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  884.313506] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  884.317512] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  884.321508] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  884.325506] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  884.329505] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  884.333504] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  884.337502] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  884.339506] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  884.343511] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9000
>[  884.345515] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  884.347510] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc99c0
>[  884.349507] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  884.351501] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  884.353493] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  884.355500] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  884.357491] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  884.359497] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  884.361495] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  884.363507] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9180
>[  884.365508] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  884.367501] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9840
>[  884.369509] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  884.371496] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  884.373488] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  884.375490] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  884.377483] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  884.379490] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  884.381502] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  884.381943] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  884.383521] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  884.385490] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  884.387485] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  884.389488] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  884.391519] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  884.393504] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  884.395510] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  884.397482] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  884.399482] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  884.401480] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  884.403491] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  884.403889] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9900
>[  884.405497] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  884.407481] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  884.409494] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203c00
>[  884.411512] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203000
>[  884.413487] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203c00
>[  884.415481] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203000
>[  884.417478] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203c00
>[  884.419483] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203000
>[  884.421482] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203c00
>[  884.423478] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203000
>[  884.425481] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  884.427492] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  884.429468] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  884.431470] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  884.433477] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  884.435489] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  884.437465] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  884.439471] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  884.441474] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  884.443465] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  884.445465] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  884.447458] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  884.449463] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  884.451464] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  884.453475] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203c00
>[  884.455468] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203000
>[  884.457466] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203c00
>[  884.459469] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203000
>[  884.461468] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9540
>[  884.463491] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  884.465456] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  884.467461] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  884.469451] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  884.471455] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  884.473448] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  884.475455] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  884.477445] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  884.479451] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  884.481463] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  884.483463] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9cc0
>[  884.485467] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  884.487447] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  884.489449] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  884.491451] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  884.493455] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9cc0
>[  884.495461] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  884.497444] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  884.499442] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  884.501443] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  884.503452] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9540
>[  884.505460] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  884.507442] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  884.509441] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  884.511438] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  884.513447] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  884.515450] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  884.517436] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  884.519437] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  884.521437] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  884.523447] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  884.525451] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  884.527434] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  884.529438] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  884.531445] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  884.533457] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9900
>[  884.535446] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  884.537430] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  884.539436] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  884.541438] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  884.543423] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76d80
>[  884.545429] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  884.547426] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76d80
>[  884.549428] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  884.551425] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76d80
>[  884.553435] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  884.555443] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  884.557419] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  884.559424] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  884.561424] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  884.563432] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9840
>[  884.565437] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  884.567420] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  884.569420] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  884.571421] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  884.573428] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9180
>[  884.575427] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  884.577415] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  884.579420] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  884.581432] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc99c0
>[  884.583422] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  884.585420] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9000
>[  884.589432] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  884.591420] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9000
>[  884.593420] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  884.597409] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  884.601413] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  884.603418] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  884.605410] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  884.613405] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  884.619404] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  884.629399] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  884.633395] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  884.645405] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc99c0
>[  884.651409] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  884.659413] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  884.667391] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  884.671391] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203c00
>[  884.675392] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203b40
>[  884.677387] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9180
>[  884.679388] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  884.683390] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  884.685383] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  884.687382] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  884.691387] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  884.695379] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  884.699380] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  884.703376] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  884.705375] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  884.707377] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  884.713374] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  884.721395] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9840
>[  884.749491] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  885.027402] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  885.029265] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  885.033258] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  885.039276] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  885.041259] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  885.043256] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  885.045251] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  885.047255] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  885.051264] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  885.053251] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  885.055249] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  885.057249] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  885.059254] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  885.061248] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  885.063247] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  885.065245] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  885.067247] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  885.069250] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  885.071241] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  885.073247] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9900
>[  885.075257] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  885.077234] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  885.079245] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  885.081253] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  885.083247] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  885.085246] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb000
>[  885.087252] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  885.091237] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  885.093239] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddbd80
>[  885.095235] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb6c0
>[  885.097235] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddbd80
>[  885.099238] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb6c0
>[  885.101233] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddbd80
>[  885.103232] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb6c0
>[  885.105231] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddbd80
>[  885.107233] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb6c0
>[  885.109233] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9540
>[  885.111242] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  885.113220] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  885.115227] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  885.117218] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  885.119223] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  885.121230] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  885.123219] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  885.125219] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  885.127214] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  885.129218] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  885.131218] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  885.133227] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddbd80
>[  885.135221] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb6c0
>[  885.137220] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddbd80
>[  885.139225] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb6c0
>[  885.141218] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddbd80
>[  885.143218] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb6c0
>[  885.145221] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddbd80
>[  885.147219] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb6c0
>[  885.149216] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddbd80
>[  885.151214] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb6c0
>[  885.153214] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddbd80
>[  885.155220] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb6c0
>[  885.157213] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddbd80
>[  885.159214] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  885.161209] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  885.163219] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9cc0
>[  885.165214] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  885.167202] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  885.169197] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  885.171213] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9cc0
>[  885.173220] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  885.175226] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  885.177200] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  885.179204] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  885.181198] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  885.183194] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  885.185204] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  885.187208] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  885.189200] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76d80
>[  885.191202] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  885.197203] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9540
>[  885.205212] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  885.391273] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76d80
>[  885.393142] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  885.395127] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76d80
>[  885.397131] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  885.399128] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  885.403126] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  885.405125] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  885.407123] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  885.409124] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  885.411125] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  885.413121] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  885.415120] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  885.417120] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  885.419123] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  885.421142] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  885.423106] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  885.425111] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  885.427107] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  885.429114] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  885.431109] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  885.433103] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  885.435110] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  885.437101] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  885.439104] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  885.441104] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  885.443113] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  885.445102] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  885.447098] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  885.449101] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  885.451102] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  885.453111] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  885.455117] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  885.457102] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  885.459103] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  885.461099] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  885.465095] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  885.467101] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  885.469096] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  885.471096] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  885.473095] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  885.475097] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  885.477094] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  885.481095] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  885.483100] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  885.485101] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  885.487085] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  885.489086] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  885.493086] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  885.495085] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  885.501085] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  885.505092] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9900
>[  885.509114] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  885.511081] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  885.513087] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  885.517094] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  885.523086] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9840
>[  885.531093] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  885.541076] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9180
>[  885.675173] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  885.683027] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  885.689022] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  885.695019] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  885.701019] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  885.705017] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  885.709024] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc99c0
>[  885.715019] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  885.717003] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  885.721016] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9000
>[  885.723022] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  885.725002] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  885.726996] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  885.729004] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  885.733014] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9000
>[  885.735009] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  885.736996] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  885.741005] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  885.743001] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  885.744996] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  885.747002] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  885.748998] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  885.750998] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  885.752998] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  885.756993] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  885.759000] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc99c0
>[  885.760997] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  885.762987] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  885.764988] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  885.766982] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  885.768990] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  885.770996] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  885.772979] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  885.774985] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  885.776979] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  885.778984] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  885.780981] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  885.782991] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9180
>[  885.784997] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  885.786992] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  885.790990] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  885.792974] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  885.794980] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  885.798975] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  885.803933] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[  885.803942] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  885.804975] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  885.806967] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  885.863099] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  885.904958] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  885.928958] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  885.938959] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9840
>[  885.944929] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  885.950924] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  885.958931] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb6c0
>[  885.960936] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  885.964922] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  885.970917] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  885.978920] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  885.982910] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  885.988921] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  885.994914] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  886.004905] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  886.024899] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  886.144987] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  886.174944] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  886.176858] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  886.178852] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb000
>[  886.180880] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  886.182848] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb000
>[  886.184843] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb6c0
>[  886.186845] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb000
>[  886.188853] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  886.190850] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  886.192838] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.194840] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  886.196829] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.198832] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  886.200831] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.202835] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  886.204831] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.206824] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  886.208832] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.210837] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  886.212823] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.214824] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  886.216819] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.218826] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  886.220822] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.222825] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  886.224823] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.226823] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  886.228830] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9900
>[  886.230838] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.232816] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  886.234825] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.236814] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  886.238816] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.240815] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  886.242812] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.244815] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  886.246820] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.248811] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  886.250816] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.252806] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  886.254809] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.256805] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  886.258815] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.260806] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  886.262812] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.264809] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  886.266805] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.268807] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  886.270805] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.272808] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  886.273016] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.274808] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  886.276812] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.278814] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  886.280813] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.282826] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  886.284802] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.286795] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  886.288804] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.290800] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  886.292804] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.294805] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  886.296795] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.302800] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  886.332807] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  886.380907] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  886.382793] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  886.388787] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.392782] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  886.394763] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.398764] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  886.400765] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.402757] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  886.404757] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.406750] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  886.408766] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9540
>[  886.410776] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.412751] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  886.414755] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.416755] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  886.418767] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9cc0
>[  886.420755] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9540
>[  886.422766] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.424749] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  886.426747] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.428751] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  886.430749] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  886.432765] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  886.434758] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  886.436745] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  886.438747] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  886.440746] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  886.442749] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  886.444745] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  886.446738] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  886.448771] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb6c0
>[  886.450757] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9cc0
>[  886.452758] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  886.454742] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  886.456741] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  886.458745] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  886.460739] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  886.462739] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  886.464736] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  886.466755] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  886.470753] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  886.472749] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  886.476734] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  886.886796] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  886.894670] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddbd80
>[  886.900638] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  886.908604] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  886.912592] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  886.916571] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  886.918572] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  886.920569] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  886.924581] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddbd80
>[  886.926574] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb6c0
>[  886.930577] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddbd80
>[  886.932572] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb6c0
>[  886.936570] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddbd80
>[  886.938573] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030eddb6c0
>[  886.940626] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  886.942569] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c0c0
>[  886.944578] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c480
>[  886.946590] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  886.948572] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  886.950581] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  886.952558] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  886.954591] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  886.956559] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c0c0
>[  886.958567] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  886.960561] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  886.962556] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  886.964555] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  886.966550] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  886.968564] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  886.970571] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  886.972551] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  886.974553] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  886.976546] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  886.978557] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  886.980558] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  886.982565] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  886.984549] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  886.986546] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  886.986773] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  886.988544] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  886.990547] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  886.992557] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9900
>[  886.994566] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  886.996542] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  886.998543] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  887.000542] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  887.002556] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  887.004555] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  887.006545] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  887.008548] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  887.010544] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  887.012533] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  887.014537] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  887.016547] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  887.018548] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  887.020541] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9840
>[  887.020819] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  887.022550] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  887.024540] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9840
>[  887.026553] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  887.028539] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  887.030535] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  887.032527] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  887.034533] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  887.036523] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  887.038527] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  887.038746] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  887.040537] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c780
>[  887.042539] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  887.044536] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9180
>[  887.046533] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  887.048527] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  887.050528] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  887.052526] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  887.054524] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  887.056518] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  887.058529] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  887.060521] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  887.062513] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  887.064517] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  887.066530] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  887.068527] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc99c0
>[  887.070534] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  887.072518] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  887.074519] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  887.076510] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  887.078520] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  887.080521] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  887.082520] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  887.084515] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  887.086507] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  887.088509] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  887.092510] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  887.098509] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  887.248590] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  887.250545] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c000
>[  887.252505] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9000
>[  887.254517] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  887.256483] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  887.258503] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9000
>[  887.260493] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  887.262470] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  887.264467] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc99c0
>[  887.266470] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9180
>[  887.268467] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  887.272466] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc99c0
>[  887.274472] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  887.276446] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  887.278455] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  887.284447] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76d80
>[  887.797763] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  888.900101] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  888.903944] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  888.907909] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  888.909903] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  888.911922] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9840
>[  888.913894] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  888.915886] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c240
>[  888.917893] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  888.919860] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  888.920156] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  888.921854] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  888.923854] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  888.925846] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  888.927858] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  888.929852] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  888.931843] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  888.933846] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  888.935842] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  888.937842] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  888.939843] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  888.941884] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  888.942314] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9900
>[  888.943858] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9cb40
>[  888.945853] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9540
>[  888.946201] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  888.947847] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  888.949841] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  888.951851] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  888.953846] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  888.955840] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  888.957842] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  888.958463] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  888.959855] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9540
>[  888.961846] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  888.962301] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  888.963834] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  888.965828] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  888.967832] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  888.969834] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  888.971838] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  888.973840] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  888.974163] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  888.975827] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  888.977830] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  888.978058] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  888.979827] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  888.981836] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  888.983835] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  888.985826] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  888.987833] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  888.989825] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  888.990078] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  888.991819] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  888.993824] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  888.995815] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  888.997830] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  888.999838] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  889.001824] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.002120] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  889.003822] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.005826] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  889.007834] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  889.009821] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  889.011818] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  889.013816] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  889.015809] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  889.017819] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  889.019822] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  889.020113] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  889.021809] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  889.023812] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  889.024060] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  889.025810] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  889.027809] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  889.029811] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  889.030039] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  889.031804] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  889.033811] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  889.035802] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  889.036016] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  889.037812] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  889.039807] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  889.041805] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  889.043805] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  889.045799] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  889.047806] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  889.049813] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  889.051802] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  889.053801] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  889.055810] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9900
>[  889.057812] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  889.059801] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  889.061801] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  889.062037] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  889.063798] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  889.065795] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  889.067796] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  889.073804] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9840
>[  889.081801] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  889.111796] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc99c0
>[  889.117915] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  889.173844] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  889.175763] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  889.179764] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76cc0
>[  889.181762] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  889.183757] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  889.185751] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  889.187757] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  889.189754] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76d80
>[  889.191748] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  889.193752] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76d80
>[  889.195747] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  889.197749] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76d80
>[  889.199747] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  889.201760] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9180
>[  889.203760] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76d80
>[  889.205752] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  889.207752] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76d80
>[  889.209753] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  889.211751] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  889.213748] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  889.215737] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  889.217743] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  889.219739] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  889.221736] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  889.223737] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  889.225734] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  889.227741] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  889.229746] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76d80
>[  889.231731] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  889.233739] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76d80
>[  889.235730] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  889.237738] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76d80
>[  889.239741] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  889.243732] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  889.247730] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  889.247970] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  889.249732] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  889.251730] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  889.253728] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  889.255738] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9000
>[  889.257748] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  889.259730] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.263728] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  889.265724] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.267727] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  889.269732] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  889.271733] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9000
>[  889.273727] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9180
>[  889.275734] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.277724] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  889.279718] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.283720] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  889.285719] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.285954] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  889.287725] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9000
>[  889.289734] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.291712] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  889.293716] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.295709] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  889.297717] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.301711] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  889.303716] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.305708] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  889.307707] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.309708] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  889.311702] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.313708] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  889.313944] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.315701] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  889.317715] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc99c0
>[  889.319714] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.320011] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  889.321714] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9840
>[  889.323711] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.325700] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  889.325978] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.327707] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  889.329704] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  889.331694] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  889.333697] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  889.335692] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  889.336003] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  889.337709] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9900
>[  889.339753] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  889.341720] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  889.343710] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  889.345726] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  889.346208] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  889.347714] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9cc00
>[  889.349710] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c9c0
>[  889.351726] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  889.352025] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  889.353712] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  889.355692] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  889.357750] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  889.359698] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  889.361701] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  889.363692] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  889.365684] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  889.367695] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  889.369689] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  889.371697] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  889.373704] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  889.377691] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.379684] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  889.381691] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9cc0
>[  889.383697] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.385681] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  889.385915] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  889.387689] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9540
>[  889.389699] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  889.391692] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  889.393721] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  889.395715] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  889.397688] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  889.397986] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  889.399685] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9540
>[  889.401695] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  889.403680] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  889.405682] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9cc0
>[  889.407688] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  889.409679] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  889.413681] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  889.414040] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  889.415687] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  889.419677] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  889.423674] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  889.429670] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  889.431672] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  889.433674] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  889.441679] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  889.445662] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  889.451663] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9900
>[  889.945616] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  890.081574] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  890.121491] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9840
>[  890.241524] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  890.475444] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  890.479302] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  891.323147] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  891.341138] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  891.343020] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9cc0
>[  891.346995] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  891.348991] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  891.350992] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  891.351373] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  891.354986] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  891.356979] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9cc00
>[  891.358986] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  891.360974] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  891.362968] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  891.366966] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  891.368967] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  891.372963] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  891.376973] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  891.384986] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9900
>[  891.390984] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c240
>[  891.396955] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c000
>[  891.400984] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  891.408955] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  897.007072] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02a80
>[  897.008953] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c023c0
>[  897.010932] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02a80
>[  897.011232] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c023c0
>[  897.012936] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02a80
>[  897.014926] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c023c0
>[  897.016922] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02a80
>[  897.018935] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c023c0
>[  897.019202] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02a80
>[  897.020923] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c023c0
>[  897.022917] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02a80
>[  897.023137] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c023c0
>[  897.024942] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02a80
>[  897.026921] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c023c0
>[  897.027171] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02a80
>[  897.028912] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c023c0
>[  897.030919] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02a80
>[  897.032910] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c023c0
>[  897.034935] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  897.036929] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  897.038927] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  897.040927] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02a80
>[  897.041282] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02f00
>[  897.042934] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e300
>[  897.044917] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  897.046919] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  897.047232] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  897.048925] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02a80
>[  897.050930] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  897.052915] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e240
>[  897.053229] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  897.054915] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.056913] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  897.058920] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c020c0
>[  897.060927] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  897.062909] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  897.063219] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.064908] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  897.066918] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02cc0
>[  897.068913] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  897.069213] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  897.070913] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  897.072915] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02000
>[  897.073252] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c240
>[  897.074924] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  897.076908] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  897.077142] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  897.078901] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  897.080902] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  897.082896] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  897.084899] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  897.085160] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  897.086906] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  897.088899] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  897.090897] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  897.091131] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  897.092893] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  897.093107] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  897.094901] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e600
>[  897.096906] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02600
>[  897.097276] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02480
>[  897.098931] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  897.100897] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ea80
>[  897.102907] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02600
>[  897.104894] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c240
>[  897.106890] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c480
>[  897.108883] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c240
>[  897.110890] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c480
>[  897.112881] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c240
>[  897.114911] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c029c0
>[  897.116888] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02300
>[  897.118882] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c029c0
>[  897.119102] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02300
>[  897.120884] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c029c0
>[  897.122878] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02300
>[  897.124882] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c480
>[  897.125147] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c0c0
>[  897.126890] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c029c0
>[  897.128876] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02300
>[  897.130881] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c029c0
>[  897.132907] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c480
>[  897.134908] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c780
>[  897.136883] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c480
>[  897.138873] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c780
>[  897.140877] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c480
>[  897.142874] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c780
>[  897.144875] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02300
>[  897.146877] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02600
>[  897.148891] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c480
>[  897.150888] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c000
>[  897.151171] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c480
>[  897.152873] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c000
>[  897.154886] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  897.156879] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  897.158873] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e3c0
>[  897.160885] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02300
>[  897.162869] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02480
>[  897.164874] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c480
>[  897.167109] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9cc00
>[  897.168862] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c480
>[  897.169125] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9cc00
>[  897.170901] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  897.172867] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  897.174874] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  897.176872] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  897.178879] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02300
>[  897.178931] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02000
>[  897.180884] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  897.182876] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02300
>[  897.184900] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1ee40
>[  897.188911] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.190911] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  897.194901] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02cc0
>[  897.196907] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.198907] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  897.200905] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.202903] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  897.204904] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.208903] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  897.222900] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.230897] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  897.246977] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.260973] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  897.268984] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.276967] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  897.284973] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.292957] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  897.298959] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.306956] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  897.312949] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.322946] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  897.332948] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.338905] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  897.354942] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c020c0
>[  897.364953] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02a80
>[  897.370947] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c020c0
>[  897.386931] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.540870] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.542874] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.544865] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.546865] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.548864] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.550867] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.552875] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.554870] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.556863] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.558861] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.560860] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.560923] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.562822] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.564861] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.566862] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.568870] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.570868] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.572854] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.574858] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.576853] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.578855] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.580854] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.582853] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.584860] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.586861] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.588854] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.590851] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.592845] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.594852] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.596846] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.598846] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.600846] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.602856] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.604850] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.606845] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.608840] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.610842] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.612840] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.614846] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.616841] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.618849] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.620847] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.622843] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.624837] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.626836] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.628833] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.630837] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.632832] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.634845] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.636844] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.638839] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.640831] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.642828] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.644830] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.646830] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.648827] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.650827] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.652839] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.654836] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.656826] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.658823] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.660823] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.662823] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.664822] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  897.666776] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e780
>[  897.668834] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.670830] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.672818] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.674819] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.676762] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.678818] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.680817] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.682814] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.684826] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.686824] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.688817] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.690812] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.692811] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.694814] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.696810] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.698812] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.700814] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.702821] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.704818] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.706807] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.708808] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.710808] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.712804] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.714803] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.716803] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.718816] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.720809] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.722801] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.724800] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.726806] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.728798] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.730798] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.732794] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.734814] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.736803] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.738799] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.740795] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.742797] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.744794] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.746792] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.748789] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.750795] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.752800] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  897.754797] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  897.760796] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  902.019269] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02b40
>[  902.021257] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c023c0
>[  902.023191] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02b40
>[  902.025128] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c023c0
>[  902.027145] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02b40
>[  902.029122] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c023c0
>[  902.033267] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02b40
>[  902.035141] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c023c0
>[  902.037161] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e480
>[  902.039156] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02b40
>[  902.043250] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02780
>[  902.045251] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02b40
>[  902.047247] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02780
>[  902.049261] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02b40
>[  902.053252] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c000
>[  902.059243] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c0c0
>[  903.166855] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c780
>[  903.172848] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c0c0
>[  903.182850] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c780
>[  903.198845] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c020c0
>[  903.204835] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02240
>[  903.208831] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c020c0
>[  903.210827] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02240
>[  903.212830] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c020c0
>[  903.216835] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02240
>[  903.218831] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c0c0
>[  903.220826] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c240
>[  903.222825] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c0c0
>[  903.224826] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c240
>[  903.228824] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c0c0
>[  903.230819] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c240
>[  903.232835] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c0c0
>[  903.234825] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c240
>[  903.236820] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c0c0
>[  903.240819] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c240
>[  903.242817] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c0c0
>[  903.246816] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c240
>[  903.248826] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c0c0
>[  903.252821] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c020c0
>[  903.254812] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c023c0
>[  903.256813] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c020c0
>[  903.260685] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c023c0
>[  903.264685] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f53c0
>[  903.268742] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c020c0
>[  903.272672] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c240
>[  903.276677] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02b40
>[  903.278703] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f5540
>[  903.280697] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f5c00
>[  903.286698] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02780
>[  903.294793] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  903.300796] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  903.304796] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  903.312793] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  903.618685] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9cc00
>[  903.626681] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c9c0
>[  903.644676] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9cc00
>[  903.658668] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9c9c0
>[  903.676661] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f5540
>[  903.700664] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c9cc00
>[  904.580368] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  904.582375] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  904.584365] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  904.588358] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  904.594323] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  904.598338] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  904.602331] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  906.073801] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  906.077787] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  906.083803] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  906.087783] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  906.091783] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  906.097749] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  906.101778] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  906.105775] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  906.109774] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  906.113788] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  906.115780] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  906.117776] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  906.119768] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  906.121769] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  906.123773] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  906.125768] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  906.127768] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  906.129767] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  906.133718] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203b40
>[  906.137651] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203000
>[  906.139775] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203b40
>[  906.141773] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203000
>[  906.143773] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203b40
>[  906.145766] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203000
>[  906.147784] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203b40
>[  906.151767] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203000
>[  906.155781] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030f203b40
>[  906.165710] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02f00
>[  906.377686] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02cc0
>[  906.387685] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02f00
>[  906.421674] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02cc0
>[  906.587611] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02f00
>[  906.591613] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02cc0
>[  906.593607] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02f00
>[  906.595610] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02cc0
>[  906.597615] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02f00
>[  906.599611] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02cc0
>[  906.601605] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02f00
>[  906.605605] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02cc0
>[  906.609604] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02f00
>[  906.611604] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c02cc0
>[  906.613606] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  906.617596] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  906.623591] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  906.649593] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  906.651582] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>
>
>
>
>
>
>[  906.925610] xrandr --output DP2-2 --auto --output DP2-1 --auto
>               --> try to enable them, fails
>[  906.955391] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1e900
>[  906.963361] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeb3c0
>[  906.969358] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeb000
>[  906.981482] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc99c0
>[  907.009459] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  907.011461] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc99c0
>[  907.017461] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  907.021454] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc99c0
>[  907.029451] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  907.031460] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc99c0
>[  907.039325] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802f9f1eb40
>[  907.125420] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfebd80
>[  907.129407] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeb3c0
>[  907.131421] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfebd80
>[  907.135301] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de16c0
>[  907.139296] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de19c0
>[  907.143406] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeb3c0
>[  907.147413] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeba80
>[  907.149418] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeb3c0
>[  907.155370] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeba80
>[  907.157397] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeb3c0
>[  907.173400] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  907.225385] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeba80
>[  907.349351] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeb540
>[  907.369343] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeba80
>[  907.381344] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9000
>[  907.415336] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeb540
>[  907.417320] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeb780
>[  907.441295] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeb540
>[  907.455294] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeb780
>[  907.457298] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeb540
>[  907.541279] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeb780
>[  907.571261] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeb540
>[  907.605239] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeb780
>[  907.609273] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeb540
>[  908.047113] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030dfeb780
>[  908.797094] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  908.797100] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
>[  908.797102] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
>[  908.797110] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  908.797116] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  908.797437] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[  908.797742] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[  908.797753] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  908.797756] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
>[  908.797759] [drm:drm_mode_debug_printmodeline] Modeline 32:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  908.797763] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  908.797843] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[  908.797845] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1]
>[  908.797846] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[  908.797850] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1] disconnected
>[  908.797853] [drm:drm_mode_getconnector] [CONNECTOR:46:?]
>[  908.797855] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2]
>[  908.797856] [drm:intel_dp_detect] [CONNECTOR:46:DP-2]
>[  908.797857] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2] disconnected
>[  908.797861] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  908.797863] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3]
>[  908.799160] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  908.799163] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  908.799181] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  908.799671] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  908.800678] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  908.800679] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  908.802386] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  908.802390] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  908.802404] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  908.802883] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  908.804557] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  908.804559] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  908.805428] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  908.805431] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  908.805442] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  908.805935] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  908.807615] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  908.807617] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  908.808470] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  908.808472] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  908.808483] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  908.808973] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  908.810006] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  908.810015] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3] probed modes :
>[  908.810018] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  908.810021] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  908.810024] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  908.810027] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  908.810030] [drm:drm_mode_debug_printmodeline] Modeline 61:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  908.810033] [drm:drm_mode_debug_printmodeline] Modeline 69:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  908.810036] [drm:drm_mode_debug_printmodeline] Modeline 70:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  908.810039] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  908.810042] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  908.810045] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  908.810048] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  908.810051] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  908.810059] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  908.810080] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  908.810082] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4]
>[  908.810649] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  908.810651] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  908.811955] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  908.811958] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  908.811965] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  908.812447] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  908.813472] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  908.813474] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  908.815215] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  908.815217] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  908.815229] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  908.815721] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  908.817399] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  908.817401] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  908.818267] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  908.818268] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  908.818273] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  908.818742] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  908.820432] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  908.820434] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  908.821287] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  908.821289] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  908.821294] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  908.821769] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  908.822798] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  908.822805] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4] probed modes :
>[  908.822808] [drm:drm_mode_debug_printmodeline] Modeline 73:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  908.822810] [drm:drm_mode_debug_printmodeline] Modeline 76:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  908.822813] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  908.822815] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  908.822818] [drm:drm_mode_debug_printmodeline] Modeline 74:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  908.822820] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  908.822823] [drm:drm_mode_debug_printmodeline] Modeline 83:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  908.822825] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  908.822827] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  908.822830] [drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  908.822832] [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  908.822835] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  908.822840] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  908.822852] [drm:drm_mode_getconnector] [CONNECTOR:57:?]
>[  908.822854] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5]
>[  908.822855] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5] disconnected
>[  908.822858] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[  908.822860] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[  908.822861] [drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[  908.823490] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  908.823492] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  908.835551] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  908.835552] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[  908.835556] [drm:drm_mode_getconnector] [CONNECTOR:50:?]
>[  908.835566] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2]
>[  908.835567] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-2]
>[  908.835765] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  908.835767] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  908.835768] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2] disconnected
>[  908.837576] [drm:drm_mode_setcrtc] [CRTC:24]
>[  908.837581] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-3]
>[  908.837583] [drm:drm_mode_setcrtc] [CONNECTOR:55:DP-4]
>[  908.837585] [drm:intel_crtc_set_config] [CRTC:24] [FB:87] #connectors=2 (x y) (0 0)
>[  908.837588] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  908.837589] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=1, fb_changed=1
>[  908.837591] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  908.837592] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  908.837594] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  908.837595] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[  908.837596] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:24]
>[  908.837599] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  908.837606] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[  908.837610] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  908.837612] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  908.837613] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  908.837614] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  908.837615] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  908.837617] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  908.837618] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  908.837619] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  908.837620] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  908.837622] [drm:check_crtc_state] [CRTC:20]
>[  908.837629] [drm:check_crtc_state] [CRTC:24]
>[  908.837631] [drm:check_crtc_state] [CRTC:28]
>[  908.837632] [drm:check_shared_dpll_state] WRPLL 1
>[  908.837634] [drm:check_shared_dpll_state] WRPLL 2
>[  908.839342] [drm:drm_mode_addfb2] [FB:89]
>[  908.839370] [drm:drm_mode_setcrtc] [CRTC:24]
>[  908.839373] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-3]
>[  908.839374] [drm:drm_mode_setcrtc] [CONNECTOR:55:DP-4]
>[  908.839375] [drm:intel_crtc_set_config] [CRTC:24] [FB:89] #connectors=2 (x y) (0 0)
>[  908.839378] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  908.839379] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=1, fb_changed=1
>[  908.839381] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  908.839381] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  908.839382] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  908.839383] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[  908.839384] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:24]
>[  908.839386] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  908.839392] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[  908.839395] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  908.839396] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  908.839397] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  908.839398] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  908.839399] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  908.839399] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  908.839400] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  908.839401] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  908.839402] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  908.839403] [drm:check_crtc_state] [CRTC:20]
>[  908.839408] [drm:check_crtc_state] [CRTC:24]
>[  908.839410] [drm:check_crtc_state] [CRTC:28]
>[  908.839411] [drm:check_shared_dpll_state] WRPLL 1
>[  908.839412] [drm:check_shared_dpll_state] WRPLL 2
>[  908.839448] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[8] ENCODERS[9]
>[  908.839585] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=516/851
>[  908.839587] [drm:intel_panel_actually_set_backlight] set backlight PWM = 520
>[  908.839591] [drm:intel_edp_backlight_power] panel power control backlight disable
>[  909.042237] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/851
>[  909.042240] [drm:intel_panel_actually_set_backlight] set backlight PWM = 10
>[  909.042295] [drm:drm_mode_setcrtc] [CRTC:20]
>[  909.042297] [drm:intel_crtc_set_config] [CRTC:20] [NOFB]
>[  909.042302] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=0
>[  909.042304] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [NOCRTC]
>[  909.042306] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  909.042308] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  909.042311] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  909.042314] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  909.052142] [drm:intel_edp_backlight_off] 
>[  909.255458] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  909.262283] [drm:edp_panel_off] Turn eDP port A panel power off
>[  909.262291] [drm:wait_panel_off] Wait for panel power off time
>[  909.262295] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[  909.315433] [drm:wait_panel_status] Wait complete
>[  909.315447] [drm:intel_fbc_update] no output, disabling
>[  909.315452] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c9e76300
>[  909.315463] [drm:intel_display_power_put] disabling always-on
>[  909.315469] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  909.315471] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  909.315473] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  909.315474] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  909.315475] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  909.315476] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  909.315477] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  909.315478] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  909.315480] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  909.315481] [drm:check_crtc_state] [CRTC:20]
>[  909.315483] [drm:check_crtc_state] [CRTC:24]
>[  909.315485] [drm:check_crtc_state] [CRTC:28]
>[  909.315487] [drm:check_shared_dpll_state] WRPLL 1
>[  909.315488] [drm:check_shared_dpll_state] WRPLL 2
>[  909.315538] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  909.315550] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76180
>[  909.315557] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  909.315564] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c9e76180
>[  909.316240] [drm:drm_mode_setcrtc] [CRTC:20]
>[  909.316245] [drm:drm_mode_setcrtc] [CONNECTOR:31:eDP-1]
>[  909.316248] [drm:intel_crtc_set_config] [CRTC:20] [FB:87] #connectors=1 (x y) (0 0)
>[  909.316250] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  909.316252] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=0
>[  909.316253] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  909.316255] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  909.316256] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  909.316258] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  909.316260] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  909.316262] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[  909.316264] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[  909.316266] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz
>[  909.316268] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[  909.316269] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000
>[  909.316272] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[  909.316273] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  909.316275] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[  909.316276] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  909.316277] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  909.316279] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64
>[  909.316281] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  909.316282] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  909.316283] [drm:intel_dump_pipe_config] requested mode:
>[  909.316286] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x0 0x9
>[  909.316287] [drm:intel_dump_pipe_config] adjusted mode:
>[  909.316289] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  909.316291] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9
>[  909.316292] [drm:intel_dump_pipe_config] port clock: 270000
>[  909.316293] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  909.316295] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  909.316296] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  909.316297] [drm:intel_dump_pipe_config] ips: 1
>[  909.316298] [drm:intel_dump_pipe_config] double wide: 0
>[  909.316302] [drm:intel_display_power_get] enabling always-on
>[  909.316306] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8802c8dc9540
>[  909.316322] [drm:edp_panel_on] Turn eDP port A panel power on
>[  909.316326] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  909.865278] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000
>[  909.878590] [drm:wait_panel_status] Wait complete
>[  909.878602] [drm:wait_panel_on] Wait for panel power on
>[  909.878608] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[  910.091814] [drm:wait_panel_status] Wait complete
>[  910.091826] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  910.091832] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  910.092908] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  910.093496] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  910.094069] [drm:intel_dp_start_link_train] clock recovery OK
>[  910.094950] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  910.095171] [drm:intel_edp_backlight_on] 
>[  910.095174] [drm:intel_panel_enable_backlight] pipe A
>[  910.095179] [drm:intel_panel_actually_set_backlight] set backlight PWM = 851
>[  910.098484] [drm:intel_psr_match_conditions] PSR disable by flag
>[  910.098487] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  910.105147] [drm:ironlake_update_primary_plane] Writing base 0A67C000 00000000 0 0 7680
>[  910.131815] [drm:intel_fbc_update] disabled per chip default
>[  910.131825] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[  910.131830] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  910.131832] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  910.131834] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  910.131835] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  910.131837] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  910.131838] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  910.131839] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  910.131841] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  910.131842] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  910.131843] [drm:check_crtc_state] [CRTC:20]
>[  910.131851] [drm:check_crtc_state] [CRTC:24]
>[  910.131853] [drm:check_crtc_state] [CRTC:28]
>[  910.131855] [drm:check_shared_dpll_state] WRPLL 1
>[  910.131857] [drm:check_shared_dpll_state] WRPLL 2
>[  910.131916] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9840
>[  910.145176] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145197] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145208] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145219] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145229] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145240] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145250] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145261] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145272] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145282] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145292] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145302] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145312] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145322] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145332] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145343] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145353] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145363] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145373] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145384] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145394] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145404] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145414] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145424] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145435] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145445] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145455] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145465] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145475] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145485] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145495] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145505] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145515] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145526] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145536] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145546] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145556] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145566] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145576] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145586] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145596] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145606] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145617] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.145627] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1600
>[  910.145666] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=516/851
>[  910.145668] [drm:intel_panel_actually_set_backlight] set backlight PWM = 520
>[  910.145742] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1f00
>[  910.156275] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1cc0
>[  910.166223] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  910.170198] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  910.180236] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  910.188214] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  910.192221] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  910.198234] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  910.204308] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  910.210304] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc99c0
>[  910.218204] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9900
>[  910.224292] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  910.234288] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1e40
>[  910.242242] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  910.244279] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1e40
>[  910.254282] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  910.258279] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1e40
>[  910.266294] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  910.276281] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9c00
>[  911.863625] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4de1540
>[  911.871757] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1e40
>[  911.875715] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f10c0
>[  911.879721] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1e40
>
>
>
>[  912.656727] xrandr --output DP2-2 --auto --output DP2-1 --auto
>               --> try to enable them, fails (same command as before)
>[  913.100722] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[  913.100731] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  914.123048] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  914.123053] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
>[  914.123054] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
>[  914.123062] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  914.123068] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  914.123375] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[  914.123685] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[  914.123696] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  914.123699] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
>[  914.123702] [drm:drm_mode_debug_printmodeline] Modeline 32:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  914.123706] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  914.123791] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[  914.123793] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1]
>[  914.123795] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[  914.123799] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1] disconnected
>[  914.123803] [drm:drm_mode_getconnector] [CONNECTOR:46:?]
>[  914.123804] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2]
>[  914.123805] [drm:intel_dp_detect] [CONNECTOR:46:DP-2]
>[  914.123807] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2] disconnected
>[  914.123811] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  914.123813] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3]
>[  914.125124] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  914.125126] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  914.125136] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  914.125639] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  914.126649] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  914.126651] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  914.128434] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  914.128438] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  914.128461] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  914.128957] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  914.130650] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  914.130652] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  914.131544] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  914.131549] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  914.131568] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  914.132079] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  914.133771] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  914.133773] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  914.134617] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  914.134620] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  914.134627] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  914.135106] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  914.136148] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  914.136160] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3] probed modes :
>[  914.136164] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  914.136167] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  914.136171] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  914.136174] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  914.136177] [drm:drm_mode_debug_printmodeline] Modeline 61:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  914.136180] [drm:drm_mode_debug_printmodeline] Modeline 69:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  914.136183] [drm:drm_mode_debug_printmodeline] Modeline 70:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  914.136187] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  914.136190] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  914.136193] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  914.136197] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  914.136200] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  914.136215] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  914.136246] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  914.136249] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4]
>[  914.136789] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  914.136790] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  914.138059] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  914.138061] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  914.138071] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  914.138556] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  914.139571] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  914.139572] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  914.141313] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  914.141314] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  914.141322] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  914.141796] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  914.143471] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  914.143472] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  914.144340] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  914.144342] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  914.144365] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  914.144843] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  914.146520] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  914.146521] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  914.147379] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  914.147381] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  914.147386] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  914.147860] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  914.148887] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  914.148894] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4] probed modes :
>[  914.148897] [drm:drm_mode_debug_printmodeline] Modeline 73:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  914.148900] [drm:drm_mode_debug_printmodeline] Modeline 76:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  914.148902] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  914.148905] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  914.148907] [drm:drm_mode_debug_printmodeline] Modeline 74:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  914.148909] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  914.148912] [drm:drm_mode_debug_printmodeline] Modeline 83:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  914.148914] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  914.148917] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  914.148919] [drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  914.148922] [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  914.148924] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  914.148930] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  914.148947] [drm:drm_mode_getconnector] [CONNECTOR:57:?]
>[  914.148949] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5]
>[  914.148950] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5] disconnected
>[  914.148953] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[  914.148955] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[  914.148957] [drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[  914.149579] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  914.149580] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  914.160278] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  914.160280] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[  914.160310] [drm:drm_mode_getconnector] [CONNECTOR:50:?]
>[  914.160311] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2]
>[  914.160312] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-2]
>[  914.160503] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  914.160504] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  914.160505] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2] disconnected
>[  914.161529] [drm:drm_mode_setcrtc] [CRTC:24]
>[  914.161532] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-3]
>[  914.161533] [drm:drm_mode_setcrtc] [CONNECTOR:55:DP-4]
>[  914.161535] [drm:intel_crtc_set_config] [CRTC:24] [FB:87] #connectors=2 (x y) (0 0)
>[  914.161539] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  914.161540] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=1, fb_changed=1
>[  914.161541] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  914.161542] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  914.161543] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  914.161544] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[  914.161545] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:24]
>[  914.161548] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  914.161556] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[  914.161563] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  914.161564] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  914.161565] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  914.161566] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  914.161567] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  914.161568] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  914.161569] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  914.161570] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  914.161570] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  914.161572] [drm:check_crtc_state] [CRTC:20]
>[  914.161582] [drm:check_crtc_state] [CRTC:24]
>[  914.161583] [drm:check_crtc_state] [CRTC:28]
>[  914.161584] [drm:check_shared_dpll_state] WRPLL 1
>[  914.161586] [drm:check_shared_dpll_state] WRPLL 2
>[  914.161630] [drm:drm_mode_setcrtc] [CRTC:24]
>[  914.161632] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-3]
>[  914.161633] [drm:drm_mode_setcrtc] [CONNECTOR:55:DP-4]
>[  914.161635] [drm:intel_crtc_set_config] [CRTC:24] [FB:89] #connectors=2 (x y) (0 0)
>[  914.161636] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  914.161638] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=1, fb_changed=1
>[  914.161639] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  914.161652] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  914.161653] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  914.161654] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[  914.161654] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:24]
>[  914.161656] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  914.161659] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[  914.161661] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  914.161662] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  914.161663] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  914.161664] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  914.161665] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  914.161665] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  914.161666] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  914.161667] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  914.161668] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  914.161668] [drm:check_crtc_state] [CRTC:20]
>[  914.161673] [drm:check_crtc_state] [CRTC:24]
>[  914.161674] [drm:check_crtc_state] [CRTC:28]
>[  914.161675] [drm:check_shared_dpll_state] WRPLL 1
>[  914.161676] [drm:check_shared_dpll_state] WRPLL 2
>[  914.161701] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[8] ENCODERS[9]
>[  914.161917] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=516/851
>[  914.161921] [drm:intel_panel_actually_set_backlight] set backlight PWM = 520
>[  914.161927] [drm:intel_edp_backlight_power] panel power control backlight disable
>[  914.363625] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/851
>[  914.363629] [drm:intel_panel_actually_set_backlight] set backlight PWM = 10
>[  914.363676] [drm:drm_mode_setcrtc] [CRTC:20]
>[  914.363679] [drm:intel_crtc_set_config] [CRTC:20] [NOFB]
>[  914.363683] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=0
>[  914.363684] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [NOCRTC]
>[  914.363686] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  914.363687] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  914.363689] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  914.363692] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  914.380271] [drm:intel_edp_backlight_off] 
>[  914.583511] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  914.597007] [drm:edp_panel_off] Turn eDP port A panel power off
>[  914.597015] [drm:wait_panel_off] Wait for panel power off time
>[  914.597018] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[  914.650155] [drm:wait_panel_status] Wait complete
>[  914.650168] [drm:intel_fbc_update] no output, disabling
>[  914.650178] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c9e76540
>[  914.650188] [drm:intel_display_power_put] disabling always-on
>[  914.650195] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  914.650198] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  914.650200] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  914.650201] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  914.650202] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  914.650204] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  914.650205] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  914.650206] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  914.650207] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  914.650209] [drm:check_crtc_state] [CRTC:20]
>[  914.650211] [drm:check_crtc_state] [CRTC:24]
>[  914.650213] [drm:check_crtc_state] [CRTC:28]
>[  914.650214] [drm:check_shared_dpll_state] WRPLL 1
>[  914.650216] [drm:check_shared_dpll_state] WRPLL 2
>[  914.650234] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c9e76600
>[  914.650862] [drm:drm_mode_setcrtc] [CRTC:20]
>[  914.650867] [drm:drm_mode_setcrtc] [CONNECTOR:31:eDP-1]
>[  914.650869] [drm:intel_crtc_set_config] [CRTC:20] [FB:87] #connectors=1 (x y) (0 0)
>[  914.650872] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  914.650873] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=0
>[  914.650875] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  914.650876] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  914.650878] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  914.650879] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  914.650882] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  914.650884] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[  914.650885] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[  914.650888] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz
>[  914.650890] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[  914.650891] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000
>[  914.650893] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[  914.650895] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  914.650896] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[  914.650897] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  914.650899] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  914.650901] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64
>[  914.650902] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  914.650904] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  914.650905] [drm:intel_dump_pipe_config] requested mode:
>[  914.650907] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x0 0x9
>[  914.650908] [drm:intel_dump_pipe_config] adjusted mode:
>[  914.650911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  914.650913] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9
>[  914.650914] [drm:intel_dump_pipe_config] port clock: 270000
>[  914.650915] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  914.650916] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  914.650918] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  914.650919] [drm:intel_dump_pipe_config] ips: 1
>[  914.650920] [drm:intel_dump_pipe_config] double wide: 0
>[  914.650924] [drm:intel_display_power_get] enabling always-on
>[  914.650927] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c023c0
>[  914.650944] [drm:edp_panel_on] Turn eDP port A panel power on
>[  914.650948] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  915.199959] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[  915.199965] [drm:wait_panel_status] Wait complete
>[  915.199969] [drm:wait_panel_on] Wait for panel power on
>[  915.199972] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[  915.413204] [drm:wait_panel_status] Wait complete
>[  915.413216] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  915.413222] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  915.414297] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  915.414880] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  915.415452] [drm:intel_dp_start_link_train] clock recovery OK
>[  915.416840] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  915.417064] [drm:intel_edp_backlight_on] 
>[  915.417066] [drm:intel_panel_enable_backlight] pipe A
>[  915.417070] [drm:intel_panel_actually_set_backlight] set backlight PWM = 851
>[  915.419846] [drm:intel_psr_match_conditions] PSR disable by flag
>[  915.419849] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  915.426504] [drm:ironlake_update_primary_plane] Writing base 0A67C000 00000000 0 0 7680
>[  915.453192] [drm:intel_fbc_update] disabled per chip default
>[  915.453202] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[  915.453207] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  915.453209] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  915.453211] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  915.453212] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  915.453213] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  915.453215] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  915.453216] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  915.453217] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  915.453219] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  915.453220] [drm:check_crtc_state] [CRTC:20]
>[  915.453228] [drm:check_crtc_state] [CRTC:24]
>[  915.453230] [drm:check_crtc_state] [CRTC:28]
>[  915.453232] [drm:check_shared_dpll_state] WRPLL 1
>[  915.453234] [drm:check_shared_dpll_state] WRPLL 2
>[  915.453266] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=516/851
>[  915.453268] [drm:intel_panel_actually_set_backlight] set backlight PWM = 520
>[  915.453350] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  917.242091] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  918.237403] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1a80
>[  918.241287] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  918.245265] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1a80
>[  918.247302] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea540
>[  918.249315] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  918.253301] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  918.255314] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  918.257262] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  918.259260] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  918.263270] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9300
>[  918.265273] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  918.267259] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  918.269256] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  918.271267] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea6c0
>[  918.273259] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  918.275255] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea6c0
>[  918.277259] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9180
>[  918.279286] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  918.281248] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  918.283251] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  918.285245] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  918.287252] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  918.289247] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  918.291258] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  918.295255] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eaf00
>[  918.297253] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9180
>[  918.299261] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  918.303247] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  918.305238] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  918.309246] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  918.313246] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  918.317240] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  918.319240] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  918.321245] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9300
>[  918.323244] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  918.327240] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76480
>[  918.331234] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  918.333239] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76480
>[  918.335229] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  918.337230] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76480
>[  918.339229] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  918.341239] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  918.343240] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  918.345237] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76480
>[  918.349239] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  918.351243] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  918.353225] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.355220] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  918.357231] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea0c0
>[  918.361226] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eaa80
>[  918.363226] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea0c0
>[  918.367227] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eaa80
>[  918.371222] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea0c0
>[  918.381220] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eaa80
>[  918.387218] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea0c0
>[  918.389216] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eaa80
>[  918.397217] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9540
>[  918.401237] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.407212] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  918.417205] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9540
>[  918.418712] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[  918.418721] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  918.429218] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  918.435227] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.437198] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  918.441195] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.445191] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  918.447197] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.449200] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9540
>[  918.451206] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  918.453191] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.455187] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  918.457206] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  918.459196] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea600
>[  918.461202] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.463190] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  918.465196] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eab40
>[  918.467188] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.469183] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  918.471185] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.473182] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  918.475177] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.477180] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  918.479183] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.481193] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  918.483186] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.485173] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  918.487181] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.489176] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  918.491186] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eab40
>[  918.493180] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea600
>[  918.495182] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eab40
>[  918.497182] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea600
>[  918.499177] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eab40
>[  918.501177] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea600
>[  918.503178] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eab40
>[  918.507174] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea600
>[  918.509173] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eab40
>[  918.511175] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea600
>[  918.513173] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eab40
>[  918.515171] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea600
>[  918.517173] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  918.519180] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  918.521160] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  918.523163] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  918.525156] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  918.527160] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  918.529159] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  918.531153] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  918.533158] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  918.535175] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  918.537170] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.541158] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76480
>[  918.543159] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.545156] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76480
>[  918.547158] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.549155] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76480
>[  918.551149] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.553172] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76480
>[  918.555156] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  918.555488] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9300
>[  918.557160] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9180
>[  918.559220] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  918.561148] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1480
>[  918.563154] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  918.565156] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1480
>[  918.565628] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9300
>[  918.568010] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9180
>[  918.569185] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  918.573176] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  918.579176] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  918.583170] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76480
>[  918.585180] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eab40
>[  918.587146] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  918.591250] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea780
>[  918.593189] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9300
>[  918.595168] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  918.597142] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  918.599144] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  918.601137] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  918.603140] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  918.605139] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9540
>[  918.605205] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc90c0
>[  918.607146] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  918.609191] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  918.611138] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  918.613137] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  918.615130] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  918.617131] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  918.621132] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  918.623130] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  918.625122] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  918.629123] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  918.631119] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  918.633122] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  918.649120] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  918.669159] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eaa80
>[  918.705193] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  918.709120] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  918.717106] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  918.723097] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  918.725087] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  918.735124] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9540
>[  918.741096] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  918.751091] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  918.755084] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  918.759090] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  918.761073] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  918.767078] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  918.771073] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  918.775074] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  918.779082] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  918.783091] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  918.785066] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  918.787071] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  918.791070] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  918.795065] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  918.797072] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  918.799071] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eaf00
>[  918.801068] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  918.805066] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eaf00
>[  918.807071] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  918.811068] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  918.813074] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  918.815056] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  918.819062] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9540
>[  918.821065] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  918.823052] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  918.825047] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  918.825440] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  918.829061] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  918.831050] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  918.833055] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  918.836050] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  918.838044] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  918.840047] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  918.842047] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  918.844040] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  918.844341] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  918.846045] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  918.848039] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  918.850042] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  918.852043] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  918.856044] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  918.858040] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  918.860039] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  920.135716] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1a80
>[  920.137609] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  920.139589] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  920.142589] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  920.144583] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  920.146584] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  920.148585] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  920.150597] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  920.152578] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  920.154585] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  920.156573] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  920.158578] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  920.160583] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  920.162588] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  920.164570] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  920.166575] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  920.168569] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  920.170564] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  920.172565] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  920.174564] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  920.176565] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  920.178567] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  920.180574] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  920.182584] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  920.184562] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  920.186565] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  920.188564] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  920.190575] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea0c0
>[  920.192568] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  920.194564] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea0c0
>[  920.196583] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  920.198559] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea0c0
>[  920.200562] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  920.202562] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea0c0
>[  920.204561] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  920.206563] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea0c0
>[  920.208596] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  920.210582] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea0c0
>[  920.212583] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  920.214584] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea0c0
>[  920.216576] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  920.218580] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea0c0
>[  920.220583] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  920.222578] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea0c0
>[  920.224578] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  920.226608] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea0c0
>[  920.228561] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  920.230558] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea0c0
>[  920.232556] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  920.234565] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  920.236548] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  920.238547] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  920.240545] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  920.244543] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  920.340598] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  920.342568] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  920.344568] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  920.346554] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  920.348551] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  920.350546] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  920.352540] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  920.354533] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  920.356523] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  920.358559] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  920.360557] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  920.362538] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  920.364542] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  920.366528] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  920.368510] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  920.370503] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  920.372492] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  920.374483] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  920.376503] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  920.378495] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea540
>[  920.380492] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  920.382517] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea540
>[  920.384502] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  920.386495] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  920.388498] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  920.390491] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  920.392491] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  920.394483] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  920.396496] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  920.398500] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  920.400485] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.402487] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  920.404496] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  920.406486] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  920.408493] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.409751] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  920.410477] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.412487] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  920.412711] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.414479] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  920.414567] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.416483] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  920.418490] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  920.420513] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  920.422512] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  920.424476] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  920.426611] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  920.428614] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  920.430606] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  920.432622] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  920.434612] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  920.436603] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  920.438529] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  920.440604] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  920.442500] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  920.444616] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  920.446516] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  920.448614] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1480
>[  920.450601] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  920.452600] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1480
>[  920.454599] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  920.456598] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1480
>[  920.458598] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  920.460550] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  920.462503] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  920.464660] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1480
>[  920.466599] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1c00
>[  920.468591] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1480
>[  920.470594] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1c00
>[  920.472592] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1480
>[  920.474532] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea540
>[  920.476605] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1c00
>[  920.476687] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  920.478459] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1c00
>[  920.480461] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  920.482471] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.482893] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  920.484483] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  920.486465] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1c00
>[  920.488458] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1b40
>[  920.490460] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.490752] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  920.492463] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  920.494461] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  920.496476] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.498460] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  920.500460] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  920.502467] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.504443] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  920.506447] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.508446] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  920.510480] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  920.512446] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  920.514447] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea300
>[  920.516454] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1c00
>[  920.518455] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.518842] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  920.520460] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.522443] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  920.524434] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.526449] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1d80
>[  920.528444] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f19c0
>[  920.530456] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea840
>[  920.532453] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  920.534462] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  920.536445] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  920.538453] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  920.540431] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76480
>[  920.542441] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  920.544427] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76480
>[  920.546439] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1d80
>[  920.548433] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1e40
>[  920.550428] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1d80
>[  920.552430] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1e40
>[  920.554423] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1d80
>[  920.556425] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1e40
>[  920.558430] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1d80
>[  920.560442] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1e40
>[  920.562434] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1d80
>[  920.564431] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1e40
>[  920.566437] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1d80
>[  920.568430] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1e40
>[  920.570429] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1d80
>[  920.572428] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1e40
>[  920.574431] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1d80
>[  920.576430] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1e40
>[  920.578424] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1d80
>[  920.580426] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1e40
>[  920.582432] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  920.584437] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  920.586420] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  920.588427] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  920.590413] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  920.592413] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  920.594408] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  920.596421] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1d80
>[  920.598416] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1900
>[  920.600407] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1d80
>[  920.602407] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1900
>[  920.604405] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1d80
>[  920.606408] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1900
>[  920.608409] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1d80
>[  920.610418] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  920.612425] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  920.614408] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  920.616406] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1900
>[  920.618406] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1cc0
>[  920.620399] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1900
>[  920.622406] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1cc0
>[  920.624397] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1900
>[  920.626410] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1cc0
>[  920.628408] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1900
>[  920.630411] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1cc0
>[  920.632406] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1900
>[  920.634406] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1cc0
>[  920.636464] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1900
>[  920.638411] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1cc0
>[  920.640405] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1900
>[  920.642407] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  920.644393] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  920.646399] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1cc0
>[  920.648395] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1540
>[  920.650388] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1cc0
>[  920.652393] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1540
>[  920.656393] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1cc0
>[  920.660390] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1540
>[  920.664394] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1cc0
>[  920.674396] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  920.696371] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1540
>[  920.700382] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  920.702388] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1f00
>[  920.704380] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1240
>[  920.706382] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1f00
>[  920.708379] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1240
>[  920.710380] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1f00
>[  920.712378] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1240
>[  920.714377] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1f00
>[  920.716383] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1240
>[  920.718379] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1f00
>[  920.720375] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1240
>[  920.722378] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  920.724377] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  920.726387] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  920.728369] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  920.730361] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  920.732364] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  920.734361] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  920.736369] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1f00
>[  920.738363] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f10c0
>[  920.740357] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1f00
>[  920.742363] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f10c0
>[  920.744354] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1f00
>[  920.746366] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  920.746845] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  920.748372] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  920.750366] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  920.752351] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  920.754392] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  920.756361] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f10c0
>[  920.758361] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1f00
>[  920.760350] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f10c0
>[  920.762355] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1f00
>[  920.764348] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f10c0
>[  920.766396] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea9c0
>[  920.768355] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  920.770371] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  920.772350] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  920.774349] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  920.774808] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  920.776346] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  920.778345] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  920.780349] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  920.780616] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  920.782348] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  920.784340] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  920.786356] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  920.788362] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  920.790346] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  920.792343] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  920.794337] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  920.796351] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  920.798364] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  920.800338] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76480
>[  920.802344] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  920.804334] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76480
>[  920.806351] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  920.808352] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  920.810339] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  920.812336] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  920.814332] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  920.816343] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  920.818348] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  920.820328] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.824332] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  920.826330] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.828329] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  920.832329] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.834324] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  920.838342] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  920.840345] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.842323] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  920.844320] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  920.846327] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1f00
>[  920.848325] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1240
>[  920.850317] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1f00
>[  920.854327] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1240
>[  920.858327] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  920.860314] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  920.864323] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  920.866328] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  920.870336] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  920.872316] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  920.874308] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  920.876315] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1f00
>[  920.880309] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1540
>[  920.882312] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1f00
>[  920.886324] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  920.890328] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1540
>[  920.894317] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1cc0
>[  920.896316] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  920.898315] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  920.900319] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  920.902307] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  920.904303] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  920.906312] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  920.908319] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  920.910303] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  920.914301] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  920.916303] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  920.920299] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  920.922296] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  920.924290] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  920.928295] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  920.930297] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  920.932296] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  920.936291] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  920.938293] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  920.942330] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea480
>[  920.950335] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1540
>[  920.952305] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  921.020398] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1d80
>[  921.024269] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  921.028277] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  921.032278] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  921.036276] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  921.040254] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  921.042252] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  921.046253] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  921.048249] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  921.052265] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  921.054260] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  921.058253] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1e40
>[  921.060256] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  921.062266] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  921.064244] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  921.066254] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  921.070256] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  921.072258] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  921.074238] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  921.078246] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  921.080242] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f19c0
>[  921.082243] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1c00
>[  921.084247] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  921.086259] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  921.088241] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  921.090232] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  921.092235] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  921.096235] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  921.098233] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  921.100241] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  921.102244] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  921.102546] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  921.104228] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  921.106235] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  921.108232] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  921.110241] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  921.112237] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  921.114226] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  921.116225] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  921.116482] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  921.118229] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  921.120234] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  921.122234] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  921.124221] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  921.126228] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  921.128223] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  921.130231] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  921.132230] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  921.134232] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  921.136237] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  921.138260] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  921.142238] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea9c0
>[  921.146224] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eaf00
>[  921.148222] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea9c0
>[  921.150214] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eaf00
>[  921.152224] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea9c0
>[  921.156218] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eaf00
>[  921.158219] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea9c0
>[  921.164215] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eaf00
>[  921.176253] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea9c0
>[  921.214244] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  921.250206] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  921.296211] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  921.304185] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  921.314174] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  921.324162] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  921.338153] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eaf00
>[  921.354147] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ead80
>[  921.380264] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f19c0
>[  921.388159] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  921.394173] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  921.400135] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  921.402139] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  921.406128] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  921.420252] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1b40
>[  921.432128] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  921.434138] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  921.522231] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  921.540116] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  921.544091] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76480
>[  921.548074] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  921.550068] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1480
>[  921.552071] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  921.554062] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1480
>[  921.556098] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eaf00
>[  921.558073] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea540
>[  921.560073] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eaf00
>[  921.562073] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  921.564085] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  921.566068] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  921.568066] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.570057] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  921.572062] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.574065] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  921.578077] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  921.578371] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  921.580078] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  921.582067] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  921.584060] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  921.586060] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  921.586295] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  921.588057] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  921.590087] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  921.592062] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  921.594049] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  921.596052] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.598055] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.600046] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.602049] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.604043] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.606054] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.608047] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.610050] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.612049] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.614044] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.616046] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.618044] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.620047] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.622048] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.624037] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.626044] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.628042] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.630046] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.632041] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.634034] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.636039] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.638040] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.640040] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.642061] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.644031] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.646039] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.648034] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.650027] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.652031] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.654027] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.656033] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.658027] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.660023] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.662029] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.664035] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  921.666036] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  921.668029] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.670023] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  921.672025] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.674017] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  921.676023] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.678025] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  921.680026] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.682025] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  921.684016] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.686025] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  921.688019] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.692028] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  921.694017] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.702021] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  921.720011] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.748150] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  921.754025] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  921.758015] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.764001] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  921.768017] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  921.772000] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.773988] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  921.777990] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.779986] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  921.781987] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.785993] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  921.787985] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.789980] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  921.791981] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.793975] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  921.795981] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.797982] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  921.801991] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.803976] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e766c0
>[  921.805979] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.809976] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.811975] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.813971] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.815973] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.817974] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.819966] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.821974] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.823964] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  921.825981] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  921.827989] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.829969] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  921.831968] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.833962] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  921.835967] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.837969] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  921.841964] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.843958] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  921.845966] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.849958] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  921.853964] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.857965] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  921.859960] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.861961] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  921.863953] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.867965] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  921.871960] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.873951] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  921.875952] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.879948] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  921.881950] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.885954] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  921.887947] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.889949] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  921.891972] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.893945] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  921.895947] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.897944] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  921.899954] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.901949] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  921.903937] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.907945] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  921.909940] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.911938] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  921.913933] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.915937] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  921.917941] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.919939] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  921.921938] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.923930] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  921.925938] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.927933] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  921.929926] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.931929] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  921.933929] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.935930] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  921.937929] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.939923] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  921.941929] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  921.943922] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f16c0
>[  921.945931] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.947933] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  921.949935] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.951929] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  921.953919] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.955925] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  921.957926] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.959916] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  921.961919] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  921.963915] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76b40
>[  921.967941] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  921.971929] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  922.145933] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  922.151874] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  922.155880] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76480
>[  922.159870] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  922.163885] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  922.165868] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  922.169850] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  922.173849] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  922.177913] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea540
>[  922.181864] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea300
>[  922.183853] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea540
>[  922.187849] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea300
>[  922.191844] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea540
>[  922.199850] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  922.201854] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  922.207837] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  922.219867] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  922.235852] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  922.245869] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  922.249840] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  922.263841] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  922.271819] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  922.272081] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  922.275810] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e769c0
>[  922.297951] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  922.411898] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1a80
>[  922.421891] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  922.425791] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  922.437785] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76540
>[  922.445801] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea300
>[  922.449755] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea840
>[  922.723787] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1a80
>[  922.773790] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  922.777641] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea300
>[  922.805754] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1a80
>[  922.807627] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  922.811635] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  922.817616] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76300
>[  922.825620] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  922.831627] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  922.837617] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  922.841621] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76e40
>[  922.845620] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  922.849618] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  922.853612] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  922.855608] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  922.859614] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e760c0
>[  922.863605] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  922.867600] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  922.871595] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  922.875594] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[  922.881733] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  922.889610] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  922.897588] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  922.901586] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1600
>[  922.923606] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea480
>[  922.955640] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  923.149587] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  923.169530] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  923.179495] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea240
>[  923.207615] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1e40
>[  923.224412] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eae40
>[  923.225613] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eac00
>[  923.241480] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  923.249605] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1c00
>[  923.253589] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f19c0
>[  923.267606] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  923.273581] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1c00
>[  923.277584] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1b40
>[  923.281590] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1c00
>[  923.289578] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1b40
>[  923.295572] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1c00
>[  923.299575] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1b40
>[  923.301592] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  923.305566] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1c00
>[  923.309570] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1480
>[  923.311564] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1c00
>[  923.315569] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1480
>[  923.319563] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1c00
>[  923.321560] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1480
>[  923.325562] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1c00
>[  923.327559] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1480
>[  923.331568] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1c00
>[  923.333605] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  923.335555] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1480
>[  923.337557] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  923.339553] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1480
>[  923.341559] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  923.343550] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1480
>[  923.347575] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  923.349561] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  923.351552] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  923.353514] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  923.355549] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  923.357560] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  923.359545] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  923.361570] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  923.363578] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f13c0
>[  923.365490] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  923.367562] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  923.369541] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.371543] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  923.373542] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.375540] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  923.377540] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.379539] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  923.381457] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76c00
>[  923.383546] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.385534] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.387537] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.389539] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.391536] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.393534] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.395534] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.397548] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.399536] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.401531] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.403529] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.405537] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.407532] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.409527] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.411528] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.413560] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.415533] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.417539] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.419524] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.421528] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.423523] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.425523] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.427523] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.429522] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.431535] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.433435] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.435519] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.437522] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.439516] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.441518] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.443515] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.445521] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.447529] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.449520] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.451514] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.453516] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.455513] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.457511] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.459508] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.461520] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  923.463546] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76000
>[  923.465517] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.467515] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.469518] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.471506] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.473503] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.475506] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.477510] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.479502] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.481535] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.483510] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.485501] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.487501] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.489503] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.491504] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.493499] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.495498] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.497514] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.499505] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.501503] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.503498] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.505497] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.507493] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.509494] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.511493] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.515509] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.517503] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.519488] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.521493] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.527487] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.531500] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.549490] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.553477] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.555477] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.559475] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.563502] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.567480] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.569468] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  923.577476] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  923.951347] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.955336] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1900
>[  923.957334] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  923.961330] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1900
>[  923.969327] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1300
>[  930.195106] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  930.199196] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.201264] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.203187] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.205186] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.207178] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.209188] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.211252] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.213180] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.215172] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.217167] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.219176] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.221037] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.223157] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.225157] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.229163] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.231192] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.233133] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.239142] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.243145] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.247135] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.251154] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.255109] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.259108] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.261168] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.265100] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.267095] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.271127] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.275087] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.279100] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.283076] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.289074] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.293082] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.299069] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.303056] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.307057] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.309056] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.319053] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.321078] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.331070] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.335030] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.343045] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.353031] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.363038] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.369021] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.379022] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.381036] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.391030] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.393023] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.401021] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.411039] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.413008] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.419011] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.425002] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.431010] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.436998] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.438994] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.447000] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.455011] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.458987] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  930.468983] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76f00
>[  930.480913] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea180
>[  930.490997] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea780
>[  930.502977] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea180
>[  930.506969] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1840
>[  931.192737] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  931.196730] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  931.202725] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  931.206716] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  932.036424] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  932.042439] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  932.046420] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  932.048412] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  932.066415] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  932.942104] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  932.944096] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  932.948086] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  932.952085] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  932.954094] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  932.956082] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76240
>[  932.958083] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e763c0
>[  932.962043] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  932.963967] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  932.965963] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  932.967958] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  932.971951] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  932.973938] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  932.975935] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76780
>[  932.977957] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  932.979967] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  932.981961] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  932.986082] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  932.988079] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  932.989980] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  932.992053] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  932.996088] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  933.000101] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac780
>[  933.004080] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  933.006067] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  933.012082] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  933.026076] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  933.028068] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  933.036059] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  934.367620] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  934.373617] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  934.375619] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  934.381614] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  934.387570] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  934.399580] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76900
>[  934.691487] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  934.763552] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  935.861053] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  935.863034] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  935.865034] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  935.867032] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  935.869047] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  935.871029] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  935.873033] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  935.875040] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  935.877034] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  935.879042] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  935.881027] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  935.883026] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  935.885024] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  935.887026] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  935.889042] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  935.893034] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  935.895019] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  935.899033] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  935.909044] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  935.911021] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1180
>[  935.925033] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac000
>[  935.929027] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  935.939026] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f10c0
>[  935.945007] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  935.949018] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f10c0
>[  935.954999] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  935.959019] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f10c0
>[  935.966998] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  935.972995] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f10c0
>[  935.975001] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>[  935.982998] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f10c0
>[  935.993009] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edac180
>[  935.994991] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030edacb40
>[  936.052971] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  936.734638] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  936.738645] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76600
>[  936.742659] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76a80
>[  936.744627] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030d53e240
>[  936.748731] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f1780
>
>
>
>[  936.969431] xrandr --output DP2-2 --auto --output DP2-1 --auto --right-of DP2-2
>               --> try to enable them, fails (same command as before, with --right-of)
>[  937.062567] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c020c0
>[  937.066601] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c029c0
>[  937.068620] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c020c0
>[  937.070598] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c029c0
>[  937.074610] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c020c0
>[  937.076604] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c029c0
>[  937.078618] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c020c0
>[  937.082599] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.084591] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef540
>[  937.086591] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.088610] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef540
>[  937.090603] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.092597] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef540
>[  937.096591] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.100588] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef540
>[  937.102587] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.104587] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef540
>[  937.106599] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.108612] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef540
>[  937.110587] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.112586] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef540
>[  937.114579] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.116581] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef540
>[  937.118564] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.120585] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef540
>[  937.122579] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.124592] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef540
>[  937.126584] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.128598] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef540
>[  937.130574] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.132576] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef540
>[  937.134573] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.136577] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef540
>[  937.138588] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.140586] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef540
>[  937.142578] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.144579] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef540
>[  937.146482] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.150569] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef540
>[  937.152467] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff880306dc69c0
>[  937.154448] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff880306dc6240
>[  937.158596] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.162565] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef0c0
>[  937.164561] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.166564] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef0c0
>[  937.168585] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.170560] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef0c0
>[  937.172565] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.176570] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef0c0
>[  937.178577] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.180556] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef0c0
>[  937.184561] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.186556] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef0c0
>[  937.188588] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.192569] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef0c0
>[  937.194552] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.196470] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef0c0
>[  937.200555] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.202549] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef0c0
>[  937.206561] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.212550] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef0c0
>[  937.218559] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.220546] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef0c0
>[  937.224558] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.228556] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef0c0
>[  937.234538] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.238556] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef0c0
>[  937.244475] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff880306dc6d80
>[  937.248469] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea3c0
>[  937.258410] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eac00
>[  937.260400] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02ea3c0
>[  937.270536] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b02eac00
>[  937.278535] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.288541] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0efe40
>[  937.304483] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.306527] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0efe40
>[  937.316518] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.320511] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0efe40
>[  937.334521] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff880306dc69c0
>[  937.346508] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff880306dc6000
>[  937.348526] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff880306dc69c0
>[  937.358542] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.368514] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff880306dc6000
>[  937.370494] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.384495] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0efe40
>[  937.388512] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.406501] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0efe40
>[  937.434480] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  937.452477] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0efe40
>[  937.468480] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff880306dc6900
>[  937.470461] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff880306dc66c0
>[  937.500452] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c029c0
>[  938.344155] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0ef3c0
>[  939.226023] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  939.226028] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
>[  939.226030] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
>[  939.226038] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  939.226044] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  939.226360] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[  939.226662] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[  939.226672] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  939.226675] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
>[  939.226678] [drm:drm_mode_debug_printmodeline] Modeline 32:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  939.226682] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  939.226763] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[  939.226764] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1]
>[  939.226766] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[  939.226770] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1] disconnected
>[  939.226773] [drm:drm_mode_getconnector] [CONNECTOR:46:?]
>[  939.226774] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2]
>[  939.226775] [drm:intel_dp_detect] [CONNECTOR:46:DP-2]
>[  939.226776] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2] disconnected
>[  939.226780] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  939.226782] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3]
>[  939.228051] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  939.228056] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  939.228073] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  939.228553] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  939.229570] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  939.229572] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  939.231273] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  939.231279] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  939.231294] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  939.231776] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  939.233449] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  939.233451] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  939.234312] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  939.234313] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  939.234318] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  939.234793] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  939.236466] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  939.236468] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  939.237318] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  939.237319] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  939.237324] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  939.237800] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  939.238839] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  939.238846] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3] probed modes :
>[  939.238849] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  939.238851] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  939.238854] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  939.238856] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  939.238859] [drm:drm_mode_debug_printmodeline] Modeline 61:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  939.238861] [drm:drm_mode_debug_printmodeline] Modeline 69:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  939.238864] [drm:drm_mode_debug_printmodeline] Modeline 70:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  939.238866] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  939.238869] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  939.238871] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  939.238873] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  939.238876] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  939.238883] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  939.238904] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  939.238906] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4]
>[  939.239481] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  939.239483] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  939.240780] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  939.240781] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  939.240789] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  939.241268] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  939.242282] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  939.242284] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  939.244025] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  939.244026] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  939.244035] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  939.244520] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  939.246203] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  939.246205] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  939.247076] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  939.247078] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  939.247086] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  939.247560] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  939.249251] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  939.249252] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  939.250114] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  939.250115] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  939.250123] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  939.250597] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  939.251642] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  939.251653] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4] probed modes :
>[  939.251657] [drm:drm_mode_debug_printmodeline] Modeline 73:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  939.251661] [drm:drm_mode_debug_printmodeline] Modeline 76:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  939.251664] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  939.251668] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  939.251671] [drm:drm_mode_debug_printmodeline] Modeline 74:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  939.251675] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  939.251678] [drm:drm_mode_debug_printmodeline] Modeline 83:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  939.251682] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  939.251685] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  939.251689] [drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  939.251692] [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  939.251695] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  939.251704] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  939.251724] [drm:drm_mode_getconnector] [CONNECTOR:57:?]
>[  939.251727] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5]
>[  939.251729] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5] disconnected
>[  939.251732] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[  939.251735] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[  939.251737] [drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[  939.252318] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  939.252320] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  939.264451] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  939.264454] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[  939.264461] [drm:drm_mode_getconnector] [CONNECTOR:50:?]
>[  939.264463] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2]
>[  939.264464] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-2]
>[  939.264659] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  939.264662] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  939.264664] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2] disconnected
>[  939.266090] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88030e0ef0c0
>[  939.275721] [drm:drm_mode_addfb2] [FB:88]
>[  939.275890] [drm:drm_mode_setcrtc] [CRTC:20]
>[  939.275894] [drm:drm_mode_setcrtc] [CONNECTOR:31:eDP-1]
>[  939.275896] [drm:intel_crtc_set_config] [CRTC:20] [FB:88] #connectors=1 (x y) (0 0)
>[  939.275900] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=1
>[  939.275902] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  939.275905] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  939.275907] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[  939.275908] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[  939.275910] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz
>[  939.275912] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[  939.275912] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000
>[  939.275914] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[  939.275916] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  939.275917] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[  939.275918] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  939.275919] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  939.275920] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64
>[  939.275921] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  939.275922] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  939.275923] [drm:intel_dump_pipe_config] requested mode:
>[  939.275924] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x0 0x9
>[  939.275925] [drm:intel_dump_pipe_config] adjusted mode:
>[  939.275927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  939.275928] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9
>[  939.275929] [drm:intel_dump_pipe_config] port clock: 270000
>[  939.275930] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  939.275931] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  939.275932] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.275933] [drm:intel_dump_pipe_config] ips: 1
>[  939.275933] [drm:intel_dump_pipe_config] double wide: 0
>[  939.275937] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e0efe40
>[  939.279687] [drm:ironlake_update_primary_plane] Writing base 03212000 00000000 0 0 15360
>[  939.289083] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c969c840
>[  939.305631] [drm:drm_mode_setcrtc] [CRTC:24]
>[  939.305643] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-3]
>[  939.305645] [drm:drm_mode_setcrtc] [CONNECTOR:55:DP-4]
>[  939.305648] [drm:intel_crtc_set_config] [CRTC:24] [FB:88] #connectors=2 (x y) (0 0)
>[  939.305654] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  939.305656] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=1, fb_changed=1
>[  939.305658] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  939.305659] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  939.305660] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  939.305662] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[  939.305663] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:24]
>[  939.305668] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  939.305678] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[  939.305686] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  939.305688] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  939.305690] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  939.305691] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  939.305692] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  939.305693] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  939.305695] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  939.305696] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  939.305697] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  939.305699] [drm:check_crtc_state] [CRTC:20]
>[  939.305710] [drm:check_crtc_state] [CRTC:24]
>[  939.305712] [drm:check_crtc_state] [CRTC:28]
>[  939.305713] [drm:check_shared_dpll_state] WRPLL 1
>[  939.305715] [drm:check_shared_dpll_state] WRPLL 2
>[  939.305794] [drm:drm_mode_setcrtc] [CRTC:24]
>[  939.305797] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-3]
>[  939.305798] [drm:drm_mode_setcrtc] [CONNECTOR:55:DP-4]
>[  939.305800] [drm:intel_crtc_set_config] [CRTC:24] [FB:89] #connectors=2 (x y) (0 0)
>[  939.305802] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  939.305804] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=1, fb_changed=1
>[  939.305805] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  939.305806] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  939.305807] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  939.305809] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[  939.305810] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:24]
>[  939.305812] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  939.305816] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[  939.305819] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  939.305820] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  939.305822] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  939.305823] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  939.305824] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  939.305825] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  939.305826] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  939.305828] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  939.305829] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  939.305830] [drm:check_crtc_state] [CRTC:20]
>[  939.305837] [drm:check_crtc_state] [CRTC:24]
>[  939.305838] [drm:check_crtc_state] [CRTC:28]
>[  939.305840] [drm:check_shared_dpll_state] WRPLL 1
>[  939.305841] [drm:check_shared_dpll_state] WRPLL 2
>[  939.305874] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[8] ENCODERS[9]
>[  939.305905] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff88030e0ef0c0
>[  939.306144] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=516/851
>[  939.306150] [drm:intel_panel_actually_set_backlight] set backlight PWM = 520
>[  939.306156] [drm:intel_edp_backlight_power] panel power control backlight disable
>[  939.507789] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/851
>[  939.507793] [drm:intel_panel_actually_set_backlight] set backlight PWM = 10
>[  939.507838] [drm:drm_mode_setcrtc] [CRTC:20]
>[  939.507841] [drm:intel_crtc_set_config] [CRTC:20] [NOFB]
>[  939.507844] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=0
>[  939.507846] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [NOCRTC]
>[  939.507848] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  939.507850] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  939.507851] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  939.507853] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  939.527760] [drm:intel_edp_backlight_off] 
>[  939.731013] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  939.744509] [drm:edp_panel_off] Turn eDP port A panel power off
>[  939.744516] [drm:wait_panel_off] Wait for panel power off time
>[  939.744519] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[  939.797652] [drm:wait_panel_status] Wait complete
>[  939.797665] [drm:intel_fbc_update] no output, disabling
>[  939.797670] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c4c029c0
>[  939.797686] [drm:intel_display_power_put] disabling always-on
>[  939.797691] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  939.797693] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  939.797695] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  939.797696] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  939.797697] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  939.797698] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  939.797700] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  939.797701] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  939.797702] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  939.797703] [drm:check_crtc_state] [CRTC:20]
>[  939.797705] [drm:check_crtc_state] [CRTC:24]
>[  939.797707] [drm:check_crtc_state] [CRTC:28]
>[  939.797709] [drm:check_shared_dpll_state] WRPLL 1
>[  939.797710] [drm:check_shared_dpll_state] WRPLL 2
>[  939.797760] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02780
>[  939.797772] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02540
>[  939.797779] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02780
>[  939.797785] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02540
>[  939.797791] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02780
>[  939.797797] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02540
>[  939.797803] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02780
>[  939.797809] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02540
>[  939.797815] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02780
>[  939.797821] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02540
>[  939.797827] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02780
>[  939.797833] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02540
>[  939.797839] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02780
>[  939.797844] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02540
>[  939.797851] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02780
>[  939.797856] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02540
>[  939.797862] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02780
>[  939.797868] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02540
>[  939.797874] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02780
>[  939.797880] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c02540
>[  939.797886] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c4c02780
>[  939.798888] [drm:drm_mode_addfb2] [FB:87]
>[  939.799168] [drm:drm_mode_setcrtc] [CRTC:20]
>[  939.799172] [drm:drm_mode_setcrtc] [CONNECTOR:31:eDP-1]
>[  939.799174] [drm:intel_crtc_set_config] [CRTC:20] [FB:87] #connectors=1 (x y) (0 0)
>[  939.799176] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  939.799178] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=0
>[  939.799179] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  939.799180] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  939.799181] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  939.799183] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  939.799185] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  939.799187] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[  939.799188] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[  939.799190] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz
>[  939.799192] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[  939.799193] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000
>[  939.799195] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[  939.799196] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  939.799197] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[  939.799198] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  939.799200] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  939.799201] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64
>[  939.799202] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  939.799204] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  939.799204] [drm:intel_dump_pipe_config] requested mode:
>[  939.799207] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x0 0x9
>[  939.799207] [drm:intel_dump_pipe_config] adjusted mode:
>[  939.799209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  939.799211] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9
>[  939.799212] [drm:intel_dump_pipe_config] port clock: 270000
>[  939.799213] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  939.799214] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  939.799216] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  939.799216] [drm:intel_dump_pipe_config] ips: 1
>[  939.799217] [drm:intel_dump_pipe_config] double wide: 0
>[  939.799221] [drm:intel_display_power_get] enabling always-on
>[  939.799224] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800b00f60c0
>[  939.802497] [drm:edp_panel_on] Turn eDP port A panel power on
>[  939.802502] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  940.347456] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000
>[  940.360781] [drm:wait_panel_status] Wait complete
>[  940.360789] [drm:wait_panel_on] Wait for panel power on
>[  940.360792] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[  940.574036] [drm:wait_panel_status] Wait complete
>[  940.574047] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  940.574054] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  940.575138] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  940.575721] [drm:intel_dp_start_link_train] clock recovery OK
>[  940.576600] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  940.576824] [drm:intel_edp_backlight_on] 
>[  940.576826] [drm:intel_panel_enable_backlight] pipe A
>[  940.576830] [drm:intel_panel_actually_set_backlight] set backlight PWM = 851
>[  940.580652] [drm:intel_psr_match_conditions] PSR disable by flag
>[  940.580654] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  940.587367] [drm:ironlake_update_primary_plane] Writing base 0A67C000 00000000 0 0 7680
>[  940.610693] [drm:intel_fbc_update] disabled per chip default
>[  940.610703] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[  940.610709] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  940.610710] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  940.610712] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  940.610713] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  940.610714] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  940.610716] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  940.610717] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  940.610719] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  940.610720] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  940.610722] [drm:check_crtc_state] [CRTC:20]
>[  940.610729] [drm:check_crtc_state] [CRTC:24]
>[  940.610731] [drm:check_crtc_state] [CRTC:28]
>[  940.610733] [drm:check_shared_dpll_state] WRPLL 1
>[  940.610735] [drm:check_shared_dpll_state] WRPLL 2
>[  940.610768] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=516/851
>[  940.610770] [drm:intel_panel_actually_set_backlight] set backlight PWM = 520
>[  940.610867] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6600
>[  940.632126] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff880306dc6240
>[  940.632211] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff880306dc6d80
>[  940.632285] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff880306dc6240
>[  940.632352] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff880306dc6d80
>[  940.632464] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff880306dc6240
>[  940.632603] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff880306dc6d80
>[  940.656249] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  940.656256] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
>[  940.656258] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
>[  940.656579] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[  940.656879] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[  940.656893] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  940.656896] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
>[  940.656899] [drm:drm_mode_debug_printmodeline] Modeline 32:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  940.656904] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  940.657059] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[  940.657061] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1]
>[  940.657063] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[  940.657068] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1] disconnected
>[  940.657071] [drm:drm_mode_getconnector] [CONNECTOR:46:?]
>[  940.657073] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2]
>[  940.657075] [drm:intel_dp_detect] [CONNECTOR:46:DP-2]
>[  940.657076] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2] disconnected
>[  940.657085] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  940.657087] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3]
>[  940.658356] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  940.658360] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  940.658371] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  940.658866] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  940.659886] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  940.659889] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  940.661616] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  940.661624] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  940.661661] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  940.662271] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  940.664000] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  940.664004] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  940.664825] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  940.664826] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  940.664838] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  940.665310] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  940.666986] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  940.666988] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  940.667812] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  940.667815] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  940.667826] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  940.668304] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  940.669337] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  940.669346] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3] probed modes :
>[  940.669349] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  940.669352] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  940.669355] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  940.669357] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  940.669360] [drm:drm_mode_debug_printmodeline] Modeline 61:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  940.669362] [drm:drm_mode_debug_printmodeline] Modeline 69:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  940.669364] [drm:drm_mode_debug_printmodeline] Modeline 70:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  940.669367] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  940.669369] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  940.669372] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  940.669374] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  940.669376] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  940.669389] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  940.669422] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  940.669424] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4]
>[  940.669974] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  940.669976] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  940.671233] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  940.671236] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  940.671244] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  940.671719] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  940.672734] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  940.672736] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  940.674436] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  940.674441] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  940.674458] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  940.674938] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  940.676657] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  940.676660] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  940.677479] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  940.677482] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  940.677491] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  940.677980] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  940.679676] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  940.679679] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  940.680486] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  940.680489] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  940.680498] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  940.681435] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  940.682486] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  940.682495] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4] probed modes :
>[  940.682498] [drm:drm_mode_debug_printmodeline] Modeline 73:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  940.682501] [drm:drm_mode_debug_printmodeline] Modeline 76:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  940.682503] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  940.682506] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  940.682508] [drm:drm_mode_debug_printmodeline] Modeline 74:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  940.682511] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  940.682513] [drm:drm_mode_debug_printmodeline] Modeline 83:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  940.682516] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  940.682518] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  940.682520] [drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  940.682523] [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  940.682525] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  940.682537] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  940.682573] [drm:drm_mode_getconnector] [CONNECTOR:57:?]
>[  940.682575] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5]
>[  940.682577] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5] disconnected
>[  940.682581] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[  940.682582] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[  940.682584] [drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[  940.683169] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  940.683172] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  940.693930] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  940.693934] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[  940.693946] [drm:drm_mode_getconnector] [CONNECTOR:50:?]
>[  940.693948] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2]
>[  940.693950] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-2]
>[  940.694127] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  940.694128] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  940.694130] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2] disconnected
>[  940.867799] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0a80
>[  940.888550] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0d80
>[  940.891521] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0a80
>[  940.891680] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0d80
>[  940.891731] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0a80
>[  942.256355] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b02ea180
>[  942.256472] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b02eaa80
>[  942.256550] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b02ea180
>[  942.275170] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b02eaa80
>[  942.846918] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e769c0
>[  943.662917] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[  943.662926] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>
>
>
>[  945.557375] xrandr --output DP2-2 --auto --output DP2-1 --auto --right-of DP2-2
>               --> try to enable them, fails (same command as before, with --right-of)
>[  946.703509] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  946.703514] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
>[  946.703516] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
>[  946.703523] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  946.703530] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  946.703838] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[  946.704142] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[  946.704151] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  946.704154] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
>[  946.704156] [drm:drm_mode_debug_printmodeline] Modeline 32:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  946.704160] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  946.704238] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[  946.704239] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1]
>[  946.704241] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[  946.704245] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1] disconnected
>[  946.704248] [drm:drm_mode_getconnector] [CONNECTOR:46:?]
>[  946.704249] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2]
>[  946.704250] [drm:intel_dp_detect] [CONNECTOR:46:DP-2]
>[  946.704252] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2] disconnected
>[  946.704256] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  946.704257] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3]
>[  946.705525] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  946.705529] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  946.705555] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  946.706034] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  946.707054] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  946.707056] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  946.711301] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  946.711306] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  946.711330] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  946.711840] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  946.713540] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  946.713541] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  946.714393] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  946.714395] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  946.714403] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  946.714874] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  946.716572] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  946.716574] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  946.717434] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  946.717437] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  946.717445] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  946.717927] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  946.718977] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  946.718985] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3] probed modes :
>[  946.718989] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  946.718991] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  946.718994] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  946.718996] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  946.718999] [drm:drm_mode_debug_printmodeline] Modeline 61:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  946.719001] [drm:drm_mode_debug_printmodeline] Modeline 69:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  946.719004] [drm:drm_mode_debug_printmodeline] Modeline 70:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  946.719006] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  946.719008] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  946.719011] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  946.719013] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  946.719016] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  946.719027] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  946.719054] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  946.719056] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4]
>[  946.719615] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  946.719616] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  946.720904] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  946.720906] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  946.720910] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  946.721383] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  946.722392] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  946.722394] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  946.724117] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  946.724118] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  946.724126] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  946.724600] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  946.726290] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  946.726292] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  946.727152] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  946.727154] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  946.727160] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  946.727633] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  946.729329] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  946.729331] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  946.730176] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  946.730177] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  946.730185] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  946.730659] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  946.731689] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  946.731698] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4] probed modes :
>[  946.731702] [drm:drm_mode_debug_printmodeline] Modeline 73:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  946.731717] [drm:drm_mode_debug_printmodeline] Modeline 76:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  946.731720] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  946.731723] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  946.731726] [drm:drm_mode_debug_printmodeline] Modeline 74:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  946.731730] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  946.731733] [drm:drm_mode_debug_printmodeline] Modeline 83:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  946.731736] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  946.731739] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  946.731742] [drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  946.731746] [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  946.731749] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  946.731756] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  946.731776] [drm:drm_mode_getconnector] [CONNECTOR:57:?]
>[  946.731778] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5]
>[  946.731780] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5] disconnected
>[  946.731784] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[  946.731787] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[  946.731789] [drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[  946.732383] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  946.732385] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  946.745055] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  946.745057] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[  946.745060] [drm:drm_mode_getconnector] [CONNECTOR:50:?]
>[  946.745061] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2]
>[  946.745062] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-2]
>[  946.745258] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  946.745259] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  946.745260] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2] disconnected
>[  946.746477] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c4c02000
>[  946.757459] [drm:drm_mode_setcrtc] [CRTC:20]
>[  946.757466] [drm:drm_mode_setcrtc] [CONNECTOR:31:eDP-1]
>[  946.757470] [drm:intel_crtc_set_config] [CRTC:20] [FB:88] #connectors=1 (x y) (0 0)
>[  946.757475] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=1
>[  946.757479] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  946.757484] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  946.757489] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[  946.757491] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[  946.757500] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz
>[  946.757504] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[  946.757505] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000
>[  946.757510] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[  946.757512] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  946.757515] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[  946.757517] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  946.757519] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  946.757521] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64
>[  946.757523] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  946.757525] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  946.757527] [drm:intel_dump_pipe_config] requested mode:
>[  946.757530] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x0 0x9
>[  946.757532] [drm:intel_dump_pipe_config] adjusted mode:
>[  946.757535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  946.757538] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9
>[  946.757539] [drm:intel_dump_pipe_config] port clock: 270000
>[  946.757541] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  946.757543] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  946.757546] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  946.757547] [drm:intel_dump_pipe_config] ips: 1
>[  946.757548] [drm:intel_dump_pipe_config] double wide: 0
>[  946.757555] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800b00f3180
>[  946.761504] [drm:ironlake_update_primary_plane] Writing base 03212000 00000000 0 0 15360
>[  946.775411] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800b02ea3c0
>[  946.790841] [drm:drm_mode_setcrtc] [CRTC:24]
>[  946.790849] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-3]
>[  946.790851] [drm:drm_mode_setcrtc] [CONNECTOR:55:DP-4]
>[  946.790853] [drm:intel_crtc_set_config] [CRTC:24] [FB:88] #connectors=2 (x y) (0 0)
>[  946.790858] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  946.790860] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=1, fb_changed=1
>[  946.790862] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  946.790863] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  946.790865] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  946.790866] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[  946.790868] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:24]
>[  946.790871] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  946.790880] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[  946.790885] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  946.790887] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  946.790889] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  946.790890] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  946.790892] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  946.790893] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  946.790894] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  946.790895] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  946.790897] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  946.790899] [drm:check_crtc_state] [CRTC:20]
>[  946.790909] [drm:check_crtc_state] [CRTC:24]
>[  946.790910] [drm:check_crtc_state] [CRTC:28]
>[  946.790912] [drm:check_shared_dpll_state] WRPLL 1
>[  946.790914] [drm:check_shared_dpll_state] WRPLL 2
>[  946.790965] [drm:drm_mode_setcrtc] [CRTC:24]
>[  946.790967] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-3]
>[  946.790968] [drm:drm_mode_setcrtc] [CONNECTOR:55:DP-4]
>[  946.790970] [drm:intel_crtc_set_config] [CRTC:24] [FB:89] #connectors=2 (x y) (0 0)
>[  946.790972] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  946.790974] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=1, fb_changed=1
>[  946.790975] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  946.790976] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  946.790977] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  946.790978] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[  946.790980] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:24]
>[  946.790982] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  946.790986] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[  946.790989] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  946.790991] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  946.790992] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  946.790993] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  946.790994] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  946.790995] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  946.790997] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  946.790998] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  946.790999] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  946.791000] [drm:check_crtc_state] [CRTC:20]
>[  946.791007] [drm:check_crtc_state] [CRTC:24]
>[  946.791009] [drm:check_crtc_state] [CRTC:28]
>[  946.791010] [drm:check_shared_dpll_state] WRPLL 1
>[  946.791012] [drm:check_shared_dpll_state] WRPLL 2
>[  946.791044] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[8] ENCODERS[9]
>[  946.791085] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800b00f3840
>[  946.791376] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=516/851
>[  946.791381] [drm:intel_panel_actually_set_backlight] set backlight PWM = 520
>[  946.791406] [drm:intel_edp_backlight_power] panel power control backlight disable
>[  946.991731] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/851
>[  946.991735] [drm:intel_panel_actually_set_backlight] set backlight PWM = 10
>[  946.991783] [drm:drm_mode_setcrtc] [CRTC:20]
>[  946.991786] [drm:intel_crtc_set_config] [CRTC:20] [NOFB]
>[  946.991789] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=0
>[  946.991791] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [NOCRTC]
>[  946.991792] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  946.991794] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  946.991795] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  946.991798] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  947.011634] [drm:intel_edp_backlight_off] 
>[  947.214950] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  947.228450] [drm:edp_panel_off] Turn eDP port A panel power off
>[  947.228457] [drm:wait_panel_off] Wait for panel power off time
>[  947.228461] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[  947.281592] [drm:wait_panel_status] Wait complete
>[  947.281606] [drm:intel_fbc_update] no output, disabling
>[  947.281610] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c9e763c0
>[  947.281621] [drm:intel_display_power_put] disabling always-on
>[  947.281626] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  947.281628] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  947.281630] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  947.281631] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  947.281632] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  947.281633] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  947.281635] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  947.281636] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  947.281637] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  947.281638] [drm:check_crtc_state] [CRTC:20]
>[  947.281640] [drm:check_crtc_state] [CRTC:24]
>[  947.281642] [drm:check_crtc_state] [CRTC:28]
>[  947.281644] [drm:check_shared_dpll_state] WRPLL 1
>[  947.281645] [drm:check_shared_dpll_state] WRPLL 2
>[  947.281664] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c9e76540
>[  947.282977] [drm:drm_mode_addfb2] [FB:87]
>[  947.283307] [drm:drm_mode_setcrtc] [CRTC:20]
>[  947.283312] [drm:drm_mode_setcrtc] [CONNECTOR:31:eDP-1]
>[  947.283315] [drm:intel_crtc_set_config] [CRTC:20] [FB:87] #connectors=1 (x y) (0 0)
>[  947.283317] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  947.283319] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=0
>[  947.283320] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  947.283322] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  947.283323] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  947.283325] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  947.283327] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  947.283329] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[  947.283331] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[  947.283333] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz
>[  947.283335] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[  947.283337] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000
>[  947.283339] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[  947.283341] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  947.283342] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[  947.283343] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  947.283345] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  947.283347] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64
>[  947.283348] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  947.283350] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  947.283351] [drm:intel_dump_pipe_config] requested mode:
>[  947.283353] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x0 0x9
>[  947.283354] [drm:intel_dump_pipe_config] adjusted mode:
>[  947.283356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  947.283358] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9
>[  947.283360] [drm:intel_dump_pipe_config] port clock: 270000
>[  947.283361] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  947.283362] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  947.283364] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  947.283365] [drm:intel_dump_pipe_config] ips: 1
>[  947.283366] [drm:intel_dump_pipe_config] double wide: 0
>[  947.283370] [drm:intel_display_power_get] enabling always-on
>[  947.283373] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c4c020c0
>[  947.286911] [drm:edp_panel_on] Turn eDP port A panel power on
>[  947.286915] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  947.831398] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000
>[  947.858049] [drm:wait_panel_status] Wait complete
>[  947.858057] [drm:wait_panel_on] Wait for panel power on
>[  947.858061] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[  948.071302] [drm:wait_panel_status] Wait complete
>[  948.071314] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  948.071321] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  948.072398] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  948.072983] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  948.073553] [drm:intel_dp_start_link_train] clock recovery OK
>[  948.074942] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  948.075165] [drm:intel_edp_backlight_on] 
>[  948.075167] [drm:intel_panel_enable_backlight] pipe A
>[  948.075172] [drm:intel_panel_actually_set_backlight] set backlight PWM = 851
>[  948.077941] [drm:intel_psr_match_conditions] PSR disable by flag
>[  948.077944] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  948.084631] [drm:ironlake_update_primary_plane] Writing base 0A67C000 00000000 0 0 7680
>[  948.111286] [drm:intel_fbc_update] disabled per chip default
>[  948.111296] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[  948.111301] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  948.111302] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  948.111304] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  948.111305] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  948.111307] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  948.111308] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  948.111309] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  948.111310] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  948.111312] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  948.111313] [drm:check_crtc_state] [CRTC:20]
>[  948.111320] [drm:check_crtc_state] [CRTC:24]
>[  948.111322] [drm:check_crtc_state] [CRTC:28]
>[  948.111324] [drm:check_shared_dpll_state] WRPLL 1
>[  948.111326] [drm:check_shared_dpll_state] WRPLL 2
>[  948.111357] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=516/851
>[  948.111359] [drm:intel_panel_actually_set_backlight] set backlight PWM = 520
>[  948.111457] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c4c02240
>[  948.132276] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f3cc0
>[  948.132477] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f3900
>[  948.132808] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f3cc0
>[  948.137503] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e769c0
>[  948.137804] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76240
>[  948.137973] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e769c0
>[  948.165312] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  948.165318] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
>[  948.165320] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
>[  948.165633] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[  948.165958] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[  948.165970] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  948.165973] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
>[  948.165977] [drm:drm_mode_debug_printmodeline] Modeline 32:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  948.165981] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  948.166075] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[  948.166076] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1]
>[  948.166077] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[  948.166081] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1] disconnected
>[  948.166084] [drm:drm_mode_getconnector] [CONNECTOR:46:?]
>[  948.166085] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2]
>[  948.166086] [drm:intel_dp_detect] [CONNECTOR:46:DP-2]
>[  948.166087] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2] disconnected
>[  948.166090] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  948.166092] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3]
>[  948.167365] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  948.167367] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  948.167376] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  948.167865] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  948.168869] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  948.168872] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  948.170587] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  948.170591] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  948.170608] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  948.171089] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  948.172778] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  948.172781] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  948.173613] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  948.173616] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  948.173626] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  948.174102] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  948.175979] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  948.175982] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  948.176757] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  948.176760] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  948.176771] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  948.177251] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  948.178641] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  948.178652] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3] probed modes :
>[  948.178655] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  948.178659] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  948.178662] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  948.178664] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  948.178667] [drm:drm_mode_debug_printmodeline] Modeline 61:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  948.178670] [drm:drm_mode_debug_printmodeline] Modeline 69:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  948.178673] [drm:drm_mode_debug_printmodeline] Modeline 70:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  948.178676] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  948.178679] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  948.178682] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  948.178684] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  948.178687] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  948.178702] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  948.178733] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  948.178735] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4]
>[  948.179282] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  948.179284] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  948.180552] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  948.180555] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  948.180575] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  948.181055] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  948.183105] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  948.183108] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  948.184813] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  948.184816] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  948.184828] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  948.185308] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  948.186983] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  948.186985] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  948.187826] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  948.187829] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  948.187842] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  948.188320] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  948.189992] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  948.189994] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  948.190834] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  948.190836] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  948.190844] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  948.191324] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  948.192376] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  948.192389] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4] probed modes :
>[  948.192393] [drm:drm_mode_debug_printmodeline] Modeline 73:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  948.192397] [drm:drm_mode_debug_printmodeline] Modeline 76:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  948.192401] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  948.192404] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  948.192408] [drm:drm_mode_debug_printmodeline] Modeline 74:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  948.192411] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  948.192415] [drm:drm_mode_debug_printmodeline] Modeline 83:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  948.192418] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  948.192422] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  948.192425] [drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  948.192429] [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  948.192432] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  948.192447] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  948.192489] [drm:drm_mode_getconnector] [CONNECTOR:57:?]
>[  948.192492] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5]
>[  948.192494] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5] disconnected
>[  948.192499] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[  948.192501] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[  948.192504] [drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[  948.193040] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  948.193041] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  948.204523] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  948.204525] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[  948.204530] [drm:drm_mode_getconnector] [CONNECTOR:50:?]
>[  948.204532] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2]
>[  948.204533] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-2]
>[  948.204723] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  948.204724] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  948.204725] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2] disconnected
>[  948.405379] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc9540
>[  948.427826] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc9c00
>[  948.427991] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc9540
>[  948.428105] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc9c00
>[  948.428156] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc9540
>[  949.330176] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b02ea780
>[  949.330289] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b02ea840
>[  949.330356] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b02ea780
>[  950.268048] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f3540
>[  951.166820] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[  951.166829] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  966.406023] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f30c0
>[  966.416017] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f3540
>[  966.418031] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc9540
>[  966.420005] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f30c0
>[  966.424002] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f3c00
>[  966.428011] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f30c0
>[  966.432000] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f3c00
>[  966.434011] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f30c0
>[  966.436002] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f3c00
>[  966.438021] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc9e40
>[  966.439997] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f30c0
>[  966.441996] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f3240
>[  966.443995] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f30c0
>[  966.446004] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f3240
>[  966.447982] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76000
>[  966.450004] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76b40
>[  966.452001] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76000
>[  966.453997] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76b40
>[  966.456000] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76000
>[  966.458020] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc9480
>[  966.459997] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc99c0
>[  966.462006] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc9480
>[  966.463994] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc99c0
>[  966.466010] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc9480
>[  966.468027] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b02ea840
>[  966.469993] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b02eab40
>[  966.471994] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b02ea840
>[  966.473994] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b02eab40
>[  966.475991] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b02ea840
>[  966.477994] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76b40
>[  966.479984] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76240
>[  966.481984] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76b40
>[  966.483996] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76240
>[  966.485941] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc99c0
>[  966.487964] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc90c0
>[  966.489882] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc99c0
>[  966.491890] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc90c0
>[  966.493903] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc99c0
>[  966.495912] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc90c0
>[  966.497915] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc99c0
>[  966.501990] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc90c0
>[  966.503975] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76b40
>[  966.505975] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76f00
>[  966.509977] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76b40
>[  966.511984] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76f00
>[  966.515982] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76b40
>[  966.519970] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76f00
>[  966.525973] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76b40
>[  966.527981] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc99c0
>[  966.531969] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc9180
>[  966.535931] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc99c0
>[  966.537971] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76f00
>[  966.547959] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76300
>[  966.553957] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76f00
>[  966.565975] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76300
>[  966.669922] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76f00
>[  967.419656] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f30c0
>[  967.423641] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f3e40
>[  967.429651] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f30c0
>[  967.451651] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f3e40
>[  967.469632] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f30c0
>[  967.529615] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f3e40
>[  975.215101] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  975.215114] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
>[  975.215118] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
>[  975.215134] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  975.215146] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  975.215544] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[  975.215896] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[  975.215926] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  975.215936] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
>[  975.215948] [drm:drm_mode_debug_printmodeline] Modeline 32:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  975.215962] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  975.216265] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[  975.216273] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1]
>[  975.216279] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[  975.216290] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1] disconnected
>[  975.216302] [drm:drm_mode_getconnector] [CONNECTOR:46:?]
>[  975.216308] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2]
>[  975.216313] [drm:intel_dp_detect] [CONNECTOR:46:DP-2]
>[  975.216319] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2] disconnected
>[  975.216334] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  975.216340] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3]
>[  975.217637] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  975.217646] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  975.217680] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  975.218220] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  975.219348] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  975.219357] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  975.221098] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  975.221108] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  975.221130] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  975.221676] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  975.223452] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  975.223459] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  975.224248] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  975.224254] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  975.224273] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  975.224779] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  975.226515] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  975.226519] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  975.227328] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  975.227335] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  975.227355] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  975.227844] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  975.228947] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  975.228964] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3] probed modes :
>[  975.228970] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  975.228976] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  975.228982] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  975.228987] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  975.228992] [drm:drm_mode_debug_printmodeline] Modeline 61:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  975.228997] [drm:drm_mode_debug_printmodeline] Modeline 69:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  975.229003] [drm:drm_mode_debug_printmodeline] Modeline 70:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  975.229009] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  975.229013] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  975.229018] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  975.229023] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  975.229029] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  975.229050] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  975.229098] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  975.229103] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4]
>[  975.230261] [drm:intel_dp_check_mst_status] got esi2 02 10 00
>[  975.230266] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  975.230391] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  975.230395] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  975.231293] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  975.231297] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  975.231302] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  975.231794] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  975.233534] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  975.233536] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  975.233546] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  975.234030] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  975.235762] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  975.235766] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  975.236597] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  975.236599] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  975.236609] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  975.237092] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  975.238862] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  975.238866] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  975.239692] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  975.239695] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  975.239712] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  975.240202] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  975.241264] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  975.241281] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4] probed modes :
>[  975.241287] [drm:drm_mode_debug_printmodeline] Modeline 73:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  975.241292] [drm:drm_mode_debug_printmodeline] Modeline 76:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  975.241297] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  975.241302] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  975.241307] [drm:drm_mode_debug_printmodeline] Modeline 74:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  975.241332] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  975.241338] [drm:drm_mode_debug_printmodeline] Modeline 83:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  975.241343] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  975.241348] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  975.241353] [drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  975.241358] [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  975.241362] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  975.241379] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  975.241419] [drm:drm_mode_getconnector] [CONNECTOR:57:?]
>[  975.241423] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5]
>[  975.241426] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5] disconnected
>[  975.241432] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[  975.241436] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[  975.241439] [drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[  975.241947] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  975.241952] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  975.254667] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  975.254669] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[  975.254677] [drm:drm_mode_getconnector] [CONNECTOR:50:?]
>[  975.254679] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2]
>[  975.254681] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-2]
>[  975.254882] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  975.254884] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  975.254887] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2] disconnected
>[  975.256607] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802c8dc9480
>[  975.268113] [drm:drm_mode_addfb2] [FB:88]
>[  975.268295] [drm:drm_mode_setcrtc] [CRTC:20]
>[  975.268299] [drm:drm_mode_setcrtc] [CONNECTOR:31:eDP-1]
>[  975.268302] [drm:intel_crtc_set_config] [CRTC:20] [FB:88] #connectors=1 (x y) (0 0)
>[  975.268306] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=1
>[  975.268308] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  975.268311] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  975.268314] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[  975.268316] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[  975.268319] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz
>[  975.268321] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[  975.268323] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000
>[  975.268325] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[  975.268327] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  975.268329] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[  975.268330] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  975.268332] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  975.268334] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64
>[  975.268336] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  975.268337] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  975.268338] [drm:intel_dump_pipe_config] requested mode:
>[  975.268342] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x0 0x9
>[  975.268343] [drm:intel_dump_pipe_config] adjusted mode:
>[  975.268346] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  975.268349] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9
>[  975.268350] [drm:intel_dump_pipe_config] port clock: 270000
>[  975.268352] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  975.268354] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  975.268356] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  975.268357] [drm:intel_dump_pipe_config] ips: 1
>[  975.268358] [drm:intel_dump_pipe_config] double wide: 0
>[  975.268365] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9d80
>[  975.270949] [drm:ironlake_update_primary_plane] Writing base 03212000 00000000 0 0 15360
>[  975.278782] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800b00f03c0
>[  975.295351] [drm:drm_mode_setcrtc] [CRTC:24]
>[  975.295359] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-3]
>[  975.295361] [drm:drm_mode_setcrtc] [CONNECTOR:55:DP-4]
>[  975.295364] [drm:intel_crtc_set_config] [CRTC:24] [FB:88] #connectors=2 (x y) (0 0)
>[  975.295367] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  975.295369] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=1, fb_changed=1
>[  975.295371] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  975.295372] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  975.295374] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  975.295376] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[  975.295377] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:24]
>[  975.295381] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  975.295389] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[  975.295394] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  975.295396] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  975.295398] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  975.295399] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  975.295400] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  975.295402] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  975.295403] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  975.295404] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  975.295406] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  975.295407] [drm:check_crtc_state] [CRTC:20]
>[  975.295416] [drm:check_crtc_state] [CRTC:24]
>[  975.295418] [drm:check_crtc_state] [CRTC:28]
>[  975.295420] [drm:check_shared_dpll_state] WRPLL 1
>[  975.295422] [drm:check_shared_dpll_state] WRPLL 2
>[  975.295462] [drm:drm_mode_setcrtc] [CRTC:24]
>[  975.295465] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-3]
>[  975.295466] [drm:drm_mode_setcrtc] [CONNECTOR:55:DP-4]
>[  975.295468] [drm:intel_crtc_set_config] [CRTC:24] [FB:89] #connectors=2 (x y) (0 0)
>[  975.295470] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  975.295472] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=1, fb_changed=1
>[  975.295473] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  975.295475] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  975.295476] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  975.295477] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[  975.295479] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:24]
>[  975.295481] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 0
>[  975.295486] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[  975.295490] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  975.295491] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  975.295493] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  975.295494] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  975.295496] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  975.295497] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  975.295498] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  975.295500] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  975.295501] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  975.295502] [drm:check_crtc_state] [CRTC:20]
>[  975.295509] [drm:check_crtc_state] [CRTC:24]
>[  975.295511] [drm:check_crtc_state] [CRTC:28]
>[  975.295513] [drm:check_shared_dpll_state] WRPLL 1
>[  975.295514] [drm:check_shared_dpll_state] WRPLL 2
>[  975.295557] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[8] ENCODERS[9]
>[  975.295606] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800b00f06c0
>[  975.295937] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=516/851
>[  975.295942] [drm:intel_panel_actually_set_backlight] set backlight PWM = 520
>[  975.295951] [drm:intel_edp_backlight_power] panel power control backlight disable
>[  975.498008] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/851
>[  975.498012] [drm:intel_panel_actually_set_backlight] set backlight PWM = 10
>[  975.498056] [drm:drm_mode_setcrtc] [CRTC:20]
>[  975.498059] [drm:intel_crtc_set_config] [CRTC:20] [NOFB]
>[  975.498062] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=0
>[  975.498064] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [NOCRTC]
>[  975.498065] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  975.498067] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  975.498069] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch
>[  975.498071] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  975.517977] [drm:intel_edp_backlight_off] 
>[  975.721228] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  975.734717] [drm:edp_panel_off] Turn eDP port A panel power off
>[  975.734725] [drm:wait_panel_off] Wait for panel power off time
>[  975.734728] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[  975.787866] [drm:wait_panel_status] Wait complete
>[  975.787879] [drm:intel_fbc_update] no output, disabling
>[  975.787884] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c9e76840
>[  975.787894] [drm:intel_display_power_put] disabling always-on
>[  975.787899] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  975.787901] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  975.787902] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  975.787904] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  975.787905] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  975.787906] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  975.787907] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  975.787908] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  975.787910] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  975.787911] [drm:check_crtc_state] [CRTC:20]
>[  975.787913] [drm:check_crtc_state] [CRTC:24]
>[  975.787915] [drm:check_crtc_state] [CRTC:28]
>[  975.787916] [drm:check_shared_dpll_state] WRPLL 1
>[  975.787918] [drm:check_shared_dpll_state] WRPLL 2
>[  975.787937] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c9e76c00
>[  975.789190] [drm:drm_mode_addfb2] [FB:87]
>[  975.789532] [drm:drm_mode_setcrtc] [CRTC:20]
>[  975.789537] [drm:drm_mode_setcrtc] [CONNECTOR:31:eDP-1]
>[  975.789539] [drm:intel_crtc_set_config] [CRTC:20] [FB:87] #connectors=1 (x y) (0 0)
>[  975.789542] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  975.789544] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=0
>[  975.789545] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[  975.789547] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[  975.789548] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[  975.789550] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[  975.789552] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  975.789554] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[  975.789555] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[  975.789558] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz
>[  975.789560] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[  975.789561] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000
>[  975.789564] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[  975.789566] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  975.789567] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[  975.789568] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  975.789570] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  975.789571] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64
>[  975.789573] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  975.789574] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  975.789575] [drm:intel_dump_pipe_config] requested mode:
>[  975.789577] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x0 0x9
>[  975.789579] [drm:intel_dump_pipe_config] adjusted mode:
>[  975.789581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  975.789583] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9
>[  975.789584] [drm:intel_dump_pipe_config] port clock: 270000
>[  975.789585] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  975.789587] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  975.789588] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  975.789589] [drm:intel_dump_pipe_config] ips: 1
>[  975.789590] [drm:intel_dump_pipe_config] double wide: 0
>[  975.789594] [drm:intel_display_power_get] enabling always-on
>[  975.789597] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8802c8dc9180
>[  975.792638] [drm:edp_panel_on] Turn eDP port A panel power on
>[  975.792644] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  976.337671] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control abcd0000
>[  976.351008] [drm:wait_panel_status] Wait complete
>[  976.351016] [drm:wait_panel_on] Wait for panel power on
>[  976.351020] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[  976.564249] [drm:wait_panel_status] Wait complete
>[  976.564261] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  976.564268] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  976.565346] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  976.565926] [drm:intel_dp_start_link_train] clock recovery OK
>[  976.566804] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  976.567027] [drm:intel_edp_backlight_on] 
>[  976.567028] [drm:intel_panel_enable_backlight] pipe A
>[  976.567033] [drm:intel_panel_actually_set_backlight] set backlight PWM = 851
>[  976.570871] [drm:intel_psr_match_conditions] PSR disable by flag
>[  976.570873] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  976.577578] [drm:ironlake_update_primary_plane] Writing base 0A67C000 00000000 0 0 7680
>[  976.600908] [drm:intel_fbc_update] disabled per chip default
>[  976.600918] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[  976.600924] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[  976.600926] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  976.600927] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[  976.600929] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[  976.600930] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  976.600931] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[  976.600933] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  976.600934] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[  976.600935] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  976.600936] [drm:check_crtc_state] [CRTC:20]
>[  976.600945] [drm:check_crtc_state] [CRTC:24]
>[  976.600947] [drm:check_crtc_state] [CRTC:28]
>[  976.600949] [drm:check_shared_dpll_state] WRPLL 1
>[  976.600951] [drm:check_shared_dpll_state] WRPLL 2
>[  976.600984] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=516/851
>[  976.600986] [drm:intel_panel_actually_set_backlight] set backlight PWM = 520
>[  976.601073] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0e40
>
>
>
>[  976.618376] xrandr --output DP2-2 --auto --output DP2-1 --auto --right-of DP2-2
>               --> try to enable them, fails (same command as before, with --right-of)
>[  976.622702] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0f00
>[  976.622795] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0e40
>[  976.622871] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0f00
>[  976.622985] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0e40
>[  976.623176] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0f00
>[  976.623276] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0e40
>[  976.643260] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  976.643267] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
>[  976.643269] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
>[  976.643587] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[  976.643887] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[  976.643898] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  976.643901] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
>[  976.643903] [drm:drm_mode_debug_printmodeline] Modeline 32:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[  976.643907] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  976.644002] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[  976.644004] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1]
>[  976.644006] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[  976.644011] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1] disconnected
>[  976.644015] [drm:drm_mode_getconnector] [CONNECTOR:46:?]
>[  976.644016] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2]
>[  976.644017] [drm:intel_dp_detect] [CONNECTOR:46:DP-2]
>[  976.644018] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2] disconnected
>[  976.644024] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  976.644026] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3]
>[  976.645295] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  976.645299] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  976.645320] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  976.645846] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  976.646943] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  976.646950] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  976.648675] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  976.648679] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  976.648699] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  976.649175] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  976.650866] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  976.650874] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  976.651700] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  976.651706] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  976.651724] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  976.652210] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  976.653898] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  976.653902] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  976.654715] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  976.654718] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  976.654733] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  976.655216] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  976.656257] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  976.656267] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3] probed modes :
>[  976.656271] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  976.656274] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  976.656277] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  976.656280] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  976.656283] [drm:drm_mode_debug_printmodeline] Modeline 61:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  976.656286] [drm:drm_mode_debug_printmodeline] Modeline 69:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  976.656289] [drm:drm_mode_debug_printmodeline] Modeline 70:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  976.656292] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  976.656294] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  976.656297] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  976.656299] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  976.656302] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  976.656316] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  976.656347] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  976.656350] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4]
>[  976.656885] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  976.656887] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  976.658166] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  976.658172] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  976.658203] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  976.658683] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  976.659709] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  976.659711] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  976.661417] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  976.661420] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  976.661425] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  976.661900] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  976.663586] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  976.663588] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  976.664418] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  976.664420] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  976.664426] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  976.664901] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  976.666573] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  976.666575] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  976.667405] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[  976.667408] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  976.667417] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  976.667902] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[  976.668933] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  976.668942] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4] probed modes :
>[  976.668945] [drm:drm_mode_debug_printmodeline] Modeline 73:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  976.668948] [drm:drm_mode_debug_printmodeline] Modeline 76:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[  976.668951] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  976.668953] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  976.668956] [drm:drm_mode_debug_printmodeline] Modeline 74:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  976.668958] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  976.668961] [drm:drm_mode_debug_printmodeline] Modeline 83:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  976.668963] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  976.668965] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  976.668968] [drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  976.668970] [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  976.668973] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  976.668983] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  976.669016] [drm:drm_mode_getconnector] [CONNECTOR:57:?]
>[  976.669017] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5]
>[  976.669019] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5] disconnected
>[  976.669023] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[  976.669024] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[  976.669026] [drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[  976.669616] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[  976.669617] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[  976.680818] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  976.680820] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[  976.680833] [drm:drm_mode_getconnector] [CONNECTOR:50:?]
>[  976.680835] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2]
>[  976.680835] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-2]
>[  976.681041] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  976.681043] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  976.681044] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2] disconnected
>[  976.865783] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e763c0
>[  976.889169] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030edac6c0
>[  976.893365] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030edac000
>[  976.893655] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030edac6c0
>[  976.923391] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76000
>[  977.469592] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6540
>[  977.469663] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6600
>[  977.469711] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6540
>[  978.074145] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff88030edac000
>[  979.649806] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[  979.649819] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>
>
>
>[  998.391313] restart X (which in turns calls 'xrandr --output DP2-2 --auto --output DP2-1 --auto --right-of DP2-2' after a while)
>               --> this will restore the external screens, initially without any xrandr set-up (in clone mode)
>[ 1000.777706] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1000.779703] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0000
>[ 1000.781641] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1000.783706] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0000
>[ 1000.785710] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e766c0
>[ 1000.787698] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76900
>[ 1000.789737] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e766c0
>[ 1000.791702] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76900
>[ 1000.793619] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9fac840
>[ 1000.795583] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e766c0
>[ 1000.797570] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9fac300
>[ 1000.799550] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9face40
>[ 1000.801549] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9fac300
>[ 1000.803567] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e769c0
>[ 1000.805553] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76600
>[ 1000.807548] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e769c0
>[ 1000.809538] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76600
>[ 1000.811542] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e769c0
>[ 1000.813534] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76600
>[ 1000.815500] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e769c0
>[ 1000.817537] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76600
>[ 1000.819531] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e769c0
>[ 1000.821510] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76600
>[ 1000.823493] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e769c0
>[ 1000.825516] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76600
>[ 1000.827526] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6600
>[ 1000.829518] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6f00
>[ 1000.831510] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6600
>[ 1000.833516] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6f00
>[ 1000.835514] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e769c0
>[ 1000.837506] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6600
>[ 1000.839497] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6480
>[ 1000.841470] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6600
>[ 1000.843490] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6480
>[ 1000.845593] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9facc00
>[ 1000.847625] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9face40
>[ 1000.849629] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9facc00
>[ 1000.851633] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9face40
>[ 1000.853623] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9facc00
>[ 1000.855550] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76300
>[ 1000.857622] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76540
>[ 1000.859607] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76300
>[ 1000.861599] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76540
>[ 1000.863607] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76300
>[ 1000.865558] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9face40
>[ 1000.867615] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9fac240
>[ 1000.869607] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9face40
>[ 1000.871620] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9fac240
>[ 1000.873620] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9face40
>[ 1000.875517] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76540
>[ 1000.877587] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76f00
>[ 1000.879585] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76540
>[ 1000.881597] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76f00
>[ 1000.884597] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1000.886587] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1000.888596] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1000.890591] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1000.892582] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1000.894531] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1000.896558] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1000.898556] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1000.900564] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1000.902557] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1000.904553] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1000.906568] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1000.908555] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1000.910554] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1000.912552] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1000.914551] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1000.916552] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1000.918548] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1000.920465] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1000.922564] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1000.924557] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1000.926549] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1000.930546] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1000.932547] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1000.934552] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1000.938557] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1000.942545] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1000.956553] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.012523] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.014518] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.018515] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.020513] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.022526] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.024517] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.026512] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.028472] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.030510] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.032510] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.034515] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.036508] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.038519] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.040513] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.042505] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.044505] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.046503] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.048502] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.050510] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.052502] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.054499] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.056512] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.058498] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.060500] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.062508] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.064497] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.066496] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.068496] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.070497] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.072507] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.074501] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.076493] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.078492] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.080493] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0b40
>[ 1001.082496] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6600
>[ 1001.084502] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6540
>[ 1001.086498] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6600
>[ 1001.088506] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6540
>[ 1001.090501] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6600
>[ 1001.092494] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6540
>[ 1001.094493] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6600
>[ 1001.096495] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6540
>[ 1001.098492] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6600
>[ 1001.100498] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6540
>[ 1001.102491] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6600
>[ 1001.104488] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6540
>[ 1001.106501] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6600
>[ 1001.108487] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6540
>[ 1001.110487] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6600
>[ 1001.112487] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6540
>[ 1001.114482] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f6600
>[ 1001.116418] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76540
>[ 1001.118479] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76c00
>[ 1001.120478] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76540
>[ 1001.122493] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76c00
>[ 1001.124481] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76540
>[ 1001.126476] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76c00
>[ 1001.128473] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76540
>[ 1001.130475] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76c00
>[ 1001.132474] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76540
>[ 1001.134481] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76c00
>[ 1001.136473] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76540
>[ 1001.138482] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76c00
>[ 1001.140477] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.140546] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.142470] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.144466] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.146467] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.148465] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.150475] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.152466] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.154464] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.156477] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.158462] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.160464] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.162462] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.164460] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.166461] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.168458] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.170461] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.172472] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.174463] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0900
>[ 1001.736148] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9fac240
>[ 1001.742253] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.746250] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1001.752249] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.758247] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1001.762247] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.766243] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1001.770242] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.776241] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1001.780239] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.782238] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1001.786237] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.790241] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1001.792234] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.796233] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1001.800237] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.804231] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1001.810240] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.816227] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1001.822253] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.824227] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1001.832222] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1001.834223] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1001.844221] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1002.010160] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.018156] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1002.022170] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.024155] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1002.028106] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.032151] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1002.036146] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.040155] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1002.044143] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.050147] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1002.052141] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.058139] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1002.062093] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.070138] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1002.078134] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.098061] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1002.228086] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.236076] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1002.246071] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.252073] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f06c0
>[ 1002.255956] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9facf00
>[ 1002.260076] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9faccc0
>[ 1002.262074] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9facf00
>[ 1002.264069] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9faccc0
>[ 1002.268071] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9facf00
>[ 1002.272085] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9faccc0
>[ 1002.274075] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9facf00
>[ 1002.280067] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9faccc0
>[ 1002.284070] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9facf00
>[ 1002.292065] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76540
>[ 1002.298052] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76480
>[ 1002.310057] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76540
>[ 1002.312048] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76480
>[ 1002.491991] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.495981] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0540
>[ 1002.499986] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.501975] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0540
>[ 1002.503975] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.507975] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0540
>[ 1002.509974] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.511973] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0540
>[ 1002.513970] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.515972] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0540
>[ 1002.517969] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.519971] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0540
>[ 1002.521985] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.523976] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0540
>[ 1002.525974] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.527971] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0540
>[ 1002.529969] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.531972] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0540
>[ 1002.533973] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.535967] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0540
>[ 1002.537980] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.539972] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0540
>[ 1002.541964] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.543963] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0540
>[ 1002.545963] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.547962] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0540
>[ 1002.549970] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.551961] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0540
>[ 1002.553957] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.555968] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0c00
>[ 1002.557958] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.559959] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0c00
>[ 1002.561960] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.563956] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0c00
>[ 1002.565958] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.567952] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0c00
>[ 1002.569955] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.573959] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0c00
>[ 1002.575953] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.577951] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0c00
>[ 1002.581953] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.583954] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0c00
>[ 1002.585949] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.589954] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0c00
>[ 1002.593946] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.595943] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0c00
>[ 1002.607948] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9faccc0
>[ 1002.617937] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.619936] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.629932] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.631930] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.635929] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.645929] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.653924] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.655930] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.659922] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f00c0
>[ 1002.669927] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9fac6c0
>[ 1002.675918] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.679916] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.685912] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.691914] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.695910] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.697905] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.701872] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.705909] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.711915] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.713908] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.715903] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.719903] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.725908] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.731905] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.735893] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.739899] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.745893] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.749896] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.753887] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.757885] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.759885] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.765883] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.775881] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.777875] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.789886] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.791874] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.795769] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0840
>[ 1002.807758] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76300
>[ 1002.931827] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.935823] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0cc0
>[ 1002.937832] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.941823] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0cc0
>[ 1002.953836] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9fac900
>[ 1002.963769] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.967810] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0e40
>[ 1002.971823] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.981804] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0e40
>[ 1002.987818] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1002.989811] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0e40
>[ 1003.003820] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9facc00
>[ 1003.015795] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1003.023801] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0a80
>[ 1003.051789] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1003.269099] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0a80
>[ 1003.269645] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1003.269757] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0a80
>[ 1003.269882] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1003.270012] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0a80
>[ 1003.270182] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800b00f0300
>[ 1003.270444] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76600
>[ 1003.313297] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76b40
>[ 1003.313373] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c9e76600
>[ 1003.772926] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c9face40
>[ 1003.772942] [drm:intel_fbc_update] no output, disabling
>[ 1003.786786] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800b00f0780
>[ 1003.786798] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800b00f0480
>[ 1003.796142] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebcde0
>[ 1003.796145] [drm:drm_atomic_get_plane_state] Added [PLANE:17] ffff8800b00f09c0 state to ffff880306ebcde0
>[ 1003.796146] [drm:drm_atomic_check_only] checking ffff880306ebcde0
>[ 1003.796147] [drm:drm_atomic_commit] commiting ffff880306ebcde0
>[ 1003.796148] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebcde0
>[ 1003.796149] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebcde0
>[ 1003.796150] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebcde0
>[ 1003.796151] [drm:drm_atomic_get_plane_state] Added [PLANE:19] ffff8800b00f0300 state to ffff880306ebcde0
>[ 1003.796151] [drm:drm_atomic_check_only] checking ffff880306ebcde0
>[ 1003.796152] [drm:drm_atomic_commit] commiting ffff880306ebcde0
>[ 1003.796153] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebcde0
>[ 1003.796153] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebcde0
>[ 1003.796154] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebcde0
>[ 1003.796155] [drm:drm_atomic_get_plane_state] Added [PLANE:21] ffff8800b00f0a80 state to ffff880306ebcde0
>[ 1003.796155] [drm:drm_atomic_check_only] checking ffff880306ebcde0
>[ 1003.796155] [drm:drm_atomic_commit] commiting ffff880306ebcde0
>[ 1003.796156] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebcde0
>[ 1003.796156] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebcde0
>[ 1003.796157] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebcde0
>[ 1003.796158] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800b00f0e40 state to ffff880306ebcde0
>[ 1003.796158] [drm:drm_atomic_check_only] checking ffff880306ebcde0
>[ 1003.796159] [drm:drm_atomic_commit] commiting ffff880306ebcde0
>[ 1003.796159] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebcde0
>[ 1003.796160] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebcde0
>[ 1003.796161] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebcde0
>[ 1003.796161] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800b00f0780 state to ffff880306ebcde0
>[ 1003.796162] [drm:drm_atomic_check_only] checking ffff880306ebcde0
>[ 1003.796162] [drm:drm_atomic_commit] commiting ffff880306ebcde0
>[ 1003.796163] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebcde0
>[ 1003.796163] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebcde0
>[ 1003.796164] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebcde0
>[ 1003.796165] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff8800b00f0cc0 state to ffff880306ebcde0
>[ 1003.796165] [drm:drm_atomic_check_only] checking ffff880306ebcde0
>[ 1003.796166] [drm:drm_atomic_commit] commiting ffff880306ebcde0
>[ 1003.796166] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebcde0
>[ 1003.796167] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebcde0
>[ 1003.796167] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebcde0
>[ 1003.796168] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800b00f0840 state to ffff880306ebcde0
>[ 1003.796168] [drm:drm_atomic_check_only] checking ffff880306ebcde0
>[ 1003.796169] [drm:drm_atomic_commit] commiting ffff880306ebcde0
>[ 1003.796169] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebcde0
>[ 1003.796170] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebcde0
>[ 1003.796171] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebcde0
>[ 1003.796171] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800b00f0480 state to ffff880306ebcde0
>[ 1003.796172] [drm:drm_atomic_check_only] checking ffff880306ebcde0
>[ 1003.796172] [drm:drm_atomic_commit] commiting ffff880306ebcde0
>[ 1003.796173] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebcde0
>[ 1003.796173] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebcde0
>[ 1003.796174] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebcde0
>[ 1003.796174] [drm:drm_atomic_get_plane_state] Added [PLANE:29] ffff8800b00f00c0 state to ffff880306ebcde0
>[ 1003.796175] [drm:drm_atomic_check_only] checking ffff880306ebcde0
>[ 1003.796175] [drm:drm_atomic_commit] commiting ffff880306ebcde0
>[ 1003.796176] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebcde0
>[ 1003.796176] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebcde0
>[ 1003.796178] [drm:intel_crtc_set_config] [CRTC:20] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.796180] [drm:intel_set_config_compute_mode_changes] crtc has no fb, will flip
>[ 1003.796182] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=1
>[ 1003.796183] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.796185] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 1003.796186] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[ 1003.796187] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 1003.796189] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz
>[ 1003.796190] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[ 1003.796191] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000
>[ 1003.796192] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 1003.796193] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 1003.796194] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[ 1003.796194] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 1003.796195] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.796196] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64
>[ 1003.796196] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.796197] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.796197] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.796199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[ 1003.796199] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.796200] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[ 1003.796201] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9
>[ 1003.796201] [drm:intel_dump_pipe_config] port clock: 270000
>[ 1003.796202] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.796202] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.796203] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.796203] [drm:intel_dump_pipe_config] ips: 1
>[ 1003.796204] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.796205] [drm:drm_atomic_set_fb_for_plane] Set [FB:53] for plane state ffff8800b00f0c00
>[ 1003.796216] [drm:ironlake_update_primary_plane] Writing base 00226000 00000000 0 0 7680
>[ 1003.796219] [drm:intel_fbc_update] disabled per chip default
>[ 1003.803438] [drm:intel_crtc_set_config] [CRTC:24] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.803442] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[ 1003.803444] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=1, fb_changed=1
>[ 1003.803445] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[ 1003.803445] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.803446] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.803447] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[ 1003.803448] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[ 1003.803450] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 1003.803452] [drm:connected_sink_compute_bpp] [CONNECTOR:52:DP-3] checking for sink bpp constrains
>[ 1003.803455] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 1003.803456] [drm:intel_dump_pipe_config] [CRTC:24][modeset] config for pipe B
>[ 1003.803456] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 1003.803457] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 1003.803458] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.803459] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1730150, gmch_n: 8388608, link_m: 288358, link_n: 1048576, tu: 14
>[ 1003.803460] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.803461] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.803462] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.803464] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.803464] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.803466] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.803467] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1003.803467] [drm:intel_dump_pipe_config] port clock: 540000
>[ 1003.803468] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.803469] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.803470] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.803471] [drm:intel_dump_pipe_config] ips: 0
>[ 1003.803471] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.803479] [drm:drm_atomic_set_fb_for_plane] Set [FB:53] for plane state ffff8800b00f09c0
>[ 1003.803497] [drm:intel_mst_pre_enable_dp] 0
>[ 1003.836436] [drm:drm_dp_dpcd_access] too many retries, giving up
>[ 1003.836616] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[ 1003.853410] [drm:intel_dp_start_link_train] clock recovery OK
>[ 1003.874290] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[ 1003.874488] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for 532 14
>[ 1003.875109] [drm:intel_mst_enable_dp] 1
>[ 1003.881078] [drm:drm_dp_update_payload_part2] payload 0 1
>[ 1003.882447] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1003.882448] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1003.882470] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1003.882970] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1003.884003] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1003.884004] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1003.920015] [drm:ironlake_update_primary_plane] Writing base 00226000 00000000 0 0 7680
>[ 1003.920018] [drm:intel_fbc_update] more than one pipe active, disabling compression
>[ 1003.920022] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[ 1003.920027] [drm:intel_connector_check_state] [CONNECTOR:52:DP-3]
>[ 1003.920028] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[ 1003.920029] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[ 1003.920030] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[ 1003.920031] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[ 1003.920031] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[ 1003.920032] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[ 1003.920033] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[ 1003.920034] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[ 1003.920035] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[ 1003.920035] [drm:check_crtc_state] [CRTC:20]
>[ 1003.920042] [drm:check_crtc_state] [CRTC:24]
>[ 1003.920047] [drm:check_crtc_state] [CRTC:28]
>[ 1003.920049] [drm:check_shared_dpll_state] WRPLL 1
>[ 1003.920050] [drm:check_shared_dpll_state] WRPLL 2
>[ 1003.920054] [drm:intel_crtc_set_config] [CRTC:28] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.920056] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[ 1003.920057] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:28], mode_changed=1, fb_changed=0
>[ 1003.920058] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch
>[ 1003.920059] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.920060] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.920061] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.920062] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch
>[ 1003.920063] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch
>[ 1003.920064] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[ 1003.920066] [drm:connected_sink_compute_bpp] [CONNECTOR:55:DP-4] checking for sink bpp constrains
>[ 1003.920069] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 1003.920070] [drm:intel_dump_pipe_config] [CRTC:28][modeset] config for pipe C
>[ 1003.920070] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[ 1003.920071] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 1003.920072] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.920073] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1730150, gmch_n: 8388608, link_m: 288358, link_n: 1048576, tu: 14
>[ 1003.920074] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.920075] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.920076] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.920078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.920078] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.920080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.920081] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1003.920082] [drm:intel_dump_pipe_config] port clock: 540000
>[ 1003.920082] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.920083] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.920084] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.920084] [drm:intel_dump_pipe_config] ips: 0
>[ 1003.920085] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.920092] [drm:drm_atomic_set_fb_for_plane] Set [FB:53] for plane state ffff8800b00f0e40
>[ 1003.920108] [drm:intel_mst_pre_enable_dp] 1
>[ 1003.920110] [drm:drm_dp_mst_allocate_vcpi] initing vcpi for 532 14
>[ 1003.920728] [drm:intel_mst_enable_dp] 2
>[ 1003.924468] [drm:drm_dp_update_payload_part2] payload 0 2
>[ 1003.924469] [drm:drm_dp_update_payload_part2] payload 1 1
>[ 1003.925845] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1003.925846] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1003.925903] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1003.926401] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1003.927414] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1003.927415] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1003.930910] [drm:ironlake_update_primary_plane] Writing base 00226000 00000000 0 0 7680
>[ 1003.930918] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[ 1003.930922] [drm:intel_connector_check_state] [CONNECTOR:52:DP-3]
>[ 1003.930923] [drm:intel_connector_check_state] [CONNECTOR:55:DP-4]
>[ 1003.930923] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[ 1003.930924] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[ 1003.930926] [drm:check_encoder_state] [ENCODER:40:DP MST-40]
>[ 1003.930926] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[ 1003.930927] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[ 1003.930927] [drm:check_encoder_state] [ENCODER:45:TMDS-45]
>[ 1003.930929] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[ 1003.930929] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[ 1003.930930] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[ 1003.930931] [drm:check_crtc_state] [CRTC:20]
>[ 1003.930937] [drm:check_crtc_state] [CRTC:24]
>[ 1003.930942] [drm:check_crtc_state] [CRTC:28]
>[ 1003.930946] [drm:check_shared_dpll_state] WRPLL 1
>[ 1003.930947] [drm:check_shared_dpll_state] WRPLL 2
>[ 1003.930955] [drm:intel_crtc_set_config] [CRTC:20] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.930957] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 1003.930959] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.930960] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.930960] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.930962] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 1003.930964] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[ 1003.930965] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 1003.930967] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz
>[ 1003.930968] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[ 1003.930969] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000
>[ 1003.930970] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 1003.930971] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 1003.930972] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[ 1003.930973] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 1003.930974] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.930975] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64
>[ 1003.930976] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.930976] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.930977] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.930979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[ 1003.930979] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.930981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[ 1003.930982] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9
>[ 1003.930983] [drm:intel_dump_pipe_config] port clock: 270000
>[ 1003.930983] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.930984] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.930985] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.930985] [drm:intel_dump_pipe_config] ips: 1
>[ 1003.930986] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.930987] [drm:intel_crtc_set_config] [CRTC:24] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.930989] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=0, fb_changed=0
>[ 1003.930990] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.930991] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.930991] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.930993] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 1003.930994] [drm:connected_sink_compute_bpp] [CONNECTOR:52:DP-3] checking for sink bpp constrains
>[ 1003.930995] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 1003.930996] [drm:intel_dump_pipe_config] [CRTC:24][modeset] config for pipe B
>[ 1003.930996] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 1003.930997] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 1003.930998] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.930999] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1730150, gmch_n: 8388608, link_m: 288358, link_n: 1048576, tu: 14
>[ 1003.931000] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.931000] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.931001] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.931002] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.931002] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.931004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.931005] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1003.931005] [drm:intel_dump_pipe_config] port clock: 540000
>[ 1003.931006] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.931007] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.931007] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.931008] [drm:intel_dump_pipe_config] ips: 0
>[ 1003.931008] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.931009] [drm:intel_crtc_set_config] [CRTC:28] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.931010] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:28], mode_changed=0, fb_changed=0
>[ 1003.931011] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.931012] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.931013] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.931014] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[ 1003.931015] [drm:connected_sink_compute_bpp] [CONNECTOR:55:DP-4] checking for sink bpp constrains
>[ 1003.931016] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 1003.931016] [drm:intel_dump_pipe_config] [CRTC:28][modeset] config for pipe C
>[ 1003.931017] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[ 1003.931017] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 1003.931018] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.931019] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1730150, gmch_n: 8388608, link_m: 288358, link_n: 1048576, tu: 14
>[ 1003.931020] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.931020] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.931021] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.931022] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.931023] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.931024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.931025] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1003.931026] [drm:intel_dump_pipe_config] port clock: 540000
>[ 1003.931026] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.931027] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.931027] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.931028] [drm:intel_dump_pipe_config] ips: 0
>[ 1003.931028] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.931038] [drm:intel_crtc_set_config] [CRTC:20] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.931039] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 1003.931040] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.931040] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.931041] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.931042] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 1003.931043] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[ 1003.931044] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 1003.931045] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz
>[ 1003.931046] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[ 1003.931046] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000
>[ 1003.931047] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 1003.931048] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 1003.931048] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[ 1003.931049] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 1003.931049] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.931050] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64
>[ 1003.931051] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.931052] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.931052] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.931053] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[ 1003.931054] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.931055] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[ 1003.931056] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9
>[ 1003.931057] [drm:intel_dump_pipe_config] port clock: 270000
>[ 1003.931057] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.931058] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.931058] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.931059] [drm:intel_dump_pipe_config] ips: 1
>[ 1003.931059] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.931060] [drm:intel_crtc_set_config] [CRTC:24] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.931061] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=0, fb_changed=0
>[ 1003.931062] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.931063] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.931063] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.931064] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 1003.931065] [drm:connected_sink_compute_bpp] [CONNECTOR:52:DP-3] checking for sink bpp constrains
>[ 1003.931066] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 1003.931067] [drm:intel_dump_pipe_config] [CRTC:24][modeset] config for pipe B
>[ 1003.931067] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 1003.931068] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 1003.931068] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.931069] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1730150, gmch_n: 8388608, link_m: 288358, link_n: 1048576, tu: 14
>[ 1003.931070] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.931071] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.931071] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.931072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.931073] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.931074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.931075] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1003.931076] [drm:intel_dump_pipe_config] port clock: 540000
>[ 1003.931076] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.931077] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.931077] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.931078] [drm:intel_dump_pipe_config] ips: 0
>[ 1003.931078] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.931079] [drm:intel_crtc_set_config] [CRTC:28] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.931080] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:28], mode_changed=0, fb_changed=0
>[ 1003.931081] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.931081] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.931082] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.931083] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[ 1003.931084] [drm:connected_sink_compute_bpp] [CONNECTOR:55:DP-4] checking for sink bpp constrains
>[ 1003.931085] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 1003.931085] [drm:intel_dump_pipe_config] [CRTC:28][modeset] config for pipe C
>[ 1003.931086] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[ 1003.931086] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 1003.931087] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.931088] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1730150, gmch_n: 8388608, link_m: 288358, link_n: 1048576, tu: 14
>[ 1003.931089] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.931089] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.931090] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.931091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.931091] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.931093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.931094] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1003.931094] [drm:intel_dump_pipe_config] port clock: 540000
>[ 1003.931095] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.931095] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.931096] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.931097] [drm:intel_dump_pipe_config] ips: 0
>[ 1003.931097] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.938417] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebc7e0
>[ 1003.938422] [drm:drm_atomic_get_plane_state] Added [PLANE:17] ffff8800b00f0840 state to ffff880306ebc7e0
>[ 1003.938425] [drm:drm_atomic_get_crtc_state] Added [CRTC:20] ffff88030dd6fc00 state to ffff880306ebc7e0
>[ 1003.938426] [drm:drm_atomic_check_only] checking ffff880306ebc7e0
>[ 1003.938430] [drm:drm_atomic_commit] commiting ffff880306ebc7e0
>[ 1003.938442] [drm:ironlake_update_primary_plane] Writing base 00226000 00000000 0 0 7680
>[ 1003.938447] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebc7e0
>[ 1003.938449] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebc7e0
>[ 1003.938451] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebc7e0
>[ 1003.938453] [drm:drm_atomic_get_plane_state] Added [PLANE:19] ffff8800b00f0c00 state to ffff880306ebc7e0
>[ 1003.938455] [drm:drm_atomic_check_only] checking ffff880306ebc7e0
>[ 1003.938456] [drm:drm_atomic_commit] commiting ffff880306ebc7e0
>[ 1003.938458] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebc7e0
>[ 1003.938459] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebc7e0
>[ 1003.938461] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebc7e0
>[ 1003.938463] [drm:drm_atomic_get_plane_state] Added [PLANE:21] ffff8800b00f0300 state to ffff880306ebc7e0
>[ 1003.938464] [drm:drm_atomic_check_only] checking ffff880306ebc7e0
>[ 1003.938466] [drm:drm_atomic_commit] commiting ffff880306ebc7e0
>[ 1003.938467] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebc7e0
>[ 1003.938469] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebc7e0
>[ 1003.938471] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebc7e0
>[ 1003.938473] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800b00f0a80 state to ffff880306ebc7e0
>[ 1003.938475] [drm:drm_atomic_get_crtc_state] Added [CRTC:24] ffff88030dd6fc00 state to ffff880306ebc7e0
>[ 1003.938476] [drm:drm_atomic_check_only] checking ffff880306ebc7e0
>[ 1003.938478] [drm:drm_atomic_commit] commiting ffff880306ebc7e0
>[ 1003.938484] [drm:ironlake_update_primary_plane] Writing base 00226000 00000000 0 0 7680
>[ 1003.938487] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebc7e0
>[ 1003.938489] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebc7e0
>[ 1003.938491] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebc7e0
>[ 1003.938493] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800b00f09c0 state to ffff880306ebc7e0
>[ 1003.938494] [drm:drm_atomic_check_only] checking ffff880306ebc7e0
>[ 1003.938496] [drm:drm_atomic_commit] commiting ffff880306ebc7e0
>[ 1003.938497] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebc7e0
>[ 1003.938499] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebc7e0
>[ 1003.938501] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebc7e0
>[ 1003.938502] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff8800b00f0780 state to ffff880306ebc7e0
>[ 1003.938504] [drm:drm_atomic_check_only] checking ffff880306ebc7e0
>[ 1003.938505] [drm:drm_atomic_commit] commiting ffff880306ebc7e0
>[ 1003.938507] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebc7e0
>[ 1003.938508] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebc7e0
>[ 1003.938510] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebc7e0
>[ 1003.938512] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800b00f0cc0 state to ffff880306ebc7e0
>[ 1003.938514] [drm:drm_atomic_get_crtc_state] Added [CRTC:28] ffff88030dd6fc00 state to ffff880306ebc7e0
>[ 1003.938515] [drm:drm_atomic_check_only] checking ffff880306ebc7e0
>[ 1003.938517] [drm:drm_atomic_commit] commiting ffff880306ebc7e0
>[ 1003.938523] [drm:ironlake_update_primary_plane] Writing base 00226000 00000000 0 0 7680
>[ 1003.938526] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebc7e0
>[ 1003.938527] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebc7e0
>[ 1003.938529] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebc7e0
>[ 1003.938531] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800b00f0e40 state to ffff880306ebc7e0
>[ 1003.938532] [drm:drm_atomic_check_only] checking ffff880306ebc7e0
>[ 1003.938534] [drm:drm_atomic_commit] commiting ffff880306ebc7e0
>[ 1003.938535] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebc7e0
>[ 1003.938537] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebc7e0
>[ 1003.938539] [drm:drm_atomic_state_alloc] Allocate atomic state ffff880306ebc7e0
>[ 1003.938541] [drm:drm_atomic_get_plane_state] Added [PLANE:29] ffff8800b00f0480 state to ffff880306ebc7e0
>[ 1003.938542] [drm:drm_atomic_check_only] checking ffff880306ebc7e0
>[ 1003.938544] [drm:drm_atomic_commit] commiting ffff880306ebc7e0
>[ 1003.938545] [drm:drm_atomic_state_clear] Clearing atomic state ffff880306ebc7e0
>[ 1003.938547] [drm:drm_atomic_state_free] Freeing atomic state ffff880306ebc7e0
>[ 1003.938549] [drm:intel_crtc_set_config] [CRTC:20] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.938553] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 1003.938555] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.938557] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.938558] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.938561] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 1003.938563] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[ 1003.938565] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 1003.938568] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz
>[ 1003.938570] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[ 1003.938571] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000
>[ 1003.938573] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 1003.938575] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 1003.938576] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[ 1003.938578] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 1003.938580] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.938582] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64
>[ 1003.938584] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.938585] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.938586] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.938589] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[ 1003.938591] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.938593] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[ 1003.938596] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9
>[ 1003.938597] [drm:intel_dump_pipe_config] port clock: 270000
>[ 1003.938599] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.938600] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.938602] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.938603] [drm:intel_dump_pipe_config] ips: 1
>[ 1003.938604] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.938607] [drm:intel_crtc_set_config] [CRTC:24] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.938609] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=0, fb_changed=0
>[ 1003.938610] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.938612] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.938614] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.938616] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 1003.938617] [drm:connected_sink_compute_bpp] [CONNECTOR:52:DP-3] checking for sink bpp constrains
>[ 1003.938620] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 1003.938621] [drm:intel_dump_pipe_config] [CRTC:24][modeset] config for pipe B
>[ 1003.938622] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 1003.938623] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 1003.938625] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.938627] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1730150, gmch_n: 8388608, link_m: 288358, link_n: 1048576, tu: 14
>[ 1003.938629] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.938630] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.938631] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.938634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.938635] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.938638] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.938640] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1003.938641] [drm:intel_dump_pipe_config] port clock: 540000
>[ 1003.938643] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.938644] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.938646] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.938647] [drm:intel_dump_pipe_config] ips: 0
>[ 1003.938648] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.938650] [drm:intel_crtc_set_config] [CRTC:28] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.938652] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:28], mode_changed=0, fb_changed=0
>[ 1003.938654] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.938655] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.938657] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.938659] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[ 1003.938660] [drm:connected_sink_compute_bpp] [CONNECTOR:55:DP-4] checking for sink bpp constrains
>[ 1003.938662] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 1003.938664] [drm:intel_dump_pipe_config] [CRTC:28][modeset] config for pipe C
>[ 1003.938665] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[ 1003.938666] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 1003.938668] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.938670] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1730150, gmch_n: 8388608, link_m: 288358, link_n: 1048576, tu: 14
>[ 1003.938672] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.938673] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.938674] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.938677] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.938678] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.938680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.938683] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1003.938684] [drm:intel_dump_pipe_config] port clock: 540000
>[ 1003.938685] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.938687] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.938688] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.938689] [drm:intel_dump_pipe_config] ips: 0
>[ 1003.938691] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.942098] [drm:i915_gem_open] 
>[ 1003.942108] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[8] ENCODERS[9]
>[ 1003.942118] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802fe7f4c00
>[ 1003.942120] [drm:drm_atomic_get_plane_state] Added [PLANE:17] ffff88030e1f4000 state to ffff8802fe7f4c00
>[ 1003.942121] [drm:drm_atomic_get_crtc_state] Added [CRTC:20] ffff88030d6a5400 state to ffff8802fe7f4c00
>[ 1003.942122] [drm:drm_atomic_check_only] checking ffff8802fe7f4c00
>[ 1003.942125] [drm:drm_atomic_commit] commiting ffff8802fe7f4c00
>[ 1003.942134] [drm:ironlake_update_primary_plane] Writing base 00226000 00000000 0 0 7680
>[ 1003.942137] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802fe7f4c00
>[ 1003.942139] [drm:drm_atomic_state_free] Freeing atomic state ffff8802fe7f4c00
>[ 1003.942140] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802fe7f4c00
>[ 1003.942141] [drm:drm_atomic_get_plane_state] Added [PLANE:19] ffff88030e1f40c0 state to ffff8802fe7f4c00
>[ 1003.942142] [drm:drm_atomic_check_only] checking ffff8802fe7f4c00
>[ 1003.942143] [drm:drm_atomic_commit] commiting ffff8802fe7f4c00
>[ 1003.942144] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802fe7f4c00
>[ 1003.942145] [drm:drm_atomic_state_free] Freeing atomic state ffff8802fe7f4c00
>[ 1003.942146] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802fe7f4c00
>[ 1003.942148] [drm:drm_atomic_get_plane_state] Added [PLANE:21] ffff88030e1f4a80 state to ffff8802fe7f4c00
>[ 1003.942148] [drm:drm_atomic_check_only] checking ffff8802fe7f4c00
>[ 1003.942149] [drm:drm_atomic_commit] commiting ffff8802fe7f4c00
>[ 1003.942150] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802fe7f4c00
>[ 1003.942151] [drm:drm_atomic_state_free] Freeing atomic state ffff8802fe7f4c00
>[ 1003.942152] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802fe7f4c00
>[ 1003.942153] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff88030e1f4c00 state to ffff8802fe7f4c00
>[ 1003.942154] [drm:drm_atomic_get_crtc_state] Added [CRTC:24] ffff88030d6a5400 state to ffff8802fe7f4c00
>[ 1003.942155] [drm:drm_atomic_check_only] checking ffff8802fe7f4c00
>[ 1003.942156] [drm:drm_atomic_commit] commiting ffff8802fe7f4c00
>[ 1003.942161] [drm:ironlake_update_primary_plane] Writing base 00226000 00000000 0 0 7680
>[ 1003.942163] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802fe7f4c00
>[ 1003.942165] [drm:drm_atomic_state_free] Freeing atomic state ffff8802fe7f4c00
>[ 1003.942166] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802fe7f4c00
>[ 1003.942167] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff88030e1f4780 state to ffff8802fe7f4c00
>[ 1003.942168] [drm:drm_atomic_check_only] checking ffff8802fe7f4c00
>[ 1003.942169] [drm:drm_atomic_commit] commiting ffff8802fe7f4c00
>[ 1003.942170] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802fe7f4c00
>[ 1003.942171] [drm:drm_atomic_state_free] Freeing atomic state ffff8802fe7f4c00
>[ 1003.942172] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802fe7f4c00
>[ 1003.942173] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff88030e1f4f00 state to ffff8802fe7f4c00
>[ 1003.942174] [drm:drm_atomic_check_only] checking ffff8802fe7f4c00
>[ 1003.942175] [drm:drm_atomic_commit] commiting ffff8802fe7f4c00
>[ 1003.942176] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802fe7f4c00
>[ 1003.942176] [drm:drm_atomic_state_free] Freeing atomic state ffff8802fe7f4c00
>[ 1003.942177] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802fe7f4c00
>[ 1003.942179] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff88030e1f4e40 state to ffff8802fe7f4c00
>[ 1003.942180] [drm:drm_atomic_get_crtc_state] Added [CRTC:28] ffff88030d6a5400 state to ffff8802fe7f4c00
>[ 1003.942181] [drm:drm_atomic_check_only] checking ffff8802fe7f4c00
>[ 1003.942182] [drm:drm_atomic_commit] commiting ffff8802fe7f4c00
>[ 1003.942186] [drm:ironlake_update_primary_plane] Writing base 00226000 00000000 0 0 7680
>[ 1003.942188] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802fe7f4c00
>[ 1003.942189] [drm:drm_atomic_state_free] Freeing atomic state ffff8802fe7f4c00
>[ 1003.942191] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802fe7f4c00
>[ 1003.942192] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff88030e1f4cc0 state to ffff8802fe7f4c00
>[ 1003.942193] [drm:drm_atomic_check_only] checking ffff8802fe7f4c00
>[ 1003.942194] [drm:drm_atomic_commit] commiting ffff8802fe7f4c00
>[ 1003.942195] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802fe7f4c00
>[ 1003.942196] [drm:drm_atomic_state_free] Freeing atomic state ffff8802fe7f4c00
>[ 1003.942197] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802fe7f4c00
>[ 1003.942198] [drm:drm_atomic_get_plane_state] Added [PLANE:29] ffff88030e1f43c0 state to ffff8802fe7f4c00
>[ 1003.942199] [drm:drm_atomic_check_only] checking ffff8802fe7f4c00
>[ 1003.942200] [drm:drm_atomic_commit] commiting ffff8802fe7f4c00
>[ 1003.942200] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802fe7f4c00
>[ 1003.942201] [drm:drm_atomic_state_free] Freeing atomic state ffff8802fe7f4c00
>[ 1003.942203] [drm:intel_crtc_set_config] [CRTC:20] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.942205] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 1003.942207] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.942208] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.942209] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.942211] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 1003.942212] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[ 1003.942213] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 1003.942215] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz
>[ 1003.942217] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[ 1003.942218] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000
>[ 1003.942219] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 1003.942221] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 1003.942222] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[ 1003.942223] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 1003.942224] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.942226] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64
>[ 1003.942227] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.942228] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.942228] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.942230] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[ 1003.942231] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.942232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[ 1003.942234] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9
>[ 1003.942235] [drm:intel_dump_pipe_config] port clock: 270000
>[ 1003.942236] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.942237] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.942238] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.942238] [drm:intel_dump_pipe_config] ips: 1
>[ 1003.942239] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.942241] [drm:intel_crtc_set_config] [CRTC:24] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.942242] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=0, fb_changed=0
>[ 1003.942243] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.942244] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.942245] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.942246] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 1003.942247] [drm:connected_sink_compute_bpp] [CONNECTOR:52:DP-3] checking for sink bpp constrains
>[ 1003.942249] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 1003.942250] [drm:intel_dump_pipe_config] [CRTC:24][modeset] config for pipe B
>[ 1003.942251] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 1003.942252] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 1003.942253] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.942254] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1730150, gmch_n: 8388608, link_m: 288358, link_n: 1048576, tu: 14
>[ 1003.942255] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.942256] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.942257] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.942258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.942259] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.942260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.942261] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1003.942262] [drm:intel_dump_pipe_config] port clock: 540000
>[ 1003.942263] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.942264] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.942265] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.942266] [drm:intel_dump_pipe_config] ips: 0
>[ 1003.942266] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.942267] [drm:intel_crtc_set_config] [CRTC:28] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.942269] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:28], mode_changed=0, fb_changed=0
>[ 1003.942270] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.942270] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.942271] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.942273] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[ 1003.942274] [drm:connected_sink_compute_bpp] [CONNECTOR:55:DP-4] checking for sink bpp constrains
>[ 1003.942275] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 1003.942276] [drm:intel_dump_pipe_config] [CRTC:28][modeset] config for pipe C
>[ 1003.942277] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[ 1003.942277] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 1003.942278] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.942280] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1730150, gmch_n: 8388608, link_m: 288358, link_n: 1048576, tu: 14
>[ 1003.942281] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.942282] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.942283] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.942284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.942285] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.942286] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.942287] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1003.942288] [drm:intel_dump_pipe_config] port clock: 540000
>[ 1003.942289] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.942290] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.942291] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.942291] [drm:intel_dump_pipe_config] ips: 0
>[ 1003.942292] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.945562] [drm:i915_gem_open] 
>[ 1003.945592] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802c8d477e0
>[ 1003.945594] [drm:drm_atomic_get_plane_state] Added [PLANE:17] ffff8800b00f6e40 state to ffff8802c8d477e0
>[ 1003.945596] [drm:drm_atomic_get_crtc_state] Added [CRTC:20] ffff8800c77be800 state to ffff8802c8d477e0
>[ 1003.945597] [drm:drm_atomic_check_only] checking ffff8802c8d477e0
>[ 1003.945600] [drm:drm_atomic_commit] commiting ffff8802c8d477e0
>[ 1003.945610] [drm:ironlake_update_primary_plane] Writing base 00226000 00000000 0 0 7680
>[ 1003.945614] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802c8d477e0
>[ 1003.945615] [drm:drm_atomic_state_free] Freeing atomic state ffff8802c8d477e0
>[ 1003.945616] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802c8d477e0
>[ 1003.945618] [drm:drm_atomic_get_plane_state] Added [PLANE:19] ffff8800b00f6540 state to ffff8802c8d477e0
>[ 1003.945618] [drm:drm_atomic_check_only] checking ffff8802c8d477e0
>[ 1003.945619] [drm:drm_atomic_commit] commiting ffff8802c8d477e0
>[ 1003.945621] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802c8d477e0
>[ 1003.945622] [drm:drm_atomic_state_free] Freeing atomic state ffff8802c8d477e0
>[ 1003.945623] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802c8d477e0
>[ 1003.945624] [drm:drm_atomic_get_plane_state] Added [PLANE:21] ffff8800b00f6180 state to ffff8802c8d477e0
>[ 1003.945625] [drm:drm_atomic_check_only] checking ffff8802c8d477e0
>[ 1003.945626] [drm:drm_atomic_commit] commiting ffff8802c8d477e0
>[ 1003.945627] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802c8d477e0
>[ 1003.945628] [drm:drm_atomic_state_free] Freeing atomic state ffff8802c8d477e0
>[ 1003.945629] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802c8d477e0
>[ 1003.945630] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800b00f60c0 state to ffff8802c8d477e0
>[ 1003.945632] [drm:drm_atomic_get_crtc_state] Added [CRTC:24] ffff8800c77be800 state to ffff8802c8d477e0
>[ 1003.945632] [drm:drm_atomic_check_only] checking ffff8802c8d477e0
>[ 1003.945634] [drm:drm_atomic_commit] commiting ffff8802c8d477e0
>[ 1003.945638] [drm:ironlake_update_primary_plane] Writing base 00226000 00000000 0 0 7680
>[ 1003.945640] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802c8d477e0
>[ 1003.945641] [drm:drm_atomic_state_free] Freeing atomic state ffff8802c8d477e0
>[ 1003.945642] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802c8d477e0
>[ 1003.945644] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800b00f6900 state to ffff8802c8d477e0
>[ 1003.945644] [drm:drm_atomic_check_only] checking ffff8802c8d477e0
>[ 1003.945645] [drm:drm_atomic_commit] commiting ffff8802c8d477e0
>[ 1003.945646] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802c8d477e0
>[ 1003.945647] [drm:drm_atomic_state_free] Freeing atomic state ffff8802c8d477e0
>[ 1003.945648] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802c8d477e0
>[ 1003.945649] [drm:drm_atomic_get_plane_state] Added [PLANE:25] ffff8800b00f6600 state to ffff8802c8d477e0
>[ 1003.945650] [drm:drm_atomic_check_only] checking ffff8802c8d477e0
>[ 1003.945651] [drm:drm_atomic_commit] commiting ffff8802c8d477e0
>[ 1003.945652] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802c8d477e0
>[ 1003.945653] [drm:drm_atomic_state_free] Freeing atomic state ffff8802c8d477e0
>[ 1003.945655] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802c8d477e0
>[ 1003.945656] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800b00f6780 state to ffff8802c8d477e0
>[ 1003.945657] [drm:drm_atomic_get_crtc_state] Added [CRTC:28] ffff8800c77be800 state to ffff8802c8d477e0
>[ 1003.945658] [drm:drm_atomic_check_only] checking ffff8802c8d477e0
>[ 1003.945659] [drm:drm_atomic_commit] commiting ffff8802c8d477e0
>[ 1003.945663] [drm:ironlake_update_primary_plane] Writing base 00226000 00000000 0 0 7680
>[ 1003.945665] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802c8d477e0
>[ 1003.945666] [drm:drm_atomic_state_free] Freeing atomic state ffff8802c8d477e0
>[ 1003.945667] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802c8d477e0
>[ 1003.945669] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800b00f6480 state to ffff8802c8d477e0
>[ 1003.945669] [drm:drm_atomic_check_only] checking ffff8802c8d477e0
>[ 1003.945670] [drm:drm_atomic_commit] commiting ffff8802c8d477e0
>[ 1003.945671] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802c8d477e0
>[ 1003.945672] [drm:drm_atomic_state_free] Freeing atomic state ffff8802c8d477e0
>[ 1003.945673] [drm:drm_atomic_state_alloc] Allocate atomic state ffff8802c8d477e0
>[ 1003.945674] [drm:drm_atomic_get_plane_state] Added [PLANE:29] ffff8800b00f6f00 state to ffff8802c8d477e0
>[ 1003.945675] [drm:drm_atomic_check_only] checking ffff8802c8d477e0
>[ 1003.945676] [drm:drm_atomic_commit] commiting ffff8802c8d477e0
>[ 1003.945677] [drm:drm_atomic_state_clear] Clearing atomic state ffff8802c8d477e0
>[ 1003.945678] [drm:drm_atomic_state_free] Freeing atomic state ffff8802c8d477e0
>[ 1003.945680] [drm:intel_crtc_set_config] [CRTC:20] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.945683] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[ 1003.945684] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.945685] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.945686] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.945688] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 1003.945690] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[ 1003.945691] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 1003.945693] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz
>[ 1003.945695] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[ 1003.945695] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000
>[ 1003.945697] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 1003.945699] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 1003.945700] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[ 1003.945701] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 1003.945702] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.945703] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64
>[ 1003.945704] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.945705] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.945706] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.945708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[ 1003.945708] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.945710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[ 1003.945712] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9
>[ 1003.945713] [drm:intel_dump_pipe_config] port clock: 270000
>[ 1003.945714] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.945715] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.945716] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.945717] [drm:intel_dump_pipe_config] ips: 1
>[ 1003.945717] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.945719] [drm:intel_crtc_set_config] [CRTC:24] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.945720] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=0, fb_changed=0
>[ 1003.945721] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.945722] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.945723] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.945725] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 1003.945726] [drm:connected_sink_compute_bpp] [CONNECTOR:52:DP-3] checking for sink bpp constrains
>[ 1003.945727] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 1003.945728] [drm:intel_dump_pipe_config] [CRTC:24][modeset] config for pipe B
>[ 1003.945729] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 1003.945730] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 1003.945731] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.945732] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1730150, gmch_n: 8388608, link_m: 288358, link_n: 1048576, tu: 14
>[ 1003.945733] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.945734] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.945735] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.945736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.945737] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.945738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.945740] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1003.945741] [drm:intel_dump_pipe_config] port clock: 540000
>[ 1003.945742] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.945743] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.945744] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.945744] [drm:intel_dump_pipe_config] ips: 0
>[ 1003.945745] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.945746] [drm:intel_crtc_set_config] [CRTC:28] [FB:53] #connectors=1 (x y) (0 0)
>[ 1003.945747] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:28], mode_changed=0, fb_changed=0
>[ 1003.945749] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.945749] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.945750] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.945751] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[ 1003.945753] [drm:connected_sink_compute_bpp] [CONNECTOR:55:DP-4] checking for sink bpp constrains
>[ 1003.945754] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 1003.945755] [drm:intel_dump_pipe_config] [CRTC:28][modeset] config for pipe C
>[ 1003.945755] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[ 1003.945756] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 1003.945757] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.945758] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1730150, gmch_n: 8388608, link_m: 288358, link_n: 1048576, tu: 14
>[ 1003.945759] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.945760] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.945761] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.945762] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.945763] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.945764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1003.945765] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1003.945766] [drm:intel_dump_pipe_config] port clock: 540000
>[ 1003.945767] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.945768] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.945769] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.945769] [drm:intel_dump_pipe_config] ips: 0
>[ 1003.945770] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.948409] [drm:i915_gem_open] 
>[ 1003.948417] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[8] ENCODERS[9]
>[ 1003.948569] [drm:i915_gem_open] 
>[ 1003.948576] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[8] ENCODERS[9]
>[ 1003.948578] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[8] ENCODERS[9]
>[ 1003.948745] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[8] ENCODERS[9]
>[ 1003.948754] [drm:drm_mode_addfb2] [FB:87]
>[ 1003.948832] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[8] ENCODERS[9]
>[ 1003.948834] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[8] ENCODERS[9]
>[ 1003.948888] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[ 1003.948894] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[ 1003.948988] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[ 1003.948991] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[ 1003.949010] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[ 1003.949012] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[ 1003.949032] [drm:drm_mode_getconnector] [CONNECTOR:46:?]
>[ 1003.949034] [drm:drm_mode_getconnector] [CONNECTOR:46:?]
>[ 1003.949053] [drm:drm_mode_getconnector] [CONNECTOR:50:?]
>[ 1003.949055] [drm:drm_mode_getconnector] [CONNECTOR:50:?]
>[ 1003.949074] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[ 1003.949077] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[ 1003.949079] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[ 1003.949105] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[ 1003.949108] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[ 1003.949110] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[ 1003.949133] [drm:drm_mode_getconnector] [CONNECTOR:57:?]
>[ 1003.949134] [drm:drm_mode_getconnector] [CONNECTOR:57:?]
>[ 1003.949137] [drm:drm_mode_getconnector] [CONNECTOR:57:?]
>[ 1003.971955] [drm:drm_mode_addfb2] [FB:87]
>[ 1003.973179] [drm:drm_mode_setcrtc] [CRTC:20]
>[ 1003.973182] [drm:drm_mode_setcrtc] [CONNECTOR:31:eDP-1]
>[ 1003.973183] [drm:intel_crtc_set_config] [CRTC:20] [FB:87] #connectors=1 (x y) (0 0)
>[ 1003.973186] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=1
>[ 1003.973188] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.973189] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.973189] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.973191] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 1003.973193] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[ 1003.973194] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 1003.973197] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz
>[ 1003.973198] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[ 1003.973199] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000
>[ 1003.973201] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 1003.973202] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 1003.973203] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[ 1003.973204] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 1003.973205] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.973206] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64
>[ 1003.973207] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.973208] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.973208] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.973210] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 0 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x0 0x9
>[ 1003.973211] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.973212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[ 1003.973213] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9
>[ 1003.973214] [drm:intel_dump_pipe_config] port clock: 270000
>[ 1003.973215] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.973216] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.973217] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.973217] [drm:intel_dump_pipe_config] ips: 1
>[ 1003.973218] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.973220] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800b00f6cc0
>[ 1003.974785] [drm:ironlake_update_primary_plane] Writing base 01FF3000 00000000 0 0 7680
>[ 1003.986847] [drm:drm_mode_setcrtc] [CRTC:24]
>[ 1003.986854] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-3]
>[ 1003.986857] [drm:intel_crtc_set_config] [CRTC:24] [FB:87] #connectors=1 (x y) (0 0)
>[ 1003.986861] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=0, fb_changed=1
>[ 1003.986863] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1003.986864] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1003.986866] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1003.986869] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 1003.986871] [drm:connected_sink_compute_bpp] [CONNECTOR:52:DP-3] checking for sink bpp constrains
>[ 1003.986874] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 1003.986877] [drm:intel_dump_pipe_config] [CRTC:24][modeset] config for pipe B
>[ 1003.986878] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 1003.986879] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 1003.986881] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1003.986883] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1730150, gmch_n: 8388608, link_m: 288358, link_n: 1048576, tu: 14
>[ 1003.986884] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1003.986886] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1003.986887] [drm:intel_dump_pipe_config] requested mode:
>[ 1003.986889] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[ 1003.986890] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1003.986892] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[ 1003.986894] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x0 flags: 0x5
>[ 1003.986895] [drm:intel_dump_pipe_config] port clock: 540000
>[ 1003.986897] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1003.986898] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1003.986900] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1003.986901] [drm:intel_dump_pipe_config] ips: 0
>[ 1003.986902] [drm:intel_dump_pipe_config] double wide: 0
>[ 1003.986904] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c9e766c0
>[ 1003.986918] [drm:ironlake_update_primary_plane] Writing base 01FF3000 00000000 0 0 7680
>[ 1004.003571] [drm:drm_mode_setcrtc] [CRTC:28]
>[ 1004.003577] [drm:drm_mode_setcrtc] [CONNECTOR:55:DP-4]
>[ 1004.003580] [drm:intel_crtc_set_config] [CRTC:28] [FB:87] #connectors=1 (x y) (0 0)
>[ 1004.003583] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:28], mode_changed=0, fb_changed=1
>[ 1004.003585] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1004.003587] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1004.003588] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1004.003591] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[ 1004.003594] [drm:connected_sink_compute_bpp] [CONNECTOR:55:DP-4] checking for sink bpp constrains
>[ 1004.003597] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 1004.003599] [drm:intel_dump_pipe_config] [CRTC:28][modeset] config for pipe C
>[ 1004.003600] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[ 1004.003601] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 1004.003603] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1004.003605] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1730150, gmch_n: 8388608, link_m: 288358, link_n: 1048576, tu: 14
>[ 1004.003606] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1004.003607] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1004.003608] [drm:intel_dump_pipe_config] requested mode:
>[ 1004.003611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[ 1004.003612] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1004.003614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[ 1004.003616] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x0 flags: 0x5
>[ 1004.003617] [drm:intel_dump_pipe_config] port clock: 540000
>[ 1004.003619] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1004.003620] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1004.003622] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1004.003623] [drm:intel_dump_pipe_config] ips: 0
>[ 1004.003624] [drm:intel_dump_pipe_config] double wide: 0
>[ 1004.003627] [drm:drm_atomic_set_fb_for_plane] Set [FB:87] for plane state ffff8800c9e769c0
>[ 1004.003641] [drm:ironlake_update_primary_plane] Writing base 01FF3000 00000000 0 0 7680
>[ 1004.336256] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c4c029c0
>[ 1004.336433] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8800c4c02480
>[ 1004.353335] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c4c02300
>[ 1004.400777] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9fac540
>[ 1004.400831] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8800c9fac300
>[ 1004.400854] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9fac840
>
>
>--> this is probably where xprofile calls 'xrandr --output DP2-2 --auto --output DP2-1 --auto --right-of DP2-2' again
>[ 1019.323608] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800b00f1540
>[ 1019.329020] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c4c02c00
>[ 1019.331243] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c4c02f00
>[ 1021.178783] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8800c9e76840
>[ 1021.194752] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8800c9e76780
>[ 1021.197246] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8800c9e76e40
>[ 1021.395549] [drm:i915_gem_open] 
>[ 1021.403160] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[ 1021.403166] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
>[ 1021.403168] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
>[ 1021.403177] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[ 1021.403184] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[ 1021.403485] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[ 1021.403778] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[ 1021.403789] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1021.403792] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
>[ 1021.403795] [drm:drm_mode_debug_printmodeline] Modeline 32:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[ 1021.403799] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[ 1021.403918] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[ 1021.403920] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1]
>[ 1021.403921] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[ 1021.403926] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1] disconnected
>[ 1021.403929] [drm:drm_mode_getconnector] [CONNECTOR:46:?]
>[ 1021.403931] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2]
>[ 1021.403932] [drm:intel_dp_detect] [CONNECTOR:46:DP-2]
>[ 1021.403933] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2] disconnected
>[ 1021.403937] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[ 1021.403938] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3]
>[ 1021.405223] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1021.405227] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1021.405241] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1021.405721] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1021.406725] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1021.406727] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1021.408440] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1021.408443] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1021.408451] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1021.408932] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1021.410608] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1021.410610] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1021.411455] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1021.411458] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1021.411468] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1021.411951] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1021.413642] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1021.413645] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1021.414473] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1021.414475] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1021.414488] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1021.414971] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1021.415999] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1021.416008] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3] probed modes :
>[ 1021.416012] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1021.416014] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[ 1021.416017] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1021.416019] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1021.416022] [drm:drm_mode_debug_printmodeline] Modeline 61:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1021.416024] [drm:drm_mode_debug_printmodeline] Modeline 69:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1021.416027] [drm:drm_mode_debug_printmodeline] Modeline 70:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1021.416029] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1021.416032] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1021.416034] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1021.416037] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1021.416039] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1021.416052] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[ 1021.416092] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[ 1021.416094] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4]
>[ 1021.416643] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1021.416644] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1021.417908] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1021.417910] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1021.417921] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1021.418399] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1021.419403] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1021.419405] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1021.421113] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1021.421114] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1021.421119] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1021.421596] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1021.423279] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1021.423281] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1021.424124] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1021.424127] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1021.424149] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1021.424630] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1021.426311] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1021.426313] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1021.427145] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1021.427148] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1021.427168] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1021.427646] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1021.428682] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1021.428691] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4] probed modes :
>[ 1021.428694] [drm:drm_mode_debug_printmodeline] Modeline 73:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1021.428697] [drm:drm_mode_debug_printmodeline] Modeline 76:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[ 1021.428700] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1021.428702] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1021.428704] [drm:drm_mode_debug_printmodeline] Modeline 74:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1021.428707] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1021.428709] [drm:drm_mode_debug_printmodeline] Modeline 83:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1021.428712] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1021.428714] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1021.428717] [drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1021.428719] [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1021.428721] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1021.428741] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[ 1021.428805] [drm:drm_mode_getconnector] [CONNECTOR:57:?]
>[ 1021.428807] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5]
>[ 1021.428809] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5] disconnected
>[ 1021.428814] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[ 1021.428819] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[ 1021.428821] [drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[ 1021.429356] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1021.429358] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1021.429596] [drm:i915_gem_context_create_ioctl] HW context 1 created
>[ 1021.441165] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1021.441169] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[ 1021.441183] [drm:drm_mode_getconnector] [CONNECTOR:50:?]
>[ 1021.441184] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2]
>[ 1021.441185] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-2]
>[ 1021.441368] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[ 1021.441369] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1021.441371] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2] disconnected
>[ 1021.441960] [drm:i915_gem_context_destroy_ioctl] HW context 1 destroyed
>[ 1021.442723] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800b00f3900
>[ 1021.444619] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800b00f3480
>[ 1021.447065] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802c8dc9300
>[ 1021.452771] [drm:drm_mode_addfb2] [FB:88]
>[ 1021.452854] [drm:drm_mode_setcrtc] [CRTC:20]
>[ 1021.452859] [drm:drm_mode_setcrtc] [CONNECTOR:31:eDP-1]
>[ 1021.452862] [drm:intel_crtc_set_config] [CRTC:20] [FB:88] #connectors=1 (x y) (0 0)
>[ 1021.452866] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=1
>[ 1021.452869] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1021.452871] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1021.452872] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1021.452878] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[ 1021.452888] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[ 1021.452890] [drm:connected_sink_compute_bpp] clamping display bpp (was 24) to EDID reported max of 18
>[ 1021.452905] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 0a pixel clock 140100KHz
>[ 1021.452911] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[ 1021.452912] [drm:intel_dp_compute_config] DP link bw required 252180 available 432000
>[ 1021.452918] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[ 1021.452923] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[ 1021.452925] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[ 1021.452926] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[ 1021.452928] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1021.452929] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4896849, gmch_n: 8388608, link_m: 272047, link_n: 524288, tu: 64
>[ 1021.452931] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1021.452932] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1021.452933] [drm:intel_dump_pipe_config] requested mode:
>[ 1021.452938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 0 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x0 0x9
>[ 1021.452939] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1021.452942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[ 1021.452945] [drm:intel_dump_crtc_timings] crtc timings: 140100 1920 1980 2016 2092 1080 1083 1088 1116, type: 0x48 flags: 0x9
>[ 1021.452946] [drm:intel_dump_pipe_config] port clock: 270000
>[ 1021.452947] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1021.452948] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1021.452951] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1021.452952] [drm:intel_dump_pipe_config] ips: 1
>[ 1021.452953] [drm:intel_dump_pipe_config] double wide: 0
>[ 1021.452965] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9180
>[ 1021.454366] [drm:ironlake_update_primary_plane] Writing base 0B813000 00000000 0 0 15360
>[ 1021.461252] [drm:drm_mode_setcrtc] [CRTC:24]
>[ 1021.461258] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-3]
>[ 1021.461260] [drm:intel_crtc_set_config] [CRTC:24] [FB:88] #connectors=1 (x y) (0 0)
>[ 1021.461264] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=0, fb_changed=1
>[ 1021.461265] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1021.461266] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1021.461267] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1021.461269] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 1021.461271] [drm:connected_sink_compute_bpp] [CONNECTOR:52:DP-3] checking for sink bpp constrains
>[ 1021.461275] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 1021.461276] [drm:intel_dump_pipe_config] [CRTC:24][modeset] config for pipe B
>[ 1021.461277] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 1021.461278] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 1021.461279] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1021.461280] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1730150, gmch_n: 8388608, link_m: 288358, link_n: 1048576, tu: 14
>[ 1021.461281] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1021.461283] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1021.461284] [drm:intel_dump_pipe_config] requested mode:
>[ 1021.461286] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[ 1021.461286] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1021.461288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[ 1021.461290] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x0 flags: 0x5
>[ 1021.461290] [drm:intel_dump_pipe_config] port clock: 540000
>[ 1021.461291] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1021.461292] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1021.461293] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1021.461294] [drm:intel_dump_pipe_config] ips: 0
>[ 1021.461295] [drm:intel_dump_pipe_config] double wide: 0
>[ 1021.461297] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff88030e286180
>[ 1021.461309] [drm:ironlake_update_primary_plane] Writing base 0B813000 00000000 0 0 15360
>[ 1021.463747] [drm:drm_mode_setcrtc] [CRTC:28]
>[ 1021.463753] [drm:drm_mode_setcrtc] [CONNECTOR:55:DP-4]
>[ 1021.463755] [drm:intel_crtc_set_config] [CRTC:28] [FB:88] #connectors=1 (x y) (0 0)
>[ 1021.463760] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:28], mode_changed=0, fb_changed=1
>[ 1021.463762] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1021.463764] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1021.463765] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1021.463769] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[ 1021.463772] [drm:connected_sink_compute_bpp] [CONNECTOR:55:DP-4] checking for sink bpp constrains
>[ 1021.463774] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 1021.463776] [drm:intel_dump_pipe_config] [CRTC:28][modeset] config for pipe C
>[ 1021.463777] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[ 1021.463779] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 1021.463780] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1021.463782] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1730150, gmch_n: 8388608, link_m: 288358, link_n: 1048576, tu: 14
>[ 1021.463784] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1021.463785] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1021.463786] [drm:intel_dump_pipe_config] requested mode:
>[ 1021.463789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[ 1021.463790] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1021.463792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[ 1021.463794] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x0 flags: 0x5
>[ 1021.463795] [drm:intel_dump_pipe_config] port clock: 540000
>[ 1021.463797] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1021.463798] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1021.463800] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1021.463801] [drm:intel_dump_pipe_config] ips: 0
>[ 1021.463802] [drm:intel_dump_pipe_config] double wide: 0
>[ 1021.463805] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9780
>[ 1021.463816] [drm:ironlake_update_primary_plane] Writing base 0B813000 00000000 0 0 15360
>[ 1021.464550] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88030e286300
>[ 1021.477877] [drm:drm_atomic_set_fb_for_plane] Set [FB:90] for plane state ffff8802c8dc9c00
>[ 1021.480386] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff8802c8dc9480
>[ 1021.481830] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8802c8dc9300
>[ 1021.497077] [drm:drm_mode_setcrtc] [CRTC:24]
>[ 1021.497083] [drm:drm_mode_setcrtc] [CONNECTOR:52:DP-3]
>[ 1021.497086] [drm:intel_crtc_set_config] [CRTC:24] [FB:88] #connectors=1 (x y) (1920 0)
>[ 1021.497090] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=0, fb_changed=1
>[ 1021.497092] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[ 1021.497094] [drm:intel_modeset_stage_output_state] [CONNECTOR:52:DP-3] to [CRTC:24]
>[ 1021.497095] [drm:intel_modeset_stage_output_state] [CONNECTOR:55:DP-4] to [CRTC:28]
>[ 1021.497098] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[ 1021.497100] [drm:connected_sink_compute_bpp] [CONNECTOR:52:DP-3] checking for sink bpp constrains
>[ 1021.497104] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[ 1021.497106] [drm:intel_dump_pipe_config] [CRTC:24][modeset] config for pipe B
>[ 1021.497107] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[ 1021.497108] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[ 1021.497110] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[ 1021.497112] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1730150, gmch_n: 8388608, link_m: 288358, link_n: 1048576, tu: 14
>[ 1021.497113] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[ 1021.497115] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[ 1021.497116] [drm:intel_dump_pipe_config] requested mode:
>[ 1021.497118] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[ 1021.497119] [drm:intel_dump_pipe_config] adjusted mode:
>[ 1021.497121] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x0 0x5
>[ 1021.497123] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x0 flags: 0x5
>[ 1021.497124] [drm:intel_dump_pipe_config] port clock: 540000
>[ 1021.497126] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[ 1021.497127] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[ 1021.497129] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1021.497130] [drm:intel_dump_pipe_config] ips: 0
>[ 1021.497131] [drm:intel_dump_pipe_config] double wide: 0
>[ 1021.497133] [drm:drm_atomic_set_fb_for_plane] Set [FB:88] for plane state ffff8802c8dc9e40
>[ 1021.497144] [drm:ironlake_update_primary_plane] Writing base 0B813000 FFFFFFFFFFFF2E00 0 0 15360
>[ 1021.497164] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802c8dc9c00
>[ 1021.497172] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff8802c8dc9d80
>[ 1021.718685] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[ 1021.718691] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
>[ 1021.718694] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
>[ 1021.719009] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[ 1021.719314] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[ 1021.719326] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1021.719330] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
>[ 1021.719334] [drm:drm_mode_debug_printmodeline] Modeline 32:"1920x1080" 60 140100 1920 1980 2016 2092 1080 1083 1088 1116 0x48 0x9
>[ 1021.719341] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[ 1021.719436] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[ 1021.719439] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1]
>[ 1021.719441] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[ 1021.719446] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1] disconnected
>[ 1021.719450] [drm:drm_mode_getconnector] [CONNECTOR:46:?]
>[ 1021.719452] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2]
>[ 1021.719453] [drm:intel_dp_detect] [CONNECTOR:46:DP-2]
>[ 1021.719455] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:46:DP-2] disconnected
>[ 1021.719462] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[ 1021.719464] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3]
>[ 1021.720741] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1021.720745] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1021.720765] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1021.722324] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1021.723330] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1021.723332] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1021.725041] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1021.725044] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1021.725051] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1021.725533] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1021.727218] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1021.727221] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1021.728063] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1021.728067] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1021.728164] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1021.728642] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1021.730321] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1021.730323] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1021.731156] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1021.731158] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1021.731380] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1021.731869] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1021.732910] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1021.732920] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:DP-3] probed modes :
>[ 1021.732925] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1021.732928] [drm:drm_mode_debug_printmodeline] Modeline 63:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[ 1021.732931] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1021.732933] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1021.732936] [drm:drm_mode_debug_printmodeline] Modeline 61:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1021.732939] [drm:drm_mode_debug_printmodeline] Modeline 69:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1021.732942] [drm:drm_mode_debug_printmodeline] Modeline 70:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1021.732945] [drm:drm_mode_debug_printmodeline] Modeline 71:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1021.732947] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1021.732950] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1021.732953] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1021.732956] [drm:drm_mode_debug_printmodeline] Modeline 67:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1021.732969] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[ 1021.733007] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[ 1021.733009] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4]
>[ 1021.733551] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1021.733553] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1021.734822] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1021.734825] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1021.735115] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1021.735592] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1021.736591] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1021.736593] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1021.738301] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1021.738304] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1021.738315] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1021.738798] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1021.740480] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1021.740482] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1021.741323] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1021.741325] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1021.741334] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1021.741811] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1021.743483] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1021.743485] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1021.744320] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00400000, dig 0x10101110
>[ 1021.744322] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[ 1021.744334] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[ 1021.744822] [drm:intel_dp_check_mst_status] got esi 02 10 00
>[ 1021.745857] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[ 1021.745866] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:DP-4] probed modes :
>[ 1021.745869] [drm:drm_mode_debug_printmodeline] Modeline 73:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1021.745872] [drm:drm_mode_debug_printmodeline] Modeline 76:"1600x900" 60 118963 1600 1696 1864 2128 900 901 904 932 0x0 0x6
>[ 1021.745875] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1021.745877] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 1021.745879] [drm:drm_mode_debug_printmodeline] Modeline 74:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 1021.745882] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 1021.745884] [drm:drm_mode_debug_printmodeline] Modeline 83:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 1021.745887] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 1021.745889] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 1021.745892] [drm:drm_mode_debug_printmodeline] Modeline 78:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 1021.745894] [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 1021.745897] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 1021.745908] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[ 1021.745940] [drm:drm_mode_getconnector] [CONNECTOR:57:?]
>[ 1021.745942] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5]
>[ 1021.745944] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:57:DP-5] disconnected
>[ 1021.745947] [drm:drm_mode_getconnector] [CONNECTOR:43:?]
>[ 1021.745949] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1]
>[ 1021.745951] [drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[ 1021.746536] [drm:intel_dp_check_mst_status] got esi2 02 00 00
>[ 1021.746538] [drm:intel_dp_check_mst_status] got esi 02 00 00
>[ 1021.757724] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1021.757730] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:43:HDMI-A-1] disconnected
>[ 1021.757749] [drm:drm_mode_getconnector] [CONNECTOR:50:?]
>[ 1021.757752] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2]
>[ 1021.757753] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-2]
>[ 1021.757917] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[ 1021.757920] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1021.757922] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:50:HDMI-A-2] disconnected
>[ 1021.762254] [drm:i915_gem_open] 
>[ 1021.827435] [drm:i915_gem_context_create_ioctl] HW context 1 created
>[ 1021.828353] [drm:i915_gem_context_destroy_ioctl] HW context 1 destroyed
>[ 1021.875812] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9cd2f00
>[ 1021.875834] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff8802f9cd23c0
>[ 1023.098849] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88007fec1540
>[ 1023.098869] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff88007fec1000
>[ 1023.219057] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8800c4c9c0c0
>[ 1023.219080] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff8800c4c9c240
>[ 1023.338869] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88007fe82a80
>[ 1023.338900] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff88007fe82900
>[ 1023.458332] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88007fec19c0
>[ 1023.458353] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff88007fec1480
>[ 1023.579166] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88007fe82780
>[ 1023.579188] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff88007fe82c00
>[ 1023.699833] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88007fe82840
>[ 1023.699858] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff88007fe82780
>[ 1023.819932] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88007fe82c00
>[ 1023.819954] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff88007fe82840
>[ 1023.940100] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88007fe82180
>[ 1023.940124] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff88007fe82c00
>[ 1024.060949] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88007fe82840
>[ 1024.060982] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff88007fe82180
>[ 1024.180624] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8800c4de1240
>[ 1024.180642] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff8800c4de1c00
>[ 1024.300699] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88007fe82cc0
>[ 1024.300719] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff88007fe82c00
>[ 1024.419937] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8800c4de10c0
>[ 1024.419954] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff8800c4de1900
>[ 1024.540050] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8800c4de1000
>[ 1024.540067] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff8800c4de10c0
>[ 1024.639895] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88007fec1600
>[ 1024.639913] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff88007fec1f00
>[ 1024.726637] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[ 1024.726649] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[ 1025.219009] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff8802f9cd2480
>[ 1025.219032] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff8802f9cd2d80
>[ 1025.269997] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88007fec1e40
>[ 1025.270020] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff88007fec1c00
>[ 1025.290307] [drm:drm_atomic_set_fb_for_plane] Set [FB:89] for plane state ffff88007fec1480
>[ 1025.290327] [drm:drm_atomic_set_fb_for_plane] Set [FB:91] for plane state ffff88007fec1e40
>
>
>
>[ 1040.504591] close laptop screen
>[ 1042.201393] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[ 1042.201421] [drm:intel_dp_detect] [CONNECTOR:46:DP-2]
>[ 1042.201489] [drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[ 1042.213587] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1042.213611] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-2]
>[ 1042.213829] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[ 1042.213832] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1042.213869] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
>[ 1042.213875] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[ 1042.213880] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[ 1042.214187] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[ 1042.214486] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[ 1042.214637] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[ 1042.214652] [drm:intel_dp_detect] [CONNECTOR:46:DP-2]
>[ 1042.214705] [drm:intel_hdmi_detect] [CONNECTOR:43:HDMI-A-1]
>[ 1042.226916] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[ 1042.226939] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-2]
>[ 1042.227148] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[ 1042.227152] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[ 1042.227200] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
>[ 1042.227520] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[ 1042.227820] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[ 1045.232585] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[ 1045.232598] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007

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Attachments on bug 89612: 114389 | 114390 | 114391 | 114392 | 114393 | 114394 | 114395 | 114396 | 114397 | 114398 | 114399 | 114400 | 114431 | 114434 | 114435

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