Attachment 115097 Details for Bug 90043 – dmesg output after xrandr --output DP1 --off

dmesg output after xrandr --output DP1 --off

dmesg-debug.txt (text/plain), 19.25 KB, created by Marat Bakeev on 2015-04-15 21:59:34 UTC

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Creator: Marat Bakeev

Created: 2015-04-15 21:59:34 UTC

Size: 19.25 KB

patch

obsolete

>[64925.444620] [drm:drm_mode_addfb2] [FB:82]
>[64940.415604] [drm:drm_mode_addfb2] [FB:54]
>[64950.296262] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[64950.296267] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1]
>[64950.296268] [drm:intel_dp_detect] [CONNECTOR:31:eDP-1]
>[64950.296279] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[64950.296282] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:31:eDP-1] probed modes :
>[64950.296284] [drm:drm_mode_debug_printmodeline] Modeline 32:"2880x1620" 60 302500 2880 2924 2928 3076 1620 1629 1630 1640 0x48 0x5
>[64950.296286] [drm:drm_mode_debug_printmodeline] Modeline 33:"2880x1620" 50 302500 2880 2924 2928 3076 1620 1629 1630 1967 0x40 0x5
>[64950.296288] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[64950.296368] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[64950.296369] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-1]
>[64950.296373] [drm:intel_dp_detect] [CONNECTOR:40:DP-1]
>[64950.296834] [drm:intel_dp_get_dpcd] DPCD: 12 14 84 00 01 00 01 00 02 00 02 00 00 00 00
>[64950.296837] [drm:intel_dp_print_rates] source rates: 162000,270000,540000,
>[64950.296839] [drm:intel_dp_print_rates] sink rates: 162000,270000,540000,
>[64950.296840] [drm:intel_dp_print_rates] common rates: 162000,270000,540000,
>[64950.297166] [drm:intel_dp_probe_mst] Sink is not MST capable
>[64950.299044] [drm:drm_dp_i2c_do_msg] native defer
>[64950.300105] [drm:drm_dp_i2c_do_msg] native defer
>[64950.301475] [drm:drm_dp_i2c_do_msg] native defer
>[64950.302547] [drm:drm_dp_i2c_do_msg] native defer
>[64950.303908] [drm:drm_dp_i2c_do_msg] native defer
>[64950.304996] [drm:drm_dp_i2c_do_msg] native defer
>[64950.306354] [drm:drm_dp_i2c_do_msg] native defer
>[64950.307440] [drm:drm_dp_i2c_do_msg] native defer
>[64950.308808] [drm:drm_dp_i2c_do_msg] native defer
>[64950.309881] [drm:drm_dp_i2c_do_msg] native defer
>[64950.311251] [drm:drm_dp_i2c_do_msg] native defer
>[64950.312323] [drm:drm_dp_i2c_do_msg] native defer
>[64950.313681] [drm:drm_dp_i2c_do_msg] native defer
>[64950.314752] [drm:drm_dp_i2c_do_msg] native defer
>[64950.316124] [drm:drm_dp_i2c_do_msg] native defer
>[64950.317197] [drm:drm_dp_i2c_do_msg] native defer
>[64950.319267] [drm:drm_dp_i2c_do_msg] native defer
>[64950.320336] [drm:drm_dp_i2c_do_msg] native defer
>[64950.321700] [drm:drm_dp_i2c_do_msg] native defer
>[64950.322785] [drm:drm_dp_i2c_do_msg] native defer
>[64950.324141] [drm:drm_dp_i2c_do_msg] native defer
>[64950.325195] [drm:drm_dp_i2c_do_msg] native defer
>[64950.326782] [drm:drm_dp_i2c_do_msg] native defer
>[64950.327854] [drm:drm_dp_i2c_do_msg] native defer
>[64950.329223] [drm:drm_dp_i2c_do_msg] native defer
>[64950.330319] [drm:drm_dp_i2c_do_msg] native defer
>[64950.331688] [drm:drm_dp_i2c_do_msg] native defer
>[64950.332773] [drm:drm_dp_i2c_do_msg] native defer
>[64950.334132] [drm:drm_dp_i2c_do_msg] native defer
>[64950.335203] [drm:drm_dp_i2c_do_msg] native defer
>[64950.336562] [drm:drm_dp_i2c_do_msg] native defer
>[64950.337636] [drm:drm_dp_i2c_do_msg] native defer
>[64950.338702] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[64950.338768] [drm:drm_edid_to_eld] ELD monitor Philips 288P6
>[64950.338770] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 600, latency present 0 0, video latency 0 0, audio latency 0 0
>[64950.338771] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[64950.338806] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:40:DP-1] probed modes :
>[64950.338809] [drm:drm_mode_debug_printmodeline] Modeline 57:"3840x2160" 60 533280 3840 3888 3976 4000 2160 2168 2178 2222 0x48 0x9
>[64950.338811] [drm:drm_mode_debug_printmodeline] Modeline 61:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x9
>[64950.338813] [drm:drm_mode_debug_printmodeline] Modeline 58:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[64950.338815] [drm:drm_mode_debug_printmodeline] Modeline 60:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1089 1095 1125 0x40 0xa
>[64950.338816] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[64950.338818] [drm:drm_mode_debug_printmodeline] Modeline 87:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[64950.338820] [drm:drm_mode_debug_printmodeline] Modeline 100:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[64950.338822] [drm:drm_mode_debug_printmodeline] Modeline 59:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1089 1095 1125 0x40 0xa
>[64950.338824] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[64950.338826] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[64950.338828] [drm:drm_mode_debug_printmodeline] Modeline 67:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[64950.338829] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[64950.338831] [drm:drm_mode_debug_printmodeline] Modeline 63:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[64950.338833] [drm:drm_mode_debug_printmodeline] Modeline 65:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[64950.338835] [drm:drm_mode_debug_printmodeline] Modeline 66:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[64950.338837] [drm:drm_mode_debug_printmodeline] Modeline 64:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[64950.338839] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[64950.338841] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[64950.338842] [drm:drm_mode_debug_printmodeline] Modeline 99:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[64950.338844] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[64950.338846] [drm:drm_mode_debug_printmodeline] Modeline 76:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[64950.338848] [drm:drm_mode_debug_printmodeline] Modeline 77:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[64950.338850] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[64950.338852] [drm:drm_mode_debug_printmodeline] Modeline 69:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[64950.338853] [drm:drm_mode_debug_printmodeline] Modeline 89:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[64950.338855] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[64950.338857] [drm:drm_mode_debug_printmodeline] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[64950.338859] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[64950.338861] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[64950.338862] [drm:drm_mode_debug_printmodeline] Modeline 72:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[64950.338864] [drm:drm_mode_debug_printmodeline] Modeline 73:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[64950.338866] [drm:drm_mode_debug_printmodeline] Modeline 80:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[64950.338868] [drm:drm_mode_debug_printmodeline] Modeline 74:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[64950.338881] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[64950.338971] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[64950.338974] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:DP-2]
>[64950.338976] [drm:intel_dp_detect] [CONNECTOR:47:DP-2]
>[64950.338982] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:DP-2] disconnected
>[64950.338986] [drm:drm_mode_getconnector] [CONNECTOR:44:?]
>[64950.338988] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:44:HDMI-A-1]
>[64950.338990] [drm:intel_hdmi_detect] [CONNECTOR:44:HDMI-A-1]
>[64950.339191] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[64950.339195] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[64950.339197] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:44:HDMI-A-1] disconnected
>[64950.339203] [drm:drm_mode_getconnector] [CONNECTOR:51:?]
>[64950.339204] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:51:HDMI-A-2]
>[64950.339205] [drm:intel_hdmi_detect] [CONNECTOR:51:HDMI-A-2]
>[64950.339377] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[64950.339381] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[64950.339384] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:51:HDMI-A-2] disconnected
>[64950.343085] [drm:drm_mode_setcrtc] [CRTC:24]
>[64950.343088] [drm:intel_crtc_set_config] [CRTC:24] [NOFB]
>[64950.343091] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:24], mode_changed=1, fb_changed=0
>[64950.343093] [drm:intel_modeset_stage_output_state] [CONNECTOR:40:DP-1] to [NOCRTC]
>[64950.343094] [drm:intel_modeset_stage_output_state] [CONNECTOR:40:DP-1] encoder changed, full mode switch
>[64950.343098] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[64950.343099] [drm:intel_modeset_stage_output_state] [ENCODER:39:TMDS-39] crtc changed, full mode switch
>[64950.343102] [drm:intel_modeset_stage_output_state] [CRTC:24] disabled, full mode switch
>[64950.343104] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 2
>[64950.345135] [drm:hsw_audio_codec_disable] Disable audio codec on pipe B
>[64950.376030] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[64950.376034] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[64950.376037] [drm:check_encoder_state] [ENCODER:39:TMDS-39]
>[64950.376038] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[64950.376039] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[64950.376040] [drm:check_encoder_state] [ENCODER:43:DP MST-43]
>[64950.376041] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[64950.376043] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[64950.376044] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[64950.376045] [drm:check_encoder_state] [ENCODER:50:DP MST-50]
>[64950.376046] [drm:check_crtc_state] [CRTC:20]
>[64950.376053] [drm:check_crtc_state] [CRTC:24]
>[64950.376054] [drm:check_crtc_state] [CRTC:28]
>[64950.376056] [drm:check_shared_dpll_state] WRPLL 1
>[64950.376058] [drm:check_shared_dpll_state] WRPLL 2
>[64950.376974] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=600/852
>[64950.376980] [drm:intel_panel_actually_set_backlight] set backlight PWM = 603
>[64950.376990] [drm:intel_edp_backlight_power] panel power control backlight disable
>[64950.377198] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00200000, dig 0x10101011
>[64950.377199] [drm:intel_hpd_irq_handler] digital hpd port B - short
>[64950.377209] [drm:intel_dp_hpd_pulse] got hpd irq on port B - short
>[64950.579155] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=0/852
>[64950.579164] [drm:intel_panel_actually_set_backlight] set backlight PWM = 10
>[64950.579263] [drm:drm_mode_setcrtc] [CRTC:20]
>[64950.579268] [drm:intel_crtc_set_config] [CRTC:20] [NOFB]
>[64950.579276] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=0
>[64950.579281] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [NOCRTC]
>[64950.579284] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] encoder changed, full mode switch
>[64950.579288] [drm:intel_modeset_stage_output_state] [ENCODER:30:TMDS-30] crtc changed, full mode switch
>[64950.579297] [drm:intel_modeset_stage_output_state] [CRTC:20] disabled, full mode switch
>[64950.579303] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[64950.581451] [drm:intel_edp_backlight_off] 
>[64950.782112] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[64950.796004] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[64950.796021] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[64950.796209] [drm:edp_panel_off] Turn eDP port A panel power off
>[64950.796219] [drm:wait_panel_off] Wait for panel power off time
>[64950.796226] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[64950.858208] [drm:wait_panel_status] Wait complete
>[64950.858231] [drm:intel_display_power_put] disabling always-on
>[64950.858236] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[64950.858238] [drm:check_encoder_state] [ENCODER:39:TMDS-39]
>[64950.858240] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[64950.858241] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[64950.858242] [drm:check_encoder_state] [ENCODER:43:DP MST-43]
>[64950.858243] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[64950.858244] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[64950.858245] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[64950.858246] [drm:check_encoder_state] [ENCODER:50:DP MST-50]
>[64950.858248] [drm:check_crtc_state] [CRTC:20]
>[64950.858249] [drm:check_crtc_state] [CRTC:24]
>[64950.858251] [drm:check_crtc_state] [CRTC:28]
>[64950.858252] [drm:check_shared_dpll_state] WRPLL 1
>[64950.858254] [drm:check_shared_dpll_state] WRPLL 2
>[64950.864277] [drm:drm_mode_addfb2] [FB:54]
>[64950.871856] [drm:drm_mode_setcrtc] [CRTC:20]
>[64950.871867] [drm:drm_mode_setcrtc] [CONNECTOR:31:eDP-1]
>[64950.871870] [drm:intel_crtc_set_config] [CRTC:20] [FB:54] #connectors=1 (x y) (0 0)
>[64950.871878] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[64950.871880] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[64950.871882] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] encoder changed, full mode switch
>[64950.871885] [drm:intel_modeset_stage_output_state] [CONNECTOR:31:eDP-1] to [CRTC:20]
>[64950.871886] [drm:intel_modeset_stage_output_state] [ENCODER:30:TMDS-30] crtc changed, full mode switch
>[64950.871889] [drm:intel_modeset_stage_output_state] [CRTC:20] enabled, full mode switch
>[64950.871894] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[64950.871900] [drm:connected_sink_compute_bpp] [CONNECTOR:31:eDP-1] checking for sink bpp constrains
>[64950.871906] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 302500KHz
>[64950.871945] [drm:intel_dp_compute_config] DP link bw 0a lane count 4 clock 270000 bpp 24
>[64950.871948] [drm:intel_dp_compute_config] DP link bw required 726000 available 864000
>[64950.871956] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[64950.871958] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[64950.871959] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[64950.871961] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[64950.871963] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[64950.871964] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 7048760, gmch_n: 8388608, link_m: 587396, link_n: 524288, tu: 64
>[64950.871966] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[64950.871967] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[64950.871969] [drm:intel_dump_pipe_config] requested mode:
>[64950.871974] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 302500 2880 2924 2928 3076 1620 1629 1630 1640 0x0 0x5
>[64950.871975] [drm:intel_dump_pipe_config] adjusted mode:
>[64950.871977] [drm:drm_mode_debug_printmodeline] Modeline 0:"2880x1620" 60 302500 2880 2924 2928 3076 1620 1629 1630 1640 0x48 0x5
>[64950.871978] [drm:intel_dump_crtc_timings] crtc timings: 302500 2880 2924 2928 3076 1620 1629 1630 1640, type: 0x48 flags: 0x5
>[64950.871979] [drm:intel_dump_pipe_config] port clock: 270000
>[64950.871980] [drm:intel_dump_pipe_config] pipe src size: 2880x1620
>[64950.871982] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[64950.871984] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[64950.871985] [drm:intel_dump_pipe_config] ips: 0
>[64950.871986] [drm:intel_dump_pipe_config] double wide: 0
>[64950.872006] [drm:intel_display_power_get] enabling always-on
>[64950.872074] [drm:edp_panel_on] Turn eDP port A panel power on
>[64950.872080] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[64951.398024] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[64951.398029] [drm:wait_panel_status] Wait complete
>[64951.398034] [drm:wait_panel_on] Wait for panel power on
>[64951.398037] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[64951.607216] [drm:wait_panel_status] Wait complete
>[64951.607227] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[64951.607233] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[64951.608295] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[64951.608903] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[64951.609498] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[64951.610093] [drm:intel_dp_start_link_train] clock recovery OK
>[64951.610997] [drm:intel_dp_set_signal_levels] Using signal levels 05000000
>[64951.611895] [drm:intel_dp_set_signal_levels] Using signal levels 05000000
>[64951.612790] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[64951.613031] [drm:intel_edp_backlight_on] 
>[64951.613034] [drm:intel_panel_enable_backlight] pipe A
>[64951.613040] [drm:intel_panel_actually_set_backlight] set backlight PWM = 852
>[64951.614435] [drm:intel_psr_enable] PSR not supported by this panel
>[64951.614437] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[64951.629671] [drm:intel_connector_check_state] [CONNECTOR:31:eDP-1]
>[64951.629678] [drm:check_encoder_state] [ENCODER:30:TMDS-30]
>[64951.629681] [drm:check_encoder_state] [ENCODER:39:TMDS-39]
>[64951.629684] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[64951.629686] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[64951.629687] [drm:check_encoder_state] [ENCODER:43:DP MST-43]
>[64951.629689] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[64951.629691] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[64951.629693] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[64951.629695] [drm:check_encoder_state] [ENCODER:50:DP MST-50]
>[64951.629697] [drm:check_crtc_state] [CRTC:20]
>[64951.629705] [drm:check_crtc_state] [CRTC:24]
>[64951.629707] [drm:check_crtc_state] [CRTC:28]
>[64951.629710] [drm:check_shared_dpll_state] WRPLL 1
>[64951.629712] [drm:check_shared_dpll_state] WRPLL 2
>[64951.629745] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=600/852
>[64951.629748] [drm:intel_panel_actually_set_backlight] set backlight PWM = 603
>[64952.000159] [drm:drm_mode_addfb2] [FB:85]
>[64952.334204] [drm:drm_mode_addfb2] [FB:88]
>[64952.503543] [drm:drm_mode_addfb2] [FB:90]
>[64954.617673] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[64954.617682] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007

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Attachments on bug 90043: 115096 | 115097 | 115098

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