Attachment 122028 Details for Bug 93578 – dmesg/drm-nightly - blank monitor 1920x1200@60Hz

dmesg/drm-nightly - blank monitor 1920x1200@60Hz

dmsg-drm-nightly-15-02-27.log (text/plain), 32.65 KB, created by PJ on 2016-02-29 14:43:33 UTC

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Creator: PJ

Created: 2016-02-29 14:43:33 UTC

Size: 32.65 KB

patch

obsolete

>[   46.231220] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00200000, dig 0x10101012, pins 0x00000020
>[   46.231223] [drm:intel_hpd_irq_handler] digital hpd port B - long
>[   46.231224] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 5 - cnt: 0
>[   46.231232] [drm:intel_dp_hpd_pulse] got hpd irq on port B - long
>[   46.231234] [drm:intel_power_well_enable] enabling DC off
>[   46.231236] [drm:gen9_set_dc_state] Setting DC state from 02 to 00
>[   46.231238] [drm:intel_power_well_enable] enabling power well 2
>[   46.231240] [drm:skl_set_power_well] Enabling power well 2
>[   46.235595] [drm:intel_dp_get_dpcd] DPCD: 12 14 81 01 21 15 01 81 00 00 04 00 00 00 02
>[   46.235599] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink no
>[   46.235601] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[   46.235602] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000
>[   46.235603] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000
>[   46.239951] [drm:intel_dp_probe_oui] Sink OUI: b92200
>[   46.242085] [drm:intel_dp_probe_oui] Branch OUI: 0022b9
>[   46.244182] [drm:intel_dp_probe_mst] Sink is not MST capable
>[   46.244185] [drm:intel_power_well_disable] disabling power well 2
>[   46.244190] [drm:skl_set_power_well] Disabling power well 2
>[   46.244190] [drm:intel_power_well_disable] disabling DC off
>[   46.244192] [drm:skl_enable_dc6] Enabling DC6
>[   46.244194] [drm:gen9_set_dc_state] Setting DC state from 00 to 02
>[   46.244198] [drm:i915_hotplug_work_func] running encoder hotplug functions
>[   46.244200] [drm:i915_hotplug_work_func] Connector DP-1 (pin 5) received hotplug event.
>[   46.244201] [drm:intel_dp_detect] [CONNECTOR:40:DP-1]
>[   46.244202] [drm:intel_power_well_enable] enabling DC off
>[   46.244203] [drm:gen9_set_dc_state] Setting DC state from 02 to 00
>[   46.244205] [drm:intel_power_well_enable] enabling power well 2
>[   46.244206] [drm:skl_set_power_well] Enabling power well 2
>[   46.248544] [drm:intel_dp_get_dpcd] DPCD: 12 14 81 01 21 15 01 81 00 00 04 00 00 00 02
>[   46.248546] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink no
>[   46.248548] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[   46.248549] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000
>[   46.248550] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000
>[   46.255075] [drm:intel_dp_probe_oui] Sink OUI: b92200
>[   46.257247] [drm:intel_dp_probe_oui] Branch OUI: 0022b9
>[   46.259373] [drm:intel_dp_probe_mst] Sink is not MST capable
>[   46.259615] [drm:drm_dp_i2c_do_msg] native defer
>[   46.260679] [drm:drm_dp_i2c_do_msg] native defer
>[   46.261613] [drm:drm_dp_i2c_do_msg] native defer
>[   46.262684] [drm:drm_dp_i2c_do_msg] native defer
>[   46.263741] [drm:drm_dp_i2c_do_msg] native defer
>[   46.264689] [drm:drm_dp_i2c_do_msg] native defer
>[   46.265752] [drm:drm_dp_i2c_do_msg] native defer
>[   46.266786] [drm:drm_dp_i2c_do_msg] native defer
>[   46.267827] [drm:drm_dp_i2c_do_msg] native defer
>[   46.268738] [drm:drm_dp_i2c_do_msg] native defer
>[   46.269779] [drm:drm_dp_i2c_do_msg] native defer
>[   46.270812] [drm:drm_dp_i2c_do_msg] native defer
>[   46.271731] [drm:drm_dp_i2c_do_msg] native defer
>[   46.272587] [drm:drm_dp_i2c_do_msg] native defer
>[   46.273756] [drm:drm_dp_i2c_do_msg] native defer
>[   46.274682] [drm:drm_dp_i2c_do_msg] native defer
>[   46.275608] [drm:drm_dp_i2c_do_msg] native defer
>[   46.276799] [drm:drm_dp_i2c_do_msg] native defer
>[   46.277725] [drm:drm_dp_i2c_do_msg] native defer
>[   46.278643] [drm:drm_dp_i2c_do_msg] native defer
>[   46.279827] [drm:drm_dp_i2c_do_msg] native defer
>[   46.280745] [drm:drm_dp_i2c_do_msg] native defer
>[   46.281648] [drm:drm_dp_i2c_do_msg] native defer
>[   46.282839] [drm:drm_dp_i2c_do_msg] native defer
>[   46.283758] [drm:drm_dp_i2c_do_msg] native defer
>[   46.284675] [drm:drm_dp_i2c_do_msg] native defer
>[   46.285844] [drm:drm_dp_i2c_do_msg] native defer
>[   46.286747] [drm:drm_dp_i2c_do_msg] native defer
>[   46.287665] [drm:drm_dp_i2c_do_msg] native defer
>[   46.288834] [drm:drm_dp_i2c_do_msg] native defer
>[   46.289752] [drm:drm_dp_i2c_do_msg] native defer
>[   46.290670] [drm:drm_dp_i2c_do_msg] native defer
>[   46.291862] [drm:drm_dp_i2c_do_msg] native defer
>[   46.292787] [drm:drm_dp_i2c_do_msg] native defer
>[   46.293690] [drm:drm_dp_i2c_do_msg] native defer
>[   46.294867] [drm:drm_dp_i2c_do_msg] native defer
>[   46.295892] [drm:drm_dp_i2c_do_msg] native defer
>[   46.296934] [drm:drm_dp_i2c_do_msg] native defer
>[   46.297867] [drm:drm_dp_i2c_do_msg] native defer
>[   46.298932] [drm:drm_dp_i2c_do_msg] native defer
>[   46.299986] [drm:drm_dp_i2c_do_msg] native defer
>[   46.300890] [drm:drm_dp_i2c_do_msg] native defer
>[   46.301808] [drm:drm_dp_i2c_do_msg] native defer
>[   46.302978] [drm:drm_dp_i2c_do_msg] native defer
>[   46.303895] [drm:drm_dp_i2c_do_msg] native defer
>[   46.304813] [drm:drm_dp_i2c_do_msg] native defer
>[   46.305981] [drm:drm_dp_i2c_do_msg] native defer
>[   46.306901] [drm:drm_dp_i2c_do_msg] native defer
>[   46.307757] [drm:drm_dp_i2c_do_msg] native defer
>[   46.308948] [drm:drm_dp_i2c_do_msg] native defer
>[   46.309875] [drm:drm_dp_i2c_do_msg] native defer
>[   46.310800] [drm:drm_dp_i2c_do_msg] native defer
>[   46.311991] [drm:drm_dp_i2c_do_msg] native defer
>[   46.312917] [drm:drm_dp_i2c_do_msg] native defer
>[   46.313842] [drm:drm_dp_i2c_do_msg] native defer
>[   46.315670] [drm:drm_dp_i2c_do_msg] native defer
>[   46.316596] [drm:drm_dp_i2c_do_msg] native defer
>[   46.317520] [drm:drm_dp_i2c_do_msg] native defer
>[   46.318719] [drm:drm_dp_i2c_do_msg] native defer
>[   46.319653] [drm:drm_dp_i2c_do_msg] native defer
>[   46.320578] [drm:drm_dp_i2c_do_msg] native defer
>[   46.321769] [drm:drm_dp_i2c_do_msg] native defer
>[   46.322696] [drm:drm_dp_i2c_do_msg] native defer
>[   46.323621] [drm:drm_dp_i2c_do_msg] native defer
>[   46.324804] [drm:drm_dp_i2c_do_msg] native defer
>[   46.325615] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[   46.328847] [drm:intel_dp_detect] CP or sink specific irq unhandled
>[   46.328849] [drm:intel_power_well_disable] disabling power well 2
>[   46.328854] [drm:skl_set_power_well] Disabling power well 2
>[   46.328855] [drm:intel_power_well_disable] disabling DC off
>[   46.328857] [drm:skl_enable_dc6] Enabling DC6
>[   46.328858] [drm:gen9_set_dc_state] Setting DC state from 00 to 02
>[   46.328860] [drm:intel_hpd_irq_event] [CONNECTOR:40:DP-1] status updated from disconnected to connected
>[   46.328861] [drm:i915_hotplug_work_func] Connector HDMI-A-1 (pin 5) received hotplug event.
>[   46.328863] [drm:intel_hdmi_detect] [CONNECTOR:44:HDMI-A-1]
>[   46.329668] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   46.329669] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[   46.330468] [drm:do_gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   46.330470] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[   46.331285] [drm:drm_mode_getresources] [CONNECTOR:32:eDP-1]
>[   46.331286] [drm:drm_mode_getresources] [CONNECTOR:40:DP-1]
>[   46.331287] [drm:drm_mode_getresources] [CONNECTOR:44:HDMI-A-1]
>[   46.331288] [drm:drm_mode_getresources] [CONNECTOR:47:DP-2]
>[   46.331289] [drm:drm_mode_getresources] [CONNECTOR:51:HDMI-A-2]
>[   46.331290] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[9]
>[   46.331295] [drm:drm_mode_getconnector] [CONNECTOR:32:?]
>[   46.331299] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[   46.331300] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[   46.331304] [drm:drm_mode_getconnector] [CONNECTOR:44:?]
>[   46.331305] [drm:drm_mode_getconnector] [CONNECTOR:51:?]
>[   46.331318] [drm:drm_mode_getconnector] [CONNECTOR:32:?]
>[   46.331421] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[   46.331422] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:DP-1]
>[   46.331424] [drm:intel_dp_detect] [CONNECTOR:40:DP-1]
>[   46.331426] [drm:intel_power_well_enable] enabling DC off
>[   46.331428] [drm:gen9_set_dc_state] Setting DC state from 02 to 00
>[   46.331431] [drm:intel_power_well_enable] enabling power well 2
>[   46.331433] [drm:skl_set_power_well] Enabling power well 2
>[   46.333743] [drm:intel_dp_get_dpcd] DPCD: 12 14 81 01 21 15 01 81 00 00 04 00 00 00 02
>[   46.333745] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink no
>[   46.333746] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[   46.333748] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000
>[   46.333749] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000
>[   46.340289] [drm:intel_dp_probe_oui] Sink OUI: b92200
>[   46.342460] [drm:intel_dp_probe_oui] Branch OUI: 0022b9
>[   46.344625] [drm:intel_dp_probe_mst] Sink is not MST capable
>[   46.344867] [drm:drm_dp_i2c_do_msg] native defer
>[   46.345931] [drm:drm_dp_i2c_do_msg] native defer
>[   46.346875] [drm:drm_dp_i2c_do_msg] native defer
>[   46.347951] [drm:drm_dp_i2c_do_msg] native defer
>[   46.349007] [drm:drm_dp_i2c_do_msg] native defer
>[   46.349933] [drm:drm_dp_i2c_do_msg] native defer
>[   46.351005] [drm:drm_dp_i2c_do_msg] native defer
>[   46.352053] [drm:drm_dp_i2c_do_msg] native defer
>[   46.353117] [drm:drm_dp_i2c_do_msg] native defer
>[   46.354019] [drm:drm_dp_i2c_do_msg] native defer
>[   46.355084] [drm:drm_dp_i2c_do_msg] native defer
>[   46.356140] [drm:drm_dp_i2c_do_msg] native defer
>[   46.357066] [drm:drm_dp_i2c_do_msg] native defer
>[   46.357991] [drm:drm_dp_i2c_do_msg] native defer
>[   46.359182] [drm:drm_dp_i2c_do_msg] native defer
>[   46.360116] [drm:drm_dp_i2c_do_msg] native defer
>[   46.361041] [drm:drm_dp_i2c_do_msg] native defer
>[   46.362232] [drm:drm_dp_i2c_do_msg] native defer
>[   46.363159] [drm:drm_dp_i2c_do_msg] native defer
>[   46.364091] [drm:drm_dp_i2c_do_msg] native defer
>[   46.365282] [drm:drm_dp_i2c_do_msg] native defer
>[   46.366209] [drm:drm_dp_i2c_do_msg] native defer
>[   46.367142] [drm:drm_dp_i2c_do_msg] native defer
>[   46.368340] [drm:drm_dp_i2c_do_msg] native defer
>[   46.369267] [drm:drm_dp_i2c_do_msg] native defer
>[   46.370192] [drm:drm_dp_i2c_do_msg] native defer
>[   46.371391] [drm:drm_dp_i2c_do_msg] native defer
>[   46.372317] [drm:drm_dp_i2c_do_msg] native defer
>[   46.373250] [drm:drm_dp_i2c_do_msg] native defer
>[   46.374448] [drm:drm_dp_i2c_do_msg] native defer
>[   46.375307] [drm:drm_dp_i2c_do_msg] native defer
>[   46.376239] [drm:drm_dp_i2c_do_msg] native defer
>[   46.377438] [drm:drm_dp_i2c_do_msg] native defer
>[   46.378372] [drm:drm_dp_i2c_do_msg] native defer
>[   46.379177] [drm:drm_dp_i2c_do_msg] native defer
>[   46.380368] [drm:drm_dp_i2c_do_msg] native defer
>[   46.381424] [drm:drm_dp_i2c_do_msg] native defer
>[   46.382496] [drm:drm_dp_i2c_do_msg] native defer
>[   46.383421] [drm:drm_dp_i2c_do_msg] native defer
>[   46.384492] [drm:drm_dp_i2c_do_msg] native defer
>[   46.385541] [drm:drm_dp_i2c_do_msg] native defer
>[   46.386475] [drm:drm_dp_i2c_do_msg] native defer
>[   46.387332] [drm:drm_dp_i2c_do_msg] native defer
>[   46.388531] [drm:drm_dp_i2c_do_msg] native defer
>[   46.389465] [drm:drm_dp_i2c_do_msg] native defer
>[   46.390397] [drm:drm_dp_i2c_do_msg] native defer
>[   46.391551] [drm:drm_dp_i2c_do_msg] native defer
>[   46.392485] [drm:drm_dp_i2c_do_msg] native defer
>[   46.393417] [drm:drm_dp_i2c_do_msg] native defer
>[   46.394616] [drm:drm_dp_i2c_do_msg] native defer
>[   46.395560] [drm:drm_dp_i2c_do_msg] native defer
>[   46.396490] [drm:drm_dp_i2c_do_msg] native defer
>[   46.397689] [drm:drm_dp_i2c_do_msg] native defer
>[   46.398623] [drm:drm_dp_i2c_do_msg] native defer
>[   46.399481] [drm:drm_dp_i2c_do_msg] native defer
>[   46.400687] [drm:drm_dp_i2c_do_msg] native defer
>[   46.401620] [drm:drm_dp_i2c_do_msg] native defer
>[   46.402553] [drm:drm_dp_i2c_do_msg] native defer
>[   46.403737] [drm:drm_dp_i2c_do_msg] native defer
>[   46.404671] [drm:drm_dp_i2c_do_msg] native defer
>[   46.405603] [drm:drm_dp_i2c_do_msg] native defer
>[   46.406802] [drm:drm_dp_i2c_do_msg] native defer
>[   46.407729] [drm:drm_dp_i2c_do_msg] native defer
>[   46.408661] [drm:drm_dp_i2c_do_msg] native defer
>[   46.409739] [drm:drm_dp_i2c_do_msg] native defer
>[   46.410557] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[   46.413804] [drm:intel_power_well_disable] disabling power well 2
>[   46.413810] [drm:skl_set_power_well] Disabling power well 2
>[   46.413811] [drm:intel_power_well_disable] disabling DC off
>[   46.413813] [drm:skl_enable_dc6] Enabling DC6
>[   46.413814] [drm:gen9_set_dc_state] Setting DC state from 00 to 02
>[   46.413896] [drm:drm_edid_to_eld] ELD monitor DELL U2415
>[   46.413897] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0
>[   46.413898] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[   46.413916] [drm:drm_mode_debug_printmodeline] Modeline 82:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[   46.413917] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[   46.413918] [drm:drm_mode_debug_printmodeline] Modeline 83:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[   46.413919] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[   46.413920] [drm:drm_mode_debug_printmodeline] Modeline 102:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[   46.413921] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[   46.413924] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:40:DP-1] probed modes :
>[   46.413926] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x5
>[   46.413927] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   46.413928] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   46.413929] [drm:drm_mode_debug_printmodeline] Modeline 63:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   46.413931] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   46.413932] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   46.413933] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[   46.413934] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   46.413936] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   46.413937] [drm:drm_mode_debug_printmodeline] Modeline 90:"1920x1080" 25 74250 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   46.413938] [drm:drm_mode_debug_printmodeline] Modeline 89:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   46.413939] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   46.413940] [drm:drm_mode_debug_printmodeline] Modeline 68:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[   46.413942] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   46.413943] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   46.413944] [drm:drm_mode_debug_printmodeline] Modeline 66:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   46.413945] [drm:drm_mode_debug_printmodeline] Modeline 64:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   46.413947] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   46.413948] [drm:drm_mode_debug_printmodeline] Modeline 88:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[   46.413949] [drm:drm_mode_debug_printmodeline] Modeline 74:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   46.413950] [drm:drm_mode_debug_printmodeline] Modeline 75:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   46.413951] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   46.413953] [drm:drm_mode_debug_printmodeline] Modeline 69:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   46.413954] [drm:drm_mode_debug_printmodeline] Modeline 87:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[   46.413955] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[   46.413956] [drm:drm_mode_debug_printmodeline] Modeline 65:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[   46.413957] [drm:drm_mode_debug_printmodeline] Modeline 70:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   46.413958] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   46.413960] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   46.413961] [drm:drm_mode_debug_printmodeline] Modeline 72:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   46.413971] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[   46.414803] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   46.418472] [drm:drm_mode_addfb2] [FB:55]
>[   46.422094] [drm:drm_mode_addfb2] [FB:77]
>[   46.422106] [drm:drm_mode_setcrtc] [CRTC:21:crtc-0]
>[   46.422110] [drm:drm_mode_setcrtc] [CONNECTOR:32:eDP-1]
>[   46.422121] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:18] scaler_user index 0.0
>[   46.424838] [drm:drm_mode_setcrtc] [CRTC:21:crtc-0]
>[   46.424839] [drm:drm_mode_setcrtc] [CONNECTOR:32:eDP-1]
>[   46.424843] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:18] scaler_user index 0.0
>[   46.428671] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   46.428965] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   46.429003] [drm:drm_mode_setcrtc] [CRTC:21:crtc-0]
>[   46.429005] [drm:drm_mode_setcrtc] [CONNECTOR:40:DP-1]
>[   46.429011] [drm:connected_sink_compute_bpp] [CONNECTOR:40:DP-1] checking for sink bpp constrains
>[   46.429012] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   46.429014] [drm:intel_dp_compute_config] DP link computation with max lane count 1 max bw 540000 pixel clock 154000KHz
>[   46.429017] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 1 clock 540000 bpp 24
>[   46.429018] [drm:intel_dp_compute_config] DP link bw required 369600 available 432000
>[   46.429020] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   46.429021] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff88007439d800 for pipe A
>[   46.429022] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   46.429023] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   46.429024] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   46.429025] [drm:intel_dump_pipe_config] dp: 1, lanes: 1, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 1048576, tu: 64
>[   46.429026] [drm:intel_dump_pipe_config] dp: 1, lanes: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   46.429027] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   46.429028] [drm:intel_dump_pipe_config] requested mode:
>[   46.429029] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x0 0x5
>[   46.429030] [drm:intel_dump_pipe_config] adjusted mode:
>[   46.429031] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x0 0x5
>[   46.429032] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x0 flags: 0x5
>[   46.429033] [drm:intel_dump_pipe_config] port clock: 540000
>[   46.429034] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[   46.429035] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   46.429035] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   46.429036] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   46.429037] [drm:intel_dump_pipe_config] ips: 0
>[   46.429038] [drm:intel_dump_pipe_config] double wide: 0
>[   46.429039] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[   46.429039] [drm:intel_dump_pipe_config] planes on this crtc
>[   46.429040] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 enabled
>[   46.429041] [drm:intel_dump_pipe_config] 	FB:55, fb = 3840x1200 format = 0x34325258<7>[   46.429043] [drm:intel_dump_pipe_config] 	scaler:-1 src (0, 0) 1920x1080 dst (0, 0) 1920x1080
>[   46.429044] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 disabled, scaler_id = -1
>[   46.429045] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = -1
>[   46.429046] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:18] scaler_user index 0.0
>[   46.429048] [drm:intel_get_shared_dpll] CRTC:21 allocated DPLL 1
>[   46.429049] [drm:intel_get_shared_dpll] using DPLL 1 for pipe A
>[   46.429050] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:21] scaler_user index 0.31
>[   46.429053] [drm:intel_power_well_enable] enabling DC off
>[   46.429055] [drm:gen9_set_dc_state] Setting DC state from 02 to 00
>[   46.429058] [drm:intel_power_well_enable] enabling power well 2
>[   46.429060] [drm:skl_set_power_well] Enabling power well 2
>[   46.430868] [drm:intel_power_well_enable] enabling DDI B power well
>[   46.430871] [drm:skl_set_power_well] Enabling DDI B power well
>[   46.430876] [drm:intel_edp_backlight_off] 
>[   46.634931] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   46.634965] [drm:intel_disable_pipe] disabling pipe A
>[   46.647169] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   46.647216] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   46.647377] [drm:edp_panel_off] Turn eDP port A panel power off
>[   46.647415] [drm:wait_panel_off] Wait for panel power off time
>[   46.647431] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control abcd0000
>[   46.647828] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[   46.647830] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[   46.647834] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[   46.699726] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   46.699729] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   46.699730] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[   46.701329] [drm:wait_panel_status] Wait complete
>[   46.701336] [drm:intel_enable_shared_dpll] enable DPLL 1 (active 0, on? 0) for crtc 21
>[   46.701337] [drm:intel_enable_shared_dpll] enabling DPLL 1
>[   46.704178] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   46.704180] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   46.704181] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   46.714619] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[   46.714621] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   46.714622] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   46.724961] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   46.724963] [drm:intel_dp_training_pattern] 5.4 Gbps link rate without sink TPS3 support
>[   46.737420] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   46.737622] [drm:skylake_pfit_enable] for crtc_state = ffff88007439d800
>[   46.737698] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   46.737701] [drm:intel_enable_pipe] enabling pipe A
>[   46.737710] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:40:DP-1], [ENCODER:39:TMDS-39]
>[   46.737711] [drm:hsw_audio_codec_enable] Enable audio codec on pipe A, 36 bytes ELD
>[   46.754471] [drm:intel_power_well_disable] disabling DDI A/E power well
>[   46.754474] [drm:skl_set_power_well] Disabling DDI A/E power well
>[   46.754480] [drm:intel_connector_check_state] [CONNECTOR:32:eDP-1]
>[   46.754481] [drm:intel_connector_check_state] [CONNECTOR:40:DP-1]
>[   46.754483] [drm:check_encoder_state] [ENCODER:31:TMDS-31]
>[   46.754484] [drm:check_encoder_state] [ENCODER:39:TMDS-39]
>[   46.754485] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[   46.754486] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[   46.754486] [drm:check_encoder_state] [ENCODER:43:DP MST-43]
>[   46.754487] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[   46.754488] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[   46.754489] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[   46.754489] [drm:check_encoder_state] [ENCODER:50:DP MST-50]
>[   46.754491] [drm:check_crtc_state] [CRTC:21]
>[   46.754501] [drm:check_shared_dpll_state] DPLL 1
>[   46.754502] [drm:check_shared_dpll_state] DPLL 2
>[   46.754503] [drm:check_shared_dpll_state] DPLL 3
>[   46.754513] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   46.754726] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   46.755286] [drm:drm_mode_setcrtc] [CRTC:25:crtc-1]
>[   46.755289] [drm:drm_mode_setcrtc] [CONNECTOR:32:eDP-1]
>[   46.755295] [drm:connected_sink_compute_bpp] [CONNECTOR:32:eDP-1] checking for sink bpp constrains
>[   46.755296] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[   46.755299] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:25] scaler_user index 1.31
>[   46.755300] [drm:skl_update_scaler] scaler_user index 1.31: Staged freeing scaler id 0 scaler_users = 0x0
>[   46.755301] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138500KHz
>[   46.755304] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[   46.755305] [drm:intel_dp_compute_config] DP link bw required 332400 available 432000
>[   46.755306] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   46.755308] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880270603800 for pipe B
>[   46.755308] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[   46.755309] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   46.755310] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   46.755311] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6454567, gmch_n: 8388608, link_m: 268940, link_n: 524288, tu: 64
>[   46.755312] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   46.755313] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   46.755314] [drm:intel_dump_pipe_config] requested mode:
>[   46.755316] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 138500 1920 1968 2000 2080 1080 1083 1088 1111 0x0 0xa
>[   46.755316] [drm:intel_dump_pipe_config] adjusted mode:
>[   46.755318] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138500 1920 1968 2000 2080 1080 1083 1088 1111 0x48 0xa
>[   46.755319] [drm:intel_dump_crtc_timings] crtc timings: 138500 1920 1968 2000 2080 1080 1083 1088 1111, type: 0x48 flags: 0xa
>[   46.755320] [drm:intel_dump_pipe_config] port clock: 270000
>[   46.755320] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   46.755321] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   46.755322] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   46.755323] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   46.755324] [drm:intel_dump_pipe_config] ips: 0
>[   46.755325] [drm:intel_dump_pipe_config] double wide: 0
>[   46.755325] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[   46.755326] [drm:intel_dump_pipe_config] planes on this crtc
>[   46.755327] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = -1
>[   46.755328] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = -1
>[   46.755329] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = -1
>[   46.755331] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23] scaler_user index 1.3
>[   46.755332] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:25] scaler_user index 1.31
>[   46.755336] [drm:intel_power_well_enable] enabling DDI A/E power well
>[   46.755338] [drm:skl_set_power_well] Enabling DDI A/E power well
>[   46.755350] [drm:edp_panel_on] Turn eDP port A panel power on
>[   46.755357] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   47.254975] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[   47.254983] [drm:wait_panel_status] Wait complete
>[   47.255006] [drm:wait_panel_on] Wait for panel power on
>[   47.255021] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[   47.302659] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   47.302661] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   47.302662] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[   47.302671] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   47.455843] [drm:wait_panel_status] Wait complete
>[   47.455855] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   47.455901] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   47.456959] [drm:intel_dp_set_signal_levels] Using signal levels 05000000
>[   47.456960] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   47.456961] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   47.457558] [drm:intel_dp_link_training_clock_recovery] clock recovery not ok, reset
>[   47.457560] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   47.457560] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   47.457561] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   47.458158] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[   47.458159] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   47.458160] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   47.458748] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[   47.459652] [drm:intel_dp_set_signal_levels] Using signal levels 05000000
>[   47.459654] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   47.459654] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   47.460541] [drm:intel_dp_set_signal_levels] Using signal levels 05000000
>[   47.460541] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[   47.460543] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   47.461429] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[   47.461578] [drm:skylake_pfit_enable] for crtc_state = ffff880270603800
>[   47.461663] [drm:skl_wm_flush_pipe] flush pipe A (pass 1)
>[   47.471753] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   47.471756] [drm:intel_enable_pipe] enabling pipe B
>[   47.471759] [drm:intel_edp_backlight_on] 
>[   47.471760] [drm:intel_panel_enable_backlight] pipe B
>[   47.471799] [drm:intel_panel_actually_set_backlight] set backlight PWM = 274
>[   47.471838] [drm:intel_psr_match_conditions] PSR disable by flag
>[   47.471838] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   47.488548] [drm:intel_connector_check_state] [CONNECTOR:32:eDP-1]
>[   47.488551] [drm:check_encoder_state] [ENCODER:31:TMDS-31]
>[   47.488552] [drm:check_encoder_state] [ENCODER:39:TMDS-39]
>[   47.488554] [drm:check_encoder_state] [ENCODER:41:DP MST-41]
>[   47.488554] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[   47.488555] [drm:check_encoder_state] [ENCODER:43:DP MST-43]
>[   47.488556] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[   47.488557] [drm:check_encoder_state] [ENCODER:48:DP MST-48]
>[   47.488557] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[   47.488558] [drm:check_encoder_state] [ENCODER:50:DP MST-50]
>[   47.488559] [drm:check_crtc_state] [CRTC:25]
>[   47.488568] [drm:check_shared_dpll_state] DPLL 1
>[   47.488569] [drm:check_shared_dpll_state] DPLL 2
>[   47.488571] [drm:check_shared_dpll_state] DPLL 3
>[   47.488596] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=247/937
>[   47.488597] [drm:intel_panel_actually_set_backlight] set backlight PWM = 274
>[   47.488744] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[   47.488748] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[   47.549402] [drm:drm_mode_getconnector] [CONNECTOR:32:?]
>[   47.549525] [drm:drm_mode_getconnector] [CONNECTOR:40:?]
>[   47.559005] [drm:drm_mode_addfb2] [FB:80]
>[   47.573581] [drm:drm_mode_addfb2] [FB:81]

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Attachments on bug 93578: 120796 | 121569 | 121803 | 121804 | 121805 | 121806 | 121807 | 122028 | 124028 | 124135 | 128426 | 128427 | 129324 | 129325 | 130503 | 130538

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