Attachment 122353 Details for Bug 94578 – intel_reg dump --all output, before plugging external monitor in

intel_reg dump --all output, before plugging external monitor in

intel-reg-dump-01-before-plugging-in.txt (text/plain), 26.60 KB, created by Nathaniel Smith on 2016-03-16 21:28:31 UTC

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Creator: Nathaniel Smith

Created: 2016-03-16 21:28:31 UTC

Size: 26.60 KB

patch

obsolete

>                       CPU_VGACNTRL (0x00041000): 0x80002900
>Gen5	disabled
>                           PORT_DBG (0x00042308): 0x00000000
>Gen5	HW DRRS off
>         DIGITAL_PORT_HOTPLUG_CNTRL (0x00044030): 0x00000000
>                     FDI_PLL_BIOS_0 (0x00046000): 0x00000000
>                     FDI_PLL_BIOS_1 (0x00046004): 0x00000000
>                     FDI_PLL_BIOS_2 (0x00046008): 0x00000000
>            DISPLAY_PORT_PLL_BIOS_0 (0x0004600c): 0x00000000
>            DISPLAY_PORT_PLL_BIOS_1 (0x00046010): 0x00000000
>            DISPLAY_PORT_PLL_BIOS_2 (0x00046014): 0x00000000
>                   FDI_PLL_FREQ_CTL (0x00046030): 0x00000000
>                   BLC_PWM_CPU_CTL2 (0x00048250): 0x00000000
>Gen5	enable 0, pipe A, blinking 0, granularity 128
>Gen7.5	enable 0, pipe A, blinking 0, granularity 128
>                    BLC_PWM_CPU_CTL (0x00048254): 0x00000000
>Gen5	cycle 0, freq 0
>Gen7.5	cycle 0, freq 0
>                           HTOTAL_A (0x00060000): 0x00000000
>Gen2	1 active, 1 total
>Gen5	1 active, 1 total
>Gen7.5	1 active, 1 total
>                           HBLANK_A (0x00060004): 0x00000000
>Gen2	1 start, 1 end
>Gen5	1 start, 1 end
>Gen7.5	1 start, 1 end
>                            HSYNC_A (0x00060008): 0x00000000
>Gen2	1 start, 1 end
>Gen5	1 start, 1 end
>Gen7.5	1 start, 1 end
>                           VTOTAL_A (0x0006000c): 0x00000000
>Gen2	1 active, 1 total
>Gen5	1 active, 1 total
>Gen7.5	1 active, 1 total
>                           VBLANK_A (0x00060010): 0x00000000
>Gen2	1 start, 1 end
>Gen5	1 start, 1 end
>Gen7.5	1 start, 1 end
>                            VSYNC_A (0x00060014): 0x00000000
>Gen2	1 start, 1 end
>Gen5	1 start, 1 end
>Gen7.5	1 start, 1 end
>                           PIPEASRC (0x0006001c): 0x077f0437
>Gen2	1920, 1080
>Gen5	1920, 1080
>Gen7.5	1920, 1080
>                       VSYNCSHIFT_A (0x00060028): 0x00000000
>                      PIPEA_DATA_M1 (0x00060030): 0x00000000
>Gen5	TU 1, val 0x0 0
>Gen7.5	TU 1, val 0x0 0
>                      PIPEA_DATA_N1 (0x00060034): 0x00000000
>Gen5	val 0x0 0
>Gen7.5	val 0x0 0
>                      PIPEA_DATA_M2 (0x00060038): 0x00000000
>Gen5	TU 1, val 0x0 0
>                      PIPEA_DATA_N2 (0x0006003c): 0x00000000
>Gen5	val 0x0 0
>                      PIPEA_LINK_M1 (0x00060040): 0x00000000
>Gen5	val 0x0 0
>Gen7.5	val 0x0 0
>                      PIPEA_LINK_N1 (0x00060044): 0x00000000
>Gen5	val 0x0 0
>Gen7.5	val 0x0 0
>                      PIPEA_LINK_M2 (0x00060048): 0x00000000
>Gen5	val 0x0 0
>                      PIPEA_LINK_N2 (0x0006004c): 0x00000000
>Gen5	val 0x0 0
>                        FDI_TXA_CTL (0x00060100): 0x00000000
>Gen5	disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable
>                           HTOTAL_B (0x00061000): 0x00000000
>Gen2	1 active, 1 total
>Gen5	1 active, 1 total
>Gen7.5	1 active, 1 total
>                           HBLANK_B (0x00061004): 0x00000000
>Gen2	1 start, 1 end
>Gen5	1 start, 1 end
>Gen7.5	1 start, 1 end
>                            HSYNC_B (0x00061008): 0x00000000
>Gen2	1 start, 1 end
>Gen5	1 start, 1 end
>Gen7.5	1 start, 1 end
>                           VTOTAL_B (0x0006100c): 0x00000000
>Gen2	1 active, 1 total
>Gen5	1 active, 1 total
>Gen7.5	1 active, 1 total
>                           VBLANK_B (0x00061010): 0x00000000
>Gen2	1 start, 1 end
>Gen5	1 start, 1 end
>Gen7.5	1 start, 1 end
>                            VSYNC_B (0x00061014): 0x00000000
>Gen2	1 start, 1 end
>Gen5	1 start, 1 end
>Gen7.5	1 start, 1 end
>                           PIPEBSRC (0x0006101c): 0x00000000
>Gen2	1, 1
>Gen5	1, 1
>Gen7.5	1, 1
>                       VSYNCSHIFT_B (0x00061028): 0x00000000
>                      PIPEB_DATA_M1 (0x00061030): 0x00000000
>Gen5	TU 1, val 0x0 0
>Gen7.5	TU 1, val 0x0 0
>                      PIPEB_DATA_N1 (0x00061034): 0x00000000
>Gen5	val 0x0 0
>Gen7.5	val 0x0 0
>                      PIPEB_DATA_M2 (0x00061038): 0x00000000
>Gen5	TU 1, val 0x0 0
>                      PIPEB_DATA_N2 (0x0006103c): 0x00000000
>Gen5	val 0x0 0
>                      PIPEB_LINK_M1 (0x00061040): 0x00000000
>Gen5	val 0x0 0
>Gen7.5	val 0x0 0
>                      PIPEB_LINK_N1 (0x00061044): 0x00000000
>Gen5	val 0x0 0
>Gen7.5	val 0x0 0
>                      PIPEB_LINK_M2 (0x00061048): 0x00000000
>Gen5	val 0x0 0
>                      PIPEB_LINK_N2 (0x0006104c): 0x00000000
>Gen5	val 0x0 0
>                        FDI_TXB_CTL (0x00061100): 0x00000000
>Gen2	disabled, pipe A, -hsync, -vsync
>Gen5	disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable
>                           HTOTAL_C (0x00062000): 0x00000000
>Gen5	1 active, 1 total
>Gen7.5	1 active, 1 total
>                           HBLANK_C (0x00062004): 0x00000000
>Gen5	1 start, 1 end
>Gen7.5	1 start, 1 end
>                            HSYNC_C (0x00062008): 0x00000000
>Gen5	1 start, 1 end
>Gen7.5	1 start, 1 end
>                           VTOTAL_C (0x0006200c): 0x00000000
>Gen5	1 active, 1 total
>Gen7.5	1 active, 1 total
>                           VBLANK_C (0x00062010): 0x00000000
>Gen5	1 start, 1 end
>Gen7.5	1 start, 1 end
>                            VSYNC_C (0x00062014): 0x00000000
>Gen5	1 start, 1 end
>Gen7.5	1 start, 1 end
>                           PIPECSRC (0x0006201c): 0x00000000
>Gen5	1, 1
>Gen7.5	1, 1
>                       VSYNCSHIFT_C (0x00062028): 0x00000000
>                      PIPEC_DATA_M1 (0x00062030): 0x00000000
>Gen5	TU 1, val 0x0 0
>Gen7.5	TU 1, val 0x0 0
>                      PIPEC_DATA_N1 (0x00062034): 0x00000000
>Gen5	val 0x0 0
>Gen7.5	val 0x0 0
>                      PIPEC_DATA_M2 (0x00062038): 0x00000000
>Gen5	TU 1, val 0x0 0
>                      PIPEC_DATA_N2 (0x0006203c): 0x00000000
>Gen5	val 0x0 0
>                      PIPEC_LINK_M1 (0x00062040): 0x00000000
>Gen5	val 0x0 0
>Gen7.5	val 0x0 0
>                      PIPEC_LINK_N1 (0x00062044): 0x00000000
>Gen5	val 0x0 0
>Gen7.5	val 0x0 0
>                      PIPEC_LINK_M2 (0x00062048): 0x00000000
>Gen5	val 0x0 0
>                      PIPEC_LINK_N2 (0x0006204c): 0x00000000
>Gen5	val 0x0 0
>                        FDI_TXC_CTL (0x00062100): 0x00000000
>Gen5	disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable
>                          CPU_eDP_A (0x00064000): 0x80000003
>Gen7.5	enabled not reversed x2 detected
>                        PFA_WIN_POS (0x00068070): 0x00000000
>Gen5	0, 0
>Gen7.5	0, 0
>                       PFA_WIN_SIZE (0x00068074): 0x00000000
>Gen5	0, 0
>Gen7.5	0, 0
>                          PFA_CTL_1 (0x00068080): 0x00000000
>Gen5	disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1
>Gen7.5	disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1
>                          PFA_CTL_2 (0x00068084): 0x00007de4
>Gen5	vscale 0.983521
>                          PFA_CTL_3 (0x00068088): 0x00000000
>Gen5	vscale initial phase 0.000000
>                          PFA_CTL_4 (0x00068090): 0x00007c40
>Gen5	hscale 0.970703
>                        PFB_WIN_POS (0x00068870): 0x00000000
>Gen5	0, 0
>Gen7.5	0, 0
>                       PFB_WIN_SIZE (0x00068874): 0x00000000
>Gen5	0, 0
>Gen7.5	0, 0
>                          PFB_CTL_1 (0x00068880): 0x00000000
>Gen5	disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1
>Gen7.5	disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1
>                          PFB_CTL_2 (0x00068884): 0x00000000
>Gen5	vscale 0.000000
>                          PFB_CTL_3 (0x00068888): 0x00000000
>Gen5	vscale initial phase 0.000000
>                          PFB_CTL_4 (0x00068890): 0x00000000
>Gen5	hscale 0.000000
>                        PFC_WIN_POS (0x00069070): 0x00000000
>Gen5	0, 0
>Gen7.5	0, 0
>                       PFC_WIN_SIZE (0x00069074): 0x00000000
>Gen5	0, 0
>Gen7.5	0, 0
>                          PFC_CTL_1 (0x00069080): 0x00000000
>Gen5	disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1
>Gen7.5	disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1
>                          PFC_CTL_2 (0x00069084): 0x00000000
>Gen5	vscale 0.000000
>                          PFC_CTL_3 (0x00069088): 0x00000000
>Gen5	vscale initial phase 0.000000
>                          PFC_CTL_4 (0x00069090): 0x00000000
>Gen5	hscale 0.000000
>                          PIPEACONF (0x00070008): 0x00000000
>Gen2	disabled, single-wide
>Gen5	disabled, single-wide
>Gen7.5	disabled, single-wide
>                           DSPACNTR (0x00070180): 0xd9000400
>Gen2	enabled, pipe B
>Gen5	enabled, pipe B
>Gen7.5	enabled, pipe B
>                           DSPABASE (0x00070184): 0x00000000
>                         DSPASTRIDE (0x00070188): 0x00001e00
>Gen2	7680 bytes
>Gen5	120
>Gen7.5	120
>                           DSPASURF (0x0007019c): 0x02a3a000
>                        DSPATILEOFF (0x000701a4): 0x00000000
>Gen5	0, 0
>Gen7.5	0, 0
>                          PIPEBCONF (0x00071008): 0x00000000
>Gen2	disabled, single-wide
>Gen5	disabled, single-wide
>Gen7.5	disabled, single-wide
>                           DSPBCNTR (0x00071180): 0x00000000
>Gen2	disabled, pipe A
>Gen5	disabled, pipe A
>Gen7.5	disabled, pipe A
>                           DSPBBASE (0x00071184): 0x00000000
>                         DSPBSTRIDE (0x00071188): 0x00000000
>Gen2	0 bytes
>Gen5	0
>Gen7.5	0
>                           DSPBSURF (0x0007119c): 0x00000000
>                        DSPBTILEOFF (0x000711a4): 0x00000000
>Gen5	0, 0
>Gen7.5	0, 0
>                          PIPECCONF (0x00072008): 0x00000000
>Gen5	disabled, single-wide
>Gen7.5	disabled, single-wide
>                           DSPCCNTR (0x00072180): 0x00000000
>Gen5	disabled, pipe A
>Gen7.5	disabled, pipe A
>                           DSPCBASE (0x00072184): 0x00000000
>                         DSPCSTRIDE (0x00072188): 0x00000000
>Gen5	0
>Gen7.5	0
>                           DSPCSURF (0x0007219c): 0x00000000
>                        DSPCTILEOFF (0x000721a4): 0x00000000
>Gen5	0, 0
>Gen7.5	0, 0
>                         PCH_DPLL_A (0x000c6014): 0x0354012e
>Gen5	disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 3, FPA1 P1 2, refclk default 120Mhz, sdvo/hdmi mul 1
>                         PCH_DPLL_B (0x000c6018): 0x0354012e
>Gen5	disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 3, FPA1 P1 2, refclk default 120Mhz, sdvo/hdmi mul 1
>                           PCH_FPA0 (0x000c6040): 0x0354012e
>Gen5	n = 20, m1 = 1, m2 = 46
>                           PCH_FPA1 (0x000c6044): 0x0354012e
>Gen5	n = 20, m1 = 1, m2 = 46
>                           PCH_FPB0 (0x000c6048): 0x0354012e
>Gen5	n = 20, m1 = 1, m2 = 46
>                           PCH_FPB1 (0x000c604c): 0x0354012e
>Gen5	n = 20, m1 = 1, m2 = 46
>                   PCH_DREF_CONTROL (0x000c6200): 0x0354012e
>Gen5	cpu source disable, ssc_source disable, nonspread_source disable, superspread_source enable, ssc4_mode downspread, ssc1 enable, ssc4 disable
>                    PCH_RAWCLK_FREQ (0x000c6204): 0x00000018
>Gen5	FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 24
>                   PCH_DPLL_TMR_CFG (0x000c6208): 0x00000018
>                     PCH_SSC4_PARMS (0x000c6210): 0x00000018
>                 PCH_SSC4_AUX_PARMS (0x000c6214): 0x00000018
>                PCH_DPLL_ANALOG_CTL (0x000c6300): 0x00000018
>                       PCH_DPLL_SEL (0x000c7000): 0x00000018
>Gen5	FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 24
>                      PCH_PP_STATUS (0x000c7200): 0x80000008
>Gen5	on, not ready, sequencing idle
>Gen7.5	on, not ready, sequencing idle
>                     PCH_PP_CONTROL (0x000c7204): 0xabcd0007
>Gen5	blacklight enabled, power down on reset, panel on
>Gen7.5	blacklight enabled, power down on reset, panel on
>                   PCH_PP_ON_DELAYS (0x000c7208): 0x07d00001
>                  PCH_PP_OFF_DELAYS (0x000c720c): 0x01900001
>                     PCH_PP_DIVISOR (0x000c7210): 0x0004af06
>                   BLC_PWM_PCH_CTL1 (0x000c8250): 0xc0000000
>Gen5	enable 1, override 1, inverted polarity 0
>Gen7.5	enable 1, override 1, inverted polarity 0
>                   BLC_PWM_PCH_CTL2 (0x000c8254): 0x0354012e
>Gen5	freq 852, cycle 302
>Gen7.5	freq 852, cycle 302
>                     TRANS_HTOTAL_A (0x000e0000): 0x0354012e
>Gen5	303 active, 853 total
>Gen7.5	303 active, 853 total
>                     TRANS_HBLANK_A (0x000e0004): 0x0354012e
>Gen5	303 start, 853 end
>Gen7.5	303 start, 853 end
>                      TRANS_HSYNC_A (0x000e0008): 0x0354012e
>Gen5	303 start, 853 end
>Gen7.5	303 start, 853 end
>                     TRANS_VTOTAL_A (0x000e000c): 0x0354012e
>Gen5	303 active, 853 total
>Gen7.5	303 active, 853 total
>                     TRANS_VBLANK_A (0x000e0010): 0x0354012e
>Gen5	303 start, 853 end
>Gen7.5	303 start, 853 end
>                      TRANS_VSYNC_A (0x000e0014): 0x0354012e
>Gen5	303 start, 853 end
>Gen7.5	303 start, 853 end
>                 TRANS_VSYNCSHIFT_A (0x000e0028): 0x0354012e
>                     TRANSA_DATA_M1 (0x000e0030): 0x0354012e
>Gen5	TU 2, val 0x54012e 5505326
>                     TRANSA_DATA_N1 (0x000e0034): 0x0354012e
>Gen5	val 0x54012e 5505326
>                     TRANSA_DATA_M2 (0x000e0038): 0x0354012e
>Gen5	TU 2, val 0x54012e 5505326
>                     TRANSA_DATA_N2 (0x000e003c): 0x0354012e
>Gen5	val 0x54012e 5505326
>                  TRANSA_DP_LINK_M1 (0x000e0040): 0x0354012e
>Gen5	val 0x54012e 5505326
>                  TRANSA_DP_LINK_N1 (0x000e0044): 0x0354012e
>Gen5	val 0x54012e 5505326
>                  TRANSA_DP_LINK_M2 (0x000e0048): 0x0354012e
>Gen5	val 0x54012e 5505326
>                  TRANSA_DP_LINK_N2 (0x000e004c): 0x0354012e
>Gen5	val 0x54012e 5505326
>                     TRANS_DP_CTL_A (0x000e0300): 0x00000000
>Gen5	val 0x54012e 5505326
>                     TRANS_HTOTAL_B (0x000e1000): 0x0354012e
>Gen5	303 active, 853 total
>                     TRANS_HBLANK_B (0x000e1004): 0x0354012e
>Gen5	303 start, 853 end
>                      TRANS_HSYNC_B (0x000e1008): 0x0354012e
>Gen5	303 start, 853 end
>                     TRANS_VTOTAL_B (0x000e100c): 0x0354012e
>Gen5	303 active, 853 total
>                     TRANS_VBLANK_B (0x000e1010): 0x0354012e
>Gen5	303 start, 853 end
>                      TRANS_VSYNC_B (0x000e1014): 0x0354012e
>Gen5	303 start, 853 end
>                 TRANS_VSYNCSHIFT_B (0x000e1028): 0x0354012e
>                     TRANSB_DATA_M1 (0x000e1030): 0x0354012e
>Gen5	TU 2, val 0x54012e 5505326
>                     TRANSB_DATA_N1 (0x000e1034): 0x0354012e
>Gen5	val 0x54012e 5505326
>                     TRANSB_DATA_M2 (0x000e1038): 0x0354012e
>Gen5	TU 2, val 0x54012e 5505326
>                     TRANSB_DATA_N2 (0x000e103c): 0x0354012e
>Gen5	val 0x54012e 5505326
>                  TRANSB_DP_LINK_M1 (0x000e1040): 0x0354012e
>Gen5	val 0x54012e 5505326
>                  TRANSB_DP_LINK_N1 (0x000e1044): 0x0354012e
>Gen5	val 0x54012e 5505326
>                  TRANSB_DP_LINK_M2 (0x000e1048): 0x0354012e
>Gen5	val 0x54012e 5505326
>                  TRANSB_DP_LINK_N2 (0x000e104c): 0x0354012e
>Gen5	val 0x54012e 5505326
>                           PCH_ADPA (0x000e1100): 0x0354012e
>Gen5	disabled, pipe A, +hsync, -vsync
>                              HDMIB (0x000e1140): 0x00000000
>Gen5	disabled pipe A 8bpc SDVO DVI audio disabled -vsync -hsync non-detected
>                              HDMIC (0x000e1150): 0x00000000
>Gen5	disabled pipe A 8bpc SDVO DVI audio disabled -vsync -hsync non-detected
>                              HDMID (0x000e1160): 0x00000000
>Gen5	disabled pipe A 8bpc SDVO DVI audio disabled -vsync -hsync non-detected
>                           PCH_LVDS (0x000e1180): 0x00000000
>Gen5	disabled, pipe A, 18 bit, 1 channel
>                     TRANS_DP_CTL_B (0x000e1300): 0x00000000
>Gen5	disabled, pipe A, 18 bit, 1 channel
>                     TRANS_HTOTAL_C (0x000e2000): 0x00000000
>Gen5	1 active, 1 total
>                     TRANS_HBLANK_C (0x000e2004): 0x00000000
>Gen5	1 start, 1 end
>                      TRANS_HSYNC_C (0x000e2008): 0x00000000
>Gen5	1 start, 1 end
>                     TRANS_VTOTAL_C (0x000e200c): 0x00000000
>Gen5	1 active, 1 total
>                     TRANS_VBLANK_C (0x000e2010): 0x00000000
>Gen5	1 start, 1 end
>                      TRANS_VSYNC_C (0x000e2014): 0x00000000
>Gen5	1 start, 1 end
>                 TRANS_VSYNCSHIFT_C (0x000e2028): 0x00000000
>                     TRANSC_DATA_M1 (0x000e2030): 0x00000000
>Gen5	TU 1, val 0x0 0
>                     TRANSC_DATA_N1 (0x000e2034): 0x00000000
>Gen5	val 0x0 0
>                     TRANSC_DATA_M2 (0x000e2038): 0x00000000
>Gen5	TU 1, val 0x0 0
>                     TRANSC_DATA_N2 (0x000e203c): 0x00000000
>Gen5	val 0x0 0
>                  TRANSC_DP_LINK_M1 (0x000e2040): 0x00000000
>Gen5	val 0x0 0
>                  TRANSC_DP_LINK_N1 (0x000e2044): 0x00000000
>Gen5	val 0x0 0
>                  TRANSC_DP_LINK_M2 (0x000e2048): 0x00000000
>Gen5	val 0x0 0
>                  TRANSC_DP_LINK_N2 (0x000e204c): 0x00000000
>Gen5	val 0x0 0
>                     TRANS_DP_CTL_C (0x000e2300): 0x00000000
>Gen5	val 0x0 0
>                           PCH_DP_B (0x000e4100): 0x0354012e
>                           PCH_DP_C (0x000e4200): 0x0354012e
>                           PCH_DP_D (0x000e4300): 0x0354012e
>                         TRANSACONF (0x000f0008): 0x0354012e
>Gen5	disable, inactive, rsvd
>Gen7.5	disable, inactive, rsvd
>                        FDI_RXA_CTL (0x000f000c): 0x0354012e
>Gen5	disable, train pattern pattern_1, port width X3, (null),link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report enable,scrambing enable, enhanced framing disable, RawClk
>                       FDI_RXA_MISC (0x000f0010): 0x0354012e
>Gen5	FDI Delay 302
>Gen7.5	FDI Delay 302
>                        FDI_RXA_IIR (0x000f0014): 0x0354012e
>                        FDI_RXA_IMR (0x000f0018): 0x0354012e
>                    FDI_RXA_TUSIZE1 (0x000f0030): 0x0354012e
>                    FDI_RXA_TUSIZE2 (0x000f0038): 0x0354012e
>                         TRANSBCONF (0x000f1008): 0x0354012e
>Gen5	disable, inactive, rsvd
>                        FDI_RXB_CTL (0x000f100c): 0x0354012e
>Gen5	disable, train pattern pattern_1, port width X3, (null),link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report enable,scrambing enable, enhanced framing disable, RawClk
>                       FDI_RXB_MISC (0x000f1010): 0x0354012e
>Gen5	FDI Delay 302
>                        FDI_RXB_IIR (0x000f1014): 0x0354012e
>                        FDI_RXB_IMR (0x000f1018): 0x0354012e
>                    FDI_RXB_TUSIZE1 (0x000f1030): 0x0354012e
>                    FDI_RXB_TUSIZE2 (0x000f1038): 0x0354012e
>                         TRANSCCONF (0x000f2008): 0x0354012e
>Gen5	disable, inactive, rsvd
>                        FDI_RXC_CTL (0x000f200c): 0x0354012e
>Gen5	disable, train pattern pattern_1, port width X3, (null),link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report enable,scrambing enable, enhanced framing disable, RawClk
>                       FDI_RXC_MISC (0x000f2010): 0x0354012e
>Gen5	FDI Delay 302
>                    FDI_RXC_TUSIZE1 (0x000f2030): 0x0354012e
>                    FDI_RXC_TUSIZE2 (0x000f2038): 0x0354012e
>                      FDI_PLL_CTL_1 (0x000fe000): 0x0354012e
>                      FDI_PLL_CTL_2 (0x000fe004): 0x0354012e
>                      RCS_MODE_GEN7 (0x0000229c): 0x0000a000
>                      VCS_MODE_GEN7 (0x0001229c): 0x00008000
>                      BCS_MODE_GEN7 (0x0002229c): 0x00008000
>                     VECS_MODE_GEN7 (0x0001a29c): 0x00008000
>                     HSW_FUSE_STRAP (0x00042014): 0x20100042
>                  HSW_PWR_WELL_BIOS (0x00045400): 0x40000000
>                HSW_PWR_WELL_DRIVER (0x00045404): 0xc0000000
>                  HSW_PWR_WELL_KVMR (0x00045408): 0x40000000
>                 HSW_PWR_WELL_DEBUG (0x0004540c): 0x40000000
>                  HSW_PWR_WELL_CTL5 (0x00045410): 0x0004050f
>                  HSW_PWR_WELL_CTL6 (0x00045414): 0x00000000
>                          WM_PIPE_A (0x00045100): 0x00140006
>Gen7.5	primary 20, sprite 0, pipe 6
>                      WM_LINETIME_A (0x00045270): 0x00310078
>                          WM_PIPE_B (0x00045104): 0x00000000
>Gen7.5	primary 0, sprite 0, pipe 0
>                      WM_LINETIME_B (0x00045274): 0x00000000
>                          WM_PIPE_C (0x00045200): 0x00000000
>Gen7.5	primary 0, sprite 0, pipe 0
>                      WM_LINETIME_C (0x00045278): 0x00000000
>                            WM_LP_1 (0x00045108): 0x8220db0a
>Gen7.5	enabled, latency 2, fbc 2, pri 219, cur 10
>                            WM_LP_2 (0x0004510c): 0x863a3616
>Gen7.5	enabled, latency 6, fbc 3, pri 566, cur 22
>                            WM_LP_3 (0x00045110): 0x8842b81a
>Gen7.5	enabled, latency 8, fbc 4, pri 696, cur 26
>                        WM_LP_SPR_1 (0x00045120): 0x00000000
>                        WM_LP_SPR_2 (0x00045124): 0x00000000
>                        WM_LP_SPR_3 (0x00045128): 0x00000000
>                            WM_MISC (0x00045260): 0x00000000
>                             WM_DBG (0x00045280): 0x80000000
>                    GEN8_MASTER_IRQ (0x00044200): 0x80000000
>                       GEN8_GT_ISR0 (0x00044300): 0x00000000
>                       GEN8_GT_IMR0 (0x00044304): 0xfefefede
>                       GEN8_GT_IIR0 (0x00044308): 0x00000000
>                       GEN8_GT_IER0 (0x0004430c): 0x01010121
>                       GEN8_GT_ISR1 (0x00044310): 0x00000000
>                       GEN8_GT_IMR1 (0x00044314): 0xfefefefe
>                       GEN8_GT_IIR1 (0x00044318): 0x00000000
>                       GEN8_GT_IER1 (0x0004431c): 0x01010101
>                       GEN8_GT_ISR2 (0x00044320): 0x00000000
>                       GEN8_GT_IMR2 (0x00044324): 0xffffff8f
>                       GEN8_GT_IIR2 (0x00044328): 0x00000000
>                       GEN8_GT_IER2 (0x0004432c): 0x00000070
>                       GEN8_GT_ISR3 (0x00044330): 0x00000000
>                       GEN8_GT_IMR3 (0x00044334): 0xfffffefe
>                       GEN8_GT_IIR3 (0x00044338): 0x00000000
>                       GEN8_GT_IER3 (0x0004433c): 0x00000101
>                  GEN8_DE_PIPE_ISR0 (0x00044400): 0x00000000
>                  GEN8_DE_PIPE_IMR0 (0x00044404): 0x6ffff8ef
>                  GEN8_DE_PIPE_IIR0 (0x00044408): 0x00000000
>                  GEN8_DE_PIPE_IER0 (0x0004440c): 0x90000711
>                  GEN8_DE_PIPE_ISR1 (0x00044410): 0x00000000
>                  GEN8_DE_PIPE_IMR1 (0x00044414): 0xeffff8ef
>                  GEN8_DE_PIPE_IIR1 (0x00044418): 0x00000000
>                  GEN8_DE_PIPE_IER1 (0x0004441c): 0x90000711
>                  GEN8_DE_PIPE_ISR2 (0x00044420): 0x00000000
>                  GEN8_DE_PIPE_IMR2 (0x00044424): 0xeffff8ef
>                  GEN8_DE_PIPE_IIR2 (0x00044428): 0x00000000
>                  GEN8_DE_PIPE_IER2 (0x0004442c): 0x90000711
>                   GEN8_DE_PORT_ISR (0x00044440): 0x00000000
>                   GEN8_DE_PORT_IMR (0x00044444): 0x00000008
>                   GEN8_DE_PORT_IIR (0x00044448): 0x00000000
>                   GEN8_DE_PORT_IER (0x0004444c): 0x00000001
>                   GEN8_DE_MISC_ISR (0x00044460): 0x00000000
>                   GEN8_DE_MISC_IMR (0x00044464): 0xbbf88000
>                   GEN8_DE_MISC_IIR (0x00044468): 0x00000000
>                   GEN8_DE_MISC_IER (0x0004446c): 0x00000000
>                       GEN8_PCU_ISR (0x000444e0): 0x00000000
>                       GEN8_PCU_IMR (0x000444e4): 0xffffffff
>                       GEN8_PCU_IIR (0x000444e8): 0x00000000
>                       GEN8_PCU_IER (0x000444ec): 0x00000000
>                         RENDER_IMR (0x000020a8): 0xfffffeff
>                            BSD_IMR (0x000120a8): 0xfffffefe
>                            BLT_IMR (0x000220a8): 0xfeffffff
>                       PRIVATE_PAT1 (0x000040e0): 0x000a0907
>                       PRIVATE_PAT2 (0x000040e4): 0x3b2b1b0b
>                     AUD_TCA_CONFIG (0x00065000): 0x0070fa60
>                     AUD_TCB_CONFIG (0x00065100): 0x0070fa60
>                     AUD_TCC_CONFIG (0x00065200): 0x0070fa60
>                   AUD_C1_MISC_CTRL (0x00065010): 0x00000044
>                   AUD_C2_MISC_CTRL (0x00065110): 0x00000044
>                   AUD_C3_MISC_CTRL (0x00065210): 0x00000044
>                        AUD_VID_DID (0x00065020): 0x80862808
>                            AUD_RID (0x00065024): 0x00100000
>               AUD_TCA_M_CTS_ENABLE (0x00065028): 0x00000000
>               AUD_TCB_M_CTS_ENABLE (0x00065128): 0x00000000
>               AUD_TCC_M_CTS_ENABLE (0x00065228): 0x00000000
>                          AUD_PWRST (0x0006504c): 0x0fffffff
>                  AUD_TCA_EDID_DATA (0x00065050): 0x00000000
>                  AUD_TCB_EDID_DATA (0x00065150): 0x00000000
>                  AUD_TCC_EDID_DATA (0x00065250): 0x00000000
>                     AUD_TCA_INFOFR (0x00065054): 0x00000000
>                     AUD_TCB_INFOFR (0x00065154): 0x00000000
>                     AUD_TCC_INFOFR (0x00065254): 0x00000000
>                  AUD_PIPE_CONV_CFG (0x0006507c): 0x00770007
>                    AUD_C1_DIG_CNVT (0x00065080): 0x00000000
>                    AUD_C2_DIG_CNVT (0x00065180): 0x00000000
>                    AUD_C3_DIG_CNVT (0x00065280): 0x00000000
>                    AUD_C1_STR_DESC (0x00065084): 0x00000031
>                    AUD_C2_STR_DESC (0x00065184): 0x00000031
>                    AUD_C3_STR_DESC (0x00065284): 0x00000031
>                   AUD_OUT_CHAN_MAP (0x00065088): 0x00000000
> AUD_TCA_PIN_PIPE_CONN_ENTRY_LENGTH (0x000650a8): 0x00000003
> AUD_TCB_PIN_PIPE_CONN_ENTRY_LENGTH (0x000651a8): 0x00000003
> AUD_TCC_PIN_PIPE_CONN_ENTRY_LENGTH (0x000652a8): 0x00000003
>             AUD_PIPE_CONN_SEL_CTRL (0x000650ac): 0x00030303
>            AUD_TCA_DIP_ELD_CTRL_ST (0x000650b4): 0x00005442
>            AUD_TCB_DIP_ELD_CTRL_ST (0x000651b4): 0x00005442
>            AUD_TCC_DIP_ELD_CTRL_ST (0x000652b4): 0x00005442
>                 AUD_PIN_ELD_CP_VLD (0x000650c0): 0x00000000
>               AUD_HDMI_FIFO_STATUS (0x000650d4): 0x00000000
>                           AUD_ICOI (0x00065f00): 0x00000000
>                           AUD_IRII (0x00065f04): 0x00000000
>                            AUD_ICS (0x00065f08): 0x00000000
>                 AUD_CHICKENBIT_REG (0x00065f10): 0xc0000000
>                  AUD_DP_DIP_STATUS (0x00065f20): 0x00004a52
>                      AUD_TCA_M_CTS (0x00065f44): 0x00000000
>                      AUD_TCB_M_CTS (0x00065f54): 0x00000000
>                      AUD_TCC_M_CTS (0x00065f64): 0x00000000

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Attachments on bug 94578: 122353 | 122354 | 122355 | 122356 | 122357 | 122358 | 122359

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