Attachment 123554 Details for Bug 95044 – Remove high-speed mode for GDDR3

[patch] Remove high-speed mode for GDDR3

0001-nvkm-fb-Remove-GDDR3-high-speed-mode.patch (text/plain), 2.31 KB, created by Roy on 2016-05-08 21:41:34 UTC

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Creator: Roy

Created: 2016-05-08 21:41:34 UTC

Size: 2.31 KB

patch

obsolete

>From becbb79209b84a9c2961b45631718e1ed54e8c44 Mon Sep 17 00:00:00 2001
>From: Roy Spliet <rspliet@eclipso.eu>
>Date: Sun, 8 May 2016 22:11:14 +0100
>Subject: [PATCH] nvkm/fb: Remove GDDR3 high speed mode
>
>1) NVIDIA never reads the EMRS2 value on reclocking for GDDR3 on Tesla
>2) Different vendors have different meanings for this bit. The specific Qimonda
>   spec-sheet I found only applies for a card that doesn't use this feature.
>3) FDBZ #95044: bit set, tries to select a CL of 5. The bit likely has a
>   different meaning here.
>
>So remove until we are positive this distinction needs to be made and we
>know all the boundary conditions.
>
>Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
>---
> drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c | 18 +++++-------------
> 1 file changed, 5 insertions(+), 13 deletions(-)
>
>diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c
>index 60ece0a..0dc95ae 100644
>--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c
>+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c
>@@ -41,7 +41,7 @@ ramxlat(const struct ramxlat *xlat, int id)
> }
> 
> static const struct ramxlat
>-ramgddr3_cl_lo[] = {
>+ramgddr3_cl[] = {
> 	{ 5, 5 }, { 7, 7 }, { 8, 0 }, { 9, 1 }, { 10, 2 }, { 11, 3 }, { 12, 8 },
> 	/* the below are mentioned in some, but not all, gddr3 docs */
> 	{ 13, 9 }, { 14, 6 },
>@@ -52,14 +52,7 @@ ramgddr3_cl_lo[] = {
> };
> 
> static const struct ramxlat
>-ramgddr3_cl_hi[] = {
>-	{ 10, 2 }, { 11, 3 }, { 12, 4 }, { 13, 5 }, { 14, 6 }, { 15, 7 },
>-	{ 16, 0 }, { 17, 1 },
>-	{ -1 }
>-};
>-
>-static const struct ramxlat
>-ramgddr3_wr_lo[] = {
>+ramgddr3_wr[] = {
> 	{ 5, 2 }, { 7, 4 }, { 8, 5 }, { 9, 6 }, { 10, 7 },
> 	{ 11, 0 }, { 13 , 1 },
> 	/* the below are mentioned in some, but not all, gddr3 docs */
>@@ -70,7 +63,7 @@ ramgddr3_wr_lo[] = {
> int
> nvkm_gddr3_calc(struct nvkm_ram *ram)
> {
>-	int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi;
>+	int CL, WR, CWL, DLL = 0, ODT = 0, RON;
> 
> 	switch (ram->next->bios.timing_ver) {
> 	case 0x10:
>@@ -98,9 +91,8 @@ nvkm_gddr3_calc(struct nvkm_ram *ram)
> 		ODT =  (ram->mr[1] & 0xc) >> 2;
> 	}
> 
>-	hi = ram->mr[2] & 0x1;
>-	CL  = ramxlat(hi ? ramgddr3_cl_hi : ramgddr3_cl_lo, CL);
>-	WR  = ramxlat(ramgddr3_wr_lo, WR);
>+	CL  = ramxlat(ramgddr3_cl, CL);
>+	WR  = ramxlat(ramgddr3_wr, WR);
> 	if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0)
> 		return -EINVAL;
> 
>-- 
>2.5.5
>

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