Attachment 124090 Details for Bug 95367 – [PATCH for v4.5] drm/i915: Fix watermarks for VLV/CHV

[patch] [PATCH for v4.5] drm/i915: Fix watermarks for VLV/CHV

45-0001-drm-i915-Fix-watermarks-for-VLV-CHV.patch (text/plain), 4.93 KB, created by Ville Syrjala on 2016-05-25 19:41:34 UTC

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Creator: Ville Syrjala

Created: 2016-05-25 19:41:34 UTC

Size: 4.93 KB

patch

obsolete

>From 1ef89060a936433f552014bd0af9547ee2bd23d5 Mon Sep 17 00:00:00 2001
>From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
>Date: Wed, 9 Mar 2016 19:07:25 +0200
>Subject: [PATCH for v4.5] drm/i915: Fix watermarks for VLV/CHV
>MIME-Version: 1.0
>Content-Type: text/plain; charset=UTF-8
>Content-Transfer-Encoding: 8bit
>
>commit caed361d83b2 upstream
>
>commit 92826fcdfc14 ("drm/i915: Calculate watermark related members in the crtc_state, v4.")
>broke thigns by removing the pre vs. post wm update distinction. We also
>lost the pre plane wm update entirely for VLV/CHV from the crtc enable
>path.
>
>This caused underruns on modeset and plane enable/disable on CHV,
>and often those can lead to a dead pipe.
>
>So let's bring back the pre vs. post thing, and let's toss in an
>explicit wm update to valleyview_crtc_enable() to avoid having to
>put it into the common code.
>
>This is more or less a partial revert of the offending commit.
>
>Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>Cc: drm-intel-fixes@lists.freedesktop.org
>Fixes: 92826fcdfc14 ("drm/i915: Calculate watermark related members in the crtc_state, v4.")
>Signed-off-by: Ville SyrjÃ¤lÃ¤ <ville.syrjala@linux.intel.com>
>Link: http://patchwork.freedesktop.org/patch/msgid/1457543247-13987-4-git-send-email-ville.syrjala@linux.intel.com
>Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>Cc: <stable@vger.kernel.org> # v4.5
>---
> drivers/gpu/drm/i915/intel_atomic.c  |  3 ++-
> drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++------
> drivers/gpu/drm/i915/intel_drv.h     |  2 +-
> 3 files changed, 18 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
>index d0b1c9afa35e..6314446f58fa 100644
>--- a/drivers/gpu/drm/i915/intel_atomic.c
>+++ b/drivers/gpu/drm/i915/intel_atomic.c
>@@ -96,7 +96,8 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> 	crtc_state->update_pipe = false;
> 	crtc_state->disable_lp_wm = false;
> 	crtc_state->disable_cxsr = false;
>-	crtc_state->wm_changed = false;
>+	crtc_state->update_wm_pre = false;
>+	crtc_state->update_wm_post = false;
> 
> 	return &crtc_state->base;
> }
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 39b00b9daf2d..207391e89599 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -4816,7 +4816,7 @@ static void intel_post_plane_update(struct intel_crtc *crtc)
> 
> 	crtc->wm.cxsr_allowed = true;
> 
>-	if (pipe_config->wm_changed && pipe_config->base.active)
>+	if (pipe_config->update_wm_post && pipe_config->base.active)
> 		intel_update_watermarks(&crtc->base);
> 
> 	if (atomic->update_fbc)
>@@ -4850,7 +4850,7 @@ static void intel_pre_plane_update(struct intel_crtc *crtc)
> 		intel_set_memory_cxsr(dev_priv, false);
> 	}
> 
>-	if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed)
>+	if (!needs_modeset(&pipe_config->base) && pipe_config->update_wm_pre)
> 		intel_update_watermarks(&crtc->base);
> }
> 
>@@ -6229,6 +6229,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
> 
> 	intel_crtc_load_lut(crtc);
> 
>+	intel_update_watermarks(crtc);
> 	intel_enable_pipe(intel_crtc);
> 
> 	assert_vblank_disabled(crtc);
>@@ -11881,8 +11882,14 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
> 			 plane->base.id, was_visible, visible,
> 			 turn_off, turn_on, mode_changed);
> 
>-	if (turn_on || turn_off) {
>-		pipe_config->wm_changed = true;
>+	if (turn_on) {
>+		pipe_config->update_wm_pre = true;
>+
>+		/* must disable cxsr around plane enable/disable */
>+		if (plane->type != DRM_PLANE_TYPE_CURSOR)
>+			pipe_config->disable_cxsr = true;
>+	} else if (turn_off) {
>+		pipe_config->update_wm_post = true;
> 
> 		/* must disable cxsr around plane enable/disable */
> 		if (plane->type != DRM_PLANE_TYPE_CURSOR) {
>@@ -11891,7 +11898,9 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
> 			pipe_config->disable_cxsr = true;
> 		}
> 	} else if (intel_wm_need_update(plane, plane_state)) {
>-		pipe_config->wm_changed = true;
>+		/* FIXME bollocks */
>+		pipe_config->update_wm_pre = true;
>+		pipe_config->update_wm_post = true;
> 	}
> 
> 	if (visible || was_visible)
>@@ -12036,7 +12045,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
> 	}
> 
> 	if (mode_changed && !crtc_state->active)
>-		pipe_config->wm_changed = true;
>+		pipe_config->update_wm_post = true;
> 
> 	if (mode_changed && crtc_state->enable &&
> 	    dev_priv->display.crtc_compute_clock &&
>diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>index 1ae61f488987..c6f045ecb15a 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -367,7 +367,7 @@ struct intel_crtc_state {
> 
> 	bool update_pipe; /* can a fast modeset be performed? */
> 	bool disable_cxsr;
>-	bool wm_changed; /* watermarks are updated */
>+	bool update_wm_pre, update_wm_post; /* watermarks are updated */
> 
> 	/* Pipe source size (ie. panel fitter input size)
> 	 * All planes will be positioned inside this space,
>-- 
>2.7.4
>

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Attachments on bug 95367: 123650 | 123651 | 123652 | 124090 | 124091

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