Attachment 124807 Details for Bug 96753 – dmesg.log

dmesg.log

dmesg.log (text/plain), 67.87 KB, created by Humberto Israel Perez Rodriguez on 2016-06-30 18:37:11 UTC

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Creator: Humberto Israel Perez Rodriguez

Created: 2016-06-30 18:37:11 UTC

Size: 67.87 KB

patch

obsolete

>[  104.125172] kms_panel_fitting: executing
>[  104.126238] [drm:i915_gem_open] 
>[  104.127304] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  104.128332] [drm:i915_pages_create_for_stolen] offset=0x7f9000, size=16384
>[  104.129421] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  104.130353] [drm:i915_pages_create_for_stolen] offset=0x7fd000, size=16384
>[  104.131293] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  104.132266] [drm:i915_pages_create_for_stolen] offset=0x801000, size=16384
>[  104.133258] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  104.134213] [drm:i915_pages_create_for_stolen] offset=0x805000, size=16384
>[  104.135544] [drm:i915_gem_open] 
>[  104.167424] [drm:drm_mode_addfb2] [FB:88]
>[  104.181364] [drm:drm_mode_addfb2] [FB:107]
>[  104.188737] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  104.189120] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[  104.189487] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[  104.189868] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[  104.190253] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  104.190644] [drm:skl_update_scaler] scaler_user index 0.31: staged scaling request for 640x480->1920x1080 scaler_users = 0x80000000
>[  104.191053] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  104.191474] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  104.191894] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[  104.192316] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  104.192745] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046c0d1000 for pipe A
>[  104.193189] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  104.193621] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  104.194060] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  104.194502] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  104.194953] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  104.195406] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  104.195855] [drm:intel_dump_pipe_config] requested mode:
>[  104.196291] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 640 1968 2018 2052 480 1084 1086 1122 0x48 0xa
>[  104.196761] [drm:intel_dump_pipe_config] adjusted mode:
>[  104.197221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  104.197700] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  104.198174] [drm:intel_dump_pipe_config] port clock: 270000
>[  104.198645] [drm:intel_dump_pipe_config] pipe src size: 640x480
>[  104.199111] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x80000000, scaler_id: -1
>[  104.199580] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  104.200059] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00f00000, size: 0x05a00438, enabled
>[  104.200527] [drm:intel_dump_pipe_config] ips: 0
>[  104.200995] [drm:intel_dump_pipe_config] double wide: 0
>[  104.201461] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  104.201954] [drm:intel_dump_pipe_config] planes on this crtc
>[  104.202451] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  104.202459] [drm:intel_dump_pipe_config] 	FB:60, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  104.202952] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  104.203463] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  104.203979] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  104.204487] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[  104.205012] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[  104.205534] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  104.206053] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[  104.206583] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[  104.207108] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  104.207644] [drm:skl_update_scaler] scaler_user index 0.31: staged scaling request for 640x480->1920x1080 scaler_users = 0x80000000
>[  104.208192] [drm:intel_atomic_setup_scalers] Attached scaler id 0.0 to CRTC:26
>[  104.208767] [drm:intel_edp_backlight_off] 
>[  104.283268] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  104.284802] [drm:intel_disable_pipe] disabling pipe A
>[  104.291722] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  104.292814] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x19001818, pins 0x00000010
>[  104.292815] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[  104.292827] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[  104.297336] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  104.298814] [drm:edp_panel_off] Turn eDP port A panel power off
>[  104.300237] [drm:wait_panel_off] Wait for panel power off time
>[  104.301642] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000002 control 00000060
>[  104.313303] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  104.313904] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  104.314476] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[  104.318469] [drm:wait_panel_status] Wait complete
>[  104.319042] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[  104.319054] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  104.319057] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  104.320770] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[  104.321338] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[  104.321910] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[  104.322474] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[  104.323047] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[  104.323620] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[  104.325200] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[  104.326792] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[  104.328370] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[  104.329912] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[  104.331444] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[  104.332968] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[  104.333525] [drm:verify_single_dpll_state] PORT PLL A
>[  104.334055] [drm:verify_single_dpll_state] PORT PLL B
>[  104.334573] [drm:verify_single_dpll_state] PORT PLL C
>[  104.335090] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[  104.335604] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[  104.434140] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000060
>[  104.450196] [drm:wait_panel_status] Wait complete
>[  104.450736] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000068
>[  104.451259] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  104.477484] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  104.478032] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  104.478548] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[  104.526576] [drm:intel_dp_get_dpcd] DPCD: 11 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  104.526579] [drm:edp_panel_on] Turn eDP port A panel power on
>[  104.526580] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  104.526583] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000068
>[  104.526584] [drm:wait_panel_status] Wait complete
>[  104.526585] [drm:wait_panel_on] Wait for panel power on
>[  104.526587] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 0000006b
>[  104.578324] [drm:wait_panel_status] Wait complete
>[  104.579749] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  104.580512] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  104.580512] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  104.580739] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  104.581272] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  104.581313] [drm:skylake_pfit_enable] for crtc_state = ffff88046c0d1000
>[  104.581314] [drm:skylake_pfit_enable] for crtc_state = ffff88046c0d1000 scaler_id = 0
>[  104.581373] [drm:skl_wm_flush_pipe] flush pipe B (pass 2)
>[  104.584693] [drm:skl_wm_flush_pipe] flush pipe C (pass 2)
>[  104.587919] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  104.587923] [drm:intel_enable_pipe] enabling pipe A
>[  104.587929] [drm:intel_edp_backlight_on] 
>[  104.587930] [drm:intel_panel_enable_backlight] pipe A
>[  104.587932] [drm:intel_panel_actually_set_backlight] set backlight PWM = 28800
>[  104.587934] [drm:intel_psr_enable] PSR not supported on this platform
>[  104.587934] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  104.592072] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[  104.592077] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[  104.592109] [drm:verify_single_dpll_state] PORT PLL A
>[  104.592157] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[  104.592159] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  104.592160] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  104.592161] [drm:skl_update_scaler] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  104.592171] [drm:intel_edp_backlight_off] 
>[  104.605960] [drm:intel_dp_get_dpcd] EDP DPCD : 02 fb c7
>[  104.606374] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink no
>[  104.606789] [drm:intel_dp_print_rates] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  104.607207] [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[  104.607618] [drm:intel_dp_print_rates] common rates: 162000, 270000
>[  104.642392] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  104.642832] [drm:intel_disable_pipe] disabling pipe A
>[  104.645886] [drm:edp_panel_off] Turn eDP port A panel power off
>[  104.646286] [drm:wait_panel_off] Wait for panel power off time
>[  104.646674] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000002 control 00000060
>[  104.658899] [drm:wait_panel_status] Wait complete
>[  104.659328] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[  104.659734] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  104.659735] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  104.659735] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[  104.660995] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[  104.661438] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  104.661881] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  104.662309] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[  104.662743] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[  104.663174] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[  104.663604] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[  104.664032] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[  104.664468] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[  104.664893] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[  104.665319] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[  104.665738] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[  104.666150] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[  104.666564] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[  104.666967] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[  104.667366] [drm:verify_single_dpll_state] PORT PLL A
>[  104.667768] [drm:verify_single_dpll_state] PORT PLL B
>[  104.668162] [drm:verify_single_dpll_state] PORT PLL C
>[  104.668559] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  104.668944] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  104.669332] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  104.669700] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  104.670074] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[  104.670989] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  104.671104] [drm:drm_mode_addfb2] [FB:80]
>[  104.671736] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  104.976900] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[  104.977289] [drm:wait_panel_status] Wait complete
>[  104.977649] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000068
>[  104.978024] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  105.004399] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  105.004814] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  105.005187] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[  105.097102] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  105.097109] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  105.097112] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[  105.097120] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[  105.097121] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[  105.097123] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  105.097124] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  105.097126] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  105.097127] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[  105.097128] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  105.097130] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a592800 for pipe A
>[  105.097130] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  105.097131] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  105.097132] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  105.097133] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  105.097134] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  105.097134] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  105.097135] [drm:intel_dump_pipe_config] requested mode:
>[  105.097136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  105.097137] [drm:intel_dump_pipe_config] adjusted mode:
>[  105.097138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  105.097140] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  105.097140] [drm:intel_dump_pipe_config] port clock: 270000
>[  105.097141] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  105.097141] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  105.097142] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  105.097143] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  105.097143] [drm:intel_dump_pipe_config] ips: 0
>[  105.097144] [drm:intel_dump_pipe_config] double wide: 0
>[  105.097145] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  105.097146] [drm:intel_dump_pipe_config] planes on this crtc
>[  105.097147] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[  105.097147] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  105.097148] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  105.097149] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[  105.097150] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[  105.097152] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  105.097154] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[  105.097155] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[  105.097156] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  105.097262] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[  105.097263] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[  105.097263] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[  105.097264] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[  105.097264] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[  105.097265] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[  105.097266] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[  105.097266] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[  105.097267] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[  105.097267] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[  105.097270] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[  105.097272] [drm:verify_single_dpll_state] PORT PLL A
>[  105.097273] [drm:verify_single_dpll_state] PORT PLL B
>[  105.097277] [drm:verify_single_dpll_state] PORT PLL C
>[  105.097288] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[  105.097289] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[  105.097344] [drm:edp_panel_on] Turn eDP port A panel power on
>[  105.097345] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  105.097348] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000068
>[  105.097350] [drm:wait_panel_status] Wait complete
>[  105.097350] [drm:wait_panel_on] Wait for panel power on
>[  105.097352] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000006b
>[  105.157324] [drm:wait_panel_status] Wait complete
>[  105.161152] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  105.161153] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  105.165079] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  105.169039] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  105.170354] [drm:skylake_pfit_enable] for crtc_state = ffff88046a592800
>[  105.170420] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[  105.171670] [drm:skl_wm_flush_pipe] flush pipe B (pass 2)
>[  105.172984] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  105.172985] [drm:intel_enable_pipe] enabling pipe A
>[  105.172991] [drm:intel_edp_backlight_on] 
>[  105.172992] [drm:intel_panel_enable_backlight] pipe A
>[  105.172993] [drm:intel_panel_actually_set_backlight] set backlight PWM = 28800
>[  105.172995] [drm:intel_psr_enable] PSR not supported on this platform
>[  105.172995] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  105.173022] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  105.173024] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  105.173027] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  105.173049] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  105.173050] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  105.173051] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  105.178177] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[  105.178180] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[  105.178208] [drm:verify_single_dpll_state] PORT PLL A
>[  105.178246] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[  105.178248] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  105.178249] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  105.178258] [drm:intel_edp_backlight_off] 
>[  105.248380] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  105.249448] [drm:intel_disable_pipe] disabling pipe A
>[  105.252230] [drm:edp_panel_off] Turn eDP port A panel power off
>[  105.253280] [drm:wait_panel_off] Wait for panel power off time
>[  105.254320] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000002 control 00000060
>[  105.266345] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  105.267392] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  105.268397] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[  105.269435] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  105.270477] [drm:wait_panel_status] Wait complete
>[  105.271509] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[  105.272587] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[  105.273664] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  105.274706] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  105.275729] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[  105.276757] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[  105.277760] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[  105.278736] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[  105.279713] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[  105.280695] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[  105.281678] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[  105.282662] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[  105.283644] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[  105.284632] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[  105.285643] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[  105.286653] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[  105.287643] [drm:verify_single_dpll_state] PORT PLL A
>[  105.288652] [drm:verify_single_dpll_state] PORT PLL B
>[  105.289648] [drm:verify_single_dpll_state] PORT PLL C
>[  105.290651] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  105.291652] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  105.292662] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  105.293633] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  105.294620] [drm:intel_power_well_disable] disabling dpio-common-a
>[  105.295575] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[  105.297693] [drm:drm_mode_addfb2] [FB:80]
>[  105.303396] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  105.304368] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[  105.305313] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[  105.306271] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[  105.307214] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  105.308181] [drm:skl_update_scaler] scaler_user index 0.31: staged scaling request for 800x600->1920x1080 scaler_users = 0x80000000
>[  105.309171] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  105.310186] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  105.311175] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[  105.312163] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  105.313164] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff880468239000 for pipe A
>[  105.314216] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  105.315253] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  105.316285] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  105.317350] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  105.318438] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  105.319509] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  105.320566] [drm:intel_dump_pipe_config] requested mode:
>[  105.321624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 800 1968 2018 2052 600 1084 1086 1122 0x48 0xa
>[  105.322754] [drm:intel_dump_pipe_config] adjusted mode:
>[  105.323880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  105.325072] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  105.326306] [drm:intel_dump_pipe_config] port clock: 270000
>[  105.327537] [drm:intel_dump_pipe_config] pipe src size: 800x600
>[  105.328750] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x80000000, scaler_id: -1
>[  105.329982] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  105.331256] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00f00000, size: 0x05a00438, enabled
>[  105.332500] [drm:intel_dump_pipe_config] ips: 0
>[  105.333714] [drm:intel_dump_pipe_config] double wide: 0
>[  105.334946] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  105.336245] [drm:intel_dump_pipe_config] planes on this crtc
>[  105.337519] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[  105.338804] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  105.340084] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  105.341335] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[  105.342579] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[  105.343816] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  105.345059] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[  105.346307] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[  105.347545] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  105.348812] [drm:skl_update_scaler] scaler_user index 0.31: staged scaling request for 800x600->1920x1080 scaler_users = 0x80000000
>[  105.350095] [drm:intel_atomic_setup_scalers] Attached scaler id 0.0 to CRTC:26
>[  105.351438] [drm:intel_power_well_enable] enabling dpio-common-a
>[  105.365170] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[  105.365655] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[  105.366110] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[  105.366568] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[  105.367019] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[  105.367485] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[  105.367942] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[  105.368406] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[  105.368855] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[  105.369309] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[  105.369772] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[  105.370228] [drm:verify_single_dpll_state] PORT PLL A
>[  105.370689] [drm:verify_single_dpll_state] PORT PLL B
>[  105.371152] [drm:verify_single_dpll_state] PORT PLL C
>[  105.371610] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[  105.372073] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[  105.373305] [drm:edp_panel_on] Turn eDP port A panel power on
>[  105.373770] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  105.382357] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000060
>[  105.422303] [drm:wait_panel_status] Wait complete
>[  105.422818] [drm:wait_panel_on] Wait for panel power on
>[  105.423294] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 00000063
>[  105.449581] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  105.450983] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  105.452381] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[  105.453810] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  105.483690] [drm:wait_panel_status] Wait complete
>[  105.484935] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  105.486197] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  105.488167] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  105.489379] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  105.490832] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  105.492600] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  105.493879] [drm:skylake_pfit_enable] for crtc_state = ffff880468239000
>[  105.494368] [drm:skylake_pfit_enable] for crtc_state = ffff880468239000 scaler_id = 0
>[  105.494888] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[  105.496143] [drm:skl_wm_flush_pipe] flush pipe B (pass 2)
>[  105.497020] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  105.497477] [drm:intel_enable_pipe] enabling pipe A
>[  105.497946] [drm:intel_edp_backlight_on] 
>[  105.498397] [drm:intel_panel_enable_backlight] pipe A
>[  105.498850] [drm:intel_panel_actually_set_backlight] set backlight PWM = 28800
>[  105.499300] [drm:intel_psr_enable] PSR not supported on this platform
>[  105.499742] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  105.500197] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  105.500615] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  105.501029] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  105.501451] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  105.501868] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  105.502270] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  105.506198] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[  105.506616] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[  105.507025] [drm:verify_single_dpll_state] PORT PLL A
>[  105.507428] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[  105.507804] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  105.508184] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  105.508576] [drm:skl_update_scaler] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  105.508972] [drm:intel_edp_backlight_off] 
>[  105.613252] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  105.613678] [drm:intel_disable_pipe] disabling pipe A
>[  105.618078] [drm:edp_panel_off] Turn eDP port A panel power off
>[  105.619185] [drm:wait_panel_off] Wait for panel power off time
>[  105.620260] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000002 control 00000060
>[  105.632263] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  105.633349] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  105.634415] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[  105.635489] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  105.635650] [drm:wait_panel_status] Wait complete
>[  105.635653] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[  105.635671] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[  105.635677] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  105.635678] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  105.635681] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[  105.635684] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[  105.635685] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[  105.635685] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[  105.635686] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[  105.635686] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[  105.635687] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[  105.635687] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[  105.635688] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[  105.635688] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[  105.635689] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[  105.635691] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[  105.635696] [drm:verify_single_dpll_state] PORT PLL A
>[  105.635696] [drm:verify_single_dpll_state] PORT PLL B
>[  105.635702] [drm:verify_single_dpll_state] PORT PLL C
>[  105.635711] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  105.635712] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  105.635736] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  105.635738] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  105.635754] [drm:intel_power_well_disable] disabling dpio-common-a
>[  105.635757] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[  105.637048] [drm:drm_mode_addfb2] [FB:80]
>[  105.647475] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  105.647478] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[  105.647485] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[  105.647485] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[  105.647487] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  105.647488] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  105.647490] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  105.647491] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[  105.647492] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  105.647493] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046c0d2800 for pipe A
>[  105.647493] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  105.647494] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  105.647494] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  105.647495] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  105.647496] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  105.647497] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  105.647497] [drm:intel_dump_pipe_config] requested mode:
>[  105.647498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  105.647499] [drm:intel_dump_pipe_config] adjusted mode:
>[  105.647500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  105.647501] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  105.647501] [drm:intel_dump_pipe_config] port clock: 270000
>[  105.647501] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  105.647502] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  105.647503] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  105.647503] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  105.647504] [drm:intel_dump_pipe_config] ips: 0
>[  105.647504] [drm:intel_dump_pipe_config] double wide: 0
>[  105.647505] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  105.647506] [drm:intel_dump_pipe_config] planes on this crtc
>[  105.647506] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[  105.647507] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  105.647507] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  105.647508] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[  105.647509] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[  105.647511] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  105.647512] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[  105.647513] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[  105.647513] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  105.647607] [drm:intel_power_well_enable] enabling dpio-common-a
>[  105.650933] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[  105.650933] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[  105.650934] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[  105.650934] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[  105.650935] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[  105.650935] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[  105.650935] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[  105.650936] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[  105.650936] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[  105.650937] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[  105.650940] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[  105.650949] [drm:verify_single_dpll_state] PORT PLL A
>[  105.650950] [drm:verify_single_dpll_state] PORT PLL B
>[  105.650959] [drm:verify_single_dpll_state] PORT PLL C
>[  105.650981] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[  105.650981] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[  105.651043] [drm:edp_panel_on] Turn eDP port A panel power on
>[  105.651044] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  105.793698] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[  105.794932] [drm:wait_panel_status] Wait complete
>[  105.796146] [drm:wait_panel_on] Wait for panel power on
>[  105.797364] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 00000063
>[  105.822897] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  105.824194] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  105.825478] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[  105.826779] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  105.857392] [drm:wait_panel_status] Wait complete
>[  105.858697] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  105.860029] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  105.862083] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  105.863404] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  105.864941] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  105.866760] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  105.868110] [drm:skylake_pfit_enable] for crtc_state = ffff88046c0d2800
>[  105.868620] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[  105.870118] [drm:skl_wm_flush_pipe] flush pipe B (pass 2)
>[  105.871001] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  105.871437] [drm:intel_enable_pipe] enabling pipe A
>[  105.871883] [drm:intel_edp_backlight_on] 
>[  105.872321] [drm:intel_panel_enable_backlight] pipe A
>[  105.872753] [drm:intel_panel_actually_set_backlight] set backlight PWM = 28800
>[  105.873189] [drm:intel_psr_enable] PSR not supported on this platform
>[  105.873619] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  105.874091] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  105.874509] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  105.874922] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  105.875334] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  105.875723] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  105.876103] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  105.880137] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[  105.880550] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[  105.880956] [drm:verify_single_dpll_state] PORT PLL A
>[  105.881426] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  105.884253] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:27:plane 2A] scaler_user index 0.2
>[  105.884669] [drm:skl_update_scaler] scaler_user index 0.2: staged scaling request for 1249x832->600x400 scaler_users = 0x4
>[  105.885055] [drm:intel_atomic_setup_scalers] Attached scaler id 0.0 to PLANE:27
>[  105.885505] [drm:skl_wm_flush_pipe] flush pipe B (pass 2)
>[  105.887438] [drm:skl_wm_flush_pipe] flush pipe C (pass 2)
>[  105.890688] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  105.891625] [drm:skl_update_plane] plane = 1 PS_PLANE_SEL(plane) = 0x4000000
>[  105.892597] [drm:intel_pipe_update_end [i915]] *ERROR* Atomic update failure on pipe A (start=26313 end=26314) time 3847 us, min 1073, max 1079, scanline start 856, end 1116
>[  105.896607] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[  105.897626] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  105.898658] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:27:plane 2A] scaler_user index 0.2
>[  105.899642] [drm:skl_update_scaler] scaler_user index 0.2: Staged freeing scaler id 0 scaler_users = 0x0
>[  105.900615] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  105.901620] [drm:intel_edp_backlight_off] 
>[  106.005391] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  106.005801] [drm:intel_disable_pipe] disabling pipe A
>[  106.009230] [drm:edp_panel_off] Turn eDP port A panel power off
>[  106.009629] [drm:wait_panel_off] Wait for panel power off time
>[  106.010021] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000002 control 00000060
>[  106.022693] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  106.023650] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  106.024613] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[  106.025605] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  106.027476] [drm:wait_panel_status] Wait complete
>[  106.028478] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[  106.029504] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[  106.030514] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  106.031526] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  106.032544] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[  106.033550] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[  106.034543] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[  106.035469] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[  106.036413] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[  106.037341] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[  106.038262] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[  106.039182] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[  106.040092] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[  106.040997] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[  106.041898] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[  106.042793] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[  106.043661] [drm:verify_single_dpll_state] PORT PLL A
>[  106.044530] [drm:verify_single_dpll_state] PORT PLL B
>[  106.045399] [drm:verify_single_dpll_state] PORT PLL C
>[  106.046257] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  106.047100] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  106.047952] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  106.048778] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  106.049608] [drm:intel_power_well_disable] disabling dpio-common-a
>[  106.050417] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[  106.052920] [drm:drm_mode_addfb2] [FB:80]
>[  106.059375] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  106.060289] [drm:drm_mode_setcrtc] [CONNECTOR:39:eDP-1]
>[  106.061203] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[  106.062150] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[  106.063089] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  106.064027] [drm:skl_update_scaler] scaler_user index 0.31: staged scaling request for 1024x768->1920x1080 scaler_users = 0x80000000
>[  106.064988] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  106.065984] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  106.066975] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[  106.067967] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  106.068980] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046a192800 for pipe A
>[  106.070037] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  106.071089] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  106.072125] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  106.073183] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  106.074276] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  106.075351] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  106.076422] [drm:intel_dump_pipe_config] requested mode:
>[  106.077487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1024 1968 2018 2052 768 1084 1086 1122 0x48 0xa
>[  106.078566] [drm:intel_dump_pipe_config] adjusted mode:
>[  106.079651] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  106.080775] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  106.081936] [drm:intel_dump_pipe_config] port clock: 270000
>[  106.083086] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  106.084196] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x80000000, scaler_id: -1
>[  106.085299] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  106.086404] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00f00000, size: 0x05a00438, enabled
>[  106.087518] [drm:intel_dump_pipe_config] ips: 0
>[  106.088615] [drm:intel_dump_pipe_config] double wide: 0
>[  106.089703] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  106.090853] [drm:intel_dump_pipe_config] planes on this crtc
>[  106.091991] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[  106.093120] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  106.094264] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] enabled
>[  106.094287] [drm:intel_dump_pipe_config] 	FB:88, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  106.095427] [drm:intel_dump_pipe_config] 	scaler:-1 src 660x340+-100+-100 dst 100x100+-100+-100
>[  106.096588] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[  106.097759] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[  106.098935] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  106.100123] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:27:plane 2A] scaler_user index 0.2
>[  106.101291] [drm:skl_update_scaler] scaler_user index 0.2: staged scaling request for 1249x832->600x400 scaler_users = 0x80000004
>[  106.102492] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[  106.103680] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[  106.104861] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  106.106063] [drm:skl_update_scaler] scaler_user index 0.31: staged scaling request for 1024x768->1920x1080 scaler_users = 0x80000004
>[  106.107317] [drm:intel_atomic_setup_scalers] Attached scaler id 0.0 to PLANE:27
>[  106.108573] [drm:intel_atomic_setup_scalers] Attached scaler id 0.1 to CRTC:26
>[  106.109885] [drm:intel_power_well_enable] enabling dpio-common-a
>[  106.113939] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[  106.114471] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[  106.114972] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[  106.115488] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[  106.115991] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[  106.116494] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[  106.116989] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[  106.117489] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[  106.117982] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[  106.118479] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[  106.119000] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[  106.119503] [drm:verify_single_dpll_state] PORT PLL A
>[  106.120014] [drm:verify_single_dpll_state] PORT PLL B
>[  106.120516] [drm:verify_single_dpll_state] PORT PLL C
>[  106.121022] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[  106.121534] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[  106.122085] [drm:edp_panel_on] Turn eDP port A panel power on
>[  106.122605] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  106.157805] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000060
>[  106.158349] [drm:wait_panel_status] Wait complete
>[  106.158860] [drm:wait_panel_on] Wait for panel power on
>[  106.159381] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 00000063
>[  106.185609] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  106.186177] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  106.186696] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[  106.187879] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  106.246997] [drm:wait_panel_status] Wait complete
>[  106.248493] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  106.249952] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  106.252150] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  106.253589] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  106.255258] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  106.257247] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  106.258742] [drm:skylake_pfit_enable] for crtc_state = ffff88046a192800
>[  106.260174] [drm:skylake_pfit_enable] for crtc_state = ffff88046a192800 scaler_id = 1
>[  106.261658] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[  106.264643] [drm:skl_wm_flush_pipe] flush pipe B (pass 2)
>[  106.269649] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  106.270742] [drm:intel_enable_pipe] enabling pipe A
>[  106.271834] [drm:intel_edp_backlight_on] 
>[  106.272885] [drm:intel_panel_enable_backlight] pipe A
>[  106.273919] [drm:intel_panel_actually_set_backlight] set backlight PWM = 28800
>[  106.274959] [drm:intel_psr_enable] PSR not supported on this platform
>[  106.276005] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  106.277062] [drm:skl_update_plane] plane = 1 PS_PLANE_SEL(plane) = 0x4000000
>[  106.278095] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  106.279114] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  106.280122] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  106.281180] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  106.282173] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  106.283113] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  106.284187] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[  106.285273] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[  106.286240] [drm:verify_single_dpll_state] PORT PLL A
>[  106.287320] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  106.288230] [drm:skl_update_plane] plane = 1 PS_PLANE_SEL(plane) = 0x4000000
>[  106.289155] [drm:intel_pipe_update_end [i915]] *ERROR* Atomic update failure on pipe A (start=26345 end=26346) time 3606 us, min 1073, max 1079, scanline start 1065, end 187
>[  106.292422] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:27:plane 2A] scaler_user index 0.2
>[  106.293375] [drm:skl_update_scaler] scaler_user index 0.2: Staged freeing scaler id 0 scaler_users = 0x80000000
>[  106.294360] [drm:skl_wm_flush_pipe] flush pipe B (pass 2)
>[  106.298412] [drm:skl_wm_flush_pipe] flush pipe C (pass 2)
>[  106.301636] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  106.304752] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  106.305634] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  106.306397] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO underrun
>[  106.307331] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  106.308201] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[  106.309086] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  106.310003] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  106.310917] [drm:skl_update_scaler] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  106.311857] [drm:intel_edp_backlight_off] 
>[  106.415452] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  106.416404] [drm:intel_disable_pipe] disabling pipe A
>[  106.420361] [drm:edp_panel_off] Turn eDP port A panel power off
>[  106.421319] [drm:wait_panel_off] Wait for panel power off time
>[  106.422288] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000002 control 00000060
>[  106.434372] [drm:wait_panel_status] Wait complete
>[  106.434398] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  106.434399] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  106.434399] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
>[  106.434407] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  106.440030] [drm:intel_disable_shared_dpll] disable PORT PLL A (active 1, on? 1) for crtc 26
>[  106.441193] [drm:intel_disable_shared_dpll] disabling PORT PLL A
>[  106.442340] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  106.443498] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  106.444643] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[  106.445764] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[  106.446823] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[  106.447891] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[  106.448936] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[  106.449978] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[  106.451020] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[  106.452051] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[  106.453078] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[  106.454084] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[  106.455088] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[  106.456099] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[  106.457097] [drm:verify_single_dpll_state] PORT PLL A
>[  106.458089] [drm:verify_single_dpll_state] PORT PLL B
>[  106.459062] [drm:verify_single_dpll_state] PORT PLL C
>[  106.460030] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  106.460990] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  106.461960] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  106.462891] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  106.463842] [drm:intel_power_well_disable] disabling dpio-common-a
>[  106.464803] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[  106.467782] kms_panel_fitting: exiting, ret=0
>[  106.468926] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  106.470017] [drm:i915_pages_create_for_stolen] offset=0x809000, size=16384
>[  106.471175] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  106.472264] [drm:i915_pages_create_for_stolen] offset=0x80d000, size=16384
>[  106.473458] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  106.474548] [drm:i915_pages_create_for_stolen] offset=0x811000, size=16384
>[  106.475722] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  106.476852] [drm:i915_pages_create_for_stolen] offset=0x815000, size=16384
>[  106.478811] [drm:connected_sink_compute_bpp] [CONNECTOR:39:eDP-1] checking for sink bpp constrains
>[  106.480009] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[  106.481217] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  106.482419] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  106.483633] [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  106.484864] [drm:intel_dp_compute_config] DP link bw required 331488 available 432000
>[  106.486085] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  106.487303] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff88046c0d1800 for pipe A
>[  106.488489] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  106.489634] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  106.490774] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  106.491908] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  106.493099] [drm:intel_dump_pipe_config] dp: 1, lanes: 2, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  106.494289] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  106.495478] [drm:intel_dump_pipe_config] requested mode:
>[  106.496671] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  106.497915] [drm:intel_dump_pipe_config] adjusted mode:
>[  106.499144] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  106.500397] [drm:intel_dump_crtc_timings] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  106.501662] [drm:intel_dump_pipe_config] port clock: 270000
>[  106.502925] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  106.504177] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  106.505411] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  106.506661] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  106.507913] [drm:intel_dump_pipe_config] ips: 0
>[  106.509145] [drm:intel_dump_pipe_config] double wide: 0
>[  106.510373] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  106.511691] [drm:intel_dump_pipe_config] planes on this crtc
>[  106.512995] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[  106.514289] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  106.515545] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  106.516803] [drm:intel_dump_pipe_config] [PLANE:28:plane 3A] disabled, scaler_id = -1
>[  106.518042] [drm:intel_modeset_checks] New cdclk calculated to be atomic 288000, actual 288000
>[  106.519284] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  106.520542] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[  106.521801] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[  106.523050] [drm:bxt_get_dpll] [CRTC:26:pipe A] using pre-allocated PORT PLL A
>[  106.524299] [drm:intel_reference_shared_dpll] using PORT PLL A for pipe A
>[  106.525571] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  106.526908] [drm:intel_power_well_enable] enabling dpio-common-a
>[  106.528003] [drm:verify_encoder_state] [ENCODER:38:DDI A]
>[  106.529044] [drm:verify_encoder_state] [ENCODER:46:DDI B]
>[  106.530117] [drm:verify_encoder_state] [ENCODER:48:DP-MST A]
>[  106.531183] [drm:verify_encoder_state] [ENCODER:49:DP-MST B]
>[  106.532249] [drm:verify_encoder_state] [ENCODER:50:DP-MST C]
>[  106.533315] [drm:verify_encoder_state] [ENCODER:53:DDI C]
>[  106.534379] [drm:verify_encoder_state] [ENCODER:55:DP-MST A]
>[  106.535446] [drm:verify_encoder_state] [ENCODER:56:DP-MST B]
>[  106.536503] [drm:verify_encoder_state] [ENCODER:57:DP-MST C]
>[  106.537539] [drm:intel_connector_verify_state] [CONNECTOR:51:HDMI-A-1]
>[  106.538599] [drm:intel_connector_verify_state] [CONNECTOR:58:HDMI-A-2]
>[  106.539661] [drm:verify_single_dpll_state] PORT PLL A
>[  106.540727] [drm:verify_single_dpll_state] PORT PLL B
>[  106.541786] [drm:verify_single_dpll_state] PORT PLL C
>[  106.542854] [drm:intel_enable_shared_dpll] enable PORT PLL A (active 1, on? 0) for crtc 26
>[  106.543952] [drm:intel_enable_shared_dpll] enabling PORT PLL A
>[  106.545503] [drm:edp_panel_on] Turn eDP port A panel power on
>[  106.545980] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  106.546458] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000060
>[  106.574876] [drm:wait_panel_status] Wait complete
>[  106.575388] [drm:wait_panel_on] Wait for panel power on
>[  106.576701] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 00000063
>[  106.602157] [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  106.603365] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  106.604571] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
>[  106.605793] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  106.628049] [drm:wait_panel_status] Wait complete
>[  106.629413] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  106.630747] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  106.632822] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  106.634154] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  106.635696] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
>[  106.637543] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
>[  106.638923] [drm:skylake_pfit_enable] for crtc_state = ffff88046c0d1800
>[  106.639443] [drm:skl_wm_flush_pipe] flush pipe C (pass 1)
>[  106.642729] [drm:skl_wm_flush_pipe] flush pipe B (pass 2)
>[  106.643602] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  106.644057] [drm:intel_enable_pipe] enabling pipe A
>[  106.644506] [drm:intel_edp_backlight_on] 
>[  106.644945] [drm:intel_panel_enable_backlight] pipe A
>[  106.645385] [drm:intel_panel_actually_set_backlight] set backlight PWM = 28800
>[  106.645830] [drm:intel_psr_enable] PSR not supported on this platform
>[  106.646263] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  106.646756] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  106.647171] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  106.647585] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  106.647995] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  106.648391] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  106.648780] [drm:skl_wm_flush_pipe] flush pipe C (pass 3)
>[  106.652754] [drm:intel_connector_verify_state] [CONNECTOR:39:eDP-1]
>[  106.653160] [drm:verify_crtc_state] [CRTC:26:pipe A]
>[  106.653565] [drm:verify_single_dpll_state] PORT PLL A
>[  107.258646] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[  107.259711] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  140.108118] gem_mmap_gtt: executing
>[  140.109233] [drm:i915_gem_open] 
>[  140.110373] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  140.111480] [drm:i915_pages_create_for_stolen] offset=0x7f9000, size=16384
>[  140.112635] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  140.113708] [drm:i915_pages_create_for_stolen] offset=0x7fd000, size=16384
>[  140.114827] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  140.115909] [drm:i915_pages_create_for_stolen] offset=0x801000, size=16384
>[  140.116991] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  140.117973] [drm:i915_pages_create_for_stolen] offset=0x805000, size=16384
>[  140.119293] [drm:i915_gem_open] 
>[  140.120294] gem_mmap_gtt: starting subtest huge-copy
>[  140.121266] gem_mmap_gtt (1447): drop_caches: 4
>[  181.330451] gem_mmap_gtt: exiting, ret=99
>[  181.330858] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  181.331240] [drm:i915_pages_create_for_stolen] offset=0x809000, size=16384
>[  181.331670] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  181.332062] [drm:i915_pages_create_for_stolen] offset=0x80d000, size=16384
>[  181.332473] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  181.333056] [drm:i915_pages_create_for_stolen] offset=0x811000, size=16384
>[  181.333507] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  181.333927] [drm:i915_pages_create_for_stolen] offset=0x815000, size=16384
>[  182.027032] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  182.027477] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[  182.027903] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8
>[  299.478217] gem_mmap_gtt: executing
>[  299.479482] [drm:i915_gem_open] 
>[  299.480785] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  299.482020] [drm:i915_pages_create_for_stolen] offset=0x7f9000, size=16384
>[  299.483305] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  299.484522] [drm:i915_pages_create_for_stolen] offset=0x7fd000, size=16384
>[  299.485756] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  299.486980] [drm:i915_pages_create_for_stolen] offset=0x801000, size=16384
>[  299.488214] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  299.489447] [drm:i915_pages_create_for_stolen] offset=0x805000, size=16384
>[  299.490953] [drm:i915_gem_open] 
>[  299.491477] gem_mmap_gtt: starting subtest huge-copy
>[  340.451849] gem_mmap_gtt: exiting, ret=99
>[  340.452314] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  340.452747] [drm:i915_pages_create_for_stolen] offset=0x809000, size=16384
>[  340.453219] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  340.453645] [drm:i915_pages_create_for_stolen] offset=0x80d000, size=16384
>[  340.454086] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  340.454518] [drm:i915_pages_create_for_stolen] offset=0x811000, size=16384
>[  340.454993] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[  340.455418] [drm:i915_pages_create_for_stolen] offset=0x815000, size=16384
>[  341.088233] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  341.088674] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:29:plane 1B] scaler_user index 1.4
>[  341.089102] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:34:plane 1C] scaler_user index 2.8

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