Attachment 125239 Details for Bug 97017 – Update ring freqs after runtime resume

[patch] Update ring freqs after runtime resume

0001-drm-i915-Restore-update-of-ring-frequencies-after-ru.patch (text/plain), 4.20 KB, created by Chris Wilson on 2016-07-21 18:05:17 UTC

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Creator: Chris Wilson

Created: 2016-07-21 18:05:17 UTC

Size: 4.20 KB

patch

obsolete

>From 9ac078dff8a666a7e65dddade3b9b14fba20ed96 Mon Sep 17 00:00:00 2001
>From: Chris Wilson <chris@chris-wilson.co.uk>
>Date: Thu, 21 Jul 2016 18:48:31 +0100
>Subject: [PATCH] drm/i915: Restore update of ring frequencies after runtime
> suspend
>
>Originally it was removed as it was part of the autoenabling RC6 work
>performed on the first batch, and so was expected to be automatically
>performed upon resume. However, rc6/rps enabling is only done after a
>full system resume and so we need to restore the call to update the ring
>frequencies. Now that PCU is reasonably fast, this can be done in line
>rather than as a deferred workqueue, after commit 3f5582dd845b ("drm/i915:
>Convert sandybridge_pcode_*() to use intel_wait_for_register()").
>
>Fixes: commit b7137e0cf1e5 ("drm/i915: Defer enabling rc6...")
>References: https://bugs.freedesktop.org/show_bug.cgi?id=97017
>Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>---
> drivers/gpu/drm/i915/i915_drv.c  |  1 +
> drivers/gpu/drm/i915/intel_drv.h |  1 +
> drivers/gpu/drm/i915/intel_pm.c  | 22 ++++++++++++++++------
> 3 files changed, 18 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>index 83afdd0597b5..c010526bab56 100644
>--- a/drivers/gpu/drm/i915/i915_drv.c
>+++ b/drivers/gpu/drm/i915/i915_drv.c
>@@ -2440,6 +2440,7 @@ static int intel_runtime_resume(struct device *device)
> 	i915_gem_init_swizzling(dev);
> 
> 	intel_runtime_pm_enable_interrupts(dev_priv);
>+	intel_update_ring_freq(dev_priv);
> 
> 	/*
> 	 * On VLV/CHV display interrupts are part of the display
>diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>index e74d851868c5..666adcc93c3a 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -1697,6 +1697,7 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
> void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
> void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
> void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
>+void intel_update_ring_freq(struct drm_i915_private *dev_priv);
> void gen6_rps_busy(struct drm_i915_private *dev_priv);
> void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
> void gen6_rps_idle(struct drm_i915_private *dev_priv);
>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>index 7c90d4e2b1a1..de6d4ba86d7e 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -5445,8 +5445,6 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
> 	int scaling_factor = 180;
> 	struct cpufreq_policy *policy;
> 
>-	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
>-
> 	policy = cpufreq_cpu_get(0);
> 	if (policy) {
> 		max_ia_freq = policy->cpuinfo.max_freq;
>@@ -6528,6 +6526,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
> 	mutex_unlock(&dev_priv->rps.hw_lock);
> 
> 	intel_autoenable_gt_powersave(dev_priv);
>+	intel_update_ring_freq(dev_priv);
> }
> 
> void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
>@@ -6592,6 +6591,21 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
> 	mutex_unlock(&dev_priv->rps.hw_lock);
> }
> 
>+void intel_update_ring_freq(struct drm_i915_private *dev_priv)
>+{
>+	if (INTEL_GEN(dev_priv) < 6)
>+		return;
>+
>+	if (IS_CHERRYVIEW(dev_priv) ||
>+	    IS_VALLEYVIEW(dev_priv) ||
>+	    IS_BROXTON(dev_priv))
>+		return;
>+
>+	mutex_lock(&dev_priv->rps.hw_lock);
>+	gen6_update_ring_freq(dev_priv);
>+	mutex_unlock(&dev_priv->rps.hw_lock);
>+}
>+
> void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
> {
> 	/* We shouldn't be disabling as we submit, so this should be less
>@@ -6613,14 +6627,10 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
> 	} else if (INTEL_GEN(dev_priv) >= 9) {
> 		gen9_enable_rc6(dev_priv);
> 		gen9_enable_rps(dev_priv);
>-		if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>-			gen6_update_ring_freq(dev_priv);
> 	} else if (IS_BROADWELL(dev_priv)) {
> 		gen8_enable_rps(dev_priv);
>-		gen6_update_ring_freq(dev_priv);
> 	} else if (INTEL_GEN(dev_priv) >= 6) {
> 		gen6_enable_rps(dev_priv);
>-		gen6_update_ring_freq(dev_priv);
> 	} else if (IS_IRONLAKE_M(dev_priv)) {
> 		ironlake_enable_drps(dev_priv);
> 		intel_init_emon(dev_priv);
>-- 
>2.8.1
>

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Attachments on bug 97017: 125227 | 125236 | 125239 | 125252

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