Attachment 126713 Details for Bug 97806 – GALLIUM_DDEBUG="pipelined 1000" ./heaven

GALLIUM_DDEBUG="pipelined 1000" ./heaven

heaven_x64_23765_00000000 (text/plain), 22.83 KB, created by Laurent carlier on 2016-09-21 18:18:52 UTC

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Creator: Laurent carlier

Created: 2016-09-21 18:18:52 UTC

Size: 22.83 KB

patch

obsolete

>Command: ./heaven_x64 -project_name Heaven -data_path ../ -engine_config ../data/heaven_4.0.cfg -system_script heaven/unigine.cpp -sound_app openal -video_app opengl -video_multisample 3 -video_fullscreen 1 -video_mode -1 -video_height 1080 -video_width 1920 -extern_define ,RELEASE,LANGUAGE_EN,QUALITY_ULTRA,TESSELLATION_EXTREME -extern_plugin ,GPUMonitor 
>Driver vendor: X.Org
>Device vendor: AMD
>Device name: AMD POLARIS10 (DRM 3.2.0 / 4.7.4-1-ARCH, LLVM 4.0.0)
>
>Draw call sequence # = 410
>HW reached sequence # = 409
>Elapsed time = 1007 ms
>
>clear:
>  buffers: 29
>  color: {f = {0.000000, 0.000000, 0.000000, 0.000000}, ui = {0, 0, 0, 0}
>  depth: 1.000000
>  stencil: 0x0
>
>
>*****************************************************************************
>Driver-specific state:
>
>
>Memory-mapped registers:
>        [1;33mGRBM_STATUS[0m <- ME0PIPE0_CMDFIFO_AVAIL = 8
>                       SRBM_RQ_PENDING = 1
>                       ME0PIPE0_CF_RQ_PENDING = 0
>                       ME0PIPE0_PF_RQ_PENDING = 0
>                       GDS_DMA_RQ_PENDING = 0
>                       DB_CLEAN = 1
>                       CB_CLEAN = 1
>                       TA_BUSY = 0
>                       GDS_BUSY = 0
>                       WD_BUSY_NO_DMA = 0
>                       VGT_BUSY = 0
>                       IA_BUSY_NO_DMA = 0
>                       IA_BUSY = 0
>                       SX_BUSY = 0
>                       WD_BUSY = 0
>                       SPI_BUSY = 0
>                       BCI_BUSY = 0
>                       SC_BUSY = 0
>                       PA_BUSY = 0
>                       DB_BUSY = 0
>                       CP_COHERENCY_BUSY = 0
>                       CP_BUSY = 0
>                       CB_BUSY = 0
>                       GUI_ACTIVE = 0
>        [1;33mGRBM_STATUS2[0m <- ME0PIPE1_CMDFIFO_AVAIL = 8
>                        ME0PIPE1_CF_RQ_PENDING = 0
>                        ME0PIPE1_PF_RQ_PENDING = 0
>                        ME1PIPE0_RQ_PENDING = 0
>                        ME1PIPE1_RQ_PENDING = 0
>                        ME1PIPE2_RQ_PENDING = 0
>                        ME1PIPE3_RQ_PENDING = 0
>                        ME2PIPE0_RQ_PENDING = 0
>                        ME2PIPE1_RQ_PENDING = 0
>                        ME2PIPE2_RQ_PENDING = 0
>                        ME2PIPE3_RQ_PENDING = 0
>                        RLC_RQ_PENDING = 0
>                        RLC_BUSY = 0
>                        TC_BUSY = 0
>                        TCC_CC_RESIDENT = 0
>                        CPF_BUSY = 0
>                        CPC_BUSY = 0
>                        CPG_BUSY = 0
>        [1;33mGRBM_STATUS_SE0[0m <- DB_CLEAN = 1
>                           CB_CLEAN = 1
>                           BCI_BUSY = 0
>                           VGT_BUSY = 0
>                           PA_BUSY = 0
>                           TA_BUSY = 0
>                           SX_BUSY = 0
>                           SPI_BUSY = 0
>                           SC_BUSY = 0
>                           DB_BUSY = 0
>                           CB_BUSY = 0
>        [1;33mGRBM_STATUS_SE1[0m <- DB_CLEAN = 1
>                           CB_CLEAN = 1
>                           BCI_BUSY = 0
>                           VGT_BUSY = 0
>                           PA_BUSY = 0
>                           TA_BUSY = 0
>                           SX_BUSY = 0
>                           SPI_BUSY = 0
>                           SC_BUSY = 0
>                           DB_BUSY = 0
>                           CB_BUSY = 0
>        [1;33mGRBM_STATUS_SE2[0m <- DB_CLEAN = 1
>                           CB_CLEAN = 1
>                           BCI_BUSY = 0
>                           VGT_BUSY = 0
>                           PA_BUSY = 0
>                           TA_BUSY = 0
>                           SX_BUSY = 0
>                           SPI_BUSY = 0
>                           SC_BUSY = 0
>                           DB_BUSY = 0
>                           CB_BUSY = 0
>        [1;33mGRBM_STATUS_SE3[0m <- DB_CLEAN = 1
>                           CB_CLEAN = 1
>                           BCI_BUSY = 0
>                           VGT_BUSY = 0
>                           PA_BUSY = 0
>                           TA_BUSY = 0
>                           SX_BUSY = 0
>                           SPI_BUSY = 0
>                           SC_BUSY = 0
>                           DB_BUSY = 0
>                           CB_BUSY = 0
>        [1;33mSDMA0_STATUS_REG[0m <- IDLE = 1
>                            REG_IDLE = 1
>                            RB_EMPTY = 1
>                            RB_FULL = 0
>                            RB_CMD_IDLE = 1
>                            RB_CMD_FULL = 0
>                            IB_CMD_IDLE = 1
>                            IB_CMD_FULL = 0
>                            BLOCK_IDLE = 1
>                            INSIDE_IB = 0
>                            EX_IDLE = 1
>                            EX_IDLE_POLL_TIMER_EXPIRE = 1
>                            PACKET_READY = 0
>                            MC_WR_IDLE = 1
>                            SRBM_IDLE = 1
>                            CONTEXT_EMPTY = 1
>                            DELTA_RPTR_FULL = 0
>                            RB_MC_RREQ_IDLE = 1
>                            IB_MC_RREQ_IDLE = 1
>                            MC_RD_IDLE = 1
>                            DELTA_RPTR_EMPTY = 1
>                            MC_RD_RET_STALL = 0
>                            MC_RD_NO_POLL_IDLE = 1
>                            PREV_CMD_IDLE = 1
>                            SEM_IDLE = 1
>                            SEM_REQ_STALL = 0
>                            SEM_RESP_STATE = 0
>                            INT_IDLE = 1
>                            INT_REQ_STALL = 0
>        [1;33mSDMA1_STATUS_REG[0m <- IDLE = 1
>                            REG_IDLE = 1
>                            RB_EMPTY = 1
>                            RB_FULL = 0
>                            RB_CMD_IDLE = 1
>                            RB_CMD_FULL = 0
>                            IB_CMD_IDLE = 1
>                            IB_CMD_FULL = 0
>                            BLOCK_IDLE = 1
>                            INSIDE_IB = 0
>                            EX_IDLE = 1
>                            EX_IDLE_POLL_TIMER_EXPIRE = 1
>                            PACKET_READY = 0
>                            MC_WR_IDLE = 1
>                            SRBM_IDLE = 1
>                            CONTEXT_EMPTY = 1
>                            DELTA_RPTR_FULL = 0
>                            RB_MC_RREQ_IDLE = 1
>                            IB_MC_RREQ_IDLE = 1
>                            MC_RD_IDLE = 1
>                            DELTA_RPTR_EMPTY = 1
>                            MC_RD_RET_STALL = 0
>                            MC_RD_NO_POLL_IDLE = 1
>                            PREV_CMD_IDLE = 1
>                            SEM_IDLE = 1
>                            SEM_REQ_STALL = 0
>                            SEM_RESP_STATE = 0
>                            INT_IDLE = 1
>                            INT_REQ_STALL = 0
>        [1;33mSRBM_STATUS[0m <- UVD_RQ_PENDING = 0
>                       SAMMSP_RQ_PENDING = 0
>                       ACP_RQ_PENDING = 0
>                       SMU_RQ_PENDING = 0
>                       GRBM_RQ_PENDING = 0
>                       HI_RQ_PENDING = 1
>                       VMC_BUSY = 0
>                       MCB_BUSY = 0
>                       MCB_NON_DISPLAY_BUSY = 0
>                       MCC_BUSY = 0
>                       MCD_BUSY = 0
>                       VMC1_BUSY = 0
>                       SEM_BUSY = 0
>                       ACP_BUSY = 0
>                       IH_BUSY = 0
>                       UVD_BUSY = 0
>                       SAMMSP_BUSY = 0
>                       GCATCL2_BUSY = 0
>                       OSATCL2_BUSY = 0
>                       BIF_BUSY = 1
>        [1;33mSRBM_STATUS2[0m <- SDMA_RQ_PENDING = 0
>                        TST_RQ_PENDING = 0
>                        SDMA1_RQ_PENDING = 0
>                        VCE0_RQ_PENDING = 0
>                        VP8_BUSY = 0
>                        SDMA_BUSY = 0
>                        SDMA1_BUSY = 0
>                        VCE0_BUSY = 1
>                        XDMA_BUSY = 0
>                        CHUB_BUSY = 0
>                        SDMA2_BUSY = 0
>                        SDMA3_BUSY = 0
>                        SAMSCP_BUSY = 0
>                        ISP_BUSY = 0
>                        VCE1_BUSY = 0
>                        ODE_BUSY = 0
>                        SDMA2_RQ_PENDING = 0
>                        SDMA3_RQ_PENDING = 0
>                        SAMSCP_RQ_PENDING = 0
>                        ISP_RQ_PENDING = 0
>                        VCE1_RQ_PENDING = 0
>        [1;33mSRBM_STATUS3[0m <- MCC0_BUSY = 0
>                        MCC1_BUSY = 0
>                        MCC2_BUSY = 0
>                        MCC3_BUSY = 0
>                        MCC4_BUSY = 0
>                        MCC5_BUSY = 0
>                        MCC6_BUSY = 0
>                        MCC7_BUSY = 0
>                        MCD0_BUSY = 0
>                        MCD1_BUSY = 0
>                        MCD2_BUSY = 0
>                        MCD3_BUSY = 0
>                        MCD4_BUSY = 0
>                        MCD5_BUSY = 0
>                        MCD6_BUSY = 0
>                        MCD7_BUSY = 0
>        [1;33mCP_STAT[0m <- ROQ_RING_BUSY = 0
>                   ROQ_INDIRECT1_BUSY = 0
>                   ROQ_INDIRECT2_BUSY = 0
>                   ROQ_STATE_BUSY = 0
>                   DC_BUSY = 0
>                   ATCL2IU_BUSY = 0
>                   PFP_BUSY = 0
>                   MEQ_BUSY = 0
>                   ME_BUSY = 0
>                   QUERY_BUSY = 0
>                   SEMAPHORE_BUSY = 0
>                   INTERRUPT_BUSY = 0
>                   SURFACE_SYNC_BUSY = 0
>                   DMA_BUSY = 0
>                   RCIU_BUSY = 0
>                   SCRATCH_RAM_BUSY = 0
>                   CPC_CPG_BUSY = 0
>                   CE_BUSY = 0
>                   TCIU_BUSY = 0
>                   ROQ_CE_RING_BUSY = 0
>                   ROQ_CE_INDIRECT1_BUSY = 0
>                   ROQ_CE_INDIRECT2_BUSY = 0
>                   CP_BUSY = 0
>        [1;33mCP_STALLED_STAT1[0m <- RBIU_TO_DMA_NOT_RDY_TO_RCV = 0
>                            RBIU_TO_SEM_NOT_RDY_TO_RCV = 0
>                            RBIU_TO_MEMWR_NOT_RDY_TO_RCV = 0
>                            ME_HAS_ACTIVE_CE_BUFFER_FLAG = 1
>                            ME_HAS_ACTIVE_DE_BUFFER_FLAG = 1
>                            ME_STALLED_ON_TC_WR_CONFIRM = 0
>                            ME_STALLED_ON_ATOMIC_RTN_DATA = 0
>                            ME_WAITING_ON_TC_READ_DATA = 0
>                            ME_WAITING_ON_REG_READ_DATA = 0
>                            RCIU_WAITING_ON_GDS_FREE = 0
>                            RCIU_WAITING_ON_GRBM_FREE = 0
>                            RCIU_WAITING_ON_VGT_FREE = 0
>                            RCIU_STALLED_ON_ME_READ = 0
>                            RCIU_STALLED_ON_DMA_READ = 0
>                            RCIU_STALLED_ON_APPEND_READ = 0
>                            RCIU_HALTED_BY_REG_VIOLATION = 0
>        [1;33mCP_STALLED_STAT2[0m <- PFP_TO_CSF_NOT_RDY_TO_RCV = 0
>                            PFP_TO_MEQ_NOT_RDY_TO_RCV = 0
>                            PFP_TO_RCIU_NOT_RDY_TO_RCV = 0
>                            PFP_TO_VGT_WRITES_PENDING = 0
>                            PFP_RCIU_READ_PENDING = 0
>                            PFP_WAITING_ON_BUFFER_DATA = 0
>                            ME_WAIT_ON_CE_COUNTER = 0
>                            ME_WAIT_ON_AVAIL_BUFFER = 0
>                            GFX_CNTX_NOT_AVAIL_TO_ME = 0
>                            ME_RCIU_NOT_RDY_TO_RCV = 0
>                            ME_TO_CONST_NOT_RDY_TO_RCV = 0
>                            ME_WAITING_DATA_FROM_PFP = 0
>                            ME_WAITING_ON_PARTIAL_FLUSH = 0
>                            MEQ_TO_ME_NOT_RDY_TO_RCV = 0
>                            STQ_TO_ME_NOT_RDY_TO_RCV = 0
>                            ME_WAITING_DATA_FROM_STQ = 0
>                            PFP_STALLED_ON_TC_WR_CONFIRM = 0
>                            PFP_STALLED_ON_ATOMIC_RTN_DATA = 0
>                            EOPD_FIFO_NEEDS_SC_EOP_DONE = 0
>                            EOPD_FIFO_NEEDS_WR_CONFIRM = 0
>                            STRMO_WR_OF_PRIM_DATA_PENDING = 0
>                            PIPE_STATS_WR_DATA_PENDING = 0
>                            APPEND_RDY_WAIT_ON_CS_DONE = 0
>                            APPEND_RDY_WAIT_ON_PS_DONE = 0
>                            APPEND_WAIT_ON_WR_CONFIRM = 0
>                            APPEND_ACTIVE_PARTITION = 0
>                            APPEND_WAITING_TO_SEND_MEMWRITE = 0
>                            SURF_SYNC_NEEDS_IDLE_CNTXS = 0
>                            SURF_SYNC_NEEDS_ALL_CLEAN = 0
>        [1;33mCP_STALLED_STAT3[0m <- CE_TO_CSF_NOT_RDY_TO_RCV = 0
>                            CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV = 0
>                            CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER = 0
>                            CE_TO_RAM_INIT_NOT_RDY = 0
>                            CE_TO_RAM_DUMP_NOT_RDY = 0
>                            CE_TO_RAM_WRITE_NOT_RDY = 0
>                            CE_TO_INC_FIFO_NOT_RDY_TO_RCV = 0
>                            CE_TO_WR_FIFO_NOT_RDY_TO_RCV = 0
>                            CE_WAITING_ON_BUFFER_DATA = 0
>                            CE_WAITING_ON_CE_BUFFER_FLAG = 0
>                            CE_WAITING_ON_DE_COUNTER = 0
>                            CE_WAITING_ON_DE_COUNTER_UNDERFLOW = 0
>                            TCIU_WAITING_ON_FREE = 0
>                            TCIU_WAITING_ON_TAGS = 0
>                            CE_STALLED_ON_TC_WR_CONFIRM = 0
>                            CE_STALLED_ON_ATOMIC_RTN_DATA = 0
>                            ATCL2IU_WAITING_ON_FREE = 0
>                            ATCL2IU_WAITING_ON_TAGS = 0
>                            ATCL1_WAITING_ON_TRANS = 0
>        [1;33mCP_CPC_STATUS[0m <- MEC1_BUSY = 0
>                         MEC2_BUSY = 0
>                         DC0_BUSY = 0
>                         DC1_BUSY = 0
>                         RCIU1_BUSY = 0
>                         RCIU2_BUSY = 0
>                         ROQ1_BUSY = 0
>                         ROQ2_BUSY = 0
>                         TCIU_BUSY = 0
>                         SCRATCH_RAM_BUSY = 0
>                         QU_BUSY = 0
>                         ATCL2IU_BUSY = 0
>                         CPG_CPC_BUSY = 0
>                         CPF_CPC_BUSY = 0
>                         CPC_BUSY = 0
>        [1;33mCP_CPC_BUSY_STAT[0m <- MEC1_LOAD_BUSY = 0
>                            MEC1_SEMAPOHRE_BUSY = 0
>                            MEC1_MUTEX_BUSY = 0
>                            MEC1_MESSAGE_BUSY = 0
>                            MEC1_EOP_QUEUE_BUSY = 0
>                            MEC1_IQ_QUEUE_BUSY = 0
>                            MEC1_IB_QUEUE_BUSY = 0
>                            MEC1_TC_BUSY = 0
>                            MEC1_DMA_BUSY = 0
>                            MEC1_PARTIAL_FLUSH_BUSY = 0
>                            MEC1_PIPE0_BUSY = 0
>                            MEC1_PIPE1_BUSY = 0
>                            MEC1_PIPE2_BUSY = 0
>                            MEC1_PIPE3_BUSY = 0
>                            MEC2_LOAD_BUSY = 0
>                            MEC2_SEMAPOHRE_BUSY = 0
>                            MEC2_MUTEX_BUSY = 0
>                            MEC2_MESSAGE_BUSY = 0
>                            MEC2_EOP_QUEUE_BUSY = 0
>                            MEC2_IQ_QUEUE_BUSY = 0
>                            MEC2_IB_QUEUE_BUSY = 0
>                            MEC2_TC_BUSY = 0
>                            MEC2_DMA_BUSY = 0
>                            MEC2_PARTIAL_FLUSH_BUSY = 0
>                            MEC2_PIPE0_BUSY = 0
>                            MEC2_PIPE1_BUSY = 0
>                            MEC2_PIPE2_BUSY = 0
>                            MEC2_PIPE3_BUSY = 0
>        [1;33mCP_CPC_STALLED_STAT1[0m <- RCIU_TX_FREE_STALL = 0
>                                RCIU_PRIV_VIOLATION = 0
>                                TCIU_TX_FREE_STALL = 0
>                                MEC1_DECODING_PACKET = 0
>                                MEC1_WAIT_ON_RCIU = 0
>                                MEC1_WAIT_ON_RCIU_READ = 0
>                                MEC1_WAIT_ON_ROQ_DATA = 0
>                                MEC2_DECODING_PACKET = 0
>                                MEC2_WAIT_ON_RCIU = 0
>                                MEC2_WAIT_ON_RCIU_READ = 0
>                                MEC2_WAIT_ON_ROQ_DATA = 0
>                                ATCL2IU_WAITING_ON_FREE = 0
>                                ATCL2IU_WAITING_ON_TAGS = 0
>                                ATCL1_WAITING_ON_TRANS = 0
>        [1;33mCP_CPF_STATUS[0m <- POST_WPTR_GFX_BUSY = 0
>                         CSF_BUSY = 0
>                         ROQ_ALIGN_BUSY = 0
>                         ROQ_RING_BUSY = 0
>                         ROQ_INDIRECT1_BUSY = 0
>                         ROQ_INDIRECT2_BUSY = 0
>                         ROQ_STATE_BUSY = 0
>                         ROQ_CE_RING_BUSY = 0
>                         ROQ_CE_INDIRECT1_BUSY = 0
>                         ROQ_CE_INDIRECT2_BUSY = 0
>                         SEMAPHORE_BUSY = 0
>                         INTERRUPT_BUSY = 0
>                         TCIU_BUSY = 0
>                         HQD_BUSY = 0
>                         PRT_BUSY = 0
>                         ATCL2IU_BUSY = 0
>                         CPF_GFX_BUSY = 0
>                         CPF_CMP_BUSY = 0
>                         GRBM_CPF_STAT_BUSY = 0
>                         CPC_CPF_BUSY = 0
>                         CPF_BUSY = 0
>        [1;33mCP_CPF_BUSY_STAT[0m <- REG_BUS_FIFO_BUSY = 0
>                            CSF_RING_BUSY = 0
>                            CSF_INDIRECT1_BUSY = 0
>                            CSF_INDIRECT2_BUSY = 0
>                            CSF_STATE_BUSY = 0
>                            CSF_CE_INDR1_BUSY = 0
>                            CSF_CE_INDR2_BUSY = 0
>                            CSF_ARBITER_BUSY = 0
>                            CSF_INPUT_BUSY = 0
>                            OUTSTANDING_READ_TAGS = 0
>                            HPD_PROCESSING_EOP_BUSY = 0
>                            HQD_DISPATCH_BUSY = 0
>                            HQD_IQ_TIMER_BUSY = 0
>                            HQD_DMA_OFFLOAD_BUSY = 0
>                            HQD_WAIT_SEMAPHORE_BUSY = 0
>                            HQD_SIGNAL_SEMAPHORE_BUSY = 0
>                            HQD_MESSAGE_BUSY = 0
>                            HQD_PQ_FETCHER_BUSY = 0
>                            HQD_IB_FETCHER_BUSY = 0
>                            HQD_IQ_FETCHER_BUSY = 0
>                            HQD_EOP_FETCHER_BUSY = 0
>                            HQD_CONSUMED_RPTR_BUSY = 0
>                            HQD_FETCHER_ARB_BUSY = 0
>                            HQD_ROQ_ALIGN_BUSY = 0
>                            HQD_ROQ_EOP_BUSY = 0
>                            HQD_ROQ_IQ_BUSY = 0
>                            HQD_ROQ_PQ_BUSY = 0
>                            HQD_ROQ_IB_BUSY = 0
>                            HQD_WPTR_POLL_BUSY = 0
>                            HQD_PQ_BUSY = 0
>                            HQD_IB_BUSY = 0
>        [1;33mCP_CPF_STALLED_STAT1[0m <- RING_FETCHING_DATA = 0
>                                INDR1_FETCHING_DATA = 0
>                                INDR2_FETCHING_DATA = 0
>                                STATE_FETCHING_DATA = 0
>                                TCIU_WAITING_ON_FREE = 0
>                                TCIU_WAITING_ON_TAGS = 0
>                                ATCL2IU_WAITING_ON_FREE = 0
>                                ATCL2IU_WAITING_ON_TAGS = 0
>                                ATCL1_WAITING_ON_TRANS = 0
>
>
>Last 60 lines of dmesg:
>
>[    5.392115] [drm] ring test on 5 succeeded in 2 usecs
>[    5.392122] [drm] ring test on 6 succeeded in 2 usecs
>[    5.392130] [drm] ring test on 7 succeeded in 3 usecs
>[    5.392136] [drm] ring test on 8 succeeded in 2 usecs
>[    5.392179] [drm] ring test on 9 succeeded in 6 usecs
>[    5.392186] [drm] ring test on 10 succeeded in 5 usecs
>[    5.418216] [drm] ring test on 11 succeeded in 2 usecs
>[    5.418218] [drm] UVD initialized successfully.
>[    5.454187] mt7601u 2-2:1.0: EEPROM ver:0b fae:00
>[    5.528282] [drm] ring test on 12 succeeded in 9 usecs
>[    5.528296] [drm] ring test on 13 succeeded in 5 usecs
>[    5.528297] [drm] VCE initialized successfully.
>[    5.750229] ieee80211 phy0: Selected rate control algorithm 'minstrel_ht'
>[    5.750965] usbcore: registered new interface driver mt7601u
>[    5.756093] mt7601u 2-2:1.0 wlp2s0u2: renamed from wlan0
>[    5.890905] [drm] fb mappable at 0xC12A6000
>[    5.890907] [drm] vram apper at 0xC0000000
>[    5.890908] [drm] size 8294400
>[    5.890909] [drm] fb depth is 24
>[    5.890910] [drm]    pitch is 7680
>[    5.891021] fbcon: amdgpudrmfb (fb0) is primary device
>[    6.692943] Console: switching to colour frame buffer device 240x67
>[    6.699033] amdgpu 0000:01:00.0: fb0: amdgpudrmfb frame buffer device
>[    6.714822] [drm] ib test on ring 0 succeeded in 0 usecs
>[    6.715020] [drm] ib test on ring 1 succeeded in 0 usecs
>[    6.715076] [drm] ib test on ring 2 succeeded in 0 usecs
>[    6.715124] [drm] ib test on ring 3 succeeded in 0 usecs
>[    6.715171] [drm] ib test on ring 4 succeeded in 0 usecs
>[    6.715216] [drm] ib test on ring 5 succeeded in 0 usecs
>[    6.715262] [drm] ib test on ring 6 succeeded in 0 usecs
>[    6.715308] [drm] ib test on ring 7 succeeded in 0 usecs
>[    6.715353] [drm] ib test on ring 8 succeeded in 0 usecs
>[    6.715394] [drm] ib test on ring 9 succeeded in 0 usecs
>[    6.715430] [drm] ib test on ring 10 succeeded in 0 usecs
>[    6.716818] [drm] ib test on ring 11 succeeded
>[    6.716951] [drm] ib test on ring 12 succeeded
>[    6.718692] [drm] Initialized amdgpu 3.2.0 20150101 for 0000:01:00.0 on minor 0
>[    8.054538] floppy0: no floppy controllers found
>[   14.273955] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: data=ordered
>[   15.247673] EXT4-fs (sda1): mounted filesystem with ordered data mode. Opts: data=ordered
>[   15.278167] systemd-journald[207]: Received request to flush runtime journal from PID 1
>[   16.325716] microcode: CPU0: new patch_level=0x010000dc
>[   16.325752] microcode: CPU1: new patch_level=0x010000dc
>[   16.325788] microcode: CPU2: new patch_level=0x010000dc
>[   16.325828] microcode: CPU3: new patch_level=0x010000dc
>[   16.325855] microcode: CPU4: new patch_level=0x010000dc
>[   16.325875] microcode: CPU5: new patch_level=0x010000dc
>[   16.382224] it87: Found IT8720F chip at 0x228, revision 8
>[   16.382249] it87: Routing internal VCCH to in7
>[   16.382254] it87: Beeping is supported
>[   16.489706] r8169 0000:03:00.0 enp3s0: link down
>[   16.489711] r8169 0000:03:00.0 enp3s0: link down
>[   16.489763] IPv6: ADDRCONF(NETDEV_UP): enp3s0: link is not ready
>[   17.024255] IPv6: ADDRCONF(NETDEV_UP): enp3s0: link is not ready
>[   17.027926] IPv6: ADDRCONF(NETDEV_UP): wlp2s0u2: link is not ready
>[   19.587051] r8169 0000:03:00.0 enp3s0: link up
>[   19.587079] IPv6: ADDRCONF(NETDEV_CHANGE): enp3s0: link becomes ready
>[   23.504196] usb 1-2: 3:1: cannot get freq at ep 0x84
>[   23.527317] usb 1-2: 3:1: cannot get freq at ep 0x84
>[ 2898.568605] CSteamControlle[20995]: segfault at eb5eee14 ip 00000000eb5eee14 sp 00000000e6afe250 error 14

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Attachments on bug 97806: 126709 | 126712 | 126713

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