Attachment 127551 Details for Bug 98214 – dmesg with drm.debug=14 and running my small debugging patch

dmesg with drm.debug=14 and running my small debugging patch

cdclk.debug (text/plain), 35.12 KB, created by Paul Bolle on 2016-10-26 07:52:09 UTC

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Creator: Paul Bolle

Created: 2016-10-26 07:52:09 UTC

Size: 35.12 KB

patch

obsolete

>[...]
><7>[ 6382.494752] [drm:drm_mode_addfb2] [FB:71]
><7>[ 6382.750151] [drm:drm_mode_addfb2] [FB:62]
><7>[ 6383.446351] i915: cdclk >= crtc_clock: 450000 >= 373250
><7>[ 6383.446354] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
><7>[ 6383.446375] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
><7>[ 6383.446395] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
><7>[ 6383.461253] [drm:connected_sink_compute_bpp] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
><7>[ 6383.461257] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
><7>[ 6383.461266] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
><7>[ 6383.461269] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
><7>[ 6383.461281] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
><7>[ 6383.461283] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
><7>[ 6383.461288] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
><7>[ 6383.461292] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff937ec5b06000 for pipe A
><7>[ 6383.461335] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
><7>[ 6383.461343] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
><7>[ 6383.461346] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
><7>[ 6383.461350] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
><7>[ 6383.461354] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
><7>[ 6383.461356] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
><7>[ 6383.461357] [drm:intel_dump_pipe_config] requested mode:
><7>[ 6383.461363] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
><7>[ 6383.461366] [drm:intel_dump_pipe_config] adjusted mode:
><7>[ 6383.461373] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
><7>[ 6383.461378] [drm:intel_dump_crtc_timings] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
><7>[ 6383.461381] [drm:intel_dump_pipe_config] port clock: 540000
><7>[ 6383.461385] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
><7>[ 6383.461388] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
><7>[ 6383.461392] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
><7>[ 6383.461397] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
><7>[ 6383.461399] [drm:intel_dump_pipe_config] ips: 0
><7>[ 6383.461400] [drm:intel_dump_pipe_config] double wide: 0
><7>[ 6383.461404] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
><7>[ 6383.461408] [drm:intel_dump_pipe_config] planes on this crtc
><7>[ 6383.461410] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
><7>[ 6383.461418] [drm:intel_dump_pipe_config] 	FB:62, fb = 3200x1800 format = XR24 little-endian (0x34325258)
><7>[ 6383.461422] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
><7>[ 6383.461425] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
><7>[ 6383.461430] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
><7>[ 6383.461439] [drm:intel_modeset_checks] New cdclk calculated to be atomic 450000, actual 337500
><7>[ 6383.461445] i915: cdclk >= crtc_clock: 450000 >= 373250
><7>[ 6383.461450] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
><7>[ 6383.461456] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
><7>[ 6383.461458] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
><7>[ 6383.461462] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
><7>[ 6383.461493] [drm:intel_power_well_enable] enabling DC off
><7>[ 6383.461497] [drm:gen9_set_dc_state] Setting DC state from 02 to 00
><7>[ 6383.461513] [drm:intel_edp_backlight_off] 
><7>[ 6383.667578] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
><7>[ 6383.667648] [drm:intel_disable_pipe] disabling pipe A
><7>[ 6383.678541] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
><7>[ 6383.678618] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
><7>[ 6383.678876] [drm:edp_panel_off] Turn eDP port A panel power off
><7>[ 6383.678917] [drm:wait_panel_off] Wait for panel power off time
><7>[ 6383.678999] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control abcd0000
><7>[ 6383.679279] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
><7>[ 6383.679283] [drm:intel_hpd_irq_handler] digital hpd port A - short
><7>[ 6383.679364] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
><7>[ 6383.730968] [drm:wait_panel_status] Wait complete
><7>[ 6383.731004] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
><7>[ 6383.731012] [drm:intel_disable_shared_dpll] disabling DPLL 0
><7>[ 6383.731027] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
><7>[ 6383.731078] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
><7>[ 6383.731086] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
><7>[ 6383.731092] [drm:verify_encoder_state] [ENCODER:36:DDI A]
><7>[ 6383.731096] [drm:verify_encoder_state] [ENCODER:45:DDI B]
><7>[ 6383.731101] [drm:wait_panel_power_cycle] Wait for panel power cycle
><7>[ 6383.731104] [drm:verify_encoder_state] [ENCODER:47:DP-MST A]
><7>[ 6383.731109] [drm:verify_encoder_state] [ENCODER:48:DP-MST B]
><7>[ 6383.731113] [drm:verify_encoder_state] [ENCODER:49:DP-MST C]
><7>[ 6383.731115] [drm:verify_encoder_state] [ENCODER:52:DDI C]
><7>[ 6383.731119] [drm:verify_encoder_state] [ENCODER:54:DP-MST A]
><7>[ 6383.731122] [drm:verify_encoder_state] [ENCODER:55:DP-MST B]
><7>[ 6383.731183] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
><7>[ 6383.731187] [drm:intel_hpd_irq_handler] digital hpd port A - long
><7>[ 6383.731191] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
><7>[ 6383.731204] [drm:verify_encoder_state] [ENCODER:56:DP-MST C]
><7>[ 6383.731209] [drm:intel_connector_verify_state] [CONNECTOR:46:DP-1]
><7>[ 6383.731213] [drm:intel_connector_verify_state] [CONNECTOR:50:HDMI-A-1]
><7>[ 6383.731217] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-2]
><7>[ 6383.731220] [drm:intel_connector_verify_state] [CONNECTOR:57:HDMI-A-2]
><7>[ 6383.731224] [drm:verify_single_dpll_state] DPLL 0
><7>[ 6383.731229] [drm:verify_single_dpll_state] DPLL 1
><7>[ 6383.731234] [drm:verify_single_dpll_state] DPLL 2
><7>[ 6383.731237] [drm:verify_single_dpll_state] DPLL 3
><7>[ 6383.731253] [drm:intel_power_well_disable] disabling DDI A/E power well
><7>[ 6383.731258] [drm:skl_set_power_well] Disabling DDI A/E power well
><7>[ 6383.731265] [drm:intel_connector_verify_state] [CONNECTOR:37:eDP-1]
><7>[ 6383.731272] [drm:verify_crtc_state] [CRTC:26:pipe A]
><7>[ 6383.731278] [drm:verify_single_dpll_state] DPLL 0
><4>[ 6383.776652] ------------[ cut here ]------------
><4>[ 6383.776765] WARNING: CPU: 3 PID: 1393 at drivers/gpu/drm/i915/intel_display.c:14180 skl_max_scale.part.120+0xeb/0x110 [i915]
><5>[ 6383.776768] WARN_ON_ONCE(cdclk < crtc_clock)
><5>[ 6383.776770] Modules linked in:
><5>[ 6383.776773]  rfcomm fuse nf_conntrack_netbios_ns nf_conntrack_broadcast ip6t_rpfilter ip6t_REJECT nf_reject_ipv6 xt_conntrack ip_set nfnetlink ebtable_broute bridge stp llc ebtable_nat cmac ip6table_raw ip6table_security ip6table_nat nf_conntrack_ipv6 nf_defrag_ipv6 nf_nat_ipv6 ip6table_mangle iptable_raw iptable_security iptable_nat nf_conntrack_ipv4 nf_defrag_ipv4 nf_nat_ipv4 nf_nat nf_conntrack iptable_mangle ebtable_filter ebtables ip6table_filter ip6_tables bnep vfat fat arc4 intel_rapl x86_pkg_temp_thermal coretemp snd_soc_skl kvm_intel snd_soc_skl_ipc snd_soc_sst_ipc snd_soc_sst_dsp snd_hda_codec_hdmi snd_hda_ext_core kvm snd_soc_sst_match dell_led snd_soc_core iTCO_wdt iTCO_vendor_support snd_hda_codec_realtek i2c_designware_platform snd_hda_codec_generic i2c_designware_core snd_compress
><5>[ 6383.776822]  iwlmvm snd_pcm_dmaengine ac97_bus irqbypass mac80211 dell_laptop snd_hda_intel uvcvideo dell_wmi dell_smbios dcdbas crct10dif_pclmul crc32_pclmul snd_hda_codec ghash_clmulni_intel snd_hda_core iwlwifi videobuf2_vmalloc videobuf2_memops videobuf2_v4l2 snd_hwdep videobuf2_core snd_seq snd_seq_device cfg80211 videodev snd_pcm media joydev btusb snd_timer pcspkr rtsx_pci_ms btrtl snd i2c_i801 i2c_smbus soundcore memstick mei_me idma64 hci_uart mei btbcm shpchp processor_thermal_device btqca intel_lpss_pci intel_soc_dts_iosf intel_pch_thermal btintel bluetooth pinctrl_sunrisepoint intel_lpss_acpi rfkill pinctrl_intel intel_lpss int3403_thermal intel_hid int340x_thermal_zone wmi sparse_keymap int3400_thermal acpi_thermal_rel acpi_als acpi_pad kfifo_buf industrialio tpm_tis tpm_tis_core tpm
><5>[ 6383.776892]  nfsd auth_rpcgss nfs_acl lockd grace sunrpc hid_multitouch i915 rtsx_pci_sdmmc mmc_core i2c_algo_bit drm_kms_helper crc32c_intel drm serio_raw nvme rtsx_pci nvme_core i2c_hid video fjes
><5>[ 6383.776920] CPU: 3 PID: 1393 Comm: Xorg Not tainted 4.8.4-1.local3.fc24.x86_64 #1
><5>[ 6383.776921] Hardware name: Dell Inc. XPS 13 9350/09JHRY, BIOS 1.4.4 06/14/2016
><5>[ 6383.776924]  0000000000000286 00000000cbb9f481 ffff937ee8d2f900 ffffffff8a3e5f3d
><5>[ 6383.776926]  ffff937ee8d2f950 0000000000000000 ffff937ee8d2f940 ffffffff8a0a7d5b
><5>[ 6383.776927]  0000376400000000 000000000005265c 000000000005b202 ffff937ee8275000
><5>[ 6383.776930] Call Trace:
><5>[ 6383.776942]  [<ffffffff8a3e5f3d>] dump_stack+0x63/0x86
><5>[ 6383.776946]  [<ffffffff8a0a7d5b>] __warn+0xcb/0xf0
><5>[ 6383.776947]  [<ffffffff8a0a7ddf>] warn_slowpath_fmt+0x5f/0x80
><5>[ 6383.776974]  [<ffffffffc038e754>] ? drm_atomic_helper_normalize_zpos+0x264/0x300 [drm_kms_helper]
><5>[ 6383.777029]  [<ffffffffc044e15b>] skl_max_scale.part.120+0xeb/0x110 [i915]
><5>[ 6383.777051]  [<ffffffffc044e246>] intel_check_primary_plane+0xc6/0xe0 [i915]
><5>[ 6383.777059]  [<ffffffffc038e754>] ? drm_atomic_helper_normalize_zpos+0x264/0x300 [drm_kms_helper]
><5>[ 6383.777080]  [<ffffffffc043f3d2>] intel_plane_atomic_check+0x132/0x1f0 [i915]
><5>[ 6383.777086]  [<ffffffffc038b524>] drm_atomic_helper_check_planes+0x84/0x200 [drm_kms_helper]
><5>[ 6383.777109]  [<ffffffffc0459d97>] intel_atomic_check+0x9a7/0x11a0 [i915]
><5>[ 6383.777114]  [<ffffffff8a22c91a>] ? __kmalloc_track_caller+0x17a/0x210
><5>[ 6383.777158]  [<ffffffffc031df07>] drm_atomic_check_only+0x187/0x610 [drm]
><5>[ 6383.777167]  [<ffffffffc031d6c8>] ? drm_atomic_get_crtc_state+0x88/0x100 [drm]
><5>[ 6383.777176]  [<ffffffffc031e3a7>] drm_atomic_commit+0x17/0x60 [drm]
><5>[ 6383.777186]  [<ffffffffc038a90c>] drm_atomic_helper_update_plane+0xec/0x130 [drm_kms_helper]
><5>[ 6383.777195]  [<ffffffffc030d16b>] __setplane_internal+0x22b/0x270 [drm]
><5>[ 6383.777202]  [<ffffffffc030d2e9>] drm_mode_cursor_universal+0x139/0x240 [drm]
><5>[ 6383.777209]  [<ffffffffc030d46e>] drm_mode_cursor_common+0x7e/0x180 [drm]
><5>[ 6383.777217]  [<ffffffffc03119de>] drm_mode_cursor2_ioctl+0xe/0x10 [drm]
><5>[ 6383.777223]  [<ffffffffc0303f0a>] drm_ioctl+0x1da/0x4b0 [drm]
><5>[ 6383.777231]  [<ffffffffc03119d0>] ? drm_mode_cursor_ioctl+0x70/0x70 [drm]
><5>[ 6383.777237]  [<ffffffff8a1161bd>] ? enqueue_hrtimer+0x3d/0x80
><5>[ 6383.777243]  [<ffffffff8a266763>] do_vfs_ioctl+0xa3/0x5e0
><5>[ 6383.777246]  [<ffffffff8a6bd151>] ? __sys_recvmsg+0x51/0x90
><5>[ 6383.777248]  [<ffffffff8a266d19>] SyS_ioctl+0x79/0x90
><5>[ 6383.777253]  [<ffffffff8a7fd4f2>] entry_SYSCALL_64_fastpath+0x1a/0xa4
><4>[ 6383.777255] ---[ end trace d4816cab65af3003 ]---
><7>[ 6383.777256] i915: cdclk < crtc_clock: 337500 < 373250
><7>[ 6383.777263] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
><7>[ 6384.339571] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
><7>[ 6384.339589] [drm:wait_panel_status] Wait complete
><7>[ 6384.339642] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
><7>[ 6384.339654] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
><7>[ 6384.389701] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
><7>[ 6384.389711] [drm:intel_hpd_irq_handler] digital hpd port A - long
><7>[ 6384.389715] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
><7>[ 6384.548098] [drm:intel_dp_get_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
><7>[ 6384.548930] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
><7>[ 6384.549341] [drm:intel_dp_get_dpcd] EDP DPCD : 02 9f 40
><7>[ 6384.549347] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink no
><7>[ 6384.549358] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000
><7>[ 6384.549363] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000
><7>[ 6384.549367] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000
><7>[ 6384.577888] [drm:drm_dp_dpcd_access] too many retries, giving up
><7>[ 6384.578347] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
><7>[ 6385.837503] [drm:intel_modeset_checks] New cdclk calculated to be atomic 337500, actual 337500
><7>[ 6385.837516] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
><7>[ 6385.837525] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
><7>[ 6385.837558] [drm:verify_encoder_state] [ENCODER:36:DDI A]
><7>[ 6385.837564] [drm:verify_encoder_state] [ENCODER:45:DDI B]
><7>[ 6385.837568] [drm:verify_encoder_state] [ENCODER:47:DP-MST A]
><7>[ 6385.837571] [drm:verify_encoder_state] [ENCODER:48:DP-MST B]
><7>[ 6385.837573] [drm:verify_encoder_state] [ENCODER:49:DP-MST C]
><7>[ 6385.837576] [drm:verify_encoder_state] [ENCODER:52:DDI C]
><7>[ 6385.837579] [drm:verify_encoder_state] [ENCODER:54:DP-MST A]
><7>[ 6385.837581] [drm:verify_encoder_state] [ENCODER:55:DP-MST B]
><7>[ 6385.837584] [drm:verify_encoder_state] [ENCODER:56:DP-MST C]
><7>[ 6385.837587] [drm:intel_connector_verify_state] [CONNECTOR:37:eDP-1]
><7>[ 6385.837590] [drm:intel_connector_verify_state] [CONNECTOR:46:DP-1]
><7>[ 6385.837594] [drm:intel_connector_verify_state] [CONNECTOR:50:HDMI-A-1]
><7>[ 6385.837597] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-2]
><7>[ 6385.837600] [drm:intel_connector_verify_state] [CONNECTOR:57:HDMI-A-2]
><7>[ 6385.837603] [drm:verify_single_dpll_state] DPLL 0
><7>[ 6385.837609] [drm:verify_single_dpll_state] DPLL 1
><7>[ 6385.837613] [drm:verify_single_dpll_state] DPLL 2
><7>[ 6385.837616] [drm:verify_single_dpll_state] DPLL 3
><7>[ 6385.837624] [drm:verify_crtc_state] [CRTC:26:pipe A]
><7>[ 6387.603833] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
><7>[ 6387.603877] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0000
><7>[ 6387.603882] [drm:intel_power_well_disable] disabling DC off
><7>[ 6387.603888] [drm:skl_enable_dc6] Enabling DC6
><7>[ 6387.603891] [drm:gen9_set_dc_state] Setting DC state from 00 to 02
><7>[ 6387.604322] [drm:intel_power_well_disable] disabling always-on
><7>[ 6387.606453] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
><7>[ 6387.606460] [drm:intel_hpd_irq_handler] digital hpd port A - long
><7>[ 6387.606464] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
><7>[ 6387.606552] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
><7>[ 7513.431650] [drm:drm_mode_addfb2] [FB:68]
><7>[ 7513.431662] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
><7>[ 7513.431670] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
><7>[ 7513.431692] [drm:connected_sink_compute_bpp] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
><7>[ 7513.431693] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
><7>[ 7513.431702] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
><7>[ 7513.431704] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
><7>[ 7513.431718] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
><7>[ 7513.431719] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
><7>[ 7513.431721] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
><7>[ 7513.431725] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff937edc4c1800 for pipe A
><7>[ 7513.431727] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
><7>[ 7513.431727] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
><7>[ 7513.431728] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
><7>[ 7513.431730] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
><7>[ 7513.431731] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
><7>[ 7513.431732] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
><7>[ 7513.431732] [drm:intel_dump_pipe_config] requested mode:
><7>[ 7513.431735] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
><7>[ 7513.431736] [drm:intel_dump_pipe_config] adjusted mode:
><7>[ 7513.431737] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
><7>[ 7513.431739] [drm:intel_dump_crtc_timings] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
><7>[ 7513.431739] [drm:intel_dump_pipe_config] port clock: 540000
><7>[ 7513.431740] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
><7>[ 7513.431741] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
><7>[ 7513.431742] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
><7>[ 7513.431743] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
><7>[ 7513.431743] [drm:intel_dump_pipe_config] ips: 0
><7>[ 7513.431744] [drm:intel_dump_pipe_config] double wide: 0
><7>[ 7513.431745] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
><7>[ 7513.431745] [drm:intel_dump_pipe_config] planes on this crtc
><7>[ 7513.431747] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
><7>[ 7513.431748] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
><7>[ 7513.431751] [drm:intel_dump_pipe_config] 	FB:66, fb = 256x256 format = AR24 little-endian (0x34325241)
><7>[ 7513.431753] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+-1789+-414 dst 1789x414+-1789+-414
><7>[ 7513.431754] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
><7>[ 7513.431768] [drm:intel_modeset_checks] New cdclk calculated to be atomic 450000, actual 450000
><7>[ 7513.431776] i915: cdclk >= crtc_clock: 450000 >= 373250
><7>[ 7513.431781] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
><7>[ 7513.431787] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
><7>[ 7513.431789] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
><7>[ 7513.431790] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
><7>[ 7513.432048] [drm:intel_power_well_enable] enabling always-on
><7>[ 7513.432050] [drm:intel_power_well_enable] enabling DC off
><7>[ 7513.432313] [drm:gen9_set_dc_state] Setting DC state from 02 to 00
><7>[ 7513.432322] [drm:intel_power_well_enable] enabling DDI A/E power well
><7>[ 7513.432324] [drm:skl_set_power_well] Enabling DDI A/E power well
><7>[ 7513.432329] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
><7>[ 7513.434554] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
><7>[ 7513.434559] [drm:verify_encoder_state] [ENCODER:36:DDI A]
><7>[ 7513.434562] [drm:verify_encoder_state] [ENCODER:45:DDI B]
><7>[ 7513.434567] [drm:verify_encoder_state] [ENCODER:47:DP-MST A]
><7>[ 7513.434569] [drm:verify_encoder_state] [ENCODER:48:DP-MST B]
><7>[ 7513.434569] [drm:verify_encoder_state] [ENCODER:49:DP-MST C]
><7>[ 7513.434570] [drm:verify_encoder_state] [ENCODER:52:DDI C]
><7>[ 7513.434571] [drm:verify_encoder_state] [ENCODER:54:DP-MST A]
><7>[ 7513.434572] [drm:verify_encoder_state] [ENCODER:55:DP-MST B]
><7>[ 7513.434573] [drm:verify_encoder_state] [ENCODER:56:DP-MST C]
><7>[ 7513.434575] [drm:intel_connector_verify_state] [CONNECTOR:46:DP-1]
><7>[ 7513.434576] [drm:intel_connector_verify_state] [CONNECTOR:50:HDMI-A-1]
><7>[ 7513.434577] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-2]
><7>[ 7513.434578] [drm:intel_connector_verify_state] [CONNECTOR:57:HDMI-A-2]
><7>[ 7513.434579] [drm:verify_single_dpll_state] DPLL 0
><7>[ 7513.434581] [drm:verify_single_dpll_state] DPLL 1
><7>[ 7513.434582] [drm:verify_single_dpll_state] DPLL 2
><7>[ 7513.434583] [drm:verify_single_dpll_state] DPLL 3
><7>[ 7513.434586] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
><7>[ 7513.434587] [drm:intel_enable_shared_dpll] enabling DPLL 0
><7>[ 7513.434611] [drm:edp_panel_on] Turn eDP port A panel power on
><7>[ 7513.434629] [drm:wait_panel_power_cycle] Wait for panel power cycle
><7>[ 7513.434704] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
><7>[ 7513.434717] [drm:wait_panel_status] Wait complete
><7>[ 7513.434749] [drm:wait_panel_on] Wait for panel power on
><7>[ 7513.434822] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control abcd0003
><7>[ 7513.484916] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
><7>[ 7513.484920] [drm:intel_hpd_irq_handler] digital hpd port A - long
><7>[ 7513.484922] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
><7>[ 7513.484978] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
><7>[ 7513.637019] [drm:wait_panel_status] Wait complete
><7>[ 7513.637052] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
><7>[ 7513.637119] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
><7>[ 7513.638352] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
><7>[ 7513.638356] [drm:intel_dp_set_signal_levels] Using vswing level 0
><7>[ 7513.638359] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
><7>[ 7513.639047] [drm:intel_dp_link_training_clock_recovery] clock recovery OK
><7>[ 7513.639050] [drm:intel_dp_training_pattern] 5.4 Gbps link rate without sink TPS3 support
><7>[ 7513.640040] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
><7>[ 7513.640043] [drm:intel_dp_set_signal_levels] Using vswing level 2
><7>[ 7513.640045] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
><7>[ 7513.641022] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
><7>[ 7513.641200] [drm:skylake_pfit_enable] for crtc_state = ffff937edc4c1800
><7>[ 7513.641309] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
><7>[ 7513.641318] [drm:intel_enable_pipe] enabling pipe A
><7>[ 7513.641329] [drm:intel_edp_backlight_on] 
><7>[ 7513.641331] [drm:intel_panel_enable_backlight] pipe A
><7>[ 7513.641391] [drm:intel_panel_actually_set_backlight] set backlight PWM = 215
><7>[ 7513.641447] [drm:intel_psr_match_conditions] PSR disable by flag
><7>[ 7513.641449] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
><7>[ 7513.641492] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
><7>[ 7513.641511] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
><7>[ 7513.658147] [drm:intel_connector_verify_state] [CONNECTOR:37:eDP-1]
><7>[ 7513.658158] [drm:verify_crtc_state] [CRTC:26:pipe A]
><7>[ 7513.658182] [drm:verify_single_dpll_state] DPLL 0
><7>[ 7514.841864] [drm:drm_mode_addfb2] [FB:71]
><7>[ 7516.682988] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
><7>[ 7516.683041] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
><7>[ 7516.683042] [drm:intel_power_well_disable] disabling DC off
><7>[ 7516.683044] [drm:skl_enable_dc6] Enabling DC6
><7>[ 7516.683045] [drm:gen9_set_dc_state] Setting DC state from 00 to 02
><7>[ 7528.796218] [drm:connected_sink_compute_bpp] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
><7>[ 7528.796222] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
><7>[ 7528.796231] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
><7>[ 7528.796235] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
><7>[ 7528.796248] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
><7>[ 7528.796250] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
><7>[ 7528.796254] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
><7>[ 7528.796259] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff937edb01d800 for pipe A
><7>[ 7528.796262] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
><7>[ 7528.796264] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
><7>[ 7528.796267] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
><7>[ 7528.796271] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
><7>[ 7528.796275] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
><7>[ 7528.796277] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
><7>[ 7528.796279] [drm:intel_dump_pipe_config] requested mode:
><7>[ 7528.796284] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
><7>[ 7528.796286] [drm:intel_dump_pipe_config] adjusted mode:
><7>[ 7528.796290] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
><7>[ 7528.796295] [drm:intel_dump_crtc_timings] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
><7>[ 7528.796297] [drm:intel_dump_pipe_config] port clock: 540000
><7>[ 7528.796299] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
><7>[ 7528.796302] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
><7>[ 7528.796304] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
><7>[ 7528.796307] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
><7>[ 7528.796309] [drm:intel_dump_pipe_config] ips: 0
><7>[ 7528.796310] [drm:intel_dump_pipe_config] double wide: 0
><7>[ 7528.796313] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
><7>[ 7528.796315] [drm:intel_dump_pipe_config] planes on this crtc
><7>[ 7528.796317] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
><7>[ 7528.796323] [drm:intel_dump_pipe_config] 	FB:71, fb = 3200x1800 format = XR24 little-endian (0x34325258)
><7>[ 7528.796327] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
><7>[ 7528.796329] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
><7>[ 7528.796333] [drm:intel_dump_pipe_config] 	FB:66, fb = 256x256 format = AR24 little-endian (0x34325241)
><7>[ 7528.796337] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+256+256 dst 1789x414+256+256
><7>[ 7528.796340] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
><7>[ 7528.796349] [drm:intel_modeset_checks] New cdclk calculated to be atomic 450000, actual 337500
><7>[ 7528.796355] i915: cdclk >= crtc_clock: 450000 >= 373250
><7>[ 7528.796360] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
><7>[ 7528.796367] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
><7>[ 7528.796369] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
><7>[ 7528.796372] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
><7>[ 7528.796404] [drm:intel_power_well_enable] enabling DC off
><7>[ 7528.796407] [drm:gen9_set_dc_state] Setting DC state from 02 to 00
><7>[ 7528.796425] [drm:intel_edp_backlight_off] 
><7>[ 7529.003094] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
><7>[ 7529.003160] [drm:intel_disable_pipe] disabling pipe A
><7>[ 7529.014008] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
><7>[ 7529.014084] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
><7>[ 7529.014338] [drm:edp_panel_off] Turn eDP port A panel power off
><7>[ 7529.014377] [drm:wait_panel_off] Wait for panel power off time
><7>[ 7529.014456] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control abcd0000
><7>[ 7529.014775] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
><7>[ 7529.014780] [drm:intel_hpd_irq_handler] digital hpd port A - short
><7>[ 7529.014802] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
><7>[ 7529.064991] [drm:wait_panel_status] Wait complete
><7>[ 7529.065021] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
><7>[ 7529.065029] [drm:intel_disable_shared_dpll] disabling DPLL 0
><7>[ 7529.065044] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
><7>[ 7529.065079] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
><7>[ 7529.065099] [drm:wait_panel_power_cycle] Wait for panel power cycle
><7>[ 7529.066658] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
><7>[ 7529.066665] [drm:intel_hpd_irq_handler] digital hpd port A - long
><7>[ 7529.066668] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
><7>[ 7529.067210] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
><7>[ 7529.067215] [drm:verify_encoder_state] [ENCODER:36:DDI A]
><7>[ 7529.067220] [drm:verify_encoder_state] [ENCODER:45:DDI B]
><7>[ 7529.067226] [drm:verify_encoder_state] [ENCODER:47:DP-MST A]
><7>[ 7529.067230] [drm:verify_encoder_state] [ENCODER:48:DP-MST B]
><7>[ 7529.067233] [drm:verify_encoder_state] [ENCODER:49:DP-MST C]
><7>[ 7529.067236] [drm:verify_encoder_state] [ENCODER:52:DDI C]
><7>[ 7529.067240] [drm:verify_encoder_state] [ENCODER:54:DP-MST A]
><7>[ 7529.067243] [drm:verify_encoder_state] [ENCODER:55:DP-MST B]
><7>[ 7529.067246] [drm:verify_encoder_state] [ENCODER:56:DP-MST C]
><7>[ 7529.067249] [drm:intel_connector_verify_state] [CONNECTOR:46:DP-1]
><7>[ 7529.067254] [drm:intel_connector_verify_state] [CONNECTOR:50:HDMI-A-1]
><7>[ 7529.067258] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-2]
><7>[ 7529.067262] [drm:intel_connector_verify_state] [CONNECTOR:57:HDMI-A-2]
><7>[ 7529.067265] [drm:verify_single_dpll_state] DPLL 0
><7>[ 7529.067271] [drm:verify_single_dpll_state] DPLL 1
><7>[ 7529.067276] [drm:verify_single_dpll_state] DPLL 2
><7>[ 7529.067279] [drm:verify_single_dpll_state] DPLL 3
><7>[ 7529.067295] [drm:intel_power_well_disable] disabling DDI A/E power well
><7>[ 7529.067300] [drm:skl_set_power_well] Disabling DDI A/E power well
><7>[ 7529.067307] [drm:intel_connector_verify_state] [CONNECTOR:37:eDP-1]
><7>[ 7529.067313] [drm:verify_crtc_state] [CRTC:26:pipe A]
><7>[ 7529.067319] [drm:verify_single_dpll_state] DPLL 0
><7>[ 7529.675176] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
><7>[ 7529.675198] [drm:wait_panel_status] Wait complete
><7>[ 7529.675254] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
><7>[ 7529.675267] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
><7>[ 7529.725388] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
><7>[ 7529.725395] [drm:intel_hpd_irq_handler] digital hpd port A - long
><7>[ 7529.725399] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 1
><7>[ 7529.883609] [drm:intel_dp_get_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
><7>[ 7529.884430] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
><7>[ 7529.884817] [drm:intel_dp_get_dpcd] EDP DPCD : 02 9f 40
><7>[ 7529.884821] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink no
><7>[ 7529.884843] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000
><7>[ 7529.884848] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000
><7>[ 7529.884851] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000
><7>[ 7529.913036] [drm:drm_dp_dpcd_access] too many retries, giving up
><7>[ 7529.913444] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
><7>[ 7532.938935] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
><7>[ 7532.938994] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0000
><7>[ 7532.938997] [drm:intel_power_well_disable] disabling DC off
><7>[ 7532.939001] [drm:skl_enable_dc6] Enabling DC6
><7>[ 7532.939003] [drm:gen9_set_dc_state] Setting DC state from 00 to 02
><7>[ 7532.939418] [drm:intel_power_well_disable] disabling always-on
><7>[ 7532.941397] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
><7>[ 7532.941402] [drm:intel_hpd_irq_handler] digital hpd port A - long
><7>[ 7532.941404] [drm:intel_hpd_irq_storm_detect] Received HPD interrupt on PIN 4 - cnt: 0
><7>[ 7532.941433] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
><7>[ 7566.828767] [drm:intel_modeset_checks] New cdclk calculated to be atomic 337500, actual 337500
><7>[ 7566.828777] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
><7>[ 7566.828784] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
><7>[ 7566.828806] [drm:intel_power_well_enable] enabling always-on
><7>[ 7566.828808] [drm:intel_power_well_enable] enabling DC off
><7>[ 7566.829073] [drm:gen9_set_dc_state] Setting DC state from 02 to 00
><7>[ 7566.829084] [drm:verify_encoder_state] [ENCODER:36:DDI A]
><7>[ 7566.829089] [drm:verify_encoder_state] [ENCODER:45:DDI B]
><7>[ 7566.829092] [drm:verify_encoder_state] [ENCODER:47:DP-MST A]
><7>[ 7566.829094] [drm:verify_encoder_state] [ENCODER:48:DP-MST B]
><7>[ 7566.829096] [drm:verify_encoder_state] [ENCODER:49:DP-MST C]
><7>[ 7566.829097] [drm:verify_encoder_state] [ENCODER:52:DDI C]
><7>[ 7566.829100] [drm:verify_encoder_state] [ENCODER:54:DP-MST A]
><7>[ 7566.829102] [drm:verify_encoder_state] [ENCODER:55:DP-MST B]
><7>[ 7566.829103] [drm:verify_encoder_state] [ENCODER:56:DP-MST C]
><7>[ 7566.829106] [drm:intel_connector_verify_state] [CONNECTOR:37:eDP-1]
><7>[ 7566.829108] [drm:intel_connector_verify_state] [CONNECTOR:46:DP-1]
><7>[ 7566.829111] [drm:intel_connector_verify_state] [CONNECTOR:50:HDMI-A-1]
><7>[ 7566.829113] [drm:intel_connector_verify_state] [CONNECTOR:53:DP-2]
><7>[ 7566.829115] [drm:intel_connector_verify_state] [CONNECTOR:57:HDMI-A-2]
><7>[ 7566.829118] [drm:verify_single_dpll_state] DPLL 0
><7>[ 7566.829121] [drm:verify_single_dpll_state] DPLL 1
><7>[ 7566.829124] [drm:verify_single_dpll_state] DPLL 2
><7>[ 7566.829126] [drm:verify_single_dpll_state] DPLL 3
><7>[ 7566.829134] [drm:verify_crtc_state] [CRTC:26:pipe A]
><7>[ 7566.829139] [drm:intel_power_well_disable] disabling DC off
><7>[ 7566.829143] [drm:skl_enable_dc6] Enabling DC6
><7>[ 7566.829145] [drm:gen9_set_dc_state] Setting DC state from 00 to 02
><7>[ 7566.829150] [drm:intel_power_well_disable] disabling always-on

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Attachments on bug 98214: 127470 | 127471 | 127472 | 127473 | 127551 | 127554

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