Attachment 128301 Details for Bug 97330 – drm/i915/dsi: Do not clear DPOUNIT_CLOCK_GATE_DISABLE from vlv_init_display_clock_gating

[patch] drm/i915/dsi: Do not clear DPOUNIT_CLOCK_GATE_DISABLE from vlv_init_display_clock_gating

0001-drm-i915-dsi-Do-not-clear-DPOUNIT_CLOCK_GATE_DISABLE.patch (text/plain), 2.20 KB, created by Hans de Goede on 2016-12-01 15:43:29 UTC

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Creator: Hans de Goede

Created: 2016-12-01 15:43:29 UTC

Size: 2.20 KB

patch

obsolete

>From f1ffad9d6217d7cad04d357689326ca8c84e419c Mon Sep 17 00:00:00 2001
>From: Hans de Goede <hdegoede@redhat.com>
>Date: Thu, 1 Dec 2016 15:44:28 +0100
>Subject: [PATCH] drm/i915/dsi: Do not clear DPOUNIT_CLOCK_GATE_DISABLE from
> vlv_init_display_clock_gating
>
>On my Cherrytrail CUBE iwork8 Air tablet PIPE-A would get stuck on loading
>i915 at boot 1 out of every 3 boots, resulting in a non functional LCD.
>Once the i915 driver has successfully loaded, the panel can be disabled /
>enabled without hitting this issue.
>
>The getting stuck is caused by vlv_init_display_clock_gating() clearing
>the DPOUNIT_CLOCK_GATE_DISABLE bit in DSPCLK_GATE_D when called from
>chv_pipe_power_well_ops.enable() on driver load, while PIPE-A is enabled
>driving the DSI LCD by the BIOS.
>
>Clearing this bit while DSI is in use is a known issue and
>intel_dsi_pre_enable() / intel_dsi_post_disable() already set / clear it
>as appropriate.
>
>This commit modifies vlv_init_display_clock_gating() to leave the
>DPOUNIT_CLOCK_GATE_DISABLE bit alone fixing PIPE-A getting stuck.
>
>BugLink: https://bugs.freedesktop.org/show_bug.cgi?id=97330
>Cc: stable@vger.kernel.org
>Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
>index 356c662..b5ce7cb 100644
>--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
>+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
>@@ -1039,7 +1039,18 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
> 
> static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
> {
>-	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
>+	u32 val;
>+
>+	/*
>+	 * When on driver load, PIPE A may be active and driving a DSI display.
>+	 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid PIPE A getting stuck
>+	 * (and never recovering) in this case. intel_dsi_post_disable() will
>+	 * clear it when we turn off the display.
>+	 */
>+	val = I915_READ(DSPCLK_GATE_D);
>+	val &= DPOUNIT_CLOCK_GATE_DISABLE;
>+	val |= VRHUNIT_CLOCK_GATE_DISABLE;
>+	I915_WRITE(DSPCLK_GATE_D, val);
> 
> 	/*
> 	 * Disable trickle feed and enable pnd deadline calculation
>-- 
>2.9.3
>

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Attachments on bug 97330: 125766 | 125812 | 125827 | 128301

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