Attachment 128863 Details for Bug 99345 – dmesg_patch_applied_v2

dmesg_patch_applied_v2

logclean (text/plain), 775.21 KB, created by Andrey on 2017-01-10 16:15:42 UTC

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Creator: Andrey

Created: 2017-01-10 16:15:42 UTC

Size: 775.21 KB

patch

obsolete

>[    0.000000] Linux version 4.9.2+ (root@localhost) (gcc version 5.4.0 (Gentoo 5.4.0 p1.0, pie-0.6.5) ) #30 SMP Tue Jan 10 17:56:26 MSK 2017
>[    0.000000] Command line: BOOT_IMAGE=/vmlinuz-4.9.2+ crypt_root=UUID=b26d3712-3152-4a24-856d-d87602543db9 root=/dev/mapper/root root_trim=yes snd_hda_intel.probe_mask=1 pcie_aspm=force pcie_aspm.policy=powersave usbcore.autosuspend=5 snd_hda_intel.bdl_pos_adj=32 drm.debug=0x1e log_buf_len=1M
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR'
>[    0.000000] x86/fpu: xstate_offset[2]:  576, xstate_sizes[2]:  256
>[    0.000000] x86/fpu: xstate_offset[3]:  832, xstate_sizes[3]:   64
>[    0.000000] x86/fpu: xstate_offset[4]:  896, xstate_sizes[4]:   64
>[    0.000000] x86/fpu: Enabled xstate features 0x1f, context size is 960 bytes, using 'compacted' format.
>[    0.000000] x86/fpu: Using 'eager' FPU context switches.
>[    0.000000] e820: BIOS-provided physical RAM map:
>[    0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000057fff] usable
>[    0.000000] BIOS-e820: [mem 0x0000000000058000-0x0000000000058fff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000000059000-0x000000000009efff] usable
>[    0.000000] BIOS-e820: [mem 0x000000000009f000-0x000000000009ffff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000000100000-0x00000000681d9fff] usable
>[    0.000000] BIOS-e820: [mem 0x00000000681da000-0x00000000681dafff] ACPI NVS
>[    0.000000] BIOS-e820: [mem 0x00000000681db000-0x00000000681dbfff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000681dc000-0x000000007a191fff] usable
>[    0.000000] BIOS-e820: [mem 0x000000007a192000-0x000000007a51ffff] reserved
>[    0.000000] BIOS-e820: [mem 0x000000007a520000-0x000000007a55dfff] ACPI data
>[    0.000000] BIOS-e820: [mem 0x000000007a55e000-0x000000007ac04fff] ACPI NVS
>[    0.000000] BIOS-e820: [mem 0x000000007ac05000-0x000000007b48efff] reserved
>[    0.000000] BIOS-e820: [mem 0x000000007b48f000-0x000000007b4fefff] type 20
>[    0.000000] BIOS-e820: [mem 0x000000007b4ff000-0x000000007b4fffff] usable
>[    0.000000] BIOS-e820: [mem 0x000000007b500000-0x000000007b5fffff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fe000000-0x00000000fe010fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec00fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000047e7fffff] usable
>[    0.000000] NX (Execute Disable) protection: active
>[    0.000000] efi: EFI v2.40 by American Megatrends
>[    0.000000] efi:  ACPI=0x7a52d000  ACPI 2.0=0x7a52d000  SMBIOS=0xf05e0  SMBIOS 3.0=0xf0600  ESRT=0x7b261598  MPS=0xfcbc0 
>[    0.000000] SMBIOS 3.0.0 present.
>[    0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
>[    0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable
>[    0.000000] e820: last_pfn = 0x47e800 max_arch_pfn = 0x400000000
>[    0.000000] MTRR default type: write-back
>[    0.000000] MTRR fixed ranges enabled:
>[    0.000000]   00000-9FFFF write-back
>[    0.000000]   A0000-BFFFF uncachable
>[    0.000000]   C0000-FFFFF write-protect
>[    0.000000] MTRR variable ranges enabled:
>[    0.000000]   0 base 0080000000 mask 7F80000000 uncachable
>[    0.000000]   1 base 007E000000 mask 7FFE000000 uncachable
>[    0.000000]   2 base 007D000000 mask 7FFF000000 uncachable
>[    0.000000]   3 disabled
>[    0.000000]   4 disabled
>[    0.000000]   5 disabled
>[    0.000000]   6 disabled
>[    0.000000]   7 disabled
>[    0.000000]   8 disabled
>[    0.000000]   9 disabled
>[    0.000000] x86/PAT: Configuration [0-7]: WB  WC  UC- UC  WB  WC  UC- WT  
>[    0.000000] e820: last_pfn = 0x7b500 max_arch_pfn = 0x400000000
>[    0.000000] found SMP MP-table at [mem 0x000fce70-0x000fce7f] mapped at [ffff978a800fce70]
>[    0.000000] esrt: Reserving ESRT space from 0x000000007b261598 to 0x000000007b2615d0.
>[    0.000000] Scanning 1 areas for low memory corruption
>[    0.000000] Base memory trampoline at [ffff978a80097000] 97000 size 24576
>[    0.000000] Using GB pages for direct mapping
>[    0.000000] BRK [0x3d9d7b000, 0x3d9d7bfff] PGTABLE
>[    0.000000] BRK [0x3d9d7c000, 0x3d9d7cfff] PGTABLE
>[    0.000000] BRK [0x3d9d7d000, 0x3d9d7dfff] PGTABLE
>[    0.000000] BRK [0x3d9d7e000, 0x3d9d7efff] PGTABLE
>[    0.000000] BRK [0x3d9d7f000, 0x3d9d7ffff] PGTABLE
>[    0.000000] BRK [0x3d9d80000, 0x3d9d80fff] PGTABLE
>[    0.000000] BRK [0x3d9d81000, 0x3d9d81fff] PGTABLE
>[    0.000000] BRK [0x3d9d82000, 0x3d9d82fff] PGTABLE
>[    0.000000] BRK [0x3d9d83000, 0x3d9d83fff] PGTABLE
>[    0.000000] log_buf_len: 1048576 bytes
>[    0.000000] early log buf free: 257032(98%)
>[    0.000000] RAMDISK: [mem 0x37861000-0x37c27fff]
>[    0.000000] ACPI: Early table checksum verification disabled
>[    0.000000] ACPI: RSDP 0x000000007A52D000 000024 (v02 DELL  )
>[    0.000000] ACPI: XSDT 0x000000007A52D0B8 0000F4 (v01 DELL   CBX3     01072009 AMI  00010013)
>[    0.000000] ACPI: FACP 0x000000007A551A48 00010C (v05 DELL   CBX3     01072009 AMI  00010013)
>[    0.000000] ACPI: DSDT 0x000000007A52D240 024807 (v02 DELL   CBX3     01072009 INTL 20160422)
>[    0.000000] ACPI: FACS 0x000000007ABFEF80 000040
>[    0.000000] ACPI: APIC 0x000000007A551B58 000084 (v03 DELL   CBX3     01072009 AMI  00010013)
>[    0.000000] ACPI: FPDT 0x000000007A551BE0 000044 (v01 DELL   CBX3     01072009 AMI  00010013)
>[    0.000000] ACPI: FIDT 0x000000007A551C28 00009C (v01 DELL   CBX3     01072009 AMI  00010013)
>[    0.000000] ACPI: MCFG 0x000000007A551CC8 00003C (v01 DELL   CBX3     01072009 MSFT 00000097)
>[    0.000000] ACPI: HPET 0x000000007A551D08 000038 (v01 DELL   CBX3     01072009 AMI. 0005000B)
>[    0.000000] ACPI: SSDT 0x000000007A551D40 000372 (v01 SataRe SataTabl 00001000 INTL 20160422)
>[    0.000000] ACPI: BOOT 0x000000007A5520B8 000028 (v01 DELL   CBX3     01072009 AMI  00010013)
>[    0.000000] ACPI: SSDT 0x000000007A5520E0 0012E1 (v02 SaSsdt SaSsdt   00003000 INTL 20160422)
>[    0.000000] ACPI: HPET 0x000000007A5533C8 000038 (v01 INTEL  KBL-ULT  00000001 MSFT 0000005F)
>[    0.000000] ACPI: SSDT 0x000000007A553400 000CDB (v02 INTEL  xh_rvp07 00000000 INTL 20160422)
>[    0.000000] ACPI: UEFI 0x000000007A5540E0 000042 (v01                 00000000      00000000)
>[    0.000000] ACPI: SSDT 0x000000007A554128 000EDE (v02 CpuRef CpuSsdt  00003000 INTL 20160422)
>[    0.000000] ACPI: LPIT 0x000000007A555008 000094 (v01 INTEL  KBL-ULT  00000000 MSFT 0000005F)
>[    0.000000] ACPI: WSMT 0x000000007A5550A0 000028 (v01 INTEL  KBL-ULT  00000000 MSFT 0000005F)
>[    0.000000] ACPI: SSDT 0x000000007A5550C8 00029F (v02 INTEL  sensrhub 00000000 INTL 20160422)
>[    0.000000] ACPI: SSDT 0x000000007A555368 003002 (v02 INTEL  PtidDevc 00001000 INTL 20160422)
>[    0.000000] ACPI: DBGP 0x000000007A558370 000034 (v01 INTEL           00000002 MSFT 0000005F)
>[    0.000000] ACPI: DBG2 0x000000007A5583A8 000054 (v00 INTEL           00000002 MSFT 0000005F)
>[    0.000000] ACPI: MSDM 0x000000007A558400 000055 (v03 DELL   CBX3     06222004 AMI  00010013)
>[    0.000000] ACPI: SSDT 0x000000007A558458 004605 (v02 DptfTa DptfTabl 00001000 INTL 20160422)
>[    0.000000] ACPI: SLIC 0x000000007A55CA60 000176 (v03 DELL   CBX3     01072009 MSFT 00010013)
>[    0.000000] ACPI: DMAR 0x000000007A55CBD8 0000F0 (v01 INTEL  KBL      00000001 INTL 00000001)
>[    0.000000] ACPI: NHLT 0x000000007A55CCC8 00002D (v00 INTEL  EDK2     00000002      01000013)
>[    0.000000] ACPI: ASF! 0x000000007A55CCF8 0000A0 (v32 INTEL   HCG     00000001 TFSM 000F4240)
>[    0.000000] ACPI: BGRT 0x000000007A55CD98 000038 (v00 \xfffffff3\xffffffee              01072009 AMI  00010013)
>[    0.000000] ACPI: Local APIC address 0xfee00000
>[    0.000000] No NUMA configuration found
>[    0.000000] Faking a node at [mem 0x0000000000000000-0x000000047e7fffff]
>[    0.000000] NODE_DATA(0) allocated [mem 0x47e6fc000-0x47e6fffff]
>[    0.000000] Zone ranges:
>[    0.000000]   DMA      [mem 0x0000000000001000-0x0000000000ffffff]
>[    0.000000]   DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
>[    0.000000]   Normal   [mem 0x0000000100000000-0x000000047e7fffff]
>[    0.000000] Movable zone start for each node
>[    0.000000] Early memory node ranges
>[    0.000000]   node   0: [mem 0x0000000000001000-0x0000000000057fff]
>[    0.000000]   node   0: [mem 0x0000000000059000-0x000000000009efff]
>[    0.000000]   node   0: [mem 0x0000000000100000-0x00000000681d9fff]
>[    0.000000]   node   0: [mem 0x00000000681dc000-0x000000007a191fff]
>[    0.000000]   node   0: [mem 0x000000007b4ff000-0x000000007b4fffff]
>[    0.000000]   node   0: [mem 0x0000000100000000-0x000000047e7fffff]
>[    0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x000000047e7fffff]
>[    0.000000] On node 0 totalpages: 4163886
>[    0.000000]   DMA zone: 64 pages used for memmap
>[    0.000000]   DMA zone: 25 pages reserved
>[    0.000000]   DMA zone: 3997 pages, LIFO batch:0
>[    0.000000]   DMA32 zone: 7751 pages used for memmap
>[    0.000000]   DMA32 zone: 496017 pages, LIFO batch:31
>[    0.000000]   Normal zone: 57248 pages used for memmap
>[    0.000000]   Normal zone: 3663872 pages, LIFO batch:31
>[    0.000000] Reserving Intel graphics memory at 0x000000007d800000-0x000000007f7fffff
>[    0.000000] ACPI: PM-Timer IO Port: 0x1808
>[    0.000000] ACPI: Local APIC address 0xfee00000
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1])
>[    0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-119
>[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
>[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
>[    0.000000] ACPI: IRQ0 used by override.
>[    0.000000] ACPI: IRQ9 used by override.
>[    0.000000] Using ACPI (MADT) for SMP configuration information
>[    0.000000] ACPI: HPET id: 0x8086a701 base: 0xfed00000
>[    0.000000] smpboot: Allowing 4 CPUs, 0 hotplug CPUs
>[    0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x00058000-0x00058fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x0009f000-0x0009ffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000fffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x681da000-0x681dafff]
>[    0.000000] PM: Registered nosave memory: [mem 0x681db000-0x681dbfff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7a192000-0x7a51ffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7a520000-0x7a55dfff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7a55e000-0x7ac04fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7ac05000-0x7b48efff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7b48f000-0x7b4fefff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7b500000-0x7b5fffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7b600000-0x7d7fffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7d800000-0x7f7fffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7f800000-0xdfffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xe0000000-0xefffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xf0000000-0xfdffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfe000000-0xfe010fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfe011000-0xfebfffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfec00000-0xfec00fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfec01000-0xfedfffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfee00000-0xfee00fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfee01000-0xfeffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xff000000-0xffffffff]
>[    0.000000] e820: [mem 0x7f800000-0xdfffffff] available for PCI devices
>[    0.000000] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns
>[    0.000000] setup_percpu: NR_CPUS:4 nr_cpumask_bits:4 nr_cpu_ids:4 nr_node_ids:1
>[    0.000000] percpu: Embedded 34 pages/cpu @ffff978efe400000 s101016 r8192 d30056 u524288
>[    0.000000] pcpu-alloc: s101016 r8192 d30056 u524288 alloc=1*2097152
>[    0.000000] pcpu-alloc: [0] 0 1 2 3 
>[    0.000000] Built 1 zonelists in Node order, mobility grouping on.  Total pages: 4098798
>[    0.000000] Policy zone: Normal
>[    0.000000] Kernel command line: BOOT_IMAGE=/vmlinuz-4.9.2+ crypt_root=UUID=b26d3712-3152-4a24-856d-d87602543db9 root=/dev/mapper/root root_trim=yes snd_hda_intel.probe_mask=1 pcie_aspm=force pcie_aspm.policy=powersave usbcore.autosuspend=5 snd_hda_intel.bdl_pos_adj=32 drm.debug=0x1e log_buf_len=1M
>[    0.000000] PCIe ASPM is forcibly enabled
>[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
>[    0.000000] Calgary: detecting Calgary via BIOS EBDA area
>[    0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing!
>[    0.000000] Memory: 16203472K/16655544K available (9226K kernel code, 1296K rwdata, 3868K rodata, 1432K init, 788K bss, 452072K reserved, 0K cma-reserved)
>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
>[    0.000000] Hierarchical RCU implementation.
>[    0.000000] 	Build-time adjustment of leaf fanout to 64.
>[    0.000000] NR_IRQS:4352 nr_irqs:1024 16
>[    0.000000] spurious 8259A interrupt: IRQ7.
>[    0.000000] Console: colour dummy device 80x25
>[    0.000000] console [tty0] enabled
>[    0.000000] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635855245 ns
>[    0.000000] hpet clockevent registered
>[    0.000000] tsc: Detected 2900.000 MHz processor
>[    0.000038] Calibrating delay loop (skipped), value calculated using timer frequency.. 5808.00 BogoMIPS (lpj=2904000)
>[    0.000045] pid_max: default: 32768 minimum: 301
>[    0.000049] ACPI: Core revision 20160831
>[    0.031688] ACPI: 8 ACPI AML tables successfully acquired and loaded
>[    0.032515] Security Framework initialized
>[    0.032518] SELinux:  Initializing.
>[    0.032525] SELinux:  Starting in permissive mode
>[    0.033267] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes)
>[    0.036415] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes)
>[    0.037792] Mount-cache hash table entries: 32768 (order: 6, 262144 bytes)
>[    0.037806] Mountpoint-cache hash table entries: 32768 (order: 6, 262144 bytes)
>[    0.038130] CPU: Physical Processor ID: 0
>[    0.038133] CPU: Processor Core ID: 0
>[    0.038139] ENERGY_PERF_BIAS: Set to 'normal', was 'performance'
>[    0.038141] ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)
>[    0.038148] mce: CPU supports 8 MCE banks
>[    0.038160] mce: [Hardware Error]: Machine check events logged
>[    0.038178] CPU0: Thermal monitoring enabled (TM1)
>[    0.038198] process: using mwait in idle threads
>[    0.038203] Last level iTLB entries: 4KB 64, 2MB 8, 4MB 8
>[    0.038205] Last level dTLB entries: 4KB 64, 2MB 0, 4MB 0, 1GB 4
>[    0.038994] Freeing SMP alternatives memory: 32K (ffffffffba0ac000 - ffffffffba0b4000)
>[    0.043856] ftrace: allocating 34362 entries in 135 pages
>[    0.059054] smpboot: Max logical packages: 2
>[    0.059062] DMAR: Host address width 39
>[    0.059065] DMAR: DRHD base: 0x000000fed90000 flags: 0x0
>[    0.059074] DMAR: dmar0: reg_base_addr fed90000 ver 1:0 cap 1c0000c40660462 ecap 19e2ff0505e
>[    0.059079] DMAR: DRHD base: 0x000000fed91000 flags: 0x1
>[    0.059084] DMAR: dmar1: reg_base_addr fed91000 ver 1:0 cap d2008c40660462 ecap f050da
>[    0.059089] DMAR: RMRR base: 0x0000007a261000 end: 0x0000007a280fff
>[    0.059092] DMAR: RMRR base: 0x0000007d000000 end: 0x0000007f7fffff
>[    0.059095] DMAR: ANDD device: 1 name: \_SB.PCI0.I2C0
>[    0.059098] DMAR: ANDD device: 2 name: \_SB.PCI0.I2C1
>[    0.059101] DMAR-IR: IOAPIC id 2 under DRHD base  0xfed91000 IOMMU 1
>[    0.059104] DMAR-IR: HPET id 0 under DRHD base 0xfed91000
>[    0.060649] DMAR-IR: Enabled IRQ remapping in xapic mode
>[    0.064790] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
>[    0.074802] TSC deadline timer enabled
>[    0.074807] smpboot: CPU0: Intel(R) Core(TM) i7-7500U CPU @ 2.70GHz (family: 0x6, model: 0x8e, stepping: 0x9)
>[    0.074815] Performance Events: PEBS fmt3+, Skylake events, 32-deep LBR, full-width counters, Intel PMU driver.
>[    0.074847] ... version:                4
>[    0.074849] ... bit width:              48
>[    0.074852] ... generic registers:      4
>[    0.074854] ... value mask:             0000ffffffffffff
>[    0.074856] ... max period:             00007fffffffffff
>[    0.074858] ... fixed-purpose events:   3
>[    0.074861] ... event mask:             000000070000000f
>[    0.075105] x86: Booting SMP configuration:
>[    0.075108] .... node  #0, CPUs:      #1 #2 #3
>[    0.261079] x86: Booted up 1 node, 4 CPUs
>[    0.261087] smpboot: Total of 4 processors activated (23245.95 BogoMIPS)
>[    0.265620] devtmpfs: initialized
>[    0.265881] PM: Registering ACPI NVS region [mem 0x681da000-0x681dafff] (4096 bytes)
>[    0.265886] PM: Registering ACPI NVS region [mem 0x7a55e000-0x7ac04fff] (6975488 bytes)
>[    0.266021] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns
>[    0.266055] pinctrl core: initialized pinctrl subsystem
>[    0.266226] RTC time: 14:57:12, date: 01/10/17
>[    0.266289] NET: Registered protocol family 16
>[    0.272167] cpuidle: using governor menu
>[    0.272254] Simple Boot Flag at 0x47 set to 0x80
>[    0.272284] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it
>[    0.272289] ACPI: bus type PCI registered
>[    0.272342] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
>[    0.272347] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820
>[    0.272359] PCI: Using configuration type 1 for base access
>[    0.272367] dmi type 0xB1 record - unknown flag
>[    0.279272] HugeTLB registered 2 MB page size, pre-allocated 0 pages
>[    0.279388] ACPI: Added _OSI(Module Device)
>[    0.279393] ACPI: Added _OSI(Processor Device)
>[    0.279395] ACPI: Added _OSI(3.0 _SCP Extensions)
>[    0.279398] ACPI: Added _OSI(Processor Aggregator Device)
>[    0.280619] ACPI: Executed 31 blocks of module-level executable AML code
>[    0.289310] ACPI: [Firmware Bug]: BIOS _OSI(Linux) query ignored
>[    0.351744] ACPI: Dynamic OEM Table Load:
>[    0.351753] ACPI: SSDT 0xFFFF978EEBBE1800 0006F6 (v02 PmRef  Cpu0Ist  00003000 INTL 20160422)
>[    0.351890] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.351945] ACPI: \_PR_.CPU0: _OSC native thermal LVT Acked
>[    0.352715] ACPI: Dynamic OEM Table Load:
>[    0.352722] ACPI: SSDT 0xFFFF978EEB4CC800 0003FF (v02 PmRef  Cpu0Cst  00003001 INTL 20160422)
>[    0.352845] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.353161] ACPI: Dynamic OEM Table Load:
>[    0.353168] ACPI: SSDT 0xFFFF978EEBBE2000 00065C (v02 PmRef  ApIst    00003000 INTL 20160422)
>[    0.353460] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.353588] ACPI: Dynamic OEM Table Load:
>[    0.353594] ACPI: SSDT 0xFFFF978EEB599200 00018A (v02 PmRef  ApCst    00003000 INTL 20160422)
>[    0.353717] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.354769] ACPI : EC: EC started
>[    0.373214] ACPI: \_SB_.PCI0.LPCB.ECDV: Used as first EC
>[    0.373219] ACPI: \_SB_.PCI0.LPCB.ECDV: GPE=0x14, EC_CMD/EC_SC=0x934, EC_DATA=0x930
>[    0.373223] ACPI: \_SB_.PCI0.LPCB.ECDV: Used as boot DSDT EC to handle transactions
>[    0.373227] ACPI: Interpreter enabled
>[    0.373264] ACPI: (supports S0 S3 S4 S5)
>[    0.373267] ACPI: Using IOAPIC for interrupt routing
>[    0.373303] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
>[    0.380450] ACPI: Power Resource [WRST] (on)
>[    0.380760] ACPI: Power Resource [WRST] (on)
>[    0.381057] ACPI: Power Resource [WRST] (on)
>[    0.381357] ACPI: Power Resource [WRST] (on)
>[    0.381658] ACPI: Power Resource [WRST] (on)
>[    0.381958] ACPI: Power Resource [WRST] (on)
>[    0.382443] ACPI: Power Resource [WRST] (on)
>[    0.382737] ACPI: Power Resource [WRST] (on)
>[    0.383031] ACPI: Power Resource [WRST] (on)
>[    0.383588] ACPI: Power Resource [WRST] (on)
>[    0.383959] ACPI: Power Resource [WRST] (on)
>[    0.384262] ACPI: Power Resource [WRST] (on)
>[    0.384559] ACPI: Power Resource [WRST] (on)
>[    0.384855] ACPI: Power Resource [WRST] (on)
>[    0.385150] ACPI: Power Resource [WRST] (on)
>[    0.385447] ACPI: Power Resource [WRST] (on)
>[    0.385755] ACPI: Power Resource [WRST] (on)
>[    0.386886] ACPI: Power Resource [WRST] (on)
>[    0.387184] ACPI: Power Resource [WRST] (on)
>[    0.387496] ACPI: Power Resource [WRST] (on)
>[    0.412776] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-fe])
>[    0.412784] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI]
>[    0.412812] acpi PNP0A08:00: _OSC failed (AE_ERROR); disabling ASPM
>[    0.413100] PCI host bridge to bus 0000:00
>[    0.413104] pci_bus 0000:00: root bus resource [io  0x0000-0x0cf7 window]
>[    0.413107] pci_bus 0000:00: root bus resource [io  0x0d00-0xffff window]
>[    0.413110] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
>[    0.413114] pci_bus 0000:00: root bus resource [mem 0x7f800000-0xdfffffff window]
>[    0.413119] pci_bus 0000:00: root bus resource [mem 0xfd000000-0xfe7fffff window]
>[    0.413124] pci_bus 0000:00: root bus resource [bus 00-fe]
>[    0.413135] pci 0000:00:00.0: [8086:5904] type 00 class 0x060000
>[    0.413263] pci 0000:00:02.0: [8086:5916] type 00 class 0x030000
>[    0.413272] pci 0000:00:02.0: reg 0x10: [mem 0xdb000000-0xdbffffff 64bit]
>[    0.413278] pci 0000:00:02.0: reg 0x18: [mem 0x90000000-0x9fffffff 64bit pref]
>[    0.413282] pci 0000:00:02.0: reg 0x20: [io  0xf000-0xf03f]
>[    0.413415] pci 0000:00:04.0: [8086:1903] type 00 class 0x118000
>[    0.413425] pci 0000:00:04.0: reg 0x10: [mem 0xdc420000-0xdc427fff 64bit]
>[    0.413617] pci 0000:00:14.0: [8086:9d2f] type 00 class 0x0c0330
>[    0.413636] pci 0000:00:14.0: reg 0x10: [mem 0xdc410000-0xdc41ffff 64bit]
>[    0.413706] pci 0000:00:14.0: PME# supported from D3hot D3cold
>[    0.413861] pci 0000:00:14.0: System wakeup disabled by ACPI
>[    0.413903] pci 0000:00:14.2: [8086:9d31] type 00 class 0x118000
>[    0.413922] pci 0000:00:14.2: reg 0x10: [mem 0xdc434000-0xdc434fff 64bit]
>[    0.414168] pci 0000:00:15.0: [8086:9d60] type 00 class 0x118000
>[    0.414376] pci 0000:00:15.0: reg 0x10: [mem 0xdc433000-0xdc433fff 64bit]
>[    0.415329] pci 0000:00:15.1: [8086:9d61] type 00 class 0x118000
>[    0.415537] pci 0000:00:15.1: reg 0x10: [mem 0xdc432000-0xdc432fff 64bit]
>[    0.416429] pci 0000:00:16.0: [8086:9d3a] type 00 class 0x078000
>[    0.416449] pci 0000:00:16.0: reg 0x10: [mem 0xdc431000-0xdc431fff 64bit]
>[    0.416522] pci 0000:00:16.0: PME# supported from D3hot
>[    0.416681] pci 0000:00:1c.0: [8086:9d10] type 01 class 0x060400
>[    0.416751] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
>[    0.416862] pci 0000:00:1c.0: System wakeup disabled by ACPI
>[    0.416911] pci 0000:00:1c.4: [8086:9d14] type 01 class 0x060400
>[    0.416980] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold
>[    0.417090] pci 0000:00:1c.4: System wakeup disabled by ACPI
>[    0.417127] pci 0000:00:1c.5: [8086:9d15] type 01 class 0x060400
>[    0.417199] pci 0000:00:1c.5: PME# supported from D0 D3hot D3cold
>[    0.417309] pci 0000:00:1c.5: System wakeup disabled by ACPI
>[    0.417364] pci 0000:00:1d.0: [8086:9d18] type 01 class 0x060400
>[    0.417435] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
>[    0.417545] pci 0000:00:1d.0: System wakeup disabled by ACPI
>[    0.417607] pci 0000:00:1f.0: [8086:9d58] type 00 class 0x060100
>[    0.417810] pci 0000:00:1f.2: [8086:9d21] type 00 class 0x058000
>[    0.417819] pci 0000:00:1f.2: reg 0x10: [mem 0xdc42c000-0xdc42ffff]
>[    0.417962] pci 0000:00:1f.3: [8086:9d71] type 00 class 0x040380
>[    0.417982] pci 0000:00:1f.3: reg 0x10: [mem 0xdc428000-0xdc42bfff 64bit]
>[    0.418007] pci 0000:00:1f.3: reg 0x20: [mem 0xdc400000-0xdc40ffff 64bit]
>[    0.418053] pci 0000:00:1f.3: PME# supported from D3hot D3cold
>[    0.418188] pci 0000:00:1f.3: System wakeup disabled by ACPI
>[    0.418225] pci 0000:00:1f.4: [8086:9d23] type 00 class 0x0c0500
>[    0.418272] pci 0000:00:1f.4: reg 0x10: [mem 0xdc430000-0xdc4300ff 64bit]
>[    0.418344] pci 0000:00:1f.4: reg 0x20: [io  0xf040-0xf05f]
>[    0.418549] pci 0000:00:1c.0: PCI bridge to [bus 01-39]
>[    0.418557] pci 0000:00:1c.0:   bridge window [mem 0xc4000000-0xda0fffff]
>[    0.418561] pci 0000:00:1c.0:   bridge window [mem 0xa0000000-0xc1ffffff 64bit pref]
>[    0.418857] pci 0000:3a:00.0: [168c:003e] type 00 class 0x028000
>[    0.419082] pci 0000:3a:00.0: reg 0x10: [mem 0xdc000000-0xdc1fffff 64bit]
>[    0.420221] pci 0000:3a:00.0: PME# supported from D0 D3hot D3cold
>[    0.420824] pci 0000:3a:00.0: System wakeup disabled by ACPI
>[    0.424813] pci 0000:00:1c.4: PCI bridge to [bus 3a]
>[    0.424819] pci 0000:00:1c.4:   bridge window [mem 0xdc000000-0xdc1fffff]
>[    0.424940] pci 0000:3b:00.0: [10ec:525a] type 00 class 0xff0000
>[    0.424968] pci 0000:3b:00.0: reg 0x14: [mem 0xdc300000-0xdc300fff]
>[    0.425083] pci 0000:3b:00.0: supports D1 D2
>[    0.425084] pci 0000:3b:00.0: PME# supported from D1 D2 D3hot D3cold
>[    0.425165] pci 0000:3b:00.0: System wakeup disabled by ACPI
>[    0.428661] pci 0000:00:1c.5: PCI bridge to [bus 3b]
>[    0.428668] pci 0000:00:1c.5:   bridge window [mem 0xdc300000-0xdc3fffff]
>[    0.429039] pci 0000:3c:00.0: [14a4:2200] type 00 class 0x010802
>[    0.429058] pci 0000:3c:00.0: reg 0x10: [mem 0xdc200000-0xdc203fff 64bit]
>[    0.429246] pci 0000:3c:00.0: System wakeup disabled by ACPI
>[    0.432825] pci 0000:00:1d.0: PCI bridge to [bus 3c]
>[    0.432831] pci 0000:00:1d.0:   bridge window [mem 0xdc200000-0xdc2fffff]
>[    0.434870] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    0.434940] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 *10 11 12 14 15)
>[    0.434985] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    0.435031] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    0.435080] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    0.435125] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    0.435178] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    0.435230] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    0.440526] ACPI: Enabled 5 GPEs in block 00 to 7F
>[    0.440899] ACPI : EC: event unblocked
>[    0.440937] ACPI: \_SB_.PCI0.LPCB.ECDV: GPE=0x14, EC_CMD/EC_SC=0x934, EC_DATA=0x930
>[    0.440944] ACPI: \_SB_.PCI0.LPCB.ECDV: Used as boot DSDT EC to handle transactions and events
>[    0.441368] vgaarb: setting as boot device: PCI:0000:00:02.0
>[    0.441380] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
>[    0.441386] vgaarb: loaded
>[    0.441388] vgaarb: bridge control possible 0000:00:02.0
>[    0.441447] SCSI subsystem initialized
>[    0.441484] libata version 3.00 loaded.
>[    0.441512] ACPI: bus type USB registered
>[    0.441535] usbcore: registered new interface driver usbfs
>[    0.441548] usbcore: registered new interface driver hub
>[    0.441571] usbcore: registered new device driver usb
>[    0.441597] pps_core: LinuxPPS API ver. 1 registered
>[    0.441601] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
>[    0.441609] PTP clock support registered
>[    0.441628] Registered efivars operations
>[    0.449193] wmi: Mapper loaded
>[    0.449251] Advanced Linux Sound Architecture Driver Initialized.
>[    0.449261] PCI: Using ACPI for IRQ routing
>[    0.473333] PCI: pci_cache_line_size set to 64 bytes
>[    0.474470] e820: reserve RAM buffer [mem 0x00058000-0x0005ffff]
>[    0.474471] e820: reserve RAM buffer [mem 0x0009f000-0x0009ffff]
>[    0.474471] e820: reserve RAM buffer [mem 0x681da000-0x6bffffff]
>[    0.474472] e820: reserve RAM buffer [mem 0x7a192000-0x7bffffff]
>[    0.474473] e820: reserve RAM buffer [mem 0x7b500000-0x7bffffff]
>[    0.474474] e820: reserve RAM buffer [mem 0x47e800000-0x47fffffff]
>[    0.474636] NetLabel: Initializing
>[    0.474639] NetLabel:  domain hash size = 128
>[    0.474642] NetLabel:  protocols = UNLABELED CIPSOv4
>[    0.474654] NetLabel:  unlabeled traffic allowed by default
>[    0.474846] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
>[    0.474853] hpet0: 8 comparators, 64-bit 24.000000 MHz counter
>[    0.476918] clocksource: Switched to clocksource hpet
>[    0.485791] VFS: Disk quotas dquot_6.6.0
>[    0.485806] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
>[    0.485866] pnp: PnP ACPI init
>[    0.486119] system 00:00: [io  0x0680-0x069f] has been reserved
>[    0.486123] system 00:00: [io  0xffff] has been reserved
>[    0.486127] system 00:00: [io  0xffff] has been reserved
>[    0.486129] system 00:00: [io  0xffff] has been reserved
>[    0.486132] system 00:00: [io  0x1800-0x18fe] has been reserved
>[    0.486135] system 00:00: [io  0x164e-0x164f] has been reserved
>[    0.486139] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.486220] pnp 00:01: Plug and Play ACPI device, IDs PNP0b00 (active)
>[    0.486266] system 00:02: [io  0x1854-0x1857] has been reserved
>[    0.486270] system 00:02: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active)
>[    0.486382] pnp 00:03: Plug and Play ACPI device, IDs PNP0303 (active)
>[    0.486399] pnp 00:04: Plug and Play ACPI device, IDs DLL075b PNP0f13 (active)
>[    0.486617] system 00:05: [mem 0xfed10000-0xfed17fff] has been reserved
>[    0.486621] system 00:05: [mem 0xfed18000-0xfed18fff] has been reserved
>[    0.486624] system 00:05: [mem 0xfed19000-0xfed19fff] has been reserved
>[    0.486629] system 00:05: [mem 0xe0000000-0xefffffff] has been reserved
>[    0.486633] system 00:05: [mem 0xfed20000-0xfed3ffff] has been reserved
>[    0.486636] system 00:05: [mem 0xfed90000-0xfed93fff] could not be reserved
>[    0.486640] system 00:05: [mem 0xfed45000-0xfed8ffff] has been reserved
>[    0.486644] system 00:05: [mem 0xff000000-0xffffffff] has been reserved
>[    0.486648] system 00:05: [mem 0xfee00000-0xfeefffff] could not be reserved
>[    0.486651] system 00:05: [mem 0xdffe0000-0xdfffffff] has been reserved
>[    0.486656] system 00:05: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.486698] system 00:06: [mem 0xfd000000-0xfdabffff] has been reserved
>[    0.486702] system 00:06: [mem 0xfdad0000-0xfdadffff] has been reserved
>[    0.486706] system 00:06: [mem 0xfdb00000-0xfdffffff] has been reserved
>[    0.486710] system 00:06: [mem 0xfe000000-0xfe01ffff] could not be reserved
>[    0.486714] system 00:06: [mem 0xfe036000-0xfe03bfff] has been reserved
>[    0.486717] system 00:06: [mem 0xfe03d000-0xfe3fffff] has been reserved
>[    0.486721] system 00:06: [mem 0xfe410000-0xfe7fffff] has been reserved
>[    0.486725] system 00:06: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.486990] system 00:07: [io  0xff00-0xfffe] has been reserved
>[    0.486996] system 00:07: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.487830] system 00:08: [mem 0xfe029000-0xfe029fff] has been reserved
>[    0.487860] system 00:08: [mem 0xfe028000-0xfe028fff] has been reserved
>[    0.487866] system 00:08: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.489685] pnp: PnP ACPI: found 9 devices
>[    0.496183] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns
>[    0.496205] pci 0000:00:1c.0: bridge window [io  0x1000-0x0fff] to [bus 01-39] add_size 1000
>[    0.496232] pci 0000:00:1c.0: res[13]=[io  0x1000-0x0fff] res_to_dev_res add_size 1000 min_align 1000
>[    0.496233] pci 0000:00:1c.0: res[13]=[io  0x1000-0x1fff] res_to_dev_res add_size 1000 min_align 1000
>[    0.496239] pci 0000:00:1c.0: BAR 13: assigned [io  0x2000-0x2fff]
>[    0.496247] pci 0000:00:1c.0: PCI bridge to [bus 01-39]
>[    0.496257] pci 0000:00:1c.0:   bridge window [io  0x2000-0x2fff]
>[    0.496262] pci 0000:00:1c.0:   bridge window [mem 0xc4000000-0xda0fffff]
>[    0.496267] pci 0000:00:1c.0:   bridge window [mem 0xa0000000-0xc1ffffff 64bit pref]
>[    0.496279] pci 0000:00:1c.4: PCI bridge to [bus 3a]
>[    0.496284] pci 0000:00:1c.4:   bridge window [mem 0xdc000000-0xdc1fffff]
>[    0.496292] pci 0000:00:1c.5: PCI bridge to [bus 3b]
>[    0.496298] pci 0000:00:1c.5:   bridge window [mem 0xdc300000-0xdc3fffff]
>[    0.496306] pci 0000:00:1d.0: PCI bridge to [bus 3c]
>[    0.496319] pci 0000:00:1d.0:   bridge window [mem 0xdc200000-0xdc2fffff]
>[    0.496328] pci_bus 0000:00: resource 4 [io  0x0000-0x0cf7 window]
>[    0.496329] pci_bus 0000:00: resource 5 [io  0x0d00-0xffff window]
>[    0.496330] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window]
>[    0.496331] pci_bus 0000:00: resource 7 [mem 0x7f800000-0xdfffffff window]
>[    0.496332] pci_bus 0000:00: resource 8 [mem 0xfd000000-0xfe7fffff window]
>[    0.496333] pci_bus 0000:01: resource 0 [io  0x2000-0x2fff]
>[    0.496333] pci_bus 0000:01: resource 1 [mem 0xc4000000-0xda0fffff]
>[    0.496334] pci_bus 0000:01: resource 2 [mem 0xa0000000-0xc1ffffff 64bit pref]
>[    0.496335] pci_bus 0000:3a: resource 1 [mem 0xdc000000-0xdc1fffff]
>[    0.496336] pci_bus 0000:3b: resource 1 [mem 0xdc300000-0xdc3fffff]
>[    0.496337] pci_bus 0000:3c: resource 1 [mem 0xdc200000-0xdc2fffff]
>[    0.496457] NET: Registered protocol family 2
>[    0.496595] TCP established hash table entries: 131072 (order: 8, 1048576 bytes)
>[    0.496789] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
>[    0.496944] TCP: Hash tables configured (established 131072 bind 65536)
>[    0.496987] UDP hash table entries: 8192 (order: 6, 262144 bytes)
>[    0.497029] UDP-Lite hash table entries: 8192 (order: 6, 262144 bytes)
>[    0.497089] NET: Registered protocol family 1
>[    0.497102] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff]
>[    0.498605] PCI: CLS 0 bytes, default 64
>[    0.498635] Unpacking initramfs...
>[    0.898845] Freeing initrd memory: 3868K (ffff978ab7861000 - ffff978ab7c28000)
>[    0.898875] DMAR: ACPI device "device:78" under DMAR at fed91000 as 00:15.0
>[    0.898880] DMAR: ACPI device "device:79" under DMAR at fed91000 as 00:15.1
>[    0.898892] DMAR: No ATSR found
>[    0.899308] DMAR: dmar0: Using Queued invalidation
>[    0.899417] dmar0: Allocated order 8 PASID table.
>[    0.899502] DMAR: dmar1: Using Queued invalidation
>[    0.899621] DMAR: Setting RMRR:
>[    0.899681] DMAR: Setting identity map for device 0000:00:02.0 [0x7d000000 - 0x7f7fffff]
>[    0.899726] DMAR: Setting identity map for device 0000:00:14.0 [0x7a261000 - 0x7a280fff]
>[    0.899736] DMAR: Prepare 0-16MiB unity mapping for LPC
>[    0.899754] DMAR: Setting identity map for device 0000:00:1f.0 [0x0 - 0xffffff]
>[    0.900081] DMAR: Intel(R) Virtualization Technology for Directed I/O
>[    0.900134] iommu: Adding device 0000:00:00.0 to group 0
>[    0.900146] iommu: Adding device 0000:00:02.0 to group 1
>[    0.900156] iommu: Adding device 0000:00:04.0 to group 2
>[    0.900174] iommu: Adding device 0000:00:14.0 to group 3
>[    0.900184] iommu: Adding device 0000:00:14.2 to group 3
>[    0.900198] iommu: Adding device 0000:00:15.0 to group 4
>[    0.900207] iommu: Adding device 0000:00:15.1 to group 4
>[    0.900218] iommu: Adding device 0000:00:16.0 to group 5
>[    0.900268] iommu: Adding device 0000:00:1c.0 to group 6
>[    0.900290] iommu: Adding device 0000:00:1c.4 to group 6
>[    0.900308] iommu: Adding device 0000:00:1c.5 to group 6
>[    0.900333] iommu: Adding device 0000:00:1d.0 to group 7
>[    0.900350] iommu: Adding device 0000:00:1f.0 to group 8
>[    0.900359] iommu: Adding device 0000:00:1f.2 to group 8
>[    0.900368] iommu: Adding device 0000:00:1f.3 to group 8
>[    0.900376] iommu: Adding device 0000:00:1f.4 to group 8
>[    0.900393] iommu: Adding device 0000:3a:00.0 to group 6
>[    0.900405] iommu: Adding device 0000:3b:00.0 to group 6
>[    0.900435] iommu: Adding device 0000:3c:00.0 to group 7
>[    0.902188] Scanning for low memory corruption every 60 seconds
>[    0.902445] futex hash table entries: 1024 (order: 4, 65536 bytes)
>[    0.902469] audit: initializing netlink subsys (disabled)
>[    0.902485] audit: type=2000 audit(1484060232.883:1): initialized
>[    0.902784] Initialise system trusted keyrings
>[    0.902866] workingset: timestamp_bits=56 max_order=22 bucket_order=0
>[    0.904967] SELinux:  Registering netfilter hooks
>[    0.906575] Key type asymmetric registered
>[    0.906579] Asymmetric key parser 'x509' registered
>[    0.906611] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249)
>[    0.906616] io scheduler noop registered (default)
>[    0.906619] io scheduler deadline registered
>[    0.906625] io scheduler cfq registered
>[    0.907352] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
>[    0.907390] efifb: probing for efifb
>[    0.907407] efifb: framebuffer at 0x90000000, using 22528k, total 22528k
>[    0.907411] efifb: mode is 3200x1800x32, linelength=12800, pages=1
>[    0.907414] efifb: scrolling: redraw
>[    0.907417] efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0
>[    0.917971] Console: switching to colour frame buffer device 400x112
>[    0.927913] fb0: EFI VGA frame buffer device
>[    0.927960] intel_idle: MWAIT substates: 0x11142120
>[    0.927961] intel_idle: v0.4.1 model 0x8E
>[    0.928155] intel_idle: lapic_timer_reliable_states 0xffffffff
>[    0.929948] ACPI: AC Adapter [AC] (on-line)
>[    0.930540] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0D:00/input/input0
>[    0.931192] ACPI: Lid Switch [LID0]
>[    0.931242] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1
>[    0.931270] ACPI: Power Button [PBTN]
>[    0.931329] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input2
>[    0.931357] ACPI: Sleep Button [SBTN]
>[    0.931395] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input3
>[    0.931420] ACPI: Power Button [PWRF]
>[    0.933358] thermal LNXTHERM:00: registered as thermal_zone0
>[    0.933380] ACPI: Thermal Zone [THM] (25 C)
>[    0.933523] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
>[    0.934269] Non-volatile memory driver v1.3
>[    0.934325] [drm] Initialized
>[    0.934540] [drm:intel_gvt_init] GVT-g is disabled by kernel params
>[    0.934544] [drm:i915_driver_load] Found SunrisePoint LP PCH
>[    0.934548] [drm:intel_power_domains_init] Allowed DC state mask 03
>[    0.934579] [drm:intel_device_info_dump] i915 device info: gen=9, pciid=0x5916 rev=0x02 flags=is_kabylake,has_fbc,has_psr,has_runtime_pm,has_csr,has_resource_streamer,has_rc6,has_dp_mst,has_gmbus_irq,has_hw_contexts,has_logical_ring_contexts,has_guc,has_hotplug,has_llc,has_ddi,has_fpga_dbg,
>[    0.934822] [drm:intel_device_info_runtime_init] slice mask: 0001
>[    0.934824] [drm:intel_device_info_runtime_init] slice total: 1
>[    0.934825] [drm:intel_device_info_runtime_init] subslice total: 3
>[    0.934827] [drm:intel_device_info_runtime_init] subslice mask 0007
>[    0.934828] [drm:intel_device_info_runtime_init] subslice per slice: 3
>[    0.934830] [drm:intel_device_info_runtime_init] EU total: 24
>[    0.934831] [drm:intel_device_info_runtime_init] EU per subslice: 8
>[    0.934833] [drm:intel_device_info_runtime_init] has slice power gating: n
>[    0.934834] [drm:intel_device_info_runtime_init] has subslice power gating: n
>[    0.934836] [drm:intel_device_info_runtime_init] has EU power gating: y
>[    0.934837] [drm:i915_driver_load] ppgtt mode: 3
>[    0.934839] [drm:i915_driver_load] use GPU sempahores? no
>[    0.934852] [drm] Memory usable by graphics device = 4096M
>[    0.934895] [drm:i915_ggtt_probe_hw] GMADR size = 256M
>[    0.934897] [drm:i915_ggtt_probe_hw] GTT stolen size = 32M
>[    0.934897] [drm] VT-d active for gfx access
>[    0.934914] checking generic (90000000 1600000) vs hw (90000000 10000000)
>[    0.934915] fb: switching to inteldrmfb from EFI VGA
>[    0.934970] Console: switching to colour dummy device 80x25
>[    0.935040] [drm] Replacing VGA console driver
>[    0.935072] [drm:i915_gem_init_stolen] Memory reserved for graphics device: 32768K, usable: 31744K
>[    0.935088] [drm:intel_opregion_setup] graphic opregion physical addr: 0x7abf8018
>[    0.935092] [drm:intel_opregion_setup] Public ACPI methods supported
>[    0.935094] [drm:intel_opregion_setup] SWSCI supported
>[    0.941014] [drm:intel_opregion_setup] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300583
>[    0.941021] [drm:intel_opregion_setup] ASLE supported
>[    0.941023] [drm:intel_opregion_setup] ASLE extension supported
>[    0.941025] [drm:intel_opregion_setup] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[    0.941082] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[    0.941087] [drm] Driver supports precise vblank timestamp query.
>[    0.941093] [drm:intel_bios_init] Set default to SSC at 120000 kHz
>[    0.941094] [drm:intel_bios_init] VBT signature "$VBT SKYLAKE        ", BDB version 206
>[    0.941096] [drm:intel_bios_init] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[    0.941097] [drm:intel_bios_init] crt_ddc_bus_pin: 2
>[    0.942952] [drm:intel_opregion_get_panel_type] Ignoring OpRegion panel type (0)
>[    0.942953] [drm:intel_bios_init] Panel type: 2 (VBT)
>[    0.942954] [drm:intel_bios_init] DRRS supported mode is seamless
>[    0.942957] [drm:intel_bios_init] Found panel mode in BIOS VBT tables:
>[    0.942960] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 0 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x8 0xa
>[    0.942961] [drm:intel_bios_init] VBT initial LVDS value 30033c
>[    0.942963] [drm:intel_bios_init] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 10, level 255
>[    0.942964] [drm:intel_bios_init] Unsupported child device size for SDVO mapping.
>[    0.942965] [drm:intel_bios_init] Expected child device config size for VBT version 206 not known; assuming 38
>[    0.942966] [drm:intel_bios_init] DRRS State Enabled:0
>[    0.942968] [drm:intel_bios_init] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[    0.942969] [drm:intel_bios_init] VBT HDMI level shift for port A: 0
>[    0.942970] [drm:intel_bios_init] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[    0.942971] [drm:intel_bios_init] VBT HDMI level shift for port B: 8
>[    0.942973] [drm:intel_bios_init] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[    0.942974] [drm:intel_bios_init] VBT HDMI level shift for port C: 8
>[    0.943006] [drm:intel_dsm_detect] no _DSM method for intel device
>[    0.943030] [drm:intel_update_rawclk] rawclk rate: 24000 kHz
>[    0.943035] [drm:gen9_set_dc_state] Setting DC state from 00 to 00
>[    0.943057] [drm:intel_power_well_enable] enabling power well 1
>[    0.943068] [drm:intel_power_well_enable] enabling MISC IO power well
>[    0.943073] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[    0.943076] [drm:intel_update_max_cdclk] Max CD clock rate: 675000 kHz
>[    0.943077] [drm:intel_update_max_cdclk] Max dotclock rate: 675000 kHz
>[    0.943091] [drm:intel_power_well_enable] enabling always-on
>[    0.943092] [drm:intel_power_well_enable] enabling DC off
>[    0.943095] [drm:gen9_set_dc_state] Setting DC state from 00 to 00
>[    0.943099] [drm:intel_power_well_enable] enabling power well 2
>[    0.943102] [drm:intel_power_well_enable] enabling DDI A/E power well
>[    0.943105] [drm:intel_power_well_enable] enabling DDI B power well
>[    0.943108] [drm:skl_set_power_well] Enabling DDI B power well
>[    0.943110] [drm:intel_power_well_enable] enabling DDI C power well
>[    0.943112] [drm:skl_set_power_well] Enabling DDI C power well
>[    0.943114] [drm:intel_power_well_enable] enabling DDI D power well
>[    0.943116] [drm:skl_set_power_well] Enabling DDI D power well
>[    0.943118] [drm:gen9_set_dc_state] Setting DC state from 00 to 00
>[    0.943132] [drm:intel_csr_ucode_init] Loading i915/kbl_dmc_ver1_01.bin
>[    0.943608] [drm:intel_fbc_init] Sanitized enable_fbc value: 0
>[    0.943616] [drm:intel_print_wm_latency] Gen9 Plane WM0 latency 2 (2.0 usec)
>[    0.943617] [drm:intel_print_wm_latency] Gen9 Plane WM1 latency 19 (19.0 usec)
>[    0.943617] [drm:intel_print_wm_latency] Gen9 Plane WM2 latency 28 (28.0 usec)
>[    0.943618] [drm:intel_print_wm_latency] Gen9 Plane WM3 latency 32 (32.0 usec)
>[    0.943619] [drm:intel_print_wm_latency] Gen9 Plane WM4 latency 63 (63.0 usec)
>[    0.943620] [drm:intel_print_wm_latency] Gen9 Plane WM5 latency 77 (77.0 usec)
>[    0.943621] [drm:intel_print_wm_latency] Gen9 Plane WM6 latency 83 (83.0 usec)
>[    0.943622] [drm:intel_print_wm_latency] Gen9 Plane WM7 latency 99 (99.0 usec)
>[    0.943623] [drm:intel_modeset_init] 3 display pipes available.
>[    0.943635] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[    0.943638] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
>[    0.943996] [drm:intel_dp_init_connector] Adding eDP connector on port A
>[    0.944003] [drm:intel_dp_init_connector] using AUX A for port A (VBT)
>[    0.944077] [drm:intel_pps_dump_state] cur t1_t3 0 t8 0 t9 0 t10 500 t11_t12 6000
>[    0.944079] [drm:intel_pps_dump_state] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
>[    0.944081] [drm:intel_dp_init_panel_power_sequencer.part.17] panel power up delay 200, power down delay 50, power cycle delay 600
>[    0.944083] [drm:intel_dp_init_panel_power_sequencer.part.17] backlight on delay 1, off delay 200
>[    0.944158] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x4af06
>[    0.944186] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[    0.944261] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000f
>[    0.944786] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[    0.945174] [drm:intel_dp_init_connector] Detected EDP PSR Panel.
>[    0.945318] [drm] Finished loading i915/kbl_dmc_ver1_01.bin (v1.1)
>[    0.945565] [drm:intel_dp_init_connector] EDP DPCD : 02 9f 40
>[    0.949733] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[    0.949734] [drm:intel_dp_init_connector] VBT doesn't support DRRS
>[    0.949785] [drm:intel_panel_setup_backlight] Connector eDP-1 backlight initialized, enabled, brightness 282/937
>[    0.949809] [drm:intel_dp_init_connector] Adding DP connector on port B
>[    0.949816] [drm:intel_dp_init_connector] using AUX B for port B (VBT)
>[    0.949824] [drm:intel_hdmi_init_connector] Adding HDMI connector on port B
>[    0.949832] [drm:intel_hdmi_init_connector] Using DDC pin 0x5 for port B (VBT)
>[    0.949849] [drm:intel_dp_init_connector] Adding DP connector on port C
>[    0.949856] [drm:intel_dp_init_connector] using AUX C for port C (VBT)
>[    0.949861] [drm:intel_hdmi_init_connector] Adding HDMI connector on port C
>[    0.949864] [drm:intel_hdmi_init_connector] Using DDC pin 0x4 for port C (VBT)
>[    0.949875] [drm:intel_modeset_setup_hw_state] [CRTC:26:pipe A] hw state readout: enabled
>[    0.949878] [drm:intel_modeset_setup_hw_state] [CRTC:30:pipe B] hw state readout: disabled
>[    0.949880] [drm:intel_modeset_setup_hw_state] [CRTC:34:pipe C] hw state readout: disabled
>[    0.949882] [drm:intel_modeset_setup_hw_state] DPLL 0 hw state readout: crtc_mask 0x00000001, on 1
>[    0.949884] [drm:intel_modeset_setup_hw_state] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[    0.949885] [drm:intel_modeset_setup_hw_state] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[    0.949886] [drm:intel_modeset_setup_hw_state] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[    0.949892] [drm:intel_modeset_setup_hw_state] [ENCODER:36:DDI A] hw state readout: enabled, pipe A
>[    0.949894] [drm:intel_modeset_setup_hw_state] [ENCODER:45:DDI B] hw state readout: disabled, pipe A
>[    0.949895] [drm:intel_modeset_setup_hw_state] [ENCODER:47:DP-MST A] hw state readout: disabled, pipe A
>[    0.949896] [drm:intel_modeset_setup_hw_state] [ENCODER:48:DP-MST B] hw state readout: disabled, pipe B
>[    0.949897] [drm:intel_modeset_setup_hw_state] [ENCODER:49:DP-MST C] hw state readout: disabled, pipe C
>[    0.949898] [drm:intel_modeset_setup_hw_state] [ENCODER:52:DDI C] hw state readout: disabled, pipe A
>[    0.949899] [drm:intel_modeset_setup_hw_state] [ENCODER:54:DP-MST A] hw state readout: disabled, pipe A
>[    0.949900] [drm:intel_modeset_setup_hw_state] [ENCODER:55:DP-MST B] hw state readout: disabled, pipe B
>[    0.949901] [drm:intel_modeset_setup_hw_state] [ENCODER:56:DP-MST C] hw state readout: disabled, pipe C
>[    0.949903] [drm:intel_modeset_setup_hw_state] [CONNECTOR:37:eDP-1] hw state readout: enabled
>[    0.949905] [drm:intel_modeset_setup_hw_state] [CONNECTOR:46:DP-1] hw state readout: disabled
>[    0.949906] [drm:intel_modeset_setup_hw_state] [CONNECTOR:50:HDMI-A-1] hw state readout: disabled
>[    0.949908] [drm:intel_modeset_setup_hw_state] [CONNECTOR:53:DP-2] hw state readout: disabled
>[    0.949909] [drm:intel_modeset_setup_hw_state] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[    0.949912] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978eeb625000
>[    0.949966] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][setup_hw_state] config ffff978eeb625000 for pipe A
>[    0.949968] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[    0.949969] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    0.949970] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    0.949971] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 362389, link_n: 524288, tu: 64
>[    0.949973] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    0.949974] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    0.949975] [drm:intel_dump_pipe_config] requested mode:
>[    0.949977] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373249 3200 3248 3280 3360 1800 1803 1808 1852 0x40 0xa
>[    0.949978] [drm:intel_dump_pipe_config] adjusted mode:
>[    0.949980] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373249 3200 3248 3280 3360 1800 1803 1808 1852 0x40 0xa
>[    0.949981] [drm:intel_dump_pipe_config] crtc timings: 373249 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x40 flags: 0xa
>[    0.949982] [drm:intel_dump_pipe_config] port clock: 540000
>[    0.949983] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[    0.949984] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0
>[    0.949986] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    0.949987] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x0c800708, enabled
>[    0.949988] [drm:intel_dump_pipe_config] ips: 0
>[    0.949989] [drm:intel_dump_pipe_config] double wide: 0
>[    0.949990] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[    0.949991] [drm:intel_dump_pipe_config] planes on this crtc
>[    0.949992] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[    0.949993] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[    0.949994] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[    0.949996] [drm:intel_dump_pipe_config] [CRTC:30:pipe B][setup_hw_state] config ffff978eeb626000 for pipe B
>[    0.949997] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[    0.949998] [drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0
>[    0.949999] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    0.950000] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    0.950002] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    0.950003] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    0.950004] [drm:intel_dump_pipe_config] requested mode:
>[    0.950006] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    0.950007] [drm:intel_dump_pipe_config] adjusted mode:
>[    0.950009] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    0.950011] [drm:intel_dump_pipe_config] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[    0.950012] [drm:intel_dump_pipe_config] port clock: 0
>[    0.950013] [drm:intel_dump_pipe_config] pipe src size: 0x0
>[    0.950014] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[    0.950015] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    0.950016] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    0.950017] [drm:intel_dump_pipe_config] ips: 0
>[    0.950018] [drm:intel_dump_pipe_config] double wide: 0
>[    0.950020] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[    0.950021] [drm:intel_dump_pipe_config] planes on this crtc
>[    0.950022] [drm:intel_dump_pipe_config] [PLANE:28:plane 1B] disabled, scaler_id = -1
>[    0.950023] [drm:intel_dump_pipe_config] [PLANE:29:cursor B] disabled, scaler_id = -1
>[    0.950024] [drm:intel_dump_pipe_config] [PLANE:31:plane 2B] disabled, scaler_id = -1
>[    0.950031] [drm:intel_dump_pipe_config] [CRTC:34:pipe C][setup_hw_state] config ffff978eeb627000 for pipe C
>[    0.950032] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[    0.950033] [drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0
>[    0.950035] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    0.950038] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    0.950039] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    0.950040] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    0.950041] [drm:intel_dump_pipe_config] requested mode:
>[    0.950043] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    0.950044] [drm:intel_dump_pipe_config] adjusted mode:
>[    0.950046] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    0.950047] [drm:intel_dump_pipe_config] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[    0.950048] [drm:intel_dump_pipe_config] port clock: 0
>[    0.950049] [drm:intel_dump_pipe_config] pipe src size: 0x0
>[    0.950050] [drm:intel_dump_pipe_config] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[    0.950051] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    0.950052] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    0.950053] [drm:intel_dump_pipe_config] ips: 0
>[    0.950054] [drm:intel_dump_pipe_config] double wide: 0
>[    0.950055] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[    0.950055] [drm:intel_dump_pipe_config] planes on this crtc
>[    0.950056] [drm:intel_dump_pipe_config] [PLANE:32:plane 1C] disabled, scaler_id = -1
>[    0.950057] [drm:intel_dump_pipe_config] [PLANE:33:cursor C] disabled, scaler_id = -1
>[    0.950058] [drm:intel_dump_pipe_config] [PLANE:35:plane 2C] disabled, scaler_id = -1
>[    0.950088] [drm:intel_power_well_disable] disabling DDI D power well
>[    0.950090] [drm:skl_set_power_well] Disabling DDI D power well
>[    0.950093] [drm:intel_power_well_disable] disabling DDI C power well
>[    0.950095] [drm:skl_set_power_well] Disabling DDI C power well
>[    0.950097] [drm:intel_power_well_disable] disabling DDI B power well
>[    0.950099] [drm:skl_set_power_well] Disabling DDI B power well
>[    0.950101] [drm:intel_power_well_disable] disabling power well 2
>[    0.950107] [drm:skl_set_power_well] Disabling power well 2
>[    0.950114] [drm:skylake_get_initial_plane_config] pipe A with fb: size=3200x1800@32, offset=0, pitch 12800, size 0x15f9000
>[    0.950375] [drm:i915_gem_init_ggtt] clearing unused GTT space: [0, fffff000]
>[    0.952479] [drm:i915_gem_context_init] LR context support initialized
>[    0.952482] [drm:i915_gem_object_create_stolen] creating stolen object: size=1000
>[    0.952486] [drm:_i915_gem_object_create_stolen] offset=0x1000, size=4096
>[    0.952490] [drm:intel_engine_create_scratch] render ring pipe control offset: 0xffffe000
>[    0.952598] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[    0.952599] [drm:_i915_gem_object_create_stolen] offset=0x2000, size=16384
>[    0.952735] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[    0.952737] [drm:_i915_gem_object_create_stolen] offset=0x6000, size=16384
>[    0.952784] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[    0.952787] [drm:_i915_gem_object_create_stolen] offset=0xa000, size=16384
>[    0.952840] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[    0.952841] [drm:_i915_gem_object_create_stolen] offset=0xe000, size=16384
>[    0.952888] [drm:gen8_init_common_ring] Execlists enabled for render ring
>[    0.952968] [drm:gen8_init_common_ring] Execlists enabled for blitter ring
>[    0.953009] [drm:gen8_init_common_ring] Execlists enabled for bsd ring
>[    0.953049] [drm:gen8_init_common_ring] Execlists enabled for video enhancement ring
>[    0.953087] [drm:intel_guc_setup] GuC fw status: path i915/kbl_guc_ver9_14.bin, fetch NONE, load NONE
>[    0.953097] [drm] GuC firmware load skipped
>[    0.953131] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[    0.953137] [drm:intel_fbdev_init] pipe A not active or no fb, skipping
>[    0.953139] [drm:intel_fbdev_init] pipe B not active or no fb, skipping
>[    0.953141] [drm:intel_fbdev_init] pipe C not active or no fb, skipping
>[    0.953143] [drm:intel_fbdev_init] no active fbs found, not using BIOS config
>[    0.953234] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1]
>[    0.953237] [drm:intel_dp_detect] Display Port TPS3 support: source yes, sink no
>[    0.953240] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[    0.953243] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000
>[    0.953245] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000
>[    0.953291] ACPI: Battery Slot [BAT0] (battery present)
>[    0.953642] [drm:drm_helper_hpd_irq_event] [CONNECTOR:37:eDP-1] status updated from unknown to connected
>[    0.953644] [drm:intel_dp_detect] [CONNECTOR:46:DP-1]
>[    0.953646] [drm:intel_power_well_enable] enabling power well 2
>[    0.953649] [drm:skl_set_power_well] Enabling power well 2
>[    0.953677] [drm:intel_power_well_disable] disabling power well 2
>[    0.953683] [drm:skl_set_power_well] Disabling power well 2
>[    0.953686] [drm:drm_helper_hpd_irq_event] [CONNECTOR:46:DP-1] status updated from unknown to disconnected
>[    0.953688] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-1]
>[    0.954013] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    0.954014] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    0.954401] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    0.954404] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[    0.954765] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    0.954766] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    0.955073] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    0.955075] [drm:drm_helper_hpd_irq_event] [CONNECTOR:50:HDMI-A-1] status updated from unknown to disconnected
>[    0.955077] [drm:intel_dp_detect] [CONNECTOR:53:DP-2]
>[    0.955079] [drm:intel_power_well_enable] enabling power well 2
>[    0.955081] [drm:skl_set_power_well] Enabling power well 2
>[    0.955108] [drm:intel_power_well_disable] disabling power well 2
>[    0.955114] [drm:skl_set_power_well] Disabling power well 2
>[    0.955130] [drm:drm_helper_hpd_irq_event] [CONNECTOR:53:DP-2] status updated from unknown to disconnected
>[    0.955131] [drm:intel_hdmi_detect] [CONNECTOR:57:HDMI-A-2]
>[    0.955514] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    0.955516] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    0.955941] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    0.955944] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[    0.956345] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    0.956347] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    0.956632] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    0.956635] [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-2] status updated from unknown to disconnected
>[    0.956825] [drm:intel_backlight_device_register] Connector eDP-1 backlight sysfs interface registered
>[    0.956832] [drm:intel_dp_connector_register] registering DPDDC-A bus for card0-eDP-1
>[    0.956873] [drm:intel_dp_connector_register] registering DPDDC-B bus for card0-DP-1
>[    0.956950] [drm:intel_dp_connector_register] registering DPDDC-C bus for card0-DP-2
>[    0.957582] [drm:intel_opregion_register] 9 outputs detected
>[    0.958880] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[    0.959793] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input4
>[    0.959824] [drm] Initialized i915 1.6.0 20160919 for 0000:00:02.0 on minor 0
>[    0.959845] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1]
>[    0.959847] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1]
>[    0.959850] [drm:intel_dp_detect] Display Port TPS3 support: source yes, sink no
>[    0.959853] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[    0.959856] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000
>[    0.959858] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000
>[    0.960289] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[    0.960294] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1] probed modes :
>[    0.960297] [drm:drm_mode_debug_printmodeline] Modeline 38:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[    0.960300] [drm:drm_mode_debug_printmodeline] Modeline 39:"3200x1800" 48 298600 3200 3248 3280 3360 1800 1803 1808 1852 0x40 0xa
>[    0.960303] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:46:DP-1]
>[    0.960305] [drm:intel_dp_detect] [CONNECTOR:46:DP-1]
>[    0.960308] [drm:intel_power_well_enable] enabling power well 2
>[    0.960310] [drm:skl_set_power_well] Enabling power well 2
>[    0.960339] [drm:intel_power_well_disable] disabling power well 2
>[    0.960355] [drm:skl_set_power_well] Disabling power well 2
>[    0.960359] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:46:DP-1] disconnected
>[    0.960361] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:HDMI-A-1]
>[    0.960363] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-1]
>[    0.960662] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    0.960663] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    0.960997] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    0.961000] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[    0.961296] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    0.961298] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    0.961613] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    0.961616] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:HDMI-A-1] disconnected
>[    0.961618] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-2]
>[    0.961620] [drm:intel_dp_detect] [CONNECTOR:53:DP-2]
>[    0.961622] [drm:intel_power_well_enable] enabling power well 2
>[    0.961625] [drm:skl_set_power_well] Enabling power well 2
>[    0.961653] [drm:intel_power_well_disable] disabling power well 2
>[    0.961660] [drm:skl_set_power_well] Disabling power well 2
>[    0.961663] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-2] disconnected
>[    0.961665] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[    0.961667] [drm:intel_hdmi_detect] [CONNECTOR:57:HDMI-A-2]
>[    0.961992] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    0.961994] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    0.962139] loop: module loaded
>[    0.962303] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    0.962305] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[    0.962326] nvme nvme0: pci function 0000:3c:00.0
>[    0.962770] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    0.962771] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    0.962877] e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
>[    0.962881] e100: Copyright(c) 1999-2006 Intel Corporation
>[    0.962894] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
>[    0.962897] e1000: Copyright (c) 1999-2006 Intel Corporation.
>[    0.962910] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
>[    0.962913] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
>[    0.963189] sky2: driver version 1.30
>[    0.963950] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    0.963953] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[    0.963955] [drm:drm_setup_crtcs] 
>[    0.963957] [drm:drm_setup_crtcs] connector 37 enabled? yes
>[    0.963958] [drm:drm_setup_crtcs] connector 46 enabled? no
>[    0.963959] [drm:drm_setup_crtcs] connector 50 enabled? no
>[    0.963960] [drm:drm_setup_crtcs] connector 53 enabled? no
>[    0.963962] [drm:drm_setup_crtcs] connector 57 enabled? no
>[    0.964157] [drm:intel_fb_initial_config] looking for cmdline mode on connector eDP-1
>[    0.964159] [drm:intel_fb_initial_config] looking for preferred mode on connector eDP-1 0
>[    0.964162] [drm:intel_fb_initial_config] connector eDP-1 on [CRTC:26:pipe A]: 3200x1800
>[    0.964164] [drm:intel_fb_initial_config] connector DP-1 not enabled, skipping
>[    0.964165] [drm:intel_fb_initial_config] connector HDMI-A-1 not enabled, skipping
>[    0.964167] [drm:intel_fb_initial_config] connector DP-2 not enabled, skipping
>[    0.964169] [drm:intel_fb_initial_config] connector HDMI-A-2 not enabled, skipping
>[    0.964171] [drm:drm_setup_crtcs] desired mode 3200x1800 set on crtc 26 (0,0)
>[    0.964173] [drm:intelfb_create] no BIOS fb, allocating a new one
>[    0.964427] ath10k_pci 0000:3a:00.0: enabling device (0000 -> 0002)
>[    0.966722] ath10k_pci 0000:3a:00.0: pci irq msi oper_irq_mode 2 irq_mode 0 reset_mode 0
>[    0.969496] [drm:intelfb_create] allocated 3200x1800 fb: 0x000c0000
>[    0.969607] fbcon: inteldrmfb (fb0) is primary device
>[    0.969667] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee6ea1000
>[    0.969670] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978eebbbbe40 state to ffff978ee6ea1000
>[    0.969672] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978eebaf9a80 state to ffff978ee6ea1000
>[    0.969673] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eebaf9a80 to [NOCRTC]
>[    0.969674] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978eebaf9a80
>[    0.969676] [drm:drm_atomic_get_plane_state] Added [PLANE:27:plane 2A] ffff978eebaf9780 state to ffff978ee6ea1000
>[    0.969677] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eebaf9780 to [NOCRTC]
>[    0.969678] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978eebaf9780
>[    0.969679] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 1B] ffff978eebaf9900 state to ffff978ee6ea1000
>[    0.969680] [drm:drm_atomic_get_plane_state] Added [PLANE:29:cursor B] ffff978eebaf9480 state to ffff978ee6ea1000
>[    0.969681] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eebaf9480 to [NOCRTC]
>[    0.969682] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978eebaf9480
>[    0.969683] [drm:drm_atomic_get_plane_state] Added [PLANE:31:plane 2B] ffff978eeac9fb40 state to ffff978ee6ea1000
>[    0.969684] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eeac9fb40 to [NOCRTC]
>[    0.969685] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978eeac9fb40
>[    0.969687] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 1C] ffff978eeac9fe40 state to ffff978ee6ea1000
>[    0.969688] [drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor C] ffff978eeac9f300 state to ffff978ee6ea1000
>[    0.969690] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eeac9f300 to [NOCRTC]
>[    0.969691] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978eeac9f300
>[    0.969693] [drm:drm_atomic_get_plane_state] Added [PLANE:35:plane 2C] ffff978eeac9fcc0 state to ffff978ee6ea1000
>[    0.969694] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eeac9fcc0 to [NOCRTC]
>[    0.969695] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978eeac9fcc0
>[    0.969698] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee6ea1800 state to ffff978ee6ea1000
>[    0.969701] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee6ea1800
>[    0.969702] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eebbbbe40 to [CRTC:26:pipe A]
>[    0.969704] [drm:drm_atomic_set_fb_for_plane] Set [FB:60] for plane state ffff978eebbbbe40
>[    0.969706] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee6ea1000
>[    0.969708] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb018a0 state to ffff978ee6ea1000
>[    0.969710] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb018a0 to [NOCRTC]
>[    0.969712] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb018a0 to [CRTC:26:pipe A]
>[    0.969719] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee6ea2000 state to ffff978ee6ea1000
>[    0.969721] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff978ee6ea2000
>[    0.969721] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eebaf9900 to [NOCRTC]
>[    0.969722] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978eebaf9900
>[    0.969724] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff978ee6ea1000
>[    0.969725] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee6ea2800 state to ffff978ee6ea1000
>[    0.969726] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff978ee6ea2800
>[    0.969727] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eeac9fe40 to [NOCRTC]
>[    0.969728] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978eeac9fe40
>[    0.969729] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff978ee6ea1000
>[    0.969730] [drm:drm_atomic_check_only] checking ffff978ee6ea1000
>[    0.969734] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[    0.969735] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[    0.969737] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee6ea1000
>[    0.969739] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[    0.969739] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[    0.969743] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[    0.969745] [drm:skl_update_scaler] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[    0.969748] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[    0.969752] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[    0.969754] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[    0.969755] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[    0.969757] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee6ea1800 for pipe A
>[    0.969758] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[    0.969759] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    0.969760] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    0.969762] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[    0.969763] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    0.969764] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    0.969764] [drm:intel_dump_pipe_config] requested mode:
>[    0.969767] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[    0.969768] [drm:intel_dump_pipe_config] adjusted mode:
>[    0.969769] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[    0.969771] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[    0.969772] [drm:intel_dump_pipe_config] port clock: 540000
>[    0.969773] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[    0.969774] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[    0.969775] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    0.969776] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    0.969777] [drm:intel_dump_pipe_config] ips: 0
>[    0.969777] [drm:intel_dump_pipe_config] double wide: 0
>[    0.969778] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[    0.969779] [drm:intel_dump_pipe_config] planes on this crtc
>[    0.969780] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] disabled, scaler_id = -1
>[    0.969781] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[    0.969782] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[    0.969784] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[    0.969788] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[    0.969789] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 60
>[    0.969790] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[    0.969793] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[    0.969794] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[    0.969796] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[    0.969803] [drm:drm_atomic_commit] commiting ffff978ee6ea1000
>[    0.970952] [drm:intel_edp_backlight_off.part.30] 
>[    1.069787] xhci_hcd 0000:00:14.0: xHCI Host Controller
>[    1.069793] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 1
>[    1.070947] xhci_hcd 0000:00:14.0: hcc params 0x200077c1 hci version 0x100 quirks 0x00109810
>[    1.070960] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported
>[    1.071051] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
>[    1.071052] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    1.071052] usb usb1: Product: xHCI Host Controller
>[    1.071053] usb usb1: Manufacturer: Linux 4.9.2+ xhci-hcd
>[    1.071054] usb usb1: SerialNumber: 0000:00:14.0
>[    1.071235] hub 1-0:1.0: USB hub found
>[    1.071263] hub 1-0:1.0: 12 ports detected
>[    1.077829] xhci_hcd 0000:00:14.0: xHCI Host Controller
>[    1.077831] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2
>[    1.077852] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
>[    1.077853] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    1.077853] usb usb2: Product: xHCI Host Controller
>[    1.077854] usb usb2: Manufacturer: Linux 4.9.2+ xhci-hcd
>[    1.077854] usb usb2: SerialNumber: 0000:00:14.0
>[    1.078063] hub 2-0:1.0: USB hub found
>[    1.078076] hub 2-0:1.0: 6 ports detected
>[    1.080291] usb: port power management may be unreliable
>[    1.081538] usbcore: registered new interface driver usb-storage
>[    1.081564] i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:PS2M] at 0x60,0x64 irq 1,12
>[    1.082229] i8042: Warning: Keylock active
>[    1.084444] serio: i8042 KBD port at 0x60,0x64 irq 1
>[    1.084446] serio: i8042 AUX port at 0x60,0x64 irq 12
>[    1.084535] mousedev: PS/2 mouse device common for all mice
>[    1.084897] rtc_cmos 00:01: RTC can wake from S4
>[    1.085428] rtc_cmos 00:01: rtc core: registered rtc_cmos as rtc0
>[    1.085564] rtc_cmos 00:01: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
>[    1.085711] i801_smbus 0000:00:1f.4: SPD Write Disable is set
>[    1.085743] i801_smbus 0000:00:1f.4: SMBus using PCI interrupt
>[    1.086164] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input5
>[    1.092730] device-mapper: ioctl: 4.35.0-ioctl (2016-06-23) initialised: dm-devel@redhat.com
>[    1.092735] intel_pstate: Intel P-state driver initializing
>[    1.092982] intel_pstate: HWP enabled
>[    1.093015] dcdbas dcdbas: Dell Systems Management Base Driver (version 5.6.0-3.2)
>[    1.093016] EFI Variables Facility v0.08 2004-May-17
>[    1.102103] hidraw: raw HID events driver (C) Jiri Kosina
>[    1.102252] usbcore: registered new interface driver usbhid
>[    1.102253] usbhid: USB HID core driver
>[    1.103979] dell_wmi: Detected Dell WMI interface version 1
>[    1.104010] input: Dell WMI hotkeys as /devices/virtual/input/input8
>[    1.104120] intel_pmc_core 0000:00:1f.2: enabling device (0000 -> 0002)
>[    1.104294] Netfilter messages via NETLINK v0.30.
>[    1.104374] nf_conntrack version 0.5.0 (65536 buckets, 262144 max)
>[    1.104414] ctnetlink v0.93: registering with nfnetlink.
>[    1.104548] ip_tables: (C) 2000-2006 Netfilter Core Team
>[    1.104559] Initializing XFRM netlink socket
>[    1.104639] NET: Registered protocol family 10
>[    1.104802] ip6_tables: (C) 2000-2006 Netfilter Core Team
>[    1.104904] NET: Registered protocol family 17
>[    1.104909] Key type dns_resolver registered
>[    1.105141] microcode: sig=0x806e9, pf=0x80, revision=0x42
>[    1.105176] microcode: Microcode Update Driver: v2.01 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
>[    1.105313] registered taskstats version 1
>[    1.105322] Loading compiled-in X.509 certificates
>[    1.106352] Loaded X.509 cert 'Build time autogenerated kernel key: f0011d6ae5e2a58a8bf4b0444932808bbba5dd50'
>[    1.107655]   Magic number: 1:646:990
>[    1.107657] machinecheck machinecheck3: hash matches
>[    1.177996] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[    1.178017] [drm:lpt_disable_backlight] cpu backlight was enabled, disabling
>[    1.178062] [drm:intel_disable_pipe] disabling pipe A
>[    1.180820]  nvme0n1: p1 p2
>[    1.187701] ath10k_pci 0000:3a:00.0: Direct firmware load for ath10k/pre-cal-pci-0000:3a:00.0.bin failed with error -2
>[    1.187711] ath10k_pci 0000:3a:00.0: Direct firmware load for ath10k/cal-pci-0000:3a:00.0.bin failed with error -2
>[    1.187719] ath10k_pci 0000:3a:00.0: Direct firmware load for ath10k/QCA6174/hw3.0/firmware-5.bin failed with error -2
>[    1.187721] ath10k_pci 0000:3a:00.0: could not fetch firmware file 'ath10k/QCA6174/hw3.0/firmware-5.bin': -2
>[    1.187726] ath10k_pci 0000:3a:00.0: qca6174 hw3.2 target 0x05030000 chip_id 0x00340aff sub 1a56:1535
>[    1.187728] ath10k_pci 0000:3a:00.0: kconfig debug 0 debugfs 1 tracing 0 dfs 0 testmode 0
>[    1.188562] ath10k_pci 0000:3a:00.0: firmware ver WLAN.RM.2.0-00180-QCARMSWPZ-1 api 4 features wowlan,ignore-otp,no-4addr-pad crc32 75dee6c5
>[    1.192191] [drm:edp_panel_off] Turn eDP port A panel power off
>[    1.192221] [drm:edp_panel_off] Wait for panel power off time
>[    1.192281] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[    1.192700] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[    1.192704] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[    1.192721] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[    1.243305] [drm:wait_panel_status] Wait complete
>[    1.243312] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[    1.243317] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[    1.243322] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[    1.243324] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[    1.243326] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[    1.243327] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[    1.243328] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[    1.243329] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[    1.243331] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[    1.243332] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[    1.243333] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[    1.243334] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[    1.243335] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[    1.243337] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[    1.243338] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[    1.243339] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[    1.243343] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[    1.243346] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[    1.243348] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[    1.243353] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[    1.243354] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[    1.243361] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[    1.243372] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[    1.244421] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[    1.244423] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[    1.244424] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[    1.250759] ath10k_pci 0000:3a:00.0: board_file api 2 bmi_id N/A crc32 6fc88fe7
>[    1.437987] usb 1-3: new full-speed USB device number 2 using xhci_hcd
>[    1.607249] usb 1-3: New USB device found, idVendor=0cf3, idProduct=e300
>[    1.607249] usb 1-3: New USB device strings: Mfr=0, Product=0, SerialNumber=0
>[    1.762980] usb 1-4: new full-speed USB device number 3 using xhci_hcd
>[    1.787143] random: fast init done
>[    1.842038] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[    1.842046] [drm:wait_panel_status] Wait complete
>[    1.842087] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[    1.842095] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[    1.886224] psmouse serio1: synaptics: queried max coordinates: x [..5666], y [..4734]
>[    1.891189] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[    1.891191] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[    1.891192] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[    1.905944] tsc: Refined TSC clocksource calibration: 2904.025 MHz
>[    1.905950] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x29dc1cff162, max_idle_ns: 440795231475 ns
>[    1.914451] psmouse serio1: synaptics: queried min coordinates: x [1276..], y [1118..]
>[    1.932572] usb 1-4: New USB device found, idVendor=04f3, idProduct=20d0
>[    1.932573] usb 1-4: New USB device strings: Mfr=4, Product=14, SerialNumber=0
>[    1.932573] usb 1-4: Product: Touchscreen
>[    1.932574] usb 1-4: Manufacturer: ELAN
>[    1.970334] psmouse serio1: synaptics: Touchpad model: 1, fw: 8.2, id: 0x1e2a1, caps: 0xf00323/0x840300/0x12e800/0x0, board id: 3038, fw id: 2375007
>[    2.005050] input: SynPS/2 Synaptics TouchPad as /devices/platform/i8042/serio1/input/input7
>[    2.050478] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[    2.050875] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[    2.050881] [drm:edp_panel_on] Turn eDP port A panel power on
>[    2.050895] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[    2.050981] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[    2.050990] [drm:wait_panel_status] Wait complete
>[    2.051017] [drm:edp_panel_on] Wait for panel power on
>[    2.051076] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 0000000b
>[    2.093987] usb 1-5: new high-speed USB device number 4 using xhci_hcd
>[    2.252769] [drm:wait_panel_status] Wait complete
>[    2.254005] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[    2.254006] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[    2.254006] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[    2.254011] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[    2.254753] [drm:intel_dp_start_link_train] clock recovery OK
>[    2.254754] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[    2.254755] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[    2.255810] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[    2.255811] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[    2.255811] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[    2.256833] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[    2.257035] [drm:skylake_pfit_enable] for crtc_state = ffff978ee6ea1800
>[    2.258913] [drm:intel_enable_pipe] enabling pipe A
>[    2.258956] [drm:intel_edp_backlight_on.part.29] 
>[    2.258957] [drm:intel_panel_enable_backlight] pipe A
>[    2.259013] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[    2.259054] [drm:intel_psr_enable] PSR disable by flag
>[    2.259055] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[    2.290981] usb 1-5: New USB device found, idVendor=0bda, idProduct=568b
>[    2.290982] usb 1-5: New USB device strings: Mfr=3, Product=1, SerialNumber=2
>[    2.290982] usb 1-5: Product: Integrated_Webcam_HD
>[    2.290983] usb 1-5: Manufacturer: CKFGH10M306030007890
>[    2.290983] usb 1-5: SerialNumber: 200901010001
>[    2.292358] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[    2.292367] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[    2.292416] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[    2.292423] [drm:intel_enable_sagv] Enabling the SAGV
>[    2.292429] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee6ea1000
>[    2.292433] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee6ea1000
>[    2.292490] [drm:i915_hotplug_work_func] running encoder hotplug functions
>[    2.292492] [drm:i915_hotplug_work_func] Connector eDP-1 (pin 4) received hotplug event.
>[    2.292493] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1]
>[    2.292495] [drm:intel_dp_detect] Display Port TPS3 support: source yes, sink no
>[    2.292497] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[    2.292499] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000
>[    2.292500] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000
>[    2.292932] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee6ea1000
>[    2.292935] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978eeb627000 state to ffff978ee6ea1000
>[    2.292936] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978eeb46f780 state to ffff978ee6ea1000
>[    2.292941] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978eeb627000
>[    2.292942] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eeb46f780 to [CRTC:26:pipe A]
>[    2.292943] [drm:drm_atomic_set_fb_for_plane] Set [FB:60] for plane state ffff978eeb46f780
>[    2.292944] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee6ea1000
>[    2.292946] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebbbdf00 state to ffff978ee6ea1000
>[    2.292947] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebbbdf00 to [NOCRTC]
>[    2.292948] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebbbdf00 to [CRTC:26:pipe A]
>[    2.292949] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978eeb626000 state to ffff978ee6ea1000
>[    2.292950] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 1B] ffff978eeb46fe40 state to ffff978ee6ea1000
>[    2.292951] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff978eeb626000
>[    2.292952] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eeb46fe40 to [NOCRTC]
>[    2.292952] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978eeb46fe40
>[    2.292953] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff978ee6ea1000
>[    2.292955] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978eeb625000 state to ffff978ee6ea1000
>[    2.292956] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 1C] ffff978eebbbbcc0 state to ffff978ee6ea1000
>[    2.292956] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff978eeb625000
>[    2.292957] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eebbbbcc0 to [NOCRTC]
>[    2.292958] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978eebbbbcc0
>[    2.292959] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff978ee6ea1000
>[    2.292960] [drm:drm_atomic_check_only] checking ffff978ee6ea1000
>[    2.292964] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[    2.292965] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[    2.292969] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[    2.292970] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 60
>[    2.292971] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[    2.292977] [drm:drm_atomic_commit] commiting ffff978ee6ea1000
>[    2.309027] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee6ea1000
>[    2.309029] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee6ea1000
>[    2.318008] Console: switching to colour frame buffer device 400x112
>[    2.318013] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee6ea1000
>[    2.318014] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee6ea2800 state to ffff978ee6ea1000
>[    2.318016] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978eeaca0180 state to ffff978ee6ea1000
>[    2.318017] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee6ea2800
>[    2.318018] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eeaca0180 to [CRTC:26:pipe A]
>[    2.318019] [drm:drm_atomic_set_fb_for_plane] Set [FB:60] for plane state ffff978eeaca0180
>[    2.318020] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee6ea1000
>[    2.318021] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebbbdf20 state to ffff978ee6ea1000
>[    2.318022] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebbbdf20 to [NOCRTC]
>[    2.318023] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebbbdf20 to [CRTC:26:pipe A]
>[    2.318024] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee6ea2000 state to ffff978ee6ea1000
>[    2.318025] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 1B] ffff978eeac9d540 state to ffff978ee6ea1000
>[    2.318026] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff978ee6ea2000
>[    2.318026] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eeac9d540 to [NOCRTC]
>[    2.318027] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978eeac9d540
>[    2.318028] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff978ee6ea1000
>[    2.318029] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee6ea1800 state to ffff978ee6ea1000
>[    2.318030] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 1C] ffff978eeac9d840 state to ffff978ee6ea1000
>[    2.318031] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff978ee6ea1800
>[    2.318032] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eeac9d840 to [NOCRTC]
>[    2.318032] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978eeac9d840
>[    2.318033] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff978ee6ea1000
>[    2.318034] [drm:drm_atomic_check_only] checking ffff978ee6ea1000
>[    2.318035] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[    2.318036] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[    2.318038] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[    2.318039] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 60
>[    2.318040] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[    2.318044] [drm:drm_atomic_commit] commiting ffff978ee6ea1000
>[    2.325681] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee6ea1000
>[    2.325683] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee6ea1000
>[    2.343600] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[    2.345687] console [netcon0] enabled
>[    2.347785] netconsole: network logging started
>[    2.352241] PM: Hibernation image not present or could not be loaded.
>[    2.352242] ALSA device list:
>[    2.354081]   No soundcards found.
>[    2.356537] Freeing unused kernel memory: 1432K (ffffffffb9f46000 - ffffffffba0ac000)
>[    2.358544] Write protecting the kernel read-only data: 14336k
>[    2.360521] Freeing unused kernel memory: 992K (ffff978e59508000 - ffff978e59600000)
>[    2.362585] Freeing unused kernel memory: 228K (ffff978e599c7000 - ffff978e59a00000)
>[    2.440557] udevd[1748]: starting version 3.1.5
>[    2.738514] [drm] RC6 on
>[    2.914108] clocksource: Switched to clocksource tsc
>[    3.372189] ath10k_pci 0000:3a:00.0: htt-ver 3.26 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
>[    3.439323] ath: EEPROM regdomain: 0x6c
>[    3.439325] ath: EEPROM indicates we should expect a direct regpair map
>[    3.439326] ath: Country alpha2 being used: 00
>[    3.439327] ath: Regpair used: 0x6c
>[    5.298207] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[    5.298267] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007
>[    5.298271] [drm:intel_power_well_disable] disabling DC off
>[    5.298276] [drm:skl_enable_dc6] Enabling DC6
>[    5.298279] [drm:gen9_set_dc_state] Setting DC state from 00 to 02
>[    7.566032] random: crng init done
>[   10.728499] EXT4-fs (dm-0): mounted filesystem with writeback data mode. Opts: (null)
>[   11.270279] udevd[2833]: starting version 3.1.5
>[   11.315226] input: Intel HID events as /devices/platform/INT33D5:00/input/input9
>[   11.326908] input: Intel Virtual Button driver as /devices/pci0000:00/0000:00:1f.0/PNP0C09:00/INT33D6:00/input/input10
>[   11.341541] intel-lpss 0000:00:15.0: enabling device (0000 -> 0002)
>[   11.348502] intel-lpss 0000:00:15.1: enabling device (0000 -> 0002)
>[   11.348537] ath10k_pci 0000:3a:00.0 wlp58s0: renamed from wlan0
>[   11.349882] rtsx_pci 0000:3b:00.0: rtsx_pci_acquire_irq: pcr->msi_en = 1, pci->irq = 130
>[   11.353941] mei_me 0000:00:16.0: enabling device (0000 -> 0002)
>[   11.389350] Bluetooth: Core ver 2.22
>[   11.389359] NET: Registered protocol family 31
>[   11.389359] Bluetooth: HCI device and connection manager initialized
>[   11.389362] Bluetooth: HCI socket layer initialized
>[   11.389364] Bluetooth: L2CAP socket layer initialized
>[   11.389367] Bluetooth: SCO socket layer initialized
>[   11.407982] Linux video capture interface: v2.00
>[   11.437495] snd_hda_intel 0000:00:1f.3: enabling device (0000 -> 0002)
>[   11.437606] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops 0xffffffffb9a864e0)
>[   11.438811] usbcore: registered new interface driver btusb
>[   11.439828] [drm:intel_power_well_enable] enabling DC off
>[   11.439830] [drm:gen9_set_dc_state] Setting DC state from 02 to 00
>[   11.439836] [drm:intel_power_well_enable] enabling power well 2
>[   11.439838] [drm:skl_set_power_well] Enabling power well 2
>[   11.448678] uvcvideo: Found UVC 1.00 device Integrated_Webcam_HD (0bda:568b)
>[   11.454416] input: Integrated_Webcam_HD as /devices/pci0000:00/0000:00:14.0/usb1/1-5/1-5:1.0/input/input11
>[   11.454448] usbcore: registered new interface driver uvcvideo
>[   11.454448] USB Video Class driver (1.1.1)
>[   11.495649] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC3246: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker
>[   11.495650] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[   11.495651] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[   11.495652] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[   11.495652] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[   11.495653] snd_hda_codec_realtek hdaudioC0D0:      Headset Mic=0x19
>[   11.495654] snd_hda_codec_realtek hdaudioC0D0:      Headphone Mic=0x1a
>[   11.495654] snd_hda_codec_realtek hdaudioC0D0:      Internal Mic=0x12
>[   11.503009] input: HDA Intel PCH Headphone Mic as /devices/pci0000:00/0000:00:1f.3/sound/card0/input12
>[   11.503043] [drm:intel_power_well_disable] disabling power well 2
>[   11.503049] [drm:skl_set_power_well] Disabling power well 2
>[   11.503051] [drm:intel_power_well_disable] disabling DC off
>[   11.503054] [drm:skl_enable_dc6] Enabling DC6
>[   11.503056] [drm:gen9_set_dc_state] Setting DC state from 00 to 02
>[   11.630064] EXT4-fs (dm-0): re-mounted. Opts: data=writeback,barrier=0,discard
>[   14.477720] IPv6: ADDRCONF(NETDEV_UP): wlp58s0: link is not ready
>[   14.787292] [drm:i915_gem_open] 
>[   14.787338] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5f97000
>[   14.787341] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee5d86840 state to ffff978ee5f97000
>[   14.787343] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5f97800 state to ffff978ee5f97000
>[   14.787345] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee5d86780 state to ffff978ee5f97000
>[   14.787346] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5d86780 to [NOCRTC]
>[   14.787347] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee5d86780
>[   14.787349] [drm:drm_atomic_get_plane_state] Added [PLANE:27:plane 2A] ffff978ee5d866c0 state to ffff978ee5f97000
>[   14.787350] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5d866c0 to [NOCRTC]
>[   14.787351] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee5d866c0
>[   14.787353] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 1B] ffff978ee5d86600 state to ffff978ee5f97000
>[   14.787354] [drm:drm_atomic_get_plane_state] Added [PLANE:29:cursor B] ffff978ee5d86540 state to ffff978ee5f97000
>[   14.787355] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5d86540 to [NOCRTC]
>[   14.787356] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee5d86540
>[   14.787358] [drm:drm_atomic_get_plane_state] Added [PLANE:31:plane 2B] ffff978ee5d86480 state to ffff978ee5f97000
>[   14.787359] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5d86480 to [NOCRTC]
>[   14.787360] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee5d86480
>[   14.787361] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 1C] ffff978ee5d863c0 state to ffff978ee5f97000
>[   14.787363] [drm:drm_atomic_get_plane_state] Added [PLANE:33:cursor C] ffff978ee5d86300 state to ffff978ee5f97000
>[   14.787364] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5d86300 to [NOCRTC]
>[   14.787365] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee5d86300
>[   14.787366] [drm:drm_atomic_get_plane_state] Added [PLANE:35:plane 2C] ffff978ee5d86240 state to ffff978ee5f97000
>[   14.787367] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5d86240 to [NOCRTC]
>[   14.787368] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee5d86240
>[   14.787371] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5f97800
>[   14.787372] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5d86840 to [CRTC:26:pipe A]
>[   14.787374] [drm:drm_atomic_set_fb_for_plane] Set [FB:60] for plane state ffff978ee5d86840
>[   14.787375] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5f97000
>[   14.787378] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656c7a0 state to ffff978ee5f97000
>[   14.787379] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978ee656c7a0 to [NOCRTC]
>[   14.787381] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978ee656c7a0 to [CRTC:26:pipe A]
>[   14.787383] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5f95000 state to ffff978ee5f97000
>[   14.787384] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff978ee5f95000
>[   14.787385] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5d86600 to [NOCRTC]
>[   14.787386] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee5d86600
>[   14.787388] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff978ee5f97000
>[   14.787391] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5d88000 state to ffff978ee5f97000
>[   14.787392] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff978ee5d88000
>[   14.787393] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5d863c0 to [NOCRTC]
>[   14.787394] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee5d863c0
>[   14.787395] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff978ee5f97000
>[   14.787396] [drm:drm_atomic_check_only] checking ffff978ee5f97000
>[   14.787400] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   14.787402] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   14.787407] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   14.787408] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 60
>[   14.787410] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[   14.787417] [drm:drm_atomic_commit] commiting ffff978ee5f97000
>[   14.796111] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5f97000
>[   14.796131] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5f97000
>[   14.810788] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5de5800
>[   14.810791] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de0800 state to ffff978ee5de5800
>[   14.810793] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee6641600 state to ffff978ee5de5800
>[   14.810795] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5de0800
>[   14.810796] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee6641600 to [CRTC:26:pipe A]
>[   14.810797] [drm:drm_atomic_set_fb_for_plane] Set [FB:60] for plane state ffff978ee6641600
>[   14.810798] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de5800
>[   14.810800] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eeac98f20 state to ffff978ee5de5800
>[   14.810801] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eeac98f20 to [NOCRTC]
>[   14.810802] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eeac98f20 to [CRTC:26:pipe A]
>[   14.810803] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5de6000 state to ffff978ee5de5800
>[   14.810805] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 1B] ffff978ee6641f00 state to ffff978ee5de5800
>[   14.810805] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff978ee5de6000
>[   14.810806] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee6641f00 to [NOCRTC]
>[   14.810807] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee6641f00
>[   14.810808] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:30:pipe B] to ffff978ee5de5800
>[   14.810809] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5de4800 state to ffff978ee5de5800
>[   14.810810] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 1C] ffff978ee6641a80 state to ffff978ee5de5800
>[   14.810811] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff978ee5de4800
>[   14.810811] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee6641a80 to [NOCRTC]
>[   14.810812] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee6641a80
>[   14.810813] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:34:pipe C] to ffff978ee5de5800
>[   14.810814] [drm:drm_atomic_check_only] checking ffff978ee5de5800
>[   14.810817] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   14.810818] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   14.810823] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   14.810824] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 60
>[   14.810825] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[   14.810831] [drm:drm_atomic_commit] commiting ffff978ee5de5800
>[   14.812872] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5de5800
>[   14.812875] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5de5800
>[   14.820211] [drm:i915_gem_open] 
>[   14.822766] [drm:drm_mode_addfb2] [FB:58]
>[   14.822842] [drm:i915_gem_object_create_stolen] creating stolen object: size=4000
>[   14.822844] [drm:_i915_gem_object_create_stolen] offset=0x12000, size=16384
>[   14.822942] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[   14.822946] [drm:drm_mode_addfb2] [FB:58]
>[   14.822951] [drm:drm_mode_addfb2] [FB:58]
>[   14.863722] [drm:drm_mode_addfb2] [FB:58]
>[   14.863965] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5de3000
>[   14.863969] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de2800 state to ffff978ee5de3000
>[   14.863970] [drm:drm_atomic_check_only] checking ffff978ee5de3000
>[   14.863976] [drm:drm_atomic_commit] commiting ffff978ee5de3000
>[   14.879519] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5de3000
>[   14.879521] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5de3000
>[   14.992774] [drm:drm_mode_addfb2] [FB:63]
>[   14.992939] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   14.992945] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[   14.992950] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d800
>[   14.992954] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8e000 state to ffff978ee5d8d800
>[   14.992958] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee54bdb40 state to ffff978ee5d8d800
>[   14.992961] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5d8e000
>[   14.992963] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee54bdb40 to [CRTC:26:pipe A]
>[   14.992965] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffff978ee54bdb40
>[   14.992968] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[   14.992971] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656c4a0 state to ffff978ee5d8d800
>[   14.992974] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978ee656c4a0 to [NOCRTC]
>[   14.992976] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978ee656c4a0 to [CRTC:26:pipe A]
>[   14.992978] [drm:drm_atomic_check_only] checking ffff978ee5d8d800
>[   14.992984] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   14.992986] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   14.992993] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   14.992995] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   14.992998] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[   14.993006] [drm:drm_atomic_commit] commiting ffff978ee5d8d800
>[   15.013041] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d800
>[   15.013049] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d800
>[   16.490195] [drm:drm_mode_addfb2] [FB:61]
>[   16.834933] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1]
>[   16.834938] [drm:intel_dp_detect] [CONNECTOR:37:eDP-1]
>[   16.834944] [drm:intel_power_well_enable] enabling DC off
>[   16.834948] [drm:gen9_set_dc_state] Setting DC state from 02 to 00
>[   16.834955] [drm:intel_dp_detect] Display Port TPS3 support: source yes, sink no
>[   16.834960] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[   16.834963] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000
>[   16.834966] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000
>[   16.834987] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   16.835072] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000f
>[   16.835471] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   16.835477] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:37:eDP-1] probed modes :
>[   16.835482] [drm:drm_mode_debug_printmodeline] Modeline 38:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   16.835485] [drm:drm_mode_debug_printmodeline] Modeline 39:"3200x1800" 48 298600 3200 3248 3280 3360 1800 1803 1808 1852 0x40 0xa
>[   16.835808] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:46:DP-1]
>[   16.835812] [drm:intel_dp_detect] [CONNECTOR:46:DP-1]
>[   16.835816] [drm:intel_power_well_enable] enabling power well 2
>[   16.835820] [drm:skl_set_power_well] Enabling power well 2
>[   16.835837] [drm:intel_power_well_disable] disabling power well 2
>[   16.835846] [drm:skl_set_power_well] Disabling power well 2
>[   16.835852] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:46:DP-1] disconnected
>[   16.835863] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-2]
>[   16.835866] [drm:intel_dp_detect] [CONNECTOR:53:DP-2]
>[   16.835868] [drm:intel_power_well_enable] enabling power well 2
>[   16.835871] [drm:skl_set_power_well] Enabling power well 2
>[   16.835886] [drm:intel_power_well_disable] disabling power well 2
>[   16.835897] [drm:skl_set_power_well] Disabling power well 2
>[   16.835902] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:53:DP-2] disconnected
>[   16.835907] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:HDMI-A-1]
>[   16.835909] [drm:intel_hdmi_detect] [CONNECTOR:50:HDMI-A-1]
>[   16.836315] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   16.836318] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[   16.836748] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   16.836756] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[   16.837196] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[   16.837199] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[   16.837621] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[   16.837630] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:50:HDMI-A-1] disconnected
>[   16.837652] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[   16.837655] [drm:intel_hdmi_detect] [CONNECTOR:57:HDMI-A-2]
>[   16.837990] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[   16.837992] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   16.838345] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[   16.838352] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[   16.838703] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   16.838706] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   16.839058] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   16.839065] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[   19.347137] wlp58s0: authenticate with b8:be:bf:68:94:7f
>[   19.391916] wlp58s0: send auth to b8:be:bf:68:94:7f (try 1/3)
>[   19.393788] wlp58s0: authenticated
>[   19.395133] wlp58s0: associate with b8:be:bf:68:94:7f (try 1/3)
>[   19.498313] wlp58s0: associate with b8:be:bf:68:94:7f (try 2/3)
>[   19.500844] wlp58s0: RX AssocResp from b8:be:bf:68:94:7f (capab=0x1 status=12 aid=0)
>[   19.500846] wlp58s0: b8:be:bf:68:94:7f denied association (code=12)
>[   19.890232] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[   19.890292] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007
>[   19.890296] [drm:intel_power_well_disable] disabling DC off
>[   19.890301] [drm:skl_enable_dc6] Enabling DC6
>[   19.890303] [drm:gen9_set_dc_state] Setting DC state from 00 to 02
>[   20.685386] wlp58s0: authenticate with b8:be:bf:68:94:7d
>[   20.729923] wlp58s0: send auth to b8:be:bf:68:94:7d (try 1/3)
>[   20.731587] wlp58s0: authenticated
>[   20.733154] wlp58s0: associate with b8:be:bf:68:94:7d (try 1/3)
>[   20.736326] wlp58s0: RX AssocResp from b8:be:bf:68:94:7d (capab=0x11 status=0 aid=10)
>[   20.739894] wlp58s0: associated
>[   20.739921] IPv6: ADDRCONF(NETDEV_CHANGE): wlp58s0: link becomes ready
>[   20.742689] ath: EEPROM regdomain: 0x8283
>[   20.742691] ath: EEPROM indicates we should expect a country code
>[   20.742692] ath: doing EEPROM country->regdmn map search
>[   20.742693] ath: country maps to regdmn code: 0x3
>[   20.742694] ath: Country alpha2 being used: RU
>[   20.742694] ath: Regpair used: 0x3
>[   20.742695] ath: regdomain 0x8283 dynamically updated by country IE
>[   20.778172] wlp58s0: Limiting TX power to 14 dBm as advertised by b8:be:bf:68:94:7d
>[   21.577910] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d88000
>[   21.577914] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee6551780 state to ffff978ee5d88000
>[   21.577915] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f800 state to ffff978ee5d88000
>[   21.577917] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee6551780 to [CRTC:26:pipe A]
>[   21.577918] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee6551780
>[   21.577918] [drm:drm_atomic_check_only] checking ffff978ee5d88000
>[   21.577923] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   21.577924] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[   21.577929] [drm:drm_atomic_commit] commiting ffff978ee5d88000
>[   21.577949] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d88000
>[   21.577951] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d88000
>[   60.166781] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d000
>[   60.166786] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d800 state to ffff978ee5d8d000
>[   60.166789] [drm:drm_atomic_check_only] checking ffff978ee5d8d000
>[   60.166793] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   60.166795] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[   60.166798] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d000
>[   60.166801] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656cf20 state to ffff978ee5d8d000
>[   60.166804] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee6731540 state to ffff978ee5d8d000
>[   60.166806] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee6731240 state to ffff978ee5d8d000
>[   60.166809] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d000
>[   60.166812] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   60.166813] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   60.166820] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   60.166826] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   60.166845] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   60.166848] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   60.166850] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   60.166853] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d8d800 for pipe A
>[   60.166855] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   60.166856] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   60.166858] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   60.166861] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   60.166863] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   60.166865] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   60.166866] [drm:intel_dump_pipe_config] requested mode:
>[   60.166871] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   60.166872] [drm:intel_dump_pipe_config] adjusted mode:
>[   60.166875] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   60.166878] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   60.166879] [drm:intel_dump_pipe_config] port clock: 540000
>[   60.166881] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   60.166883] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   60.166885] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   60.166887] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   60.166888] [drm:intel_dump_pipe_config] ips: 0
>[   60.166890] [drm:intel_dump_pipe_config] double wide: 0
>[   60.166891] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   60.166893] [drm:intel_dump_pipe_config] planes on this crtc
>[   60.166895] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   60.166898] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   60.166901] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   60.166903] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[   60.166905] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[   60.166907] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[   60.166909] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   60.166914] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d88000 state to ffff978ee5d8d000
>[   60.166916] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5d8e000 state to ffff978ee5d8d000
>[   60.166918] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[   60.166924] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   60.166926] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   60.166928] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[   60.166930] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   60.166932] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[   60.166936] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   60.166938] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   60.166941] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   60.166949] [drm:drm_atomic_commit] commiting ffff978ee5d8d000
>[   60.166957] [drm:intel_power_well_enable] enabling DC off
>[   60.166960] [drm:gen9_set_dc_state] Setting DC state from 02 to 00
>[   60.168488] [drm:intel_edp_backlight_off.part.30] 
>[   60.370559] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   60.370631] [drm:intel_disable_pipe] disabling pipe A
>[   60.377089] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   60.377198] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b
>[   60.377399] [drm:edp_panel_off] Turn eDP port A panel power off
>[   60.377455] [drm:edp_panel_off] Wait for panel power off time
>[   60.377532] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[   60.378012] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[   60.378018] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[   60.378042] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[   60.428291] [drm:wait_panel_status] Wait complete
>[   60.428308] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[   60.428328] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   60.428330] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[   60.428348] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   60.428365] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[   60.429912] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   60.429918] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   60.429922] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[   60.430629] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   60.430636] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   60.430641] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   60.430647] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   60.430650] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   60.430653] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   60.430656] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   60.430660] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   60.430663] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   60.430666] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   60.430669] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   60.430672] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   60.430675] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   60.430678] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   60.430681] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   60.430686] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   60.430689] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   60.430692] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   60.430702] [drm:intel_power_well_disable] disabling DDI A/E power well
>[   60.430706] [drm:skl_set_power_well] Disabling DDI A/E power well
>[   60.430711] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   60.430716] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   60.430720] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   60.430730] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d000
>[   60.430736] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d000
>[   61.042716] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[   61.042737] [drm:wait_panel_status] Wait complete
>[   61.042793] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[   61.042809] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[   61.092114] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   61.092120] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   61.092123] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[   61.251114] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[   61.252214] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   62.436633] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee67e5000
>[   62.436639] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee8801600 state to ffff978ee67e5000
>[   62.436644] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee67e7800 state to ffff978ee67e5000
>[   62.436646] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee8801600 to [NOCRTC]
>[   62.436649] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee8801600
>[   62.436651] [drm:drm_atomic_check_only] checking ffff978ee67e5000
>[   62.436662] [drm:drm_atomic_commit] commiting ffff978ee67e5000
>[   62.436672] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee67e5000
>[   62.436677] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee67e5000
>[   62.436687] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   62.436693] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[   62.436696] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee67e5000
>[   62.436699] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee67e3800 state to ffff978ee67e5000
>[   62.436701] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee88016c0 state to ffff978ee67e5000
>[   62.436705] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee67e3800
>[   62.436707] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee88016c0 to [CRTC:26:pipe A]
>[   62.436710] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffff978ee88016c0
>[   62.436713] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee67e5000
>[   62.436716] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eeb5675e0 state to ffff978ee67e5000
>[   62.436719] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eeb5675e0 to [NOCRTC]
>[   62.436722] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eeb5675e0 to [CRTC:26:pipe A]
>[   62.436724] [drm:drm_atomic_check_only] checking ffff978ee67e5000
>[   62.436729] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   62.436732] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   62.436734] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   62.436736] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[   62.436738] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee67e5000
>[   62.436742] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee67e5000
>[   62.436746] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   62.436747] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   62.436755] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   62.436760] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   62.436768] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   62.436772] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   62.436774] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   62.436778] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee67e3800 for pipe A
>[   62.436780] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   62.436782] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   62.436785] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   62.436788] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   62.436791] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   62.436793] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   62.436794] [drm:intel_dump_pipe_config] requested mode:
>[   62.436799] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   62.436801] [drm:intel_dump_pipe_config] adjusted mode:
>[   62.436804] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   62.436808] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   62.436810] [drm:intel_dump_pipe_config] port clock: 540000
>[   62.436812] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   62.436814] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   62.436816] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   62.436819] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   62.436820] [drm:intel_dump_pipe_config] ips: 0
>[   62.436822] [drm:intel_dump_pipe_config] double wide: 0
>[   62.436824] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   62.436826] [drm:intel_dump_pipe_config] planes on this crtc
>[   62.436829] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   62.436833] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   62.436836] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   62.436838] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   62.436840] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   62.436845] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee67e5800 state to ffff978ee67e5000
>[   62.436848] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee67e3000 state to ffff978ee67e5000
>[   62.436851] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[   62.436857] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   62.436859] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   62.436861] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[   62.436866] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   62.436869] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   62.436873] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   62.436883] [drm:drm_atomic_commit] commiting ffff978ee67e5000
>[   62.436894] [drm:intel_power_well_enable] enabling DDI A/E power well
>[   62.436898] [drm:skl_set_power_well] Enabling DDI A/E power well
>[   62.436904] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[   62.438463] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   62.438466] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   62.438470] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   62.438474] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   62.438477] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   62.438480] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   62.438482] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   62.438485] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   62.438488] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   62.438491] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   62.438494] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   62.438497] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   62.438499] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   62.438502] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   62.438505] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   62.438509] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   62.438512] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   62.438515] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   62.438520] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[   62.438522] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[   62.438535] [drm:edp_panel_on] Turn eDP port A panel power on
>[   62.438554] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   62.438630] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[   62.438648] [drm:wait_panel_status] Wait complete
>[   62.438682] [drm:edp_panel_on] Wait for panel power on
>[   62.438757] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[   62.640139] [drm:wait_panel_status] Wait complete
>[   62.641293] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   62.641296] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   62.641297] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   62.641300] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[   62.641971] [drm:intel_dp_start_link_train] clock recovery OK
>[   62.641973] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[   62.641975] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[   62.642939] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[   62.642939] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   62.642940] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   62.643884] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[   62.644048] [drm:skylake_pfit_enable] for crtc_state = ffff978ee67e3800
>[   62.644121] [drm:intel_enable_pipe] enabling pipe A
>[   62.644127] [drm:intel_edp_backlight_on.part.29] 
>[   62.644129] [drm:intel_panel_enable_backlight] pipe A
>[   62.644208] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   62.644262] [drm:intel_psr_enable] PSR disable by flag
>[   62.644262] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   62.661079] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   62.661086] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   62.661100] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   62.661106] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee67e5000
>[   62.661110] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee67e5000
>[   62.661135] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[   62.661137] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d88000 state to ffff978ee5d8e000
>[   62.661138] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[   62.661144] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[   62.677653] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[   62.677657] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[   62.677692] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[   62.677694] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   62.677817] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[   62.677820] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee65afe40 state to ffff978ee5d8e000
>[   62.677823] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d000 state to ffff978ee5d8e000
>[   62.677824] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee65afe40 to [CRTC:26:pipe A]
>[   62.677826] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee65afe40
>[   62.677827] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[   62.677834] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   62.677835] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[   62.677843] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[   62.677867] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[   62.677870] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[   62.788061] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88b8800
>[   62.788067] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5279800 state to ffff978ee88b8800
>[   62.788070] [drm:drm_atomic_check_only] checking ffff978ee88b8800
>[   62.788074] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   62.788076] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[   62.788078] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88b8800
>[   62.788081] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebbb2340 state to ffff978ee88b8800
>[   62.788084] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee97c20c0 state to ffff978ee88b8800
>[   62.788087] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee97c2900 state to ffff978ee88b8800
>[   62.788090] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88b8800
>[   62.788092] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   62.788094] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   62.788101] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   62.788105] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   62.788113] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   62.788115] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   62.788117] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   62.788120] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5279800 for pipe A
>[   62.788123] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   62.788124] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   62.788126] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   62.788129] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   62.788131] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   62.788132] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   62.788134] [drm:intel_dump_pipe_config] requested mode:
>[   62.788138] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   62.788140] [drm:intel_dump_pipe_config] adjusted mode:
>[   62.788143] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   62.788146] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   62.788147] [drm:intel_dump_pipe_config] port clock: 540000
>[   62.788149] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   62.788151] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   62.788153] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   62.788154] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   62.788156] [drm:intel_dump_pipe_config] ips: 0
>[   62.788157] [drm:intel_dump_pipe_config] double wide: 0
>[   62.788159] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   62.788161] [drm:intel_dump_pipe_config] planes on this crtc
>[   62.788163] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   62.788166] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   62.788168] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   62.788171] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[   62.788173] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[   62.788175] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[   62.788177] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   62.788181] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee527b800 state to ffff978ee88b8800
>[   62.788184] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee88de800 state to ffff978ee88b8800
>[   62.788185] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[   62.788191] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   62.788193] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   62.788195] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[   62.788198] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   62.788200] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[   62.788204] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   62.788206] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   62.788209] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   62.788217] [drm:drm_atomic_commit] commiting ffff978ee88b8800
>[   62.789500] [drm:intel_edp_backlight_off.part.30] 
>[   62.994642] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   62.994699] [drm:intel_disable_pipe] disabling pipe A
>[   63.012459] [drm:edp_panel_off] Turn eDP port A panel power off
>[   63.012499] [drm:edp_panel_off] Wait for panel power off time
>[   63.012576] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[   63.013156] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[   63.013161] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[   63.013184] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[   63.063189] [drm:wait_panel_status] Wait complete
>[   63.063206] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[   63.063226] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   63.063228] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[   63.063246] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   63.063261] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[   63.064961] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   63.064966] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   63.064969] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[   63.067730] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   63.067736] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   63.067741] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   63.067746] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   63.067749] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   63.067752] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   63.067755] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   63.067758] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   63.067761] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   63.067764] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   63.067767] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   63.067770] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   63.067773] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   63.067776] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   63.067779] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   63.067783] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   63.067786] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   63.067789] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   63.067799] [drm:intel_power_well_disable] disabling DDI A/E power well
>[   63.067803] [drm:skl_set_power_well] Disabling DDI A/E power well
>[   63.067807] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   63.067812] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   63.067816] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   63.067825] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee88b8800
>[   63.067831] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee88b8800
>[   63.666718] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[   63.666754] [drm:wait_panel_status] Wait complete
>[   63.666815] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[   63.666828] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[   63.717749] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   63.717755] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   63.717759] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[   63.875103] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[   63.876201] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   65.072483] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5de6000
>[   65.072489] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee6374000 state to ffff978ee5de6000
>[   65.072493] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de4800 state to ffff978ee5de6000
>[   65.072496] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee6374000 to [NOCRTC]
>[   65.072498] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee6374000
>[   65.072501] [drm:drm_atomic_check_only] checking ffff978ee5de6000
>[   65.072512] [drm:drm_atomic_commit] commiting ffff978ee5de6000
>[   65.072523] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5de6000
>[   65.072527] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5de6000
>[   65.072537] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   65.072543] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[   65.072546] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5de6000
>[   65.072549] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de3800 state to ffff978ee5de6000
>[   65.072551] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee6374540 state to ffff978ee5de6000
>[   65.072555] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5de3800
>[   65.072557] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee6374540 to [CRTC:26:pipe A]
>[   65.072560] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffff978ee6374540
>[   65.072562] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de6000
>[   65.072566] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2c560 state to ffff978ee5de6000
>[   65.072569] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c560 to [NOCRTC]
>[   65.072572] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c560 to [CRTC:26:pipe A]
>[   65.072574] [drm:drm_atomic_check_only] checking ffff978ee5de6000
>[   65.072579] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   65.072582] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   65.072584] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   65.072586] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[   65.072588] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de6000
>[   65.072592] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de6000
>[   65.072595] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   65.072597] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   65.072605] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   65.072610] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   65.072619] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   65.072622] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   65.072625] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   65.072628] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5de3800 for pipe A
>[   65.072630] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   65.072632] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   65.072635] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   65.072638] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   65.072640] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   65.072642] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   65.072644] [drm:intel_dump_pipe_config] requested mode:
>[   65.072649] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   65.072651] [drm:intel_dump_pipe_config] adjusted mode:
>[   65.072654] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   65.072658] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   65.072659] [drm:intel_dump_pipe_config] port clock: 540000
>[   65.072661] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   65.072664] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   65.072666] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   65.072669] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   65.072670] [drm:intel_dump_pipe_config] ips: 0
>[   65.072672] [drm:intel_dump_pipe_config] double wide: 0
>[   65.072674] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   65.072676] [drm:intel_dump_pipe_config] planes on this crtc
>[   65.072679] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   65.072682] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   65.072685] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   65.072688] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   65.072690] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   65.072695] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5de2800 state to ffff978ee5de6000
>[   65.072698] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5de7800 state to ffff978ee5de6000
>[   65.072700] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[   65.072706] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   65.072708] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   65.072711] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[   65.072715] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   65.072718] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   65.072722] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   65.072733] [drm:drm_atomic_commit] commiting ffff978ee5de6000
>[   65.072744] [drm:intel_power_well_enable] enabling DDI A/E power well
>[   65.072749] [drm:skl_set_power_well] Enabling DDI A/E power well
>[   65.072755] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[   65.074484] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   65.074487] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   65.074491] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   65.074495] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   65.074498] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   65.074500] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   65.074503] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   65.074506] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   65.074509] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   65.074512] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   65.074514] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   65.074518] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   65.074520] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   65.074523] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   65.074526] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   65.074530] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   65.074533] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   65.074536] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   65.074541] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[   65.074543] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[   65.074556] [drm:edp_panel_on] Turn eDP port A panel power on
>[   65.074576] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   65.074652] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[   65.074670] [drm:wait_panel_status] Wait complete
>[   65.074703] [drm:edp_panel_on] Wait for panel power on
>[   65.074798] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[   65.275935] [drm:wait_panel_status] Wait complete
>[   65.277083] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   65.277085] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   65.277087] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   65.277090] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[   65.277759] [drm:intel_dp_start_link_train] clock recovery OK
>[   65.277761] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[   65.277763] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[   65.278734] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[   65.278735] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   65.278737] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   65.279697] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[   65.279869] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5de3800
>[   65.279967] [drm:intel_enable_pipe] enabling pipe A
>[   65.279977] [drm:intel_edp_backlight_on.part.29] 
>[   65.279980] [drm:intel_panel_enable_backlight] pipe A
>[   65.280061] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   65.280134] [drm:intel_psr_enable] PSR disable by flag
>[   65.280135] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   65.297038] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   65.297046] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   65.297060] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   65.297067] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5de6000
>[   65.297071] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5de6000
>[   65.297095] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[   65.297098] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f800 state to ffff978ee5d8e000
>[   65.297099] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[   65.297105] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[   65.313604] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[   65.313608] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[   65.313637] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[   65.313638] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   65.313775] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[   65.313779] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee635d180 state to ffff978ee5d8e000
>[   65.313782] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d000 state to ffff978ee5d8e000
>[   65.313783] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee635d180 to [CRTC:26:pipe A]
>[   65.313785] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee635d180
>[   65.313786] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[   65.313792] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   65.313793] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[   65.313800] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[   65.313824] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[   65.313828] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[   65.424866] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f800
>[   65.424872] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d88000 state to ffff978ee5d8f800
>[   65.424874] [drm:drm_atomic_check_only] checking ffff978ee5d8f800
>[   65.424878] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   65.424880] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[   65.424883] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8f800
>[   65.424886] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656c3c0 state to ffff978ee5d8f800
>[   65.424889] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee631c6c0 state to ffff978ee5d8f800
>[   65.424891] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee631c780 state to ffff978ee5d8f800
>[   65.424894] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8f800
>[   65.424897] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   65.424898] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   65.424905] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   65.424909] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   65.424917] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   65.424920] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   65.424922] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   65.424925] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d88000 for pipe A
>[   65.424927] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   65.424928] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   65.424931] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   65.424933] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   65.424935] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   65.424937] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   65.424938] [drm:intel_dump_pipe_config] requested mode:
>[   65.424943] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   65.424944] [drm:intel_dump_pipe_config] adjusted mode:
>[   65.424947] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   65.424950] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   65.424951] [drm:intel_dump_pipe_config] port clock: 540000
>[   65.424953] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   65.424955] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   65.424957] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   65.424959] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   65.424960] [drm:intel_dump_pipe_config] ips: 0
>[   65.424962] [drm:intel_dump_pipe_config] double wide: 0
>[   65.424963] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   65.424965] [drm:intel_dump_pipe_config] planes on this crtc
>[   65.424967] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   65.424970] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   65.424972] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   65.424975] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[   65.424977] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[   65.424979] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[   65.424981] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   65.424985] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d8f000 state to ffff978ee5d8f800
>[   65.424987] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5d8d800 state to ffff978ee5d8f800
>[   65.424989] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[   65.424995] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   65.424997] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   65.424999] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[   65.425001] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   65.425003] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[   65.425007] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   65.425009] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   65.425013] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   65.425020] [drm:drm_atomic_commit] commiting ffff978ee5d8f800
>[   65.426523] [drm:intel_edp_backlight_off.part.30] 
>[   65.634675] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   65.634734] [drm:intel_disable_pipe] disabling pipe A
>[   65.647791] [drm:edp_panel_off] Turn eDP port A panel power off
>[   65.647832] [drm:edp_panel_off] Wait for panel power off time
>[   65.647909] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[   65.648408] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[   65.648413] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[   65.648429] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[   65.698258] [drm:wait_panel_status] Wait complete
>[   65.698275] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[   65.698295] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   65.698298] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[   65.698316] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   65.698332] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[   65.700280] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   65.700286] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   65.700290] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[   65.704858] [drm:skl_pcode_request] PCODE timeout, retrying with preemption disabled
>[   65.707102] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   65.707109] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   65.707113] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   65.707119] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   65.707122] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   65.707125] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   65.707129] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   65.707132] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   65.707135] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   65.707138] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   65.707141] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   65.707145] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   65.707147] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   65.707150] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   65.707153] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   65.707158] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   65.707162] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   65.707165] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   65.707174] [drm:intel_power_well_disable] disabling DDI A/E power well
>[   65.707179] [drm:skl_set_power_well] Disabling DDI A/E power well
>[   65.707183] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   65.707188] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   65.707192] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   65.707202] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f800
>[   65.707209] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f800
>[   66.290622] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[   66.290643] [drm:wait_panel_status] Wait complete
>[   66.290699] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[   66.290715] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[   66.340099] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   66.340105] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   66.340108] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[   66.499252] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[   66.500357] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   69.554823] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[   69.554887] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000000
>[   69.554893] [drm:intel_power_well_disable] disabling DC off
>[   69.554899] [drm:skl_enable_dc6] Enabling DC6
>[   69.554903] [drm:gen9_set_dc_state] Setting DC state from 00 to 02
>[   69.555288] [drm:intel_power_well_disable] disabling always-on
>[   69.567031] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   69.567038] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   69.567042] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[   69.567081] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   74.946064] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5de7800
>[   74.946070] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee979d6c0 state to ffff978ee5de7800
>[   74.946075] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de2800 state to ffff978ee5de7800
>[   74.946077] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee979d6c0 to [NOCRTC]
>[   74.946080] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee979d6c0
>[   74.946082] [drm:drm_atomic_check_only] checking ffff978ee5de7800
>[   74.946093] [drm:drm_atomic_commit] commiting ffff978ee5de7800
>[   74.946103] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5de7800
>[   74.946107] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5de7800
>[   74.946353] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   74.946358] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[   74.946361] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5de7800
>[   74.946364] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de3800 state to ffff978ee5de7800
>[   74.946367] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee979d780 state to ffff978ee5de7800
>[   74.946370] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5de3800
>[   74.946373] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee979d780 to [CRTC:26:pipe A]
>[   74.946375] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffff978ee979d780
>[   74.946378] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de7800
>[   74.946381] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2cc80 state to ffff978ee5de7800
>[   74.946385] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2cc80 to [NOCRTC]
>[   74.946388] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2cc80 to [CRTC:26:pipe A]
>[   74.946390] [drm:drm_atomic_check_only] checking ffff978ee5de7800
>[   74.946395] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   74.946398] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   74.946400] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   74.946402] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[   74.946405] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de7800
>[   74.946408] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de7800
>[   74.946411] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   74.946413] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   74.946421] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   74.946426] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   74.946434] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   74.946438] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   74.946441] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   74.946444] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5de3800 for pipe A
>[   74.946447] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   74.946449] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   74.946451] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   74.946454] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   74.946457] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   74.946459] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   74.946460] [drm:intel_dump_pipe_config] requested mode:
>[   74.946465] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   74.946467] [drm:intel_dump_pipe_config] adjusted mode:
>[   74.946471] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   74.946474] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   74.946476] [drm:intel_dump_pipe_config] port clock: 540000
>[   74.946478] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   74.946480] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   74.946482] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   74.946485] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   74.946486] [drm:intel_dump_pipe_config] ips: 0
>[   74.946488] [drm:intel_dump_pipe_config] double wide: 0
>[   74.946490] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   74.946492] [drm:intel_dump_pipe_config] planes on this crtc
>[   74.946495] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   74.946498] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   74.946501] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   74.946504] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   74.946506] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   74.946511] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5de6000 state to ffff978ee5de7800
>[   74.946514] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5de4800 state to ffff978ee5de7800
>[   74.946516] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[   74.946522] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   74.946524] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   74.946527] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[   74.946532] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   74.946543] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   74.946548] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   74.946559] [drm:drm_atomic_commit] commiting ffff978ee5de7800
>[   74.946568] [drm:intel_power_well_enable] enabling always-on
>[   74.946570] [drm:intel_power_well_enable] enabling DC off
>[   74.946824] [drm:gen9_set_dc_state] Setting DC state from 02 to 00
>[   74.946834] [drm:intel_power_well_enable] enabling DDI A/E power well
>[   74.946838] [drm:skl_set_power_well] Enabling DDI A/E power well
>[   74.946845] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[   74.948570] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   74.948574] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   74.948577] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   74.948581] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   74.948584] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   74.948587] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   74.948590] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   74.948593] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   74.948596] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   74.948598] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   74.948601] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   74.948604] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   74.948607] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   74.948609] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   74.948612] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   74.948616] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   74.948619] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   74.948622] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   74.948627] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[   74.948629] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[   74.948643] [drm:edp_panel_on] Turn eDP port A panel power on
>[   74.948662] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   74.948738] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[   74.948756] [drm:wait_panel_status] Wait complete
>[   74.948809] [drm:edp_panel_on] Wait for panel power on
>[   74.948884] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 00000003
>[   74.998189] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   74.998195] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   74.998198] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[   74.998220] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   75.149784] [drm:wait_panel_status] Wait complete
>[   75.149819] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   75.149885] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b
>[   75.151023] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   75.151026] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   75.151027] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   75.151030] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[   75.151699] [drm:intel_dp_start_link_train] clock recovery OK
>[   75.151702] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[   75.151703] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[   75.152668] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[   75.152669] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   75.152669] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   75.153614] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[   75.153779] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5de3800
>[   75.153851] [drm:intel_enable_pipe] enabling pipe A
>[   75.153861] [drm:intel_edp_backlight_on.part.29] 
>[   75.153863] [drm:intel_panel_enable_backlight] pipe A
>[   75.153942] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   75.153996] [drm:intel_psr_enable] PSR disable by flag
>[   75.153996] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   75.170643] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   75.170650] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   75.170664] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   75.170671] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5de7800
>[   75.170675] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5de7800
>[   75.170700] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d800
>[   75.170703] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f000 state to ffff978ee5d8d800
>[   75.170704] [drm:drm_atomic_check_only] checking ffff978ee5d8d800
>[   75.170710] [drm:drm_atomic_commit] commiting ffff978ee5d8d800
>[   75.187495] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d800
>[   75.187499] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d800
>[   75.187526] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[   75.187527] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   75.187670] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d800
>[   75.187675] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee6374e40 state to ffff978ee5d8d800
>[   75.187678] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f800 state to ffff978ee5d8d800
>[   75.187680] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee6374e40 to [CRTC:26:pipe A]
>[   75.187682] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee6374e40
>[   75.187683] [drm:drm_atomic_check_only] checking ffff978ee5d8d800
>[   75.187690] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   75.187692] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[   75.187700] [drm:drm_atomic_commit] commiting ffff978ee5d8d800
>[   75.187727] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d800
>[   75.187729] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d800
>[   75.297577] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee67e3000
>[   75.297582] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee67e5800 state to ffff978ee67e3000
>[   75.297585] [drm:drm_atomic_check_only] checking ffff978ee67e3000
>[   75.297589] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   75.297591] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[   75.297593] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee67e3000
>[   75.297596] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eeb567960 state to ffff978ee67e3000
>[   75.297599] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee6671b40 state to ffff978ee67e3000
>[   75.297601] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee6671d80 state to ffff978ee67e3000
>[   75.297604] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee67e3000
>[   75.297607] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   75.297608] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   75.297615] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   75.297619] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   75.297626] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   75.297629] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   75.297631] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   75.297634] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee67e5800 for pipe A
>[   75.297636] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   75.297638] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   75.297640] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   75.297642] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   75.297644] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   75.297646] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   75.297647] [drm:intel_dump_pipe_config] requested mode:
>[   75.297651] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   75.297652] [drm:intel_dump_pipe_config] adjusted mode:
>[   75.297655] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   75.297658] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   75.297659] [drm:intel_dump_pipe_config] port clock: 540000
>[   75.297661] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   75.297663] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   75.297664] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   75.297666] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   75.297667] [drm:intel_dump_pipe_config] ips: 0
>[   75.297669] [drm:intel_dump_pipe_config] double wide: 0
>[   75.297670] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   75.297672] [drm:intel_dump_pipe_config] planes on this crtc
>[   75.297674] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   75.297677] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   75.297679] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   75.297681] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[   75.297683] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[   75.297685] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[   75.297687] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   75.297691] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee67e3800 state to ffff978ee67e3000
>[   75.297693] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee67e5000 state to ffff978ee67e3000
>[   75.297695] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[   75.297701] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   75.297703] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   75.297704] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[   75.297707] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   75.297708] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[   75.297712] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   75.297714] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   75.297717] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   75.297725] [drm:drm_atomic_commit] commiting ffff978ee67e3000
>[   75.299609] [drm:intel_edp_backlight_off.part.30] 
>[   75.506693] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   75.506749] [drm:intel_disable_pipe] disabling pipe A
>[   75.522264] [drm:edp_panel_off] Turn eDP port A panel power off
>[   75.522304] [drm:edp_panel_off] Wait for panel power off time
>[   75.522381] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[   75.522884] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[   75.522888] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[   75.522903] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[   75.572955] [drm:wait_panel_status] Wait complete
>[   75.572970] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[   75.572989] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   75.572991] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[   75.573009] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   75.573023] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[   75.574765] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   75.574770] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   75.574773] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[   75.577467] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   75.577472] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   75.577476] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   75.577481] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   75.577484] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   75.577486] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   75.577489] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   75.577492] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   75.577494] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   75.577497] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   75.577499] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   75.577502] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   75.577504] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   75.577506] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   75.577509] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   75.577513] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   75.577516] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   75.577518] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   75.577527] [drm:intel_power_well_disable] disabling DDI A/E power well
>[   75.577530] [drm:skl_set_power_well] Disabling DDI A/E power well
>[   75.577534] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   75.577546] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   75.577550] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   75.577558] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee67e3000
>[   75.577564] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee67e3000
>[   76.146806] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[   76.146826] [drm:wait_panel_status] Wait complete
>[   76.146881] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[   76.146895] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[   76.196229] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   76.196235] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   76.196238] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[   76.216708] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5de4800
>[   76.216714] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee5a00a80 state to ffff978ee5de4800
>[   76.216718] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de6000 state to ffff978ee5de4800
>[   76.216720] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5a00a80 to [NOCRTC]
>[   76.216723] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee5a00a80
>[   76.216725] [drm:drm_atomic_check_only] checking ffff978ee5de4800
>[   76.216735] [drm:drm_atomic_commit] commiting ffff978ee5de4800
>[   76.216746] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5de4800
>[   76.216750] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5de4800
>[   76.216761] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   76.216767] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[   76.216770] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5de4800
>[   76.216773] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de2800 state to ffff978ee5de4800
>[   76.216776] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee5a00f00 state to ffff978ee5de4800
>[   76.216779] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5de2800
>[   76.216781] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5a00f00 to [CRTC:26:pipe A]
>[   76.216783] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffff978ee5a00f00
>[   76.216786] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de4800
>[   76.216789] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2c840 state to ffff978ee5de4800
>[   76.216792] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c840 to [NOCRTC]
>[   76.216795] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c840 to [CRTC:26:pipe A]
>[   76.216797] [drm:drm_atomic_check_only] checking ffff978ee5de4800
>[   76.216801] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   76.216804] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   76.216806] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   76.216808] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[   76.216810] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de4800
>[   76.216813] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de4800
>[   76.216817] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   76.216819] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   76.216826] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   76.216831] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   76.216839] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   76.216842] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   76.216844] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   76.216848] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5de2800 for pipe A
>[   76.216850] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   76.216852] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   76.216854] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   76.216857] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   76.216859] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   76.216861] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   76.216863] [drm:intel_dump_pipe_config] requested mode:
>[   76.216867] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   76.216869] [drm:intel_dump_pipe_config] adjusted mode:
>[   76.216872] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   76.216875] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   76.216877] [drm:intel_dump_pipe_config] port clock: 540000
>[   76.216879] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   76.216881] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   76.216883] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   76.216886] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   76.216887] [drm:intel_dump_pipe_config] ips: 0
>[   76.216889] [drm:intel_dump_pipe_config] double wide: 0
>[   76.216891] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   76.216892] [drm:intel_dump_pipe_config] planes on this crtc
>[   76.216895] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   76.216898] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   76.216901] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   76.216903] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   76.216905] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   76.216911] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5de3000 state to ffff978ee5de4800
>[   76.216914] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5de7800 state to ffff978ee5de4800
>[   76.216916] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[   76.216922] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   76.216924] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   76.216926] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[   76.216930] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   76.216933] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   76.216936] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   76.216947] [drm:drm_atomic_commit] commiting ffff978ee5de4800
>[   76.216957] [drm:intel_power_well_enable] enabling DDI A/E power well
>[   76.216962] [drm:skl_set_power_well] Enabling DDI A/E power well
>[   76.216968] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[   76.219269] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   76.219276] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   76.219280] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   76.219286] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   76.219289] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   76.219292] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   76.219295] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   76.219298] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   76.219300] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   76.219303] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   76.219306] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   76.219309] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   76.219312] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   76.219315] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   76.219318] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   76.219323] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   76.219326] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   76.219329] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   76.219336] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[   76.219338] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[   76.355195] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[   76.355201] [drm:edp_panel_on] Turn eDP port A panel power on
>[   76.355221] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   76.355303] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[   76.355321] [drm:wait_panel_status] Wait complete
>[   76.355355] [drm:edp_panel_on] Wait for panel power on
>[   76.355430] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[   76.555852] [drm:wait_panel_status] Wait complete
>[   76.557736] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   76.557739] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   76.557740] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   76.557744] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[   76.558417] [drm:intel_dp_start_link_train] clock recovery OK
>[   76.558421] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[   76.558422] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[   76.559398] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[   76.559400] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   76.559402] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   76.560365] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[   76.560539] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5de2800
>[   76.560666] [drm:intel_enable_pipe] enabling pipe A
>[   76.560672] [drm:intel_edp_backlight_on.part.29] 
>[   76.560674] [drm:intel_panel_enable_backlight] pipe A
>[   76.560753] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   76.560807] [drm:intel_psr_enable] PSR disable by flag
>[   76.560808] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   76.577621] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   76.577628] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   76.577642] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   76.577648] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5de4800
>[   76.577653] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5de4800
>[   76.578059] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   76.578060] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[   76.578065] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d800 state to ffff978ee5d8e000
>[   76.578066] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[   76.578073] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[   76.594168] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[   76.594173] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[   76.594193] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[   76.594195] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   76.594378] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[   76.594383] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee8801780 state to ffff978ee5d8e000
>[   76.594387] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f000 state to ffff978ee5d8e000
>[   76.594389] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee8801780 to [CRTC:26:pipe A]
>[   76.594392] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee8801780
>[   76.594394] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[   76.594401] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   76.594404] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[   76.594415] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[   76.594440] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[   76.594443] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[   76.707358] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88d8000
>[   76.707363] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee88dc000 state to ffff978ee88d8000
>[   76.707366] [drm:drm_atomic_check_only] checking ffff978ee88d8000
>[   76.707370] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   76.707372] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[   76.707374] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88d8000
>[   76.707377] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebbb2280 state to ffff978ee88d8000
>[   76.707380] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee97c2480 state to ffff978ee88d8000
>[   76.707382] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee97c2300 state to ffff978ee88d8000
>[   76.707384] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88d8000
>[   76.707387] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   76.707389] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   76.707395] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   76.707400] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   76.707407] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   76.707409] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   76.707412] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   76.707415] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee88dc000 for pipe A
>[   76.707417] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   76.707418] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   76.707420] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   76.707422] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   76.707424] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   76.707426] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   76.707427] [drm:intel_dump_pipe_config] requested mode:
>[   76.707431] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   76.707433] [drm:intel_dump_pipe_config] adjusted mode:
>[   76.707436] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   76.707438] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   76.707440] [drm:intel_dump_pipe_config] port clock: 540000
>[   76.707441] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   76.707443] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   76.707445] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   76.707447] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   76.707448] [drm:intel_dump_pipe_config] ips: 0
>[   76.707449] [drm:intel_dump_pipe_config] double wide: 0
>[   76.707451] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   76.707452] [drm:intel_dump_pipe_config] planes on this crtc
>[   76.707455] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   76.707457] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   76.707460] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   76.707462] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[   76.707464] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[   76.707530] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[   76.707532] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   76.707536] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee88db000 state to ffff978ee88d8000
>[   76.707538] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee88d9000 state to ffff978ee88d8000
>[   76.707539] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[   76.707545] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   76.707564] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   76.707566] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[   76.707570] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   76.707572] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[   76.707576] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   76.707578] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   76.707581] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   76.707589] [drm:drm_atomic_commit] commiting ffff978ee88d8000
>[   76.709680] [drm:intel_edp_backlight_off.part.30] 
>[   76.914777] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   76.914835] [drm:intel_disable_pipe] disabling pipe A
>[   76.928204] [drm:edp_panel_off] Turn eDP port A panel power off
>[   76.928244] [drm:edp_panel_off] Wait for panel power off time
>[   76.928321] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000000
>[   76.928746] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[   76.928750] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[   76.928765] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[   76.978878] [drm:wait_panel_status] Wait complete
>[   76.978894] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[   76.978914] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   76.978916] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[   76.978934] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   76.978949] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[   76.980742] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   76.980747] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   76.980750] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[   76.985506] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   76.985512] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   76.985516] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   76.985522] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   76.985525] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   76.985528] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   76.985531] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   76.985534] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   76.985537] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   76.985539] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   76.985542] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   76.985545] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   76.985548] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   76.985560] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   76.985563] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   76.985568] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   76.985571] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   76.985573] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   76.985583] [drm:intel_power_well_disable] disabling DDI A/E power well
>[   76.985587] [drm:skl_set_power_well] Disabling DDI A/E power well
>[   76.985591] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   76.985596] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   76.985600] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   76.985609] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee88d8000
>[   76.985615] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee88d8000
>[   76.985713] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5de7800
>[   76.985716] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee5e2ae40 state to ffff978ee5de7800
>[   76.985720] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de3000 state to ffff978ee5de7800
>[   76.985722] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5e2ae40 to [NOCRTC]
>[   76.985724] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee5e2ae40
>[   76.985726] [drm:drm_atomic_check_only] checking ffff978ee5de7800
>[   76.985736] [drm:drm_atomic_commit] commiting ffff978ee5de7800
>[   76.985744] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5de7800
>[   76.985747] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5de7800
>[   76.985756] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   76.985761] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[   76.985764] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5de7800
>[   76.985766] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de2800 state to ffff978ee5de7800
>[   76.985769] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee5e2a000 state to ffff978ee5de7800
>[   76.985772] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5de2800
>[   76.985774] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5e2a000 to [CRTC:26:pipe A]
>[   76.985776] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffff978ee5e2a000
>[   76.985779] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de7800
>[   76.985782] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2c840 state to ffff978ee5de7800
>[   76.985784] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c840 to [NOCRTC]
>[   76.985787] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c840 to [CRTC:26:pipe A]
>[   76.985789] [drm:drm_atomic_check_only] checking ffff978ee5de7800
>[   76.985793] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   76.985796] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   76.985797] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   76.985799] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[   76.985802] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de7800
>[   76.985805] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de7800
>[   76.985808] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   76.985810] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   76.985816] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   76.985821] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   76.985830] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   76.985833] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   76.985835] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   76.985839] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5de2800 for pipe A
>[   76.985841] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   76.985842] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   76.985845] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   76.985847] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   76.985850] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   76.985852] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   76.985853] [drm:intel_dump_pipe_config] requested mode:
>[   76.985858] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   76.985859] [drm:intel_dump_pipe_config] adjusted mode:
>[   76.985863] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   76.985866] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   76.985868] [drm:intel_dump_pipe_config] port clock: 540000
>[   76.985869] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   76.985871] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   76.985874] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   76.985876] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   76.985877] [drm:intel_dump_pipe_config] ips: 0
>[   76.985879] [drm:intel_dump_pipe_config] double wide: 0
>[   76.985881] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   76.985882] [drm:intel_dump_pipe_config] planes on this crtc
>[   76.985885] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   76.985888] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   76.985891] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   76.985893] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   76.985895] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   76.985899] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5de4800 state to ffff978ee5de7800
>[   76.985902] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5de6000 state to ffff978ee5de7800
>[   76.985904] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[   76.985910] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   76.985912] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   76.985915] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[   76.985918] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   76.985921] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   76.985925] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   76.985934] [drm:drm_atomic_commit] commiting ffff978ee5de7800
>[   76.985943] [drm:intel_power_well_enable] enabling DDI A/E power well
>[   76.985946] [drm:skl_set_power_well] Enabling DDI A/E power well
>[   76.985952] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[   76.985994] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   76.985998] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   76.986001] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   76.986005] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   76.986008] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   76.986011] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   76.986014] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   76.986017] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   76.986020] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   76.986022] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   76.986025] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   76.986028] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   76.986031] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   76.986034] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   76.986037] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   76.986040] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   76.986043] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   76.986045] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   76.986051] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[   76.986053] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[   77.554958] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000
>[   77.557196] [drm:wait_panel_status] Wait complete
>[   77.557259] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[   77.557276] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[   77.609858] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   77.609864] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   77.609867] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[   77.763351] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[   77.763358] [drm:edp_panel_on] Turn eDP port A panel power on
>[   77.763377] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   77.763459] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[   77.763477] [drm:wait_panel_status] Wait complete
>[   77.763511] [drm:edp_panel_on] Wait for panel power on
>[   77.763599] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[   77.964066] [drm:wait_panel_status] Wait complete
>[   77.965943] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   77.965946] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   77.965948] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   77.965951] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[   77.966624] [drm:intel_dp_start_link_train] clock recovery OK
>[   77.966627] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[   77.966628] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[   77.967601] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[   77.967603] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   77.967605] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   77.968567] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[   77.968740] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5de2800
>[   77.968842] [drm:intel_enable_pipe] enabling pipe A
>[   77.968852] [drm:intel_edp_backlight_on.part.29] 
>[   77.968856] [drm:intel_panel_enable_backlight] pipe A
>[   77.968937] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   77.968993] [drm:intel_psr_enable] PSR disable by flag
>[   77.968995] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   77.985804] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   77.985811] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   77.985825] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   77.985831] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5de7800
>[   77.985835] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5de7800
>[   77.986222] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   77.986223] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f800
>[   77.986227] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d88000 state to ffff978ee5d8f800
>[   77.986228] [drm:drm_atomic_check_only] checking ffff978ee5d8f800
>[   77.986234] [drm:drm_atomic_commit] commiting ffff978ee5d8f800
>[   78.002395] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f800
>[   78.002399] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f800
>[   78.002428] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[   78.002429] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   78.002613] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f800
>[   78.002616] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee88010c0 state to ffff978ee5d8f800
>[   78.002618] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d000 state to ffff978ee5d8f800
>[   78.002620] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee88010c0 to [CRTC:26:pipe A]
>[   78.002621] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee88010c0
>[   78.002622] [drm:drm_atomic_check_only] checking ffff978ee5d8f800
>[   78.002643] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   78.002644] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[   78.002651] [drm:drm_atomic_commit] commiting ffff978ee5d8f800
>[   78.002676] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f800
>[   78.002679] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f800
>[   79.120554] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5de7800
>[   79.120560] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de3000 state to ffff978ee5de7800
>[   79.120563] [drm:drm_atomic_check_only] checking ffff978ee5de7800
>[   79.120567] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   79.120587] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[   79.120590] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de7800
>[   79.120593] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2c6a0 state to ffff978ee5de7800
>[   79.120596] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee58fecc0 state to ffff978ee5de7800
>[   79.120599] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee58fec00 state to ffff978ee5de7800
>[   79.120602] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de7800
>[   79.120605] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   79.120607] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   79.120614] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   79.120619] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   79.120627] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   79.120630] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   79.120632] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   79.120636] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5de3000 for pipe A
>[   79.120638] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   79.120640] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   79.120642] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   79.120644] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   79.120646] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   79.120648] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   79.120649] [drm:intel_dump_pipe_config] requested mode:
>[   79.120654] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   79.120655] [drm:intel_dump_pipe_config] adjusted mode:
>[   79.120658] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   79.120661] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   79.120662] [drm:intel_dump_pipe_config] port clock: 540000
>[   79.120664] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   79.120666] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   79.120668] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   79.120670] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   79.120671] [drm:intel_dump_pipe_config] ips: 0
>[   79.120673] [drm:intel_dump_pipe_config] double wide: 0
>[   79.120674] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   79.120676] [drm:intel_dump_pipe_config] planes on this crtc
>[   79.120679] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   79.120681] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   79.120684] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   79.120686] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[   79.120688] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[   79.120690] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[   79.120694] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   79.120708] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5de0800 state to ffff978ee5de7800
>[   79.120718] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5de2800 state to ffff978ee5de7800
>[   79.120726] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[   79.120764] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   79.120766] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   79.120768] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[   79.120770] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   79.120772] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[   79.120776] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   79.120778] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   79.120782] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   79.120790] [drm:drm_atomic_commit] commiting ffff978ee5de7800
>[   79.122662] [drm:intel_edp_backlight_off.part.30] 
>[   79.330728] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   79.330778] [drm:intel_disable_pipe] disabling pipe A
>[   79.337387] [drm:edp_panel_off] Turn eDP port A panel power off
>[   79.337427] [drm:edp_panel_off] Wait for panel power off time
>[   79.337504] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[   79.338113] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[   79.338119] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[   79.338144] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[   79.388100] [drm:wait_panel_status] Wait complete
>[   79.388116] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[   79.388136] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   79.388139] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[   79.388156] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   79.388172] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[   79.389926] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   79.389932] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   79.389935] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[   79.394752] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   79.394759] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   79.394764] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   79.394770] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   79.394773] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   79.394776] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   79.394779] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   79.394783] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   79.394786] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   79.394788] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   79.394792] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   79.394795] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   79.394798] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   79.394801] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   79.394804] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   79.394809] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   79.394812] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   79.394816] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   79.394825] [drm:intel_power_well_disable] disabling DDI A/E power well
>[   79.394829] [drm:skl_set_power_well] Disabling DDI A/E power well
>[   79.394834] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   79.394839] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   79.394843] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   79.394852] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5de7800
>[   79.394859] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5de7800
>[   79.394960] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5de7800
>[   79.394964] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee58fe240 state to ffff978ee5de7800
>[   79.394967] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de6000 state to ffff978ee5de7800
>[   79.394970] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee58fe240 to [NOCRTC]
>[   79.394972] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee58fe240
>[   79.394975] [drm:drm_atomic_check_only] checking ffff978ee5de7800
>[   79.394984] [drm:drm_atomic_commit] commiting ffff978ee5de7800
>[   79.394993] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5de7800
>[   79.394996] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5de7800
>[   79.395005] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   79.395011] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[   79.395013] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5de7800
>[   79.395016] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de3000 state to ffff978ee5de7800
>[   79.395019] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee58fec00 state to ffff978ee5de7800
>[   79.395022] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5de3000
>[   79.395024] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee58fec00 to [CRTC:26:pipe A]
>[   79.395027] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffff978ee58fec00
>[   79.395030] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de7800
>[   79.395033] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2c840 state to ffff978ee5de7800
>[   79.395036] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c840 to [NOCRTC]
>[   79.395039] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c840 to [CRTC:26:pipe A]
>[   79.395041] [drm:drm_atomic_check_only] checking ffff978ee5de7800
>[   79.395046] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   79.395048] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   79.395051] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   79.395053] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[   79.395055] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de7800
>[   79.395059] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de7800
>[   79.395061] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   79.395063] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   79.395071] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   79.395076] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   79.395085] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   79.395088] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   79.395091] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   79.395094] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5de3000 for pipe A
>[   79.395096] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   79.395098] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   79.395101] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   79.395104] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   79.395106] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   79.395108] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   79.395110] [drm:intel_dump_pipe_config] requested mode:
>[   79.395115] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   79.395117] [drm:intel_dump_pipe_config] adjusted mode:
>[   79.395120] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   79.395124] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   79.395126] [drm:intel_dump_pipe_config] port clock: 540000
>[   79.395127] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   79.395130] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   79.395132] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   79.395134] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   79.395136] [drm:intel_dump_pipe_config] ips: 0
>[   79.395138] [drm:intel_dump_pipe_config] double wide: 0
>[   79.395140] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   79.395142] [drm:intel_dump_pipe_config] planes on this crtc
>[   79.395145] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   79.395148] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   79.395151] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   79.395153] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   79.395155] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   79.395160] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5de4800 state to ffff978ee5de7800
>[   79.395164] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee527b800 state to ffff978ee5de7800
>[   79.395166] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[   79.395172] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   79.395174] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   79.395177] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[   79.395181] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   79.395184] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   79.395188] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   79.395198] [drm:drm_atomic_commit] commiting ffff978ee5de7800
>[   79.395208] [drm:intel_power_well_enable] enabling DDI A/E power well
>[   79.395212] [drm:skl_set_power_well] Enabling DDI A/E power well
>[   79.395218] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[   79.395263] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   79.395267] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   79.395271] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   79.395275] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   79.395279] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   79.395282] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   79.395285] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   79.395288] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   79.395291] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   79.395294] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   79.395297] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   79.395300] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   79.395303] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   79.395306] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   79.395309] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   79.395312] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   79.395316] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   79.395319] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   79.395324] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[   79.395327] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[   79.986973] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[   79.986994] [drm:wait_panel_status] Wait complete
>[   79.987050] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[   79.987064] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[   80.036476] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   80.036482] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   80.036485] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[   80.195379] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[   80.195386] [drm:edp_panel_on] Turn eDP port A panel power on
>[   80.195407] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   80.195489] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[   80.195508] [drm:wait_panel_status] Wait complete
>[   80.195542] [drm:edp_panel_on] Wait for panel power on
>[   80.195637] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[   80.396080] [drm:wait_panel_status] Wait complete
>[   80.397947] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   80.397950] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   80.397951] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   80.397954] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[   80.398627] [drm:intel_dp_start_link_train] clock recovery OK
>[   80.398629] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[   80.398631] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[   80.399604] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[   80.399606] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   80.399608] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   80.400568] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[   80.400747] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5de3000
>[   80.400848] [drm:intel_enable_pipe] enabling pipe A
>[   80.400859] [drm:intel_edp_backlight_on.part.29] 
>[   80.400863] [drm:intel_panel_enable_backlight] pipe A
>[   80.400944] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   80.401000] [drm:intel_psr_enable] PSR disable by flag
>[   80.401002] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   80.417797] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   80.417807] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   80.417828] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   80.417838] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5de7800
>[   80.417844] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5de7800
>[   80.417883] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5279800
>[   80.417887] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de7800 state to ffff978ee5279800
>[   80.417890] [drm:drm_atomic_check_only] checking ffff978ee5279800
>[   80.417900] [drm:drm_atomic_commit] commiting ffff978ee5279800
>[   80.434424] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5279800
>[   80.434429] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5279800
>[   80.434469] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[   80.434473] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   80.434699] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5de3000
>[   80.434706] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee58fecc0 state to ffff978ee5de3000
>[   80.434711] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de2800 state to ffff978ee5de3000
>[   80.434714] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee58fecc0 to [CRTC:26:pipe A]
>[   80.434717] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee58fecc0
>[   80.434720] [drm:drm_atomic_check_only] checking ffff978ee5de3000
>[   80.434730] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   80.434733] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[   80.434748] [drm:drm_atomic_commit] commiting ffff978ee5de3000
>[   80.434880] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5de3000
>[   80.434884] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5de3000
>[   80.435057] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   81.553316] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5de0800
>[   81.553320] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de3000 state to ffff978ee5de0800
>[   81.553323] [drm:drm_atomic_check_only] checking ffff978ee5de0800
>[   81.553326] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   81.553328] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[   81.553330] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de0800
>[   81.553332] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2c660 state to ffff978ee5de0800
>[   81.553348] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee96316c0 state to ffff978ee5de0800
>[   81.553350] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee9631240 state to ffff978ee5de0800
>[   81.553353] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de0800
>[   81.553356] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   81.553357] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   81.553364] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   81.553368] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   81.553375] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   81.553377] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   81.553380] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   81.553383] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5de3000 for pipe A
>[   81.553384] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   81.553386] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   81.553388] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   81.553390] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   81.553392] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   81.553394] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   81.553395] [drm:intel_dump_pipe_config] requested mode:
>[   81.553399] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   81.553400] [drm:intel_dump_pipe_config] adjusted mode:
>[   81.553403] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   81.553406] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   81.553407] [drm:intel_dump_pipe_config] port clock: 540000
>[   81.553409] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   81.553411] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   81.553412] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   81.553414] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   81.553416] [drm:intel_dump_pipe_config] ips: 0
>[   81.553417] [drm:intel_dump_pipe_config] double wide: 0
>[   81.553419] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   81.553420] [drm:intel_dump_pipe_config] planes on this crtc
>[   81.553423] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   81.553425] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   81.553427] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   81.553429] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[   81.553431] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[   81.553433] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[   81.553435] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   81.553440] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5de7800 state to ffff978ee5de0800
>[   81.553442] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5de6000 state to ffff978ee5de0800
>[   81.553443] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[   81.553448] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   81.553450] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   81.553452] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[   81.553454] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   81.553456] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[   81.553460] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   81.553462] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   81.553465] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   81.553472] [drm:drm_atomic_commit] commiting ffff978ee5de0800
>[   81.554662] [drm:intel_edp_backlight_off.part.30] 
>[   81.762759] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   81.762815] [drm:intel_disable_pipe] disabling pipe A
>[   81.769431] [drm:edp_panel_off] Turn eDP port A panel power off
>[   81.769471] [drm:edp_panel_off] Wait for panel power off time
>[   81.769548] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[   81.770160] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[   81.770166] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[   81.770189] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[   81.820208] [drm:wait_panel_status] Wait complete
>[   81.820225] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[   81.820244] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   81.820246] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[   81.820264] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   81.820279] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[   81.821937] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   81.821943] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   81.821946] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[   81.822569] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   81.822576] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   81.822580] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   81.822586] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   81.822589] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   81.822606] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   81.822609] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   81.822619] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   81.822622] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   81.822625] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   81.822628] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   81.822631] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   81.822633] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   81.822636] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   81.822640] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   81.822644] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   81.822647] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   81.822650] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   81.822659] [drm:intel_power_well_disable] disabling DDI A/E power well
>[   81.822663] [drm:skl_set_power_well] Disabling DDI A/E power well
>[   81.822668] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   81.822672] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   81.822677] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   81.822686] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5de0800
>[   81.822692] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5de0800
>[   81.822782] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5de0800
>[   81.822786] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee9631300 state to ffff978ee5de0800
>[   81.822790] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de4800 state to ffff978ee5de0800
>[   81.822792] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee9631300 to [NOCRTC]
>[   81.822794] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee9631300
>[   81.822796] [drm:drm_atomic_check_only] checking ffff978ee5de0800
>[   81.822806] [drm:drm_atomic_commit] commiting ffff978ee5de0800
>[   81.822814] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5de0800
>[   81.822816] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5de0800
>[   81.822825] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   81.822830] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[   81.822833] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5de0800
>[   81.822835] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5de3000 state to ffff978ee5de0800
>[   81.822838] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee9631240 state to ffff978ee5de0800
>[   81.822841] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5de3000
>[   81.822843] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee9631240 to [CRTC:26:pipe A]
>[   81.822845] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffff978ee9631240
>[   81.822848] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de0800
>[   81.822851] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2c840 state to ffff978ee5de0800
>[   81.822854] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c840 to [NOCRTC]
>[   81.822856] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c840 to [CRTC:26:pipe A]
>[   81.822858] [drm:drm_atomic_check_only] checking ffff978ee5de0800
>[   81.822863] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   81.822865] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   81.822867] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   81.822869] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[   81.822872] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de0800
>[   81.822875] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5de0800
>[   81.822878] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   81.822880] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   81.822886] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   81.822891] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   81.822900] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   81.822903] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   81.822905] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   81.822909] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5de3000 for pipe A
>[   81.822911] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   81.822913] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   81.822915] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   81.822918] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   81.822920] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   81.822922] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   81.822923] [drm:intel_dump_pipe_config] requested mode:
>[   81.822928] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   81.822929] [drm:intel_dump_pipe_config] adjusted mode:
>[   81.822933] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   81.822936] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   81.822938] [drm:intel_dump_pipe_config] port clock: 540000
>[   81.822939] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   81.822941] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   81.822944] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   81.822946] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   81.822947] [drm:intel_dump_pipe_config] ips: 0
>[   81.822949] [drm:intel_dump_pipe_config] double wide: 0
>[   81.822951] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   81.822953] [drm:intel_dump_pipe_config] planes on this crtc
>[   81.822955] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   81.822958] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   81.822961] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   81.822963] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   81.822965] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   81.822970] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5de2800 state to ffff978ee5de0800
>[   81.822973] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee527b800 state to ffff978ee5de0800
>[   81.822975] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[   81.822981] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   81.822983] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   81.822985] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[   81.822990] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   81.822992] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   81.822996] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   81.823006] [drm:drm_atomic_commit] commiting ffff978ee5de0800
>[   81.823014] [drm:intel_power_well_enable] enabling DDI A/E power well
>[   81.823018] [drm:skl_set_power_well] Enabling DDI A/E power well
>[   81.823024] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[   81.823067] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   81.823071] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   81.823074] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   81.823078] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   81.823081] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   81.823083] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   81.823086] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   81.823089] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   81.823092] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   81.823095] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   81.823098] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   81.823101] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   81.823104] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   81.823107] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   81.823110] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   81.823113] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   81.823116] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   81.823118] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   81.823124] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[   81.823126] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[   82.418889] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[   82.418910] [drm:wait_panel_status] Wait complete
>[   82.418966] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[   82.418980] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[   82.468381] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   82.468387] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   82.468390] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[   82.627278] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[   82.627284] [drm:edp_panel_on] Turn eDP port A panel power on
>[   82.627304] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   82.627382] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[   82.627400] [drm:wait_panel_status] Wait complete
>[   82.627434] [drm:edp_panel_on] Wait for panel power on
>[   82.627509] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[   82.827808] [drm:wait_panel_status] Wait complete
>[   82.829688] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   82.829691] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   82.829692] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   82.829695] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[   82.830367] [drm:intel_dp_start_link_train] clock recovery OK
>[   82.830370] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[   82.830372] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[   82.831343] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[   82.831345] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   82.831346] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   82.832306] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[   82.832479] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5de3000
>[   82.832577] [drm:intel_enable_pipe] enabling pipe A
>[   82.832586] [drm:intel_edp_backlight_on.part.29] 
>[   82.832590] [drm:intel_panel_enable_backlight] pipe A
>[   82.832674] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   82.832730] [drm:intel_psr_enable] PSR disable by flag
>[   82.832732] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   82.849526] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   82.849537] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   82.849557] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   82.849567] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5de0800
>[   82.849573] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5de0800
>[   82.849998] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   82.850000] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f000
>[   82.850006] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d800 state to ffff978ee5d8f000
>[   82.850009] [drm:drm_atomic_check_only] checking ffff978ee5d8f000
>[   82.850020] [drm:drm_atomic_commit] commiting ffff978ee5d8f000
>[   82.866183] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f000
>[   82.866190] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f000
>[   82.866226] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[   82.866230] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   82.866427] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f000
>[   82.866432] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee97da900 state to ffff978ee5d8f000
>[   82.866436] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8e000 state to ffff978ee5d8f000
>[   82.866438] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee97da900 to [CRTC:26:pipe A]
>[   82.866441] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee97da900
>[   82.866444] [drm:drm_atomic_check_only] checking ffff978ee5d8f000
>[   82.866452] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   82.866455] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[   82.866482] [drm:drm_atomic_commit] commiting ffff978ee5d8f000
>[   82.866515] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f000
>[   82.866518] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f000
>[   83.985980] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88d8800
>[   83.985985] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee88dd800 state to ffff978ee88d8800
>[   83.985988] [drm:drm_atomic_check_only] checking ffff978ee88d8800
>[   83.985993] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   83.985995] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[   83.985999] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88d8800
>[   83.986004] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebbb2640 state to ffff978ee88d8800
>[   83.986008] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee97d3a80 state to ffff978ee88d8800
>[   83.986011] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee97d3300 state to ffff978ee88d8800
>[   83.986014] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88d8800
>[   83.986018] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   83.986019] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   83.986026] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   83.986031] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   83.986038] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   83.986041] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   83.986043] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   83.986046] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee88dd800 for pipe A
>[   83.986048] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   83.986050] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   83.986052] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   83.986054] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   83.986057] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   83.986058] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   83.986060] [drm:intel_dump_pipe_config] requested mode:
>[   83.986064] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   83.986066] [drm:intel_dump_pipe_config] adjusted mode:
>[   83.986069] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   83.986071] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   83.986073] [drm:intel_dump_pipe_config] port clock: 540000
>[   83.986074] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   83.986076] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   83.986078] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   83.986080] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   83.986082] [drm:intel_dump_pipe_config] ips: 0
>[   83.986083] [drm:intel_dump_pipe_config] double wide: 0
>[   83.986085] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   83.986086] [drm:intel_dump_pipe_config] planes on this crtc
>[   83.986089] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   83.986092] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   83.986094] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   83.986096] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[   83.986099] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[   83.986101] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[   83.986103] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   83.986108] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee88d9800 state to ffff978ee88d8800
>[   83.986110] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee88da800 state to ffff978ee88d8800
>[   83.986112] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[   83.986117] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   83.986119] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   83.986121] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[   83.986124] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   83.986125] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[   83.986130] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   83.986132] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   83.986135] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   83.986143] [drm:drm_atomic_commit] commiting ffff978ee88d8800
>[   83.987745] [drm:intel_edp_backlight_off.part.30] 
>[   84.194823] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   84.194880] [drm:intel_disable_pipe] disabling pipe A
>[   84.201373] [drm:edp_panel_off] Turn eDP port A panel power off
>[   84.201413] [drm:edp_panel_off] Wait for panel power off time
>[   84.201490] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[   84.202093] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[   84.202099] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[   84.202113] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[   84.252309] [drm:wait_panel_status] Wait complete
>[   84.252326] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[   84.252343] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[   84.252347] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   84.252365] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   84.252379] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[   84.253820] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   84.253826] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   84.253829] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[   84.254611] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   84.254631] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   84.254635] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   84.254641] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   84.254644] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   84.254647] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   84.254650] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   84.254653] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   84.254656] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   84.254658] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   84.254661] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   84.254665] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   84.254667] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   84.254670] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   84.254673] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   84.254677] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   84.254680] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   84.254683] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   84.254693] [drm:intel_power_well_disable] disabling DDI A/E power well
>[   84.254697] [drm:skl_set_power_well] Disabling DDI A/E power well
>[   84.254701] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   84.254706] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   84.254710] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   84.254718] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee88d8800
>[   84.254725] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee88d8800
>[   84.254817] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee527b800
>[   84.254821] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee96316c0 state to ffff978ee527b800
>[   84.254825] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee88be800 state to ffff978ee527b800
>[   84.254827] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee96316c0 to [NOCRTC]
>[   84.254829] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee96316c0
>[   84.254832] [drm:drm_atomic_check_only] checking ffff978ee527b800
>[   84.254841] [drm:drm_atomic_commit] commiting ffff978ee527b800
>[   84.254849] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee527b800
>[   84.254852] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee527b800
>[   84.254861] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   84.254866] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[   84.254869] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88b8800
>[   84.254871] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee527b800 state to ffff978ee88b8800
>[   84.254874] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee9631780 state to ffff978ee88b8800
>[   84.254877] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee527b800
>[   84.254879] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee9631780 to [CRTC:26:pipe A]
>[   84.254881] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffff978ee9631780
>[   84.254884] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88b8800
>[   84.254887] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2c840 state to ffff978ee88b8800
>[   84.254889] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c840 to [NOCRTC]
>[   84.254892] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c840 to [CRTC:26:pipe A]
>[   84.254894] [drm:drm_atomic_check_only] checking ffff978ee88b8800
>[   84.254898] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   84.254900] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   84.254902] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   84.254904] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[   84.254906] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88b8800
>[   84.254910] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88b8800
>[   84.254912] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   84.254914] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   84.254920] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   84.254925] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   84.254934] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   84.254937] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   84.254939] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   84.254942] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee527b800 for pipe A
>[   84.254944] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   84.254946] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   84.254949] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   84.254951] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   84.254954] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   84.254956] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   84.254957] [drm:intel_dump_pipe_config] requested mode:
>[   84.254962] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   84.254963] [drm:intel_dump_pipe_config] adjusted mode:
>[   84.254967] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   84.254970] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   84.254972] [drm:intel_dump_pipe_config] port clock: 540000
>[   84.254973] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   84.254975] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   84.254978] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   84.254980] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   84.254982] [drm:intel_dump_pipe_config] ips: 0
>[   84.254983] [drm:intel_dump_pipe_config] double wide: 0
>[   84.254985] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   84.254987] [drm:intel_dump_pipe_config] planes on this crtc
>[   84.254990] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   84.254993] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   84.254995] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   84.254998] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   84.255000] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   84.255005] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee84f2000 state to ffff978ee88b8800
>[   84.255007] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee84f7800 state to ffff978ee88b8800
>[   84.255009] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[   84.255015] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   84.255017] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   84.255020] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[   84.255024] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   84.255026] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   84.255030] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   84.255040] [drm:drm_atomic_commit] commiting ffff978ee88b8800
>[   84.255049] [drm:intel_power_well_enable] enabling DDI A/E power well
>[   84.255053] [drm:skl_set_power_well] Enabling DDI A/E power well
>[   84.255059] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[   84.257267] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   84.257273] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   84.257277] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   84.257283] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   84.257286] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   84.257289] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   84.257292] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   84.257295] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   84.257298] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   84.257301] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   84.257304] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   84.257307] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   84.257310] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   84.257312] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   84.257315] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   84.257319] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   84.257323] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   84.257326] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   84.257332] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[   84.257334] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[   84.851012] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[   84.851032] [drm:wait_panel_status] Wait complete
>[   84.851088] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[   84.851101] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[   84.900527] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   84.900533] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   84.900536] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[   85.059410] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[   85.059416] [drm:edp_panel_on] Turn eDP port A panel power on
>[   85.059436] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   85.059518] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[   85.059536] [drm:wait_panel_status] Wait complete
>[   85.059570] [drm:edp_panel_on] Wait for panel power on
>[   85.059659] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[   85.261162] [drm:wait_panel_status] Wait complete
>[   85.263040] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   85.263043] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   85.263044] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   85.263048] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[   85.263720] [drm:intel_dp_start_link_train] clock recovery OK
>[   85.263723] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[   85.263724] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[   85.264697] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[   85.264699] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   85.264700] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   85.265661] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[   85.265835] [drm:skylake_pfit_enable] for crtc_state = ffff978ee527b800
>[   85.265936] [drm:intel_enable_pipe] enabling pipe A
>[   85.265946] [drm:intel_edp_backlight_on.part.29] 
>[   85.265950] [drm:intel_panel_enable_backlight] pipe A
>[   85.266031] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   85.266087] [drm:intel_psr_enable] PSR disable by flag
>[   85.266089] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   85.282760] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   85.282769] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   85.282788] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   85.282797] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee88b8800
>[   85.282803] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee88b8800
>[   85.283197] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   85.283200] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f000
>[   85.283205] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d800 state to ffff978ee5d8f000
>[   85.283207] [drm:drm_atomic_check_only] checking ffff978ee5d8f000
>[   85.283216] [drm:drm_atomic_commit] commiting ffff978ee5d8f000
>[   85.299554] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f000
>[   85.299560] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f000
>[   85.299597] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[   85.299600] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   85.299799] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f000
>[   85.299819] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee5d2b840 state to ffff978ee5d8f000
>[   85.299824] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8e000 state to ffff978ee5d8f000
>[   85.299826] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5d2b840 to [CRTC:26:pipe A]
>[   85.299829] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee5d2b840
>[   85.299831] [drm:drm_atomic_check_only] checking ffff978ee5d8f000
>[   85.299840] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   85.299842] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[   85.299854] [drm:drm_atomic_commit] commiting ffff978ee5d8f000
>[   85.299886] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f000
>[   85.299890] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f000
>[   86.420325] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee6b0f800
>[   86.420332] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee9774000 state to ffff978ee6b0f800
>[   86.420335] [drm:drm_atomic_check_only] checking ffff978ee6b0f800
>[   86.420339] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   86.420341] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[   86.420346] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee6b0f800
>[   86.420350] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2cf20 state to ffff978ee6b0f800
>[   86.420353] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee635da80 state to ffff978ee6b0f800
>[   86.420358] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee635d300 state to ffff978ee6b0f800
>[   86.420365] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee6b0f800
>[   86.420373] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   86.420374] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   86.420392] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   86.420396] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   86.420403] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   86.420405] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   86.420407] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   86.420410] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee9774000 for pipe A
>[   86.420412] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   86.420413] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   86.420415] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   86.420417] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   86.420419] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   86.420420] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   86.420422] [drm:intel_dump_pipe_config] requested mode:
>[   86.420440] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   86.420441] [drm:intel_dump_pipe_config] adjusted mode:
>[   86.420445] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   86.420447] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   86.420449] [drm:intel_dump_pipe_config] port clock: 540000
>[   86.420450] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   86.420452] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   86.420454] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   86.420456] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   86.420457] [drm:intel_dump_pipe_config] ips: 0
>[   86.420459] [drm:intel_dump_pipe_config] double wide: 0
>[   86.420461] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   86.420462] [drm:intel_dump_pipe_config] planes on this crtc
>[   86.420465] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   86.420467] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   86.420470] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   86.420472] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[   86.420474] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[   86.420476] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[   86.420478] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   86.420486] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5650000 state to ffff978ee6b0f800
>[   86.420489] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5650800 state to ffff978ee6b0f800
>[   86.420491] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[   86.420497] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   86.420499] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   86.420501] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[   86.420503] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   86.420505] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[   86.420509] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   86.420511] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   86.420515] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   86.420522] [drm:drm_atomic_commit] commiting ffff978ee6b0f800
>[   86.421716] [drm:intel_edp_backlight_off.part.30] 
>[   86.626872] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   86.626929] [drm:intel_disable_pipe] disabling pipe A
>[   86.633571] [drm:edp_panel_off] Turn eDP port A panel power off
>[   86.633611] [drm:edp_panel_off] Wait for panel power off time
>[   86.633702] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[   86.634275] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[   86.634280] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[   86.634304] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[   86.684478] [drm:wait_panel_status] Wait complete
>[   86.684494] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[   86.684514] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   86.684516] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[   86.684534] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   86.684550] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[   86.685841] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   86.685847] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   86.685851] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[   86.688889] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   86.688895] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   86.688900] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   86.688905] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   86.688909] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   86.688911] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   86.688914] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   86.688918] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   86.688920] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   86.688923] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   86.688926] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   86.688930] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   86.688932] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   86.688935] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   86.688938] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   86.688942] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   86.688946] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   86.688949] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   86.688958] [drm:intel_power_well_disable] disabling DDI A/E power well
>[   86.688962] [drm:skl_set_power_well] Disabling DDI A/E power well
>[   86.688966] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   86.688971] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   86.688975] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   86.688984] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee6b0f800
>[   86.688991] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee6b0f800
>[   86.689083] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5651000
>[   86.689087] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee635d480 state to ffff978ee5651000
>[   86.689091] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5651800 state to ffff978ee5651000
>[   86.689093] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee635d480 to [NOCRTC]
>[   86.689095] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee635d480
>[   86.689097] [drm:drm_atomic_check_only] checking ffff978ee5651000
>[   86.689106] [drm:drm_atomic_commit] commiting ffff978ee5651000
>[   86.689114] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5651000
>[   86.689117] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5651000
>[   86.689126] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   86.689131] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[   86.689134] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5651000
>[   86.689137] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5652000 state to ffff978ee5651000
>[   86.689139] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee635d300 state to ffff978ee5651000
>[   86.689143] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5652000
>[   86.689145] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee635d300 to [CRTC:26:pipe A]
>[   86.689147] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffff978ee635d300
>[   86.689150] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5651000
>[   86.689153] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2c840 state to ffff978ee5651000
>[   86.689155] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c840 to [NOCRTC]
>[   86.689158] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c840 to [CRTC:26:pipe A]
>[   86.689160] [drm:drm_atomic_check_only] checking ffff978ee5651000
>[   86.689164] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   86.689167] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   86.689170] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   86.689172] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[   86.689174] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5651000
>[   86.689177] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5651000
>[   86.689180] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   86.689182] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   86.689189] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   86.689193] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   86.689202] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   86.689205] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   86.689208] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   86.689211] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5652000 for pipe A
>[   86.689213] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   86.689215] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   86.689217] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   86.689220] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   86.689222] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   86.689224] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   86.689226] [drm:intel_dump_pipe_config] requested mode:
>[   86.689230] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   86.689232] [drm:intel_dump_pipe_config] adjusted mode:
>[   86.689235] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   86.689238] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   86.689240] [drm:intel_dump_pipe_config] port clock: 540000
>[   86.689242] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   86.689244] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   86.689246] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   86.689248] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   86.689250] [drm:intel_dump_pipe_config] ips: 0
>[   86.689251] [drm:intel_dump_pipe_config] double wide: 0
>[   86.689253] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   86.689255] [drm:intel_dump_pipe_config] planes on this crtc
>[   86.689258] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   86.689261] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   86.689263] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   86.689266] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   86.689268] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   86.689273] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5652800 state to ffff978ee5651000
>[   86.689275] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5653000 state to ffff978ee5651000
>[   86.689277] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[   86.689283] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   86.689285] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   86.689288] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[   86.689292] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   86.689294] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   86.689298] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   86.689308] [drm:drm_atomic_commit] commiting ffff978ee5651000
>[   86.689316] [drm:intel_power_well_enable] enabling DDI A/E power well
>[   86.689320] [drm:skl_set_power_well] Enabling DDI A/E power well
>[   86.689326] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[   86.689368] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   86.689372] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   86.689375] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   86.689379] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   86.689382] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   86.689384] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   86.689387] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   86.689390] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   86.689393] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   86.689396] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   86.689399] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   86.689401] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   86.689404] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   86.689407] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   86.689409] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   86.689413] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   86.689416] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   86.689418] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   86.689423] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[   86.689426] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[   87.283032] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[   87.283067] [drm:wait_panel_status] Wait complete
>[   87.283128] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[   87.283142] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[   87.332547] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   87.332552] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   87.332556] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[   87.491431] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[   87.491437] [drm:edp_panel_on] Turn eDP port A panel power on
>[   87.491457] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   87.491540] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[   87.491558] [drm:wait_panel_status] Wait complete
>[   87.491592] [drm:edp_panel_on] Wait for panel power on
>[   87.491685] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[   87.692053] [drm:wait_panel_status] Wait complete
>[   87.693943] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   87.693945] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   87.693947] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   87.693950] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[   87.694633] [drm:intel_dp_start_link_train] clock recovery OK
>[   87.694636] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[   87.694638] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[   87.695630] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[   87.695632] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   87.695633] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   87.696608] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[   87.696788] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5652000
>[   87.696890] [drm:intel_enable_pipe] enabling pipe A
>[   87.696900] [drm:intel_edp_backlight_on.part.29] 
>[   87.696904] [drm:intel_panel_enable_backlight] pipe A
>[   87.696985] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   87.697042] [drm:intel_psr_enable] PSR disable by flag
>[   87.697043] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   87.713715] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   87.713726] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   87.713747] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   87.713756] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5651000
>[   87.713762] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5651000
>[   87.714168] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   87.714171] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d800
>[   87.714176] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f800 state to ffff978ee5d8d800
>[   87.714180] [drm:drm_atomic_check_only] checking ffff978ee5d8d800
>[   87.714189] [drm:drm_atomic_commit] commiting ffff978ee5d8d800
>[   87.730361] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d800
>[   87.730368] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d800
>[   87.730409] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[   87.730413] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   87.730600] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5652000
>[   87.730606] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee635d780 state to ffff978ee5652000
>[   87.730610] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5653800 state to ffff978ee5652000
>[   87.730612] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee635d780 to [CRTC:26:pipe A]
>[   87.730615] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee635d780
>[   87.730617] [drm:drm_atomic_check_only] checking ffff978ee5652000
>[   87.730626] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   87.730628] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[   87.730640] [drm:drm_atomic_commit] commiting ffff978ee5652000
>[   87.731009] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5652000
>[   87.731013] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5652000
>[   88.850927] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5655800
>[   88.850932] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5656000 state to ffff978ee5655800
>[   88.850935] [drm:drm_atomic_check_only] checking ffff978ee5655800
>[   88.850939] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   88.850941] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[   88.850943] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5655800
>[   88.850946] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2c460 state to ffff978ee5655800
>[   88.850950] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee62ee600 state to ffff978ee5655800
>[   88.850952] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee62ee540 state to ffff978ee5655800
>[   88.850955] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5655800
>[   88.850958] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   88.850959] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   88.850967] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   88.850971] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   88.850978] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   88.850981] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   88.850984] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   88.850987] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5656000 for pipe A
>[   88.850989] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   88.850990] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   88.850993] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   88.850995] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   88.850997] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   88.850998] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   88.851000] [drm:intel_dump_pipe_config] requested mode:
>[   88.851004] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   88.851005] [drm:intel_dump_pipe_config] adjusted mode:
>[   88.851008] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   88.851011] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   88.851013] [drm:intel_dump_pipe_config] port clock: 540000
>[   88.851014] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   88.851016] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   88.851018] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   88.851020] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   88.851021] [drm:intel_dump_pipe_config] ips: 0
>[   88.851023] [drm:intel_dump_pipe_config] double wide: 0
>[   88.851025] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   88.851026] [drm:intel_dump_pipe_config] planes on this crtc
>[   88.851029] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   88.851031] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   88.851088] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   88.851090] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[   88.851092] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[   88.851094] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[   88.851096] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   88.851101] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5656800 state to ffff978ee5655800
>[   88.851103] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5657000 state to ffff978ee5655800
>[   88.851105] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[   88.851111] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   88.851113] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   88.851115] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[   88.851117] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   88.851119] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[   88.851123] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   88.851126] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   88.851129] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   88.851136] [drm:drm_atomic_commit] commiting ffff978ee5655800
>[   88.852720] [drm:intel_edp_backlight_off.part.30] 
>[   89.058855] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   89.058912] [drm:intel_disable_pipe] disabling pipe A
>[   89.065482] [drm:edp_panel_off] Turn eDP port A panel power off
>[   89.065520] [drm:edp_panel_off] Wait for panel power off time
>[   89.065596] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[   89.066209] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[   89.066214] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[   89.066237] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[   89.116181] [drm:wait_panel_status] Wait complete
>[   89.116198] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[   89.116217] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   89.116220] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[   89.116237] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   89.116253] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[   89.117989] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   89.117995] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   89.117998] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[   89.120703] [drm:skl_pcode_request] PCODE timeout, retrying with preemption disabled
>[   89.122964] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   89.122970] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   89.122974] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   89.122979] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   89.122983] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   89.122985] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   89.122989] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   89.122992] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   89.122995] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   89.122997] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   89.123000] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   89.123004] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   89.123006] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   89.123009] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   89.123012] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   89.123016] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   89.123020] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   89.123023] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   89.123032] [drm:intel_power_well_disable] disabling DDI A/E power well
>[   89.123036] [drm:skl_set_power_well] Disabling DDI A/E power well
>[   89.123040] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   89.123045] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   89.123049] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   89.123058] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5655800
>[   89.123065] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5655800
>[   89.123171] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5655800
>[   89.123175] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee62eeb40 state to ffff978ee5655800
>[   89.123178] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5653000 state to ffff978ee5655800
>[   89.123181] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee62eeb40 to [NOCRTC]
>[   89.123183] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee62eeb40
>[   89.123185] [drm:drm_atomic_check_only] checking ffff978ee5655800
>[   89.123194] [drm:drm_atomic_commit] commiting ffff978ee5655800
>[   89.123201] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5655800
>[   89.123204] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5655800
>[   89.123213] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   89.123218] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[   89.123220] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5655800
>[   89.123223] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5656000 state to ffff978ee5655800
>[   89.123225] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee62ee540 state to ffff978ee5655800
>[   89.123228] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5656000
>[   89.123230] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee62ee540 to [CRTC:26:pipe A]
>[   89.123233] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffff978ee62ee540
>[   89.123235] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5655800
>[   89.123238] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2c840 state to ffff978ee5655800
>[   89.123241] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c840 to [NOCRTC]
>[   89.123243] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c840 to [CRTC:26:pipe A]
>[   89.123246] [drm:drm_atomic_check_only] checking ffff978ee5655800
>[   89.123250] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   89.123252] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   89.123254] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   89.123256] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[   89.123259] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5655800
>[   89.123262] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5655800
>[   89.123265] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   89.123266] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   89.123273] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   89.123278] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   89.123286] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   89.123289] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   89.123292] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   89.123295] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5656000 for pipe A
>[   89.123297] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   89.123299] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   89.123302] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   89.123304] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   89.123307] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   89.123309] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   89.123310] [drm:intel_dump_pipe_config] requested mode:
>[   89.123315] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   89.123317] [drm:intel_dump_pipe_config] adjusted mode:
>[   89.123320] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   89.123323] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   89.123325] [drm:intel_dump_pipe_config] port clock: 540000
>[   89.123326] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   89.123329] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   89.123331] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   89.123333] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   89.123334] [drm:intel_dump_pipe_config] ips: 0
>[   89.123336] [drm:intel_dump_pipe_config] double wide: 0
>[   89.123338] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   89.123339] [drm:intel_dump_pipe_config] planes on this crtc
>[   89.123342] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   89.123345] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   89.123348] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   89.123350] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   89.123352] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   89.123357] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5652800 state to ffff978ee5655800
>[   89.123359] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5653800 state to ffff978ee5655800
>[   89.123361] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[   89.123367] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   89.123369] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   89.123371] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[   89.123375] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   89.123378] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   89.123382] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   89.123391] [drm:drm_atomic_commit] commiting ffff978ee5655800
>[   89.123400] [drm:intel_power_well_enable] enabling DDI A/E power well
>[   89.123404] [drm:skl_set_power_well] Enabling DDI A/E power well
>[   89.123410] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[   89.127776] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   89.127783] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   89.127787] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   89.127793] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   89.127796] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   89.127799] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   89.127802] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   89.127805] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   89.127808] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   89.127811] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   89.127814] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   89.127817] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   89.127820] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   89.127822] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   89.127826] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   89.127829] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   89.127833] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   89.127835] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   89.127842] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[   89.127844] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[   89.715128] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[   89.715140] [drm:wait_panel_status] Wait complete
>[   89.715181] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[   89.715191] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[   89.764616] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   89.764622] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   89.764625] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[   89.923472] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[   89.923478] [drm:edp_panel_on] Turn eDP port A panel power on
>[   89.923495] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   89.923554] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[   89.923565] [drm:wait_panel_status] Wait complete
>[   89.923590] [drm:edp_panel_on] Wait for panel power on
>[   89.923648] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 0000000b
>[   90.124153] [drm:wait_panel_status] Wait complete
>[   90.126041] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   90.126044] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   90.126046] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   90.126049] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[   90.126724] [drm:intel_dp_start_link_train] clock recovery OK
>[   90.126728] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[   90.126730] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[   90.127705] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[   90.127707] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   90.127708] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   90.128670] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[   90.128845] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5656000
>[   90.128946] [drm:intel_enable_pipe] enabling pipe A
>[   90.128956] [drm:intel_edp_backlight_on.part.29] 
>[   90.128960] [drm:intel_panel_enable_backlight] pipe A
>[   90.129042] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   90.129098] [drm:intel_psr_enable] PSR disable by flag
>[   90.129100] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   90.145896] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   90.145907] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   90.145928] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   90.145939] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5655800
>[   90.145945] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5655800
>[   90.146357] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   90.146359] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d000
>[   90.146365] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d88000 state to ffff978ee5d8d000
>[   90.146368] [drm:drm_atomic_check_only] checking ffff978ee5d8d000
>[   90.146379] [drm:drm_atomic_commit] commiting ffff978ee5d8d000
>[   90.162526] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d000
>[   90.162532] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d000
>[   90.162568] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[   90.162571] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   90.162759] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d000
>[   90.162764] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee635dc00 state to ffff978ee5d8d000
>[   90.162768] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f800 state to ffff978ee5d8d000
>[   90.162771] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee635dc00 to [CRTC:26:pipe A]
>[   90.162774] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee635dc00
>[   90.162776] [drm:drm_atomic_check_only] checking ffff978ee5d8d000
>[   90.162784] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   90.162787] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[   90.162799] [drm:drm_atomic_commit] commiting ffff978ee5d8d000
>[   90.162829] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d000
>[   90.162833] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d000
>[   91.284221] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d88000
>[   91.284225] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d800 state to ffff978ee5d88000
>[   91.284228] [drm:drm_atomic_check_only] checking ffff978ee5d88000
>[   91.284231] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   91.284232] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[   91.284234] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d88000
>[   91.284235] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656c3e0 state to ffff978ee5d88000
>[   91.284238] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee97c2000 state to ffff978ee5d88000
>[   91.284239] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee97c2240 state to ffff978ee5d88000
>[   91.284241] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d88000
>[   91.284243] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   91.284244] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   91.284249] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   91.284252] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   91.284258] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   91.284259] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   91.284261] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   91.284263] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d8d800 for pipe A
>[   91.284265] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   91.284266] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   91.284267] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   91.284268] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   91.284270] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   91.284271] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   91.284271] [drm:intel_dump_pipe_config] requested mode:
>[   91.284275] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   91.284275] [drm:intel_dump_pipe_config] adjusted mode:
>[   91.284277] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   91.284279] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   91.284280] [drm:intel_dump_pipe_config] port clock: 540000
>[   91.284281] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   91.284282] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   91.284283] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   91.284285] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   91.284286] [drm:intel_dump_pipe_config] ips: 0
>[   91.284286] [drm:intel_dump_pipe_config] double wide: 0
>[   91.284288] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   91.284288] [drm:intel_dump_pipe_config] planes on this crtc
>[   91.284290] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   91.284292] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   91.284293] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   91.284295] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[   91.284296] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[   91.284298] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[   91.284299] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   91.284302] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d8e000 state to ffff978ee5d88000
>[   91.284304] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5d8d000 state to ffff978ee5d88000
>[   91.284305] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[   91.284310] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   91.284311] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[   91.284313] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[   91.284314] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   91.284315] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[   91.284318] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   91.284319] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   91.284321] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   91.284327] [drm:drm_atomic_commit] commiting ffff978ee5d88000
>[   91.285751] [drm:intel_edp_backlight_off.part.30] 
>[   91.490694] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   91.490734] [drm:intel_disable_pipe] disabling pipe A
>[   91.497346] [drm:edp_panel_off] Turn eDP port A panel power off
>[   91.497386] [drm:edp_panel_off] Wait for panel power off time
>[   91.497463] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000000
>[   91.499620] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[   91.499625] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[   91.499649] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[   91.547846] [drm:wait_panel_status] Wait complete
>[   91.547863] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[   91.547881] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[   91.547885] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   91.547902] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   91.547918] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[   91.549670] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   91.549673] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   91.549675] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[   91.550150] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   91.550154] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   91.550157] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   91.550161] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   91.550164] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   91.550167] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   91.550169] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   91.550172] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   91.550175] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   91.550177] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   91.550180] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   91.550183] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   91.550186] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   91.550188] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   91.550191] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   91.550194] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   91.550197] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   91.550200] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   91.550208] [drm:intel_power_well_disable] disabling DDI A/E power well
>[   91.550212] [drm:skl_set_power_well] Disabling DDI A/E power well
>[   91.550216] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   91.550220] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   91.550223] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   91.550231] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d88000
>[   91.550237] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d88000
>[   92.147082] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[   92.147104] [drm:wait_panel_status] Wait complete
>[   92.147159] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[   92.147173] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[   92.196572] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   92.196578] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   92.196582] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[   92.355477] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[   92.356592] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   92.554621] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5652800
>[   92.554627] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee87c5b40 state to ffff978ee5652800
>[   92.554632] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5656000 state to ffff978ee5652800
>[   92.554635] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee87c5b40 to [NOCRTC]
>[   92.554637] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee87c5b40
>[   92.554640] [drm:drm_atomic_check_only] checking ffff978ee5652800
>[   92.554651] [drm:drm_atomic_commit] commiting ffff978ee5652800
>[   92.554661] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5652800
>[   92.554665] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5652800
>[   92.554676] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   92.554694] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[   92.554698] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5652800
>[   92.554701] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5655800 state to ffff978ee5652800
>[   92.554704] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee87c5840 state to ffff978ee5652800
>[   92.554707] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5655800
>[   92.554710] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee87c5840 to [CRTC:26:pipe A]
>[   92.554712] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffff978ee87c5840
>[   92.554715] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5652800
>[   92.554718] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2c1e0 state to ffff978ee5652800
>[   92.554721] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c1e0 to [NOCRTC]
>[   92.554724] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c1e0 to [CRTC:26:pipe A]
>[   92.554726] [drm:drm_atomic_check_only] checking ffff978ee5652800
>[   92.554731] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   92.554734] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   92.554736] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   92.554738] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[   92.554740] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5652800
>[   92.554744] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5652800
>[   92.554747] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   92.554749] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   92.554756] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   92.554761] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   92.554770] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   92.554774] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   92.554776] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   92.554780] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5655800 for pipe A
>[   92.554782] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   92.554784] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   92.554787] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   92.554790] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   92.554792] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   92.554794] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   92.554796] [drm:intel_dump_pipe_config] requested mode:
>[   92.554801] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   92.554802] [drm:intel_dump_pipe_config] adjusted mode:
>[   92.554806] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   92.554810] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   92.554811] [drm:intel_dump_pipe_config] port clock: 540000
>[   92.554813] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   92.554816] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   92.554818] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   92.554820] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   92.554822] [drm:intel_dump_pipe_config] ips: 0
>[   92.554824] [drm:intel_dump_pipe_config] double wide: 0
>[   92.554826] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   92.554828] [drm:intel_dump_pipe_config] planes on this crtc
>[   92.554831] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   92.554834] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   92.554837] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   92.554839] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   92.554842] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   92.554847] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5657000 state to ffff978ee5652800
>[   92.554850] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5656800 state to ffff978ee5652800
>[   92.554852] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[   92.554858] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   92.554860] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[   92.554863] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[   92.554867] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   92.554870] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   92.554874] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   92.554884] [drm:drm_atomic_commit] commiting ffff978ee5652800
>[   92.554895] [drm:intel_power_well_enable] enabling DDI A/E power well
>[   92.554900] [drm:skl_set_power_well] Enabling DDI A/E power well
>[   92.554906] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[   92.556696] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   92.556700] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   92.556703] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   92.556707] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   92.556710] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   92.556713] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   92.556716] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   92.556719] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   92.556722] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   92.556725] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   92.556727] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   92.556731] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   92.556733] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   92.556736] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   92.556739] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   92.556743] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   92.556746] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   92.556749] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   92.556754] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[   92.556756] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[   92.556770] [drm:edp_panel_on] Turn eDP port A panel power on
>[   92.556789] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   92.556865] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[   92.556883] [drm:wait_panel_status] Wait complete
>[   92.556917] [drm:edp_panel_on] Wait for panel power on
>[   92.556992] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[   92.757096] [drm:wait_panel_status] Wait complete
>[   92.758236] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   92.758238] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   92.758239] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   92.758242] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[   92.758912] [drm:intel_dp_start_link_train] clock recovery OK
>[   92.758915] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[   92.758917] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[   92.759891] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[   92.759893] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   92.759894] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   92.760853] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[   92.761026] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5655800
>[   92.761124] [drm:intel_enable_pipe] enabling pipe A
>[   92.761133] [drm:intel_edp_backlight_on.part.29] 
>[   92.761137] [drm:intel_panel_enable_backlight] pipe A
>[   92.761218] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   92.761274] [drm:intel_psr_enable] PSR disable by flag
>[   92.761275] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   92.778071] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   92.778081] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   92.778101] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   92.778111] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5652800
>[   92.778117] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5652800
>[   92.778149] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d000
>[   92.778154] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8e000 state to ffff978ee5d8d000
>[   92.778156] [drm:drm_atomic_check_only] checking ffff978ee5d8d000
>[   92.778166] [drm:drm_atomic_commit] commiting ffff978ee5d8d000
>[   92.794739] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d000
>[   92.794745] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d000
>[   92.794780] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[   92.794784] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   92.794926] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d000
>[   92.794930] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee6330300 state to ffff978ee5d8d000
>[   92.794934] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d88000 state to ffff978ee5d8d000
>[   92.794937] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee6330300 to [CRTC:26:pipe A]
>[   92.794939] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee6330300
>[   92.794941] [drm:drm_atomic_check_only] checking ffff978ee5d8d000
>[   92.794949] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   92.794952] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[   92.794962] [drm:drm_atomic_commit] commiting ffff978ee5d8d000
>[   92.794993] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d000
>[   92.794997] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d000
>[   92.912496] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f800
>[   92.912501] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8e000 state to ffff978ee5d8f800
>[   92.912504] [drm:drm_atomic_check_only] checking ffff978ee5d8f800
>[   92.912507] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   92.912508] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[   92.912510] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8f800
>[   92.912512] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656c9a0 state to ffff978ee5d8f800
>[   92.912515] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee5a00240 state to ffff978ee5d8f800
>[   92.912516] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee5a00180 state to ffff978ee5d8f800
>[   92.912518] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8f800
>[   92.912521] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   92.912522] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   92.912528] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   92.912531] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   92.912537] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   92.912539] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   92.912541] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   92.912543] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d8e000 for pipe A
>[   92.912544] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   92.912546] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   92.912547] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   92.912549] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   92.912550] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   92.912551] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   92.912552] [drm:intel_dump_pipe_config] requested mode:
>[   92.912556] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   92.912557] [drm:intel_dump_pipe_config] adjusted mode:
>[   92.912559] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   92.912561] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   92.912562] [drm:intel_dump_pipe_config] port clock: 540000
>[   92.912563] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   92.912564] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   92.912566] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   92.912567] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   92.912568] [drm:intel_dump_pipe_config] ips: 0
>[   92.912569] [drm:intel_dump_pipe_config] double wide: 0
>[   92.912570] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   92.912571] [drm:intel_dump_pipe_config] planes on this crtc
>[   92.912573] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   92.912575] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   92.912577] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   92.912578] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[   92.912580] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[   92.912581] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[   92.912583] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   92.912586] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d8f000 state to ffff978ee5d8f800
>[   92.912588] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5d8d800 state to ffff978ee5d8f800
>[   92.912589] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[   92.912595] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   92.912596] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[   92.912598] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[   92.912599] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   92.912601] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[   92.912604] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   92.912605] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   92.912608] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   92.912613] [drm:drm_atomic_commit] commiting ffff978ee5d8f800
>[   92.913758] [drm:intel_edp_backlight_off.part.30] 
>[   93.122763] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   93.122818] [drm:intel_disable_pipe] disabling pipe A
>[   93.129219] [drm:edp_panel_off] Turn eDP port A panel power off
>[   93.129257] [drm:edp_panel_off] Wait for panel power off time
>[   93.129333] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[   93.129954] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[   93.129959] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[   93.129982] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[   93.179938] [drm:wait_panel_status] Wait complete
>[   93.179952] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[   93.179957] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[   93.179975] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[   93.180016] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   93.180033] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   93.181702] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   93.181707] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   93.181709] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[   93.184357] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   93.184362] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   93.184366] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   93.184371] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   93.184374] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   93.184376] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   93.184379] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   93.184381] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   93.184384] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   93.184386] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   93.184389] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   93.184392] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   93.184394] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   93.184396] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   93.184399] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   93.184403] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   93.184406] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   93.184408] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   93.184416] [drm:intel_power_well_disable] disabling DDI A/E power well
>[   93.184420] [drm:skl_set_power_well] Disabling DDI A/E power well
>[   93.184424] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   93.184428] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   93.184431] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   93.184440] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f800
>[   93.184445] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f800
>[   93.747240] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000
>[   93.758305] [drm:wait_panel_status] Wait complete
>[   93.758368] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[   93.758385] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[   93.807784] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   93.807790] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   93.807793] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[   93.963478] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[   93.964603] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   94.188800] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d000
>[   94.188805] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee671ed80 state to ffff978ee5d8d000
>[   94.188810] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f800 state to ffff978ee5d8d000
>[   94.188812] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee671ed80 to [NOCRTC]
>[   94.188815] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee671ed80
>[   94.188817] [drm:drm_atomic_check_only] checking ffff978ee5d8d000
>[   94.188828] [drm:drm_atomic_commit] commiting ffff978ee5d8d000
>[   94.188837] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d000
>[   94.188840] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d000
>[   94.188850] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   94.188854] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[   94.188857] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d000
>[   94.188860] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8e000 state to ffff978ee5d8d000
>[   94.188862] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee671ec00 state to ffff978ee5d8d000
>[   94.188866] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5d8e000
>[   94.188868] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee671ec00 to [CRTC:26:pipe A]
>[   94.188870] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffff978ee671ec00
>[   94.188873] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d000
>[   94.188876] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656cf80 state to ffff978ee5d8d000
>[   94.188880] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978ee656cf80 to [NOCRTC]
>[   94.188882] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978ee656cf80 to [CRTC:26:pipe A]
>[   94.188884] [drm:drm_atomic_check_only] checking ffff978ee5d8d000
>[   94.188889] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   94.188891] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   94.188893] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   94.188895] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[   94.188898] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d000
>[   94.188901] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d000
>[   94.188904] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   94.188906] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   94.188913] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   94.188917] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   94.188926] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   94.188929] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   94.188931] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   94.188935] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d8e000 for pipe A
>[   94.188937] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   94.188939] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   94.188941] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   94.188944] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   94.188946] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   94.188948] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   94.188950] [drm:intel_dump_pipe_config] requested mode:
>[   94.188954] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   94.188956] [drm:intel_dump_pipe_config] adjusted mode:
>[   94.188959] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   94.188962] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   94.188964] [drm:intel_dump_pipe_config] port clock: 540000
>[   94.188966] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   94.188968] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   94.188970] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   94.188972] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   94.188974] [drm:intel_dump_pipe_config] ips: 0
>[   94.188976] [drm:intel_dump_pipe_config] double wide: 0
>[   94.188978] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   94.188979] [drm:intel_dump_pipe_config] planes on this crtc
>[   94.188982] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   94.188985] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   94.188988] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   94.188990] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   94.188992] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   94.188998] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5279800 state to ffff978ee5d8d000
>[   94.189000] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee527b800 state to ffff978ee5d8d000
>[   94.189002] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[   94.189008] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   94.189010] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[   94.189013] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[   94.189017] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   94.189019] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   94.189023] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   94.189033] [drm:drm_atomic_commit] commiting ffff978ee5d8d000
>[   94.189043] [drm:intel_power_well_enable] enabling DDI A/E power well
>[   94.189048] [drm:skl_set_power_well] Enabling DDI A/E power well
>[   94.189053] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[   94.190734] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   94.190737] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   94.190740] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   94.190744] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   94.190747] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   94.190749] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   94.190752] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   94.190755] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   94.190758] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   94.190760] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   94.190763] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   94.190766] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   94.190768] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   94.190771] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   94.190773] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   94.190777] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   94.190780] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   94.190783] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   94.190788] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[   94.190790] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[   94.190802] [drm:edp_panel_on] Turn eDP port A panel power on
>[   94.190821] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   94.190897] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[   94.190915] [drm:wait_panel_status] Wait complete
>[   94.190948] [drm:edp_panel_on] Wait for panel power on
>[   94.191023] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[   94.392964] [drm:wait_panel_status] Wait complete
>[   94.394119] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   94.394122] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   94.394123] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   94.394126] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[   94.394796] [drm:intel_dp_start_link_train] clock recovery OK
>[   94.394799] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[   94.394800] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[   94.395771] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[   94.395773] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   94.395774] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   94.396733] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[   94.396905] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5d8e000
>[   94.397004] [drm:intel_enable_pipe] enabling pipe A
>[   94.397013] [drm:intel_edp_backlight_on.part.29] 
>[   94.397017] [drm:intel_panel_enable_backlight] pipe A
>[   94.397098] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   94.397154] [drm:intel_psr_enable] PSR disable by flag
>[   94.397155] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   94.413955] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   94.413966] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   94.413986] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   94.413996] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d000
>[   94.414002] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d000
>[   94.414034] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d000
>[   94.414038] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d800 state to ffff978ee5d8d000
>[   94.414041] [drm:drm_atomic_check_only] checking ffff978ee5d8d000
>[   94.414050] [drm:drm_atomic_commit] commiting ffff978ee5d8d000
>[   94.430532] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d000
>[   94.430537] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d000
>[   94.430573] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[   94.430577] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   94.430748] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d000
>[   94.430754] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee671e840 state to ffff978ee5d8d000
>[   94.430759] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8e000 state to ffff978ee5d8d000
>[   94.430763] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee671e840 to [CRTC:26:pipe A]
>[   94.430766] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee671e840
>[   94.430769] [drm:drm_atomic_check_only] checking ffff978ee5d8d000
>[   94.430778] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   94.430781] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[   94.430795] [drm:drm_atomic_commit] commiting ffff978ee5d8d000
>[   94.430829] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d000
>[   94.430833] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d000
>[   94.548997] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f000
>[   94.549002] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f800 state to ffff978ee5d8f000
>[   94.549005] [drm:drm_atomic_check_only] checking ffff978ee5d8f000
>[   94.549008] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   94.549010] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[   94.549013] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8f000
>[   94.549016] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656c4a0 state to ffff978ee5d8f000
>[   94.549019] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee87000c0 state to ffff978ee5d8f000
>[   94.549021] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee8700300 state to ffff978ee5d8f000
>[   94.549024] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8f000
>[   94.549027] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   94.549028] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   94.549035] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   94.549039] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   94.549046] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   94.549048] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   94.549050] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   94.549053] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d8f800 for pipe A
>[   94.549055] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   94.549057] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   94.549059] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   94.549061] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   94.549063] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   94.549065] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   94.549066] [drm:intel_dump_pipe_config] requested mode:
>[   94.549070] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   94.549072] [drm:intel_dump_pipe_config] adjusted mode:
>[   94.549075] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   94.549077] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   94.549079] [drm:intel_dump_pipe_config] port clock: 540000
>[   94.549080] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   94.549082] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   94.549084] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   94.549086] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   94.549087] [drm:intel_dump_pipe_config] ips: 0
>[   94.549088] [drm:intel_dump_pipe_config] double wide: 0
>[   94.549090] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   94.549091] [drm:intel_dump_pipe_config] planes on this crtc
>[   94.549094] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   94.549096] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   94.549098] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   94.549101] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[   94.549102] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[   94.549105] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[   94.549107] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   94.549111] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d8d800 state to ffff978ee5d8f000
>[   94.549113] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5d88000 state to ffff978ee5d8f000
>[   94.549115] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[   94.549121] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   94.549123] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[   94.549124] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[   94.549129] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   94.549130] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[   94.549141] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   94.549143] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   94.549146] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   94.549153] [drm:drm_atomic_commit] commiting ffff978ee5d8f000
>[   94.550779] [drm:intel_edp_backlight_off.part.30] 
>[   94.754853] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   94.754909] [drm:intel_disable_pipe] disabling pipe A
>[   94.765805] [drm:edp_panel_off] Turn eDP port A panel power off
>[   94.765845] [drm:edp_panel_off] Wait for panel power off time
>[   94.765923] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[   94.766419] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[   94.766424] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[   94.766438] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[   94.816629] [drm:wait_panel_status] Wait complete
>[   94.816645] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[   94.816665] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   94.816668] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[   94.816685] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   94.816701] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[   94.818326] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   94.818332] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   94.818335] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[   94.818952] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   94.818959] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   94.818963] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   94.818968] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   94.818972] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   94.818974] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   94.818977] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   94.818981] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   94.818983] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   94.818986] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   94.818989] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   94.818992] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   94.818995] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   94.818998] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   94.819001] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   94.819005] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   94.819008] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   94.819011] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   94.819020] [drm:intel_power_well_disable] disabling DDI A/E power well
>[   94.819024] [drm:skl_set_power_well] Disabling DDI A/E power well
>[   94.819029] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   94.819033] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   94.819037] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   94.819046] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f000
>[   94.819052] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f000
>[   95.411035] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[   95.411055] [drm:wait_panel_status] Wait complete
>[   95.411110] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[   95.411124] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[   95.470011] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   95.470017] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   95.470020] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[   95.504871] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5653000
>[   95.504877] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee8752780 state to ffff978ee5653000
>[   95.504881] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5654800 state to ffff978ee5653000
>[   95.504883] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee8752780 to [NOCRTC]
>[   95.504886] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee8752780
>[   95.504888] [drm:drm_atomic_check_only] checking ffff978ee5653000
>[   95.504898] [drm:drm_atomic_commit] commiting ffff978ee5653000
>[   95.504908] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5653000
>[   95.504912] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5653000
>[   95.504922] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   95.504927] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[   95.504930] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5653000
>[   95.504933] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5652000 state to ffff978ee5653000
>[   95.504936] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee87529c0 state to ffff978ee5653000
>[   95.504939] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5652000
>[   95.504941] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee87529c0 to [CRTC:26:pipe A]
>[   95.504943] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffff978ee87529c0
>[   95.504946] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5653000
>[   95.504949] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2cdc0 state to ffff978ee5653000
>[   95.504953] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2cdc0 to [NOCRTC]
>[   95.504955] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2cdc0 to [CRTC:26:pipe A]
>[   95.504957] [drm:drm_atomic_check_only] checking ffff978ee5653000
>[   95.504962] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   95.504964] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   95.504966] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   95.504968] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[   95.504970] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5653000
>[   95.504974] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5653000
>[   95.504977] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   95.504979] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   95.504986] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   95.504990] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   95.504999] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   95.505002] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   95.505004] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   95.505008] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5652000 for pipe A
>[   95.505010] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   95.505012] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   95.505014] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   95.505017] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   95.505019] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   95.505021] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   95.505023] [drm:intel_dump_pipe_config] requested mode:
>[   95.505027] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   95.505029] [drm:intel_dump_pipe_config] adjusted mode:
>[   95.505033] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   95.505036] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   95.505037] [drm:intel_dump_pipe_config] port clock: 540000
>[   95.505039] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   95.505041] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   95.505043] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   95.505046] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   95.505047] [drm:intel_dump_pipe_config] ips: 0
>[   95.505049] [drm:intel_dump_pipe_config] double wide: 0
>[   95.505051] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   95.505052] [drm:intel_dump_pipe_config] planes on this crtc
>[   95.505056] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   95.505058] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   95.505061] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   95.505063] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   95.505066] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   95.505070] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5654000 state to ffff978ee5653000
>[   95.505073] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5651000 state to ffff978ee5653000
>[   95.505075] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[   95.505081] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   95.505083] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[   95.505086] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[   95.505090] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   95.505093] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   95.505096] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   95.505106] [drm:drm_atomic_commit] commiting ffff978ee5653000
>[   95.505117] [drm:intel_power_well_enable] enabling DDI A/E power well
>[   95.505122] [drm:skl_set_power_well] Enabling DDI A/E power well
>[   95.505128] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[   95.507368] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   95.507372] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   95.507375] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   95.507378] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   95.507381] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   95.507384] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   95.507386] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   95.507389] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   95.507392] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   95.507394] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   95.507397] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   95.507400] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   95.507402] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   95.507405] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   95.507407] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   95.507411] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   95.507414] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   95.507417] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   95.507422] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[   95.507424] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[   95.619502] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[   95.619508] [drm:edp_panel_on] Turn eDP port A panel power on
>[   95.619527] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   95.619607] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[   95.619624] [drm:wait_panel_status] Wait complete
>[   95.619658] [drm:edp_panel_on] Wait for panel power on
>[   95.619747] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[   95.820043] [drm:wait_panel_status] Wait complete
>[   95.821936] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   95.821941] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   95.821943] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   95.821947] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[   95.822637] [drm:intel_dp_start_link_train] clock recovery OK
>[   95.822640] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[   95.822643] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[   95.823620] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[   95.823621] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   95.823623] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   95.824587] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[   95.824763] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5652000
>[   95.824869] [drm:intel_enable_pipe] enabling pipe A
>[   95.824880] [drm:intel_edp_backlight_on.part.29] 
>[   95.824884] [drm:intel_panel_enable_backlight] pipe A
>[   95.824966] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   95.825022] [drm:intel_psr_enable] PSR disable by flag
>[   95.825024] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   95.841818] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   95.841825] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   95.841840] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   95.841846] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5653000
>[   95.841850] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5653000
>[   95.842241] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   95.842242] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d88000
>[   95.842246] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d800 state to ffff978ee5d88000
>[   95.842248] [drm:drm_atomic_check_only] checking ffff978ee5d88000
>[   95.842255] [drm:drm_atomic_commit] commiting ffff978ee5d88000
>[   95.858440] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d88000
>[   95.858444] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d88000
>[   95.858466] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[   95.858469] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   95.858654] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d88000
>[   95.858659] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978eeac9fe40 state to ffff978ee5d88000
>[   95.858663] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d000 state to ffff978ee5d88000
>[   95.858665] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eeac9fe40 to [CRTC:26:pipe A]
>[   95.858666] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978eeac9fe40
>[   95.858668] [drm:drm_atomic_check_only] checking ffff978ee5d88000
>[   95.858675] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   95.858677] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[   95.858686] [drm:drm_atomic_commit] commiting ffff978ee5d88000
>[   95.858734] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d88000
>[   95.858737] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d88000
>[   95.976954] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88db800
>[   95.976958] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee88de000 state to ffff978ee88db800
>[   95.976961] [drm:drm_atomic_check_only] checking ffff978ee88db800
>[   95.976965] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   95.976967] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[   95.976969] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88db800
>[   95.976972] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebbb2180 state to ffff978ee88db800
>[   95.976975] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee97d1300 state to ffff978ee88db800
>[   95.976978] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee97d1a80 state to ffff978ee88db800
>[   95.976981] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88db800
>[   95.976984] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   95.976985] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   95.976992] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   95.976996] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   95.977004] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   95.977006] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   95.977009] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   95.977012] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee88de000 for pipe A
>[   95.977014] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   95.977015] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   95.977018] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   95.977020] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   95.977022] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   95.977024] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   95.977025] [drm:intel_dump_pipe_config] requested mode:
>[   95.977029] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   95.977031] [drm:intel_dump_pipe_config] adjusted mode:
>[   95.977034] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   95.977037] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   95.977038] [drm:intel_dump_pipe_config] port clock: 540000
>[   95.977040] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   95.977042] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   95.977044] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   95.977045] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   95.977047] [drm:intel_dump_pipe_config] ips: 0
>[   95.977048] [drm:intel_dump_pipe_config] double wide: 0
>[   95.977050] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   95.977051] [drm:intel_dump_pipe_config] planes on this crtc
>[   95.977054] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   95.977056] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   95.977059] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   95.977061] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[   95.977063] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[   95.977065] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[   95.977067] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   95.977071] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee88d9000 state to ffff978ee88db800
>[   95.977074] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee88db000 state to ffff978ee88db800
>[   95.977075] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[   95.977080] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   95.977082] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   95.977084] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[   95.977087] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   95.977089] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[   95.977092] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   95.977095] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   95.977098] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   95.977105] [drm:drm_atomic_commit] commiting ffff978ee88db800
>[   95.978778] [drm:intel_edp_backlight_off.part.30] 
>[   96.186878] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   96.186935] [drm:intel_disable_pipe] disabling pipe A
>[   96.193561] [drm:edp_panel_off] Turn eDP port A panel power off
>[   96.193601] [drm:edp_panel_off] Wait for panel power off time
>[   96.193678] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[   96.194264] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[   96.194269] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[   96.194293] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[   96.244487] [drm:wait_panel_status] Wait complete
>[   96.244503] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[   96.244509] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[   96.244528] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[   96.244574] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   96.244593] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   96.246046] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   96.246052] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   96.246055] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[   96.246881] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   96.246888] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   96.246892] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   96.246898] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   96.246902] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   96.246905] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   96.246908] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   96.246911] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   96.246914] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   96.246917] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   96.246920] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   96.246924] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   96.246927] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   96.246930] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   96.246933] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   96.246938] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   96.246941] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   96.246945] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   96.246954] [drm:intel_power_well_disable] disabling DDI A/E power well
>[   96.246959] [drm:skl_set_power_well] Disabling DDI A/E power well
>[   96.246963] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   96.246968] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   96.246972] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   96.246982] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee88db800
>[   96.246989] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee88db800
>[   96.247092] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88db800
>[   96.247096] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee97d1e40 state to ffff978ee88db800
>[   96.247099] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee88dc000 state to ffff978ee88db800
>[   96.247102] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee97d1e40 to [NOCRTC]
>[   96.247104] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee97d1e40
>[   96.247107] [drm:drm_atomic_check_only] checking ffff978ee88db800
>[   96.247116] [drm:drm_atomic_commit] commiting ffff978ee88db800
>[   96.247124] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee88db800
>[   96.247128] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee88db800
>[   96.247137] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   96.247143] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[   96.247145] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88db800
>[   96.247148] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee88de000 state to ffff978ee88db800
>[   96.247151] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee97d1a80 state to ffff978ee88db800
>[   96.247154] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee88de000
>[   96.247157] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee97d1a80 to [CRTC:26:pipe A]
>[   96.247159] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffff978ee97d1a80
>[   96.247162] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88db800
>[   96.247165] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebbb23a0 state to ffff978ee88db800
>[   96.247168] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebbb23a0 to [NOCRTC]
>[   96.247171] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebbb23a0 to [CRTC:26:pipe A]
>[   96.247173] [drm:drm_atomic_check_only] checking ffff978ee88db800
>[   96.247177] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   96.247180] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   96.247182] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   96.247184] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[   96.247187] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88db800
>[   96.247190] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88db800
>[   96.247193] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   96.247195] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   96.247202] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   96.247208] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   96.247216] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   96.247220] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   96.247222] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   96.247226] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee88de000 for pipe A
>[   96.247228] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   96.247230] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   96.247233] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   96.247235] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   96.247238] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   96.247240] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   96.247242] [drm:intel_dump_pipe_config] requested mode:
>[   96.247247] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   96.247249] [drm:intel_dump_pipe_config] adjusted mode:
>[   96.247253] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   96.247256] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   96.247258] [drm:intel_dump_pipe_config] port clock: 540000
>[   96.247260] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   96.247262] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   96.247264] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   96.247267] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   96.247269] [drm:intel_dump_pipe_config] ips: 0
>[   96.247270] [drm:intel_dump_pipe_config] double wide: 0
>[   96.247273] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   96.247274] [drm:intel_dump_pipe_config] planes on this crtc
>[   96.247277] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   96.247281] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   96.247284] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   96.247286] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   96.247288] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   96.247293] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee88d8000 state to ffff978ee88db800
>[   96.247296] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee88dd000 state to ffff978ee88db800
>[   96.247298] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[   96.247304] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   96.247307] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   96.247309] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[   96.247314] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   96.247316] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   96.247320] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   96.247331] [drm:drm_atomic_commit] commiting ffff978ee88db800
>[   96.247340] [drm:intel_power_well_enable] enabling DDI A/E power well
>[   96.247343] [drm:skl_set_power_well] Enabling DDI A/E power well
>[   96.247350] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[   96.247473] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   96.247477] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   96.247480] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   96.247484] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   96.247487] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   96.247490] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   96.247493] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   96.247496] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   96.247499] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   96.247502] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   96.247505] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   96.247508] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   96.247511] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   96.247514] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   96.247517] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   96.247521] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   96.247524] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   96.247527] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   96.247532] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[   96.247534] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[   96.818907] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000
>[   96.821159] [drm:wait_panel_status] Wait complete
>[   96.821221] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[   96.821238] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[   96.870630] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   96.870636] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   96.870639] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[   97.027261] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[   97.027267] [drm:edp_panel_on] Turn eDP port A panel power on
>[   97.027277] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   97.027335] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[   97.027346] [drm:wait_panel_status] Wait complete
>[   97.027370] [drm:edp_panel_on] Wait for panel power on
>[   97.027426] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 0000000b
>[   97.227908] [drm:wait_panel_status] Wait complete
>[   97.229783] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   97.229786] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   97.229787] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   97.229791] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[   97.230461] [drm:intel_dp_start_link_train] clock recovery OK
>[   97.230465] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[   97.230466] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[   97.231438] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[   97.231440] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   97.231441] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   97.232402] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[   97.232575] [drm:skylake_pfit_enable] for crtc_state = ffff978ee88de000
>[   97.232677] [drm:intel_enable_pipe] enabling pipe A
>[   97.232687] [drm:intel_edp_backlight_on.part.29] 
>[   97.232690] [drm:intel_panel_enable_backlight] pipe A
>[   97.232754] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   97.232810] [drm:intel_psr_enable] PSR disable by flag
>[   97.232812] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   97.249625] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   97.249637] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   97.249658] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   97.249668] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee88db800
>[   97.249674] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee88db800
>[   97.250098] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   97.250101] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d800
>[   97.250107] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f000 state to ffff978ee5d8d800
>[   97.250110] [drm:drm_atomic_check_only] checking ffff978ee5d8d800
>[   97.250121] [drm:drm_atomic_commit] commiting ffff978ee5d8d800
>[   97.266258] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d800
>[   97.266264] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d800
>[   97.266300] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[   97.266304] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   97.266498] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d800
>[   97.266503] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee671e300 state to ffff978ee5d8d800
>[   97.266507] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8e000 state to ffff978ee5d8d800
>[   97.266509] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee671e300 to [CRTC:26:pipe A]
>[   97.266512] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee671e300
>[   97.266514] [drm:drm_atomic_check_only] checking ffff978ee5d8d800
>[   97.266523] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   97.266525] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[   97.266537] [drm:drm_atomic_commit] commiting ffff978ee5d8d800
>[   97.266566] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d800
>[   97.266570] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d800
>[   98.391829] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88df000
>[   98.391834] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee88de800 state to ffff978ee88df000
>[   98.391837] [drm:drm_atomic_check_only] checking ffff978ee88df000
>[   98.391840] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   98.391842] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[   98.391844] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88df000
>[   98.391846] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebbb21c0 state to ffff978ee88df000
>[   98.391849] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee5d13cc0 state to ffff978ee88df000
>[   98.391851] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee5d13d80 state to ffff978ee88df000
>[   98.391853] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88df000
>[   98.391856] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   98.391857] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   98.391863] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   98.391867] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   98.391874] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   98.391876] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   98.391878] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   98.391881] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee88de800 for pipe A
>[   98.391883] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   98.391884] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   98.391886] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   98.391888] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   98.391889] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   98.391891] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   98.391892] [drm:intel_dump_pipe_config] requested mode:
>[   98.391895] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   98.391896] [drm:intel_dump_pipe_config] adjusted mode:
>[   98.391899] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   98.391901] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   98.391902] [drm:intel_dump_pipe_config] port clock: 540000
>[   98.391903] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   98.391905] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   98.391907] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   98.391908] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   98.391909] [drm:intel_dump_pipe_config] ips: 0
>[   98.391910] [drm:intel_dump_pipe_config] double wide: 0
>[   98.391912] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   98.391913] [drm:intel_dump_pipe_config] planes on this crtc
>[   98.391915] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   98.391917] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   98.391919] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   98.391921] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[   98.391922] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[   98.391924] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[   98.391926] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   98.391930] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee88da000 state to ffff978ee88df000
>[   98.391932] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee88de000 state to ffff978ee88df000
>[   98.391933] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[   98.391938] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   98.391940] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   98.391942] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[   98.391944] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   98.391945] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[   98.391949] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   98.391950] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   98.392028] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   98.392035] [drm:drm_atomic_commit] commiting ffff978ee88df000
>[   98.393874] [drm:intel_edp_backlight_off.part.30] 
>[   98.602919] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   98.602977] [drm:intel_disable_pipe] disabling pipe A
>[   98.618334] [drm:edp_panel_off] Turn eDP port A panel power off
>[   98.618373] [drm:edp_panel_off] Wait for panel power off time
>[   98.618451] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000000
>[   98.619053] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[   98.619059] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[   98.619083] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[   98.669100] [drm:wait_panel_status] Wait complete
>[   98.669114] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[   98.669120] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[   98.669138] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[   98.669181] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[   98.669199] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   98.670865] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   98.670871] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   98.670874] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[   98.675804] [drm:skl_pcode_request] PCODE timeout, retrying with preemption disabled
>[   98.678059] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   98.678065] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   98.678069] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   98.678075] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   98.678078] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   98.678081] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   98.678084] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   98.678087] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   98.678090] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   98.678092] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   98.678095] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   98.678098] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   98.678101] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   98.678104] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   98.678107] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   98.678111] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   98.678114] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   98.678117] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   98.678127] [drm:intel_power_well_disable] disabling DDI A/E power well
>[   98.678131] [drm:skl_set_power_well] Disabling DDI A/E power well
>[   98.678135] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   98.678139] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   98.678143] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   98.678153] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee88df000
>[   98.678159] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee88df000
>[   98.678264] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88df000
>[   98.678268] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee5d13b40 state to ffff978ee88df000
>[   98.678271] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee88dd000 state to ffff978ee88df000
>[   98.678274] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5d13b40 to [NOCRTC]
>[   98.678276] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee5d13b40
>[   98.678278] [drm:drm_atomic_check_only] checking ffff978ee88df000
>[   98.678287] [drm:drm_atomic_commit] commiting ffff978ee88df000
>[   98.678295] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee88df000
>[   98.678297] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee88df000
>[   98.678306] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[   98.678312] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[   98.678314] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88df000
>[   98.678317] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee88de800 state to ffff978ee88df000
>[   98.678319] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee5d13d80 state to ffff978ee88df000
>[   98.678322] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee88de800
>[   98.678325] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5d13d80 to [CRTC:26:pipe A]
>[   98.678327] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffff978ee5d13d80
>[   98.678330] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88df000
>[   98.678333] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebbb23a0 state to ffff978ee88df000
>[   98.678335] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebbb23a0 to [NOCRTC]
>[   98.678338] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebbb23a0 to [CRTC:26:pipe A]
>[   98.678340] [drm:drm_atomic_check_only] checking ffff978ee88df000
>[   98.678344] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[   98.678347] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[   98.678349] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[   98.678351] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[   98.678353] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88df000
>[   98.678357] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88df000
>[   98.678359] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[   98.678361] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[   98.678368] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   98.678372] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[   98.678381] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[   98.678384] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[   98.678386] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[   98.678389] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee88de800 for pipe A
>[   98.678392] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[   98.678393] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[   98.678396] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   98.678399] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[   98.678401] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   98.678403] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   98.678405] [drm:intel_dump_pipe_config] requested mode:
>[   98.678409] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[   98.678411] [drm:intel_dump_pipe_config] adjusted mode:
>[   98.678414] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[   98.678417] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[   98.678419] [drm:intel_dump_pipe_config] port clock: 540000
>[   98.678421] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[   98.678423] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[   98.678425] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   98.678427] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   98.678429] [drm:intel_dump_pipe_config] ips: 0
>[   98.678430] [drm:intel_dump_pipe_config] double wide: 0
>[   98.678432] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[   98.678434] [drm:intel_dump_pipe_config] planes on this crtc
>[   98.678437] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[   98.678440] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[   98.678443] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[   98.678445] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[   98.678447] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[   98.678451] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee88d8000 state to ffff978ee88df000
>[   98.678454] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee88db800 state to ffff978ee88df000
>[   98.678456] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[   98.678463] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[   98.678465] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[   98.678467] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[   98.678472] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[   98.678474] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[   98.678478] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[   98.678487] [drm:drm_atomic_commit] commiting ffff978ee88df000
>[   98.678496] [drm:intel_power_well_enable] enabling DDI A/E power well
>[   98.678499] [drm:skl_set_power_well] Enabling DDI A/E power well
>[   98.678505] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[   98.680683] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[   98.680690] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[   98.680694] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[   98.680699] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[   98.680702] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[   98.680705] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[   98.680708] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[   98.680712] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[   98.680715] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[   98.680717] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[   98.680720] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[   98.680724] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[   98.680726] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[   98.680729] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[   98.680732] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   98.680745] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[   98.680748] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[   98.680751] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[   98.680758] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[   98.680760] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[   99.251150] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[   99.251170] [drm:wait_panel_status] Wait complete
>[   99.251226] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[   99.251239] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[   99.300659] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[   99.300665] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[   99.300669] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[   99.459524] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[   99.459530] [drm:edp_panel_on] Turn eDP port A panel power on
>[   99.459550] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   99.459632] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[   99.459650] [drm:wait_panel_status] Wait complete
>[   99.459684] [drm:edp_panel_on] Wait for panel power on
>[   99.459773] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[   99.660723] [drm:wait_panel_status] Wait complete
>[   99.662601] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   99.662604] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[   99.662606] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[   99.662609] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[   99.663282] [drm:intel_dp_start_link_train] clock recovery OK
>[   99.663285] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[   99.663286] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[   99.664258] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[   99.664260] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[   99.664262] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[   99.665223] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[   99.665397] [drm:skylake_pfit_enable] for crtc_state = ffff978ee88de800
>[   99.665498] [drm:intel_enable_pipe] enabling pipe A
>[   99.665508] [drm:intel_edp_backlight_on.part.29] 
>[   99.665512] [drm:intel_panel_enable_backlight] pipe A
>[   99.665594] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   99.665650] [drm:intel_psr_enable] PSR disable by flag
>[   99.665652] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[   99.682319] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[   99.682329] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[   99.682348] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[   99.682358] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee88df000
>[   99.682364] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee88df000
>[   99.682763] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[   99.682766] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f000
>[   99.682772] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8e000 state to ffff978ee5d8f000
>[   99.682775] [drm:drm_atomic_check_only] checking ffff978ee5d8f000
>[   99.682785] [drm:drm_atomic_commit] commiting ffff978ee5d8f000
>[   99.699031] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f000
>[   99.699037] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f000
>[   99.699073] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[   99.699077] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[   99.699245] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f000
>[   99.699250] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee97d3540 state to ffff978ee5d8f000
>[   99.699254] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d800 state to ffff978ee5d8f000
>[   99.699256] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee97d3540 to [CRTC:26:pipe A]
>[   99.699258] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee97d3540
>[   99.699260] [drm:drm_atomic_check_only] checking ffff978ee5d8f000
>[   99.699269] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[   99.699271] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[   99.699281] [drm:drm_atomic_commit] commiting ffff978ee5d8f000
>[   99.699313] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f000
>[   99.699316] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f000
>[  100.823384] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f800
>[  100.823389] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d88000 state to ffff978ee5d8f800
>[  100.823392] [drm:drm_atomic_check_only] checking ffff978ee5d8f800
>[  100.823395] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  100.823396] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[  100.823398] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8f800
>[  100.823399] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656ce00 state to ffff978ee5d8f800
>[  100.823402] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee8700f00 state to ffff978ee5d8f800
>[  100.823403] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee8700540 state to ffff978ee5d8f800
>[  100.823405] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8f800
>[  100.823407] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  100.823408] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  100.823437] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  100.823452] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  100.823465] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  100.823467] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  100.823469] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  100.823471] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d88000 for pipe A
>[  100.823473] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  100.823474] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  100.823475] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  100.823477] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  100.823478] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  100.823479] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  100.823480] [drm:intel_dump_pipe_config] requested mode:
>[  100.823483] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  100.823484] [drm:intel_dump_pipe_config] adjusted mode:
>[  100.823486] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  100.823488] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  100.823489] [drm:intel_dump_pipe_config] port clock: 540000
>[  100.823490] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  100.823492] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  100.823493] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  100.823494] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  100.823495] [drm:intel_dump_pipe_config] ips: 0
>[  100.823496] [drm:intel_dump_pipe_config] double wide: 0
>[  100.823498] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  100.823498] [drm:intel_dump_pipe_config] planes on this crtc
>[  100.823501] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  100.823502] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  100.823504] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  100.823506] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[  100.823507] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[  100.823509] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[  100.823510] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  100.823513] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d8d000 state to ffff978ee5d8f800
>[  100.823515] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5d8f000 state to ffff978ee5d8f800
>[  100.823516] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[  100.823521] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  100.823523] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[  100.823524] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  100.823526] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  100.823527] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[  100.823530] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  100.823532] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  100.823534] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  100.823540] [drm:drm_atomic_commit] commiting ffff978ee5d8f800
>[  100.824845] [drm:intel_edp_backlight_off.part.30] 
>[  101.026919] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  101.027009] [drm:intel_disable_pipe] disabling pipe A
>[  101.033473] [drm:edp_panel_off] Turn eDP port A panel power off
>[  101.033511] [drm:edp_panel_off] Wait for panel power off time
>[  101.033588] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[  101.034100] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[  101.034105] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[  101.034120] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[  101.084239] [drm:wait_panel_status] Wait complete
>[  101.084256] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[  101.084261] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[  101.084280] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[  101.084323] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  101.084341] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  101.085973] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  101.085979] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  101.085982] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[  101.088559] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  101.088564] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  101.088568] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  101.088573] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  101.088576] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  101.088578] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  101.088581] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  101.088584] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  101.088587] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  101.088589] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  101.088592] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  101.088595] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  101.088597] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  101.088600] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  101.088603] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  101.088607] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  101.088610] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  101.088613] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  101.088621] [drm:intel_power_well_disable] disabling DDI A/E power well
>[  101.088625] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  101.088629] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  101.088633] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  101.088637] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  101.088645] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f800
>[  101.088652] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f800
>[  101.683065] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[  101.683077] [drm:wait_panel_status] Wait complete
>[  101.683127] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  101.683141] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  101.736967] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  101.736973] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  101.736976] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[  101.891461] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[  101.892545] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  102.092995] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d800
>[  102.093001] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee87003c0 state to ffff978ee5d8d800
>[  102.093005] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8e000 state to ffff978ee5d8d800
>[  102.093007] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee87003c0 to [NOCRTC]
>[  102.093010] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee87003c0
>[  102.093012] [drm:drm_atomic_check_only] checking ffff978ee5d8d800
>[  102.093023] [drm:drm_atomic_commit] commiting ffff978ee5d8d800
>[  102.093033] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d800
>[  102.093036] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d800
>[  102.093046] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  102.093051] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[  102.093053] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d800
>[  102.093056] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d88000 state to ffff978ee5d8d800
>[  102.093059] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee8700540 state to ffff978ee5d8d800
>[  102.093062] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5d88000
>[  102.093064] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee8700540 to [CRTC:26:pipe A]
>[  102.093066] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffff978ee8700540
>[  102.093069] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[  102.093073] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656c9a0 state to ffff978ee5d8d800
>[  102.093076] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978ee656c9a0 to [NOCRTC]
>[  102.093078] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978ee656c9a0 to [CRTC:26:pipe A]
>[  102.093080] [drm:drm_atomic_check_only] checking ffff978ee5d8d800
>[  102.093085] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[  102.093087] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[  102.093089] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  102.093091] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[  102.093093] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[  102.093097] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[  102.093100] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  102.093102] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  102.093109] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  102.093114] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  102.093122] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  102.093125] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  102.093128] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  102.093131] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d88000 for pipe A
>[  102.093134] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  102.093135] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  102.093138] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  102.093141] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  102.093143] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  102.093145] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  102.093146] [drm:intel_dump_pipe_config] requested mode:
>[  102.093151] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  102.093152] [drm:intel_dump_pipe_config] adjusted mode:
>[  102.093156] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  102.093159] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  102.093161] [drm:intel_dump_pipe_config] port clock: 540000
>[  102.093162] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  102.093165] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  102.093167] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  102.093169] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  102.093171] [drm:intel_dump_pipe_config] ips: 0
>[  102.093172] [drm:intel_dump_pipe_config] double wide: 0
>[  102.093174] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  102.093176] [drm:intel_dump_pipe_config] planes on this crtc
>[  102.093179] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  102.093182] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  102.093185] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  102.093187] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  102.093189] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  102.093194] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d8f800 state to ffff978ee5d8d800
>[  102.093197] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee88b8800 state to ffff978ee5d8d800
>[  102.093199] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[  102.093205] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  102.093207] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[  102.093209] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[  102.093213] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  102.093216] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  102.093220] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  102.093230] [drm:drm_atomic_commit] commiting ffff978ee5d8d800
>[  102.093240] [drm:intel_power_well_enable] enabling DDI A/E power well
>[  102.093244] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  102.093250] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[  102.094797] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  102.094801] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  102.094804] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  102.094808] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  102.094811] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  102.094813] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  102.094816] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  102.094819] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  102.094822] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  102.094824] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  102.094827] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  102.094830] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  102.094832] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  102.094835] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  102.094838] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  102.094841] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  102.094844] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  102.094847] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  102.094852] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[  102.094854] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[  102.094867] [drm:edp_panel_on] Turn eDP port A panel power on
>[  102.094886] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  102.094962] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[  102.094976] [drm:wait_panel_status] Wait complete
>[  102.095009] [drm:edp_panel_on] Wait for panel power on
>[  102.095084] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[  102.296484] [drm:wait_panel_status] Wait complete
>[  102.297635] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  102.297637] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  102.297638] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  102.297641] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[  102.298311] [drm:intel_dp_start_link_train] clock recovery OK
>[  102.298314] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[  102.298316] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[  102.299286] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[  102.299287] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  102.299289] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  102.300248] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[  102.300420] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5d88000
>[  102.300518] [drm:intel_enable_pipe] enabling pipe A
>[  102.300528] [drm:intel_edp_backlight_on.part.29] 
>[  102.300532] [drm:intel_panel_enable_backlight] pipe A
>[  102.300613] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  102.300669] [drm:intel_psr_enable] PSR disable by flag
>[  102.300671] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  102.317566] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  102.317577] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  102.317597] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  102.317606] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d800
>[  102.317613] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d800
>[  102.317645] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88be800
>[  102.317650] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d800 state to ffff978ee88be800
>[  102.317652] [drm:drm_atomic_check_only] checking ffff978ee88be800
>[  102.317661] [drm:drm_atomic_commit] commiting ffff978ee88be800
>[  102.334227] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee88be800
>[  102.334232] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee88be800
>[  102.334268] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[  102.334271] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  102.334427] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d88000
>[  102.334433] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee8700f00 state to ffff978ee5d88000
>[  102.334438] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f000 state to ffff978ee5d88000
>[  102.334441] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee8700f00 to [CRTC:26:pipe A]
>[  102.334444] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee8700f00
>[  102.334446] [drm:drm_atomic_check_only] checking ffff978ee5d88000
>[  102.334455] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  102.334458] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[  102.334471] [drm:drm_atomic_commit] commiting ffff978ee5d88000
>[  102.334504] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d88000
>[  102.334507] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d88000
>[  102.455370] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d800
>[  102.455374] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d000 state to ffff978ee5d8d800
>[  102.455376] [drm:drm_atomic_check_only] checking ffff978ee5d8d800
>[  102.455379] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  102.455380] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[  102.455382] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[  102.455384] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656ce00 state to ffff978ee5d8d800
>[  102.455386] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee65af000 state to ffff978ee5d8d800
>[  102.455387] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee65af900 state to ffff978ee5d8d800
>[  102.455389] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[  102.455391] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  102.455392] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  102.455396] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  102.455399] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  102.455404] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  102.455406] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  102.455407] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  102.455409] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d8d000 for pipe A
>[  102.455410] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  102.455411] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  102.455413] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  102.455414] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  102.455415] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  102.455416] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  102.455417] [drm:intel_dump_pipe_config] requested mode:
>[  102.455427] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  102.455428] [drm:intel_dump_pipe_config] adjusted mode:
>[  102.455430] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  102.455431] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  102.455432] [drm:intel_dump_pipe_config] port clock: 540000
>[  102.455433] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  102.455434] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  102.455435] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  102.455439] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  102.455440] [drm:intel_dump_pipe_config] ips: 0
>[  102.455441] [drm:intel_dump_pipe_config] double wide: 0
>[  102.455442] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  102.455443] [drm:intel_dump_pipe_config] planes on this crtc
>[  102.455450] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  102.455452] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  102.455453] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  102.455454] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[  102.455455] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[  102.455457] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[  102.455460] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  102.455464] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d8e000 state to ffff978ee5d8d800
>[  102.455465] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5d88000 state to ffff978ee5d8d800
>[  102.455466] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[  102.455471] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  102.455472] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[  102.455473] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  102.455474] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  102.455475] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[  102.455478] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  102.455480] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  102.455481] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  102.455486] [drm:drm_atomic_commit] commiting ffff978ee5d8d800
>[  102.456849] [drm:intel_edp_backlight_off.part.30] 
>[  102.658935] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  102.658990] [drm:intel_disable_pipe] disabling pipe A
>[  102.667606] [drm:edp_panel_off] Turn eDP port A panel power off
>[  102.667631] [drm:edp_panel_off] Wait for panel power off time
>[  102.667688] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[  102.668353] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[  102.668358] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[  102.668381] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[  102.718513] [drm:wait_panel_status] Wait complete
>[  102.718531] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[  102.718549] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[  102.718554] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  102.718571] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  102.718587] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[  102.720089] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  102.720095] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  102.720098] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[  102.720823] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  102.720829] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  102.720834] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  102.720840] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  102.720843] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  102.720846] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  102.720849] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  102.720853] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  102.720856] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  102.720858] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  102.720862] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  102.720865] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  102.720868] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  102.720871] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  102.720874] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  102.720879] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  102.720882] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  102.720885] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  102.720895] [drm:intel_power_well_disable] disabling DDI A/E power well
>[  102.720900] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  102.720904] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  102.720909] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  102.720914] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  102.720923] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d800
>[  102.720930] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d800
>[  103.283172] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000
>[  103.296329] [drm:wait_panel_status] Wait complete
>[  103.296393] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  103.296410] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  103.345821] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  103.345827] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  103.345831] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[  103.499422] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[  103.500535] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  103.725706] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5654800
>[  103.725712] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee5d0e300 state to ffff978ee5654800
>[  103.725716] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5656800 state to ffff978ee5654800
>[  103.725719] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5d0e300 to [NOCRTC]
>[  103.725721] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee5d0e300
>[  103.725724] [drm:drm_atomic_check_only] checking ffff978ee5654800
>[  103.725735] [drm:drm_atomic_commit] commiting ffff978ee5654800
>[  103.725745] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5654800
>[  103.725749] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5654800
>[  103.725759] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  103.725764] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[  103.725767] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5654800
>[  103.725770] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5657000 state to ffff978ee5654800
>[  103.725773] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee5d0e480 state to ffff978ee5654800
>[  103.725784] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5657000
>[  103.725787] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5d0e480 to [CRTC:26:pipe A]
>[  103.725790] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffff978ee5d0e480
>[  103.725792] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5654800
>[  103.725796] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2cee0 state to ffff978ee5654800
>[  103.725799] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2cee0 to [NOCRTC]
>[  103.725802] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2cee0 to [CRTC:26:pipe A]
>[  103.725804] [drm:drm_atomic_check_only] checking ffff978ee5654800
>[  103.725809] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[  103.725812] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[  103.725814] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  103.725816] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[  103.725819] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5654800
>[  103.725822] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5654800
>[  103.725826] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  103.725827] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  103.725835] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  103.725840] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  103.725849] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  103.725853] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  103.725856] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  103.725860] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5657000 for pipe A
>[  103.725862] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  103.725864] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  103.725866] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  103.725869] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  103.725872] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  103.725874] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  103.725875] [drm:intel_dump_pipe_config] requested mode:
>[  103.725880] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  103.725882] [drm:intel_dump_pipe_config] adjusted mode:
>[  103.725886] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  103.725889] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  103.725891] [drm:intel_dump_pipe_config] port clock: 540000
>[  103.725893] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  103.725895] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  103.725897] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  103.725900] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  103.725901] [drm:intel_dump_pipe_config] ips: 0
>[  103.725903] [drm:intel_dump_pipe_config] double wide: 0
>[  103.725906] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  103.725907] [drm:intel_dump_pipe_config] planes on this crtc
>[  103.725911] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  103.725914] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  103.725917] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  103.725919] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  103.725921] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  103.725926] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5655000 state to ffff978ee5654800
>[  103.725929] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5655800 state to ffff978ee5654800
>[  103.725931] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[  103.725937] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  103.725940] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[  103.725942] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[  103.725947] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  103.725949] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  103.725953] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  103.725964] [drm:drm_atomic_commit] commiting ffff978ee5654800
>[  103.725976] [drm:intel_power_well_enable] enabling DDI A/E power well
>[  103.725980] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  103.725987] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[  103.729871] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  103.729875] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  103.729879] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  103.729883] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  103.729886] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  103.729888] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  103.729891] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  103.729894] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  103.729896] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  103.729899] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  103.729902] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  103.729905] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  103.729907] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  103.729910] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  103.729913] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  103.729917] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  103.729919] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  103.729922] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  103.729927] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[  103.729929] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[  103.729942] [drm:edp_panel_on] Turn eDP port A panel power on
>[  103.729961] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  103.730037] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[  103.730055] [drm:wait_panel_status] Wait complete
>[  103.730088] [drm:edp_panel_on] Wait for panel power on
>[  103.730163] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[  103.931930] [drm:wait_panel_status] Wait complete
>[  103.933075] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  103.933077] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  103.933078] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  103.933081] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[  103.933752] [drm:intel_dp_start_link_train] clock recovery OK
>[  103.933755] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[  103.933757] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[  103.934741] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[  103.934743] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  103.934745] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  103.935706] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[  103.935879] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5657000
>[  103.935993] [drm:intel_enable_pipe] enabling pipe A
>[  103.935999] [drm:intel_edp_backlight_on.part.29] 
>[  103.936001] [drm:intel_panel_enable_backlight] pipe A
>[  103.936079] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  103.936133] [drm:intel_psr_enable] PSR disable by flag
>[  103.936134] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  103.952950] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  103.952956] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  103.952970] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  103.952977] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5654800
>[  103.952980] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5654800
>[  103.953003] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d88000
>[  103.953005] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8e000 state to ffff978ee5d88000
>[  103.953006] [drm:drm_atomic_check_only] checking ffff978ee5d88000
>[  103.953011] [drm:drm_atomic_commit] commiting ffff978ee5d88000
>[  103.969565] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d88000
>[  103.969569] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d88000
>[  103.969596] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[  103.969598] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  103.969733] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d88000
>[  103.969737] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee65af3c0 state to ffff978ee5d88000
>[  103.969740] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d000 state to ffff978ee5d88000
>[  103.969742] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee65af3c0 to [CRTC:26:pipe A]
>[  103.969743] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee65af3c0
>[  103.969745] [drm:drm_atomic_check_only] checking ffff978ee5d88000
>[  103.969751] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  103.969753] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[  103.969760] [drm:drm_atomic_commit] commiting ffff978ee5d88000
>[  103.969798] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d88000
>[  103.969800] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d88000
>[  104.095131] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[  104.095135] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d800 state to ffff978ee5d8e000
>[  104.095137] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[  104.095140] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  104.095141] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[  104.095143] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8e000
>[  104.095145] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656ce00 state to ffff978ee5d8e000
>[  104.095147] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee635dd80 state to ffff978ee5d8e000
>[  104.095149] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee635d000 state to ffff978ee5d8e000
>[  104.095151] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8e000
>[  104.095153] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  104.095154] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  104.095159] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  104.095163] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  104.095168] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  104.095170] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  104.095171] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  104.095173] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d8d800 for pipe A
>[  104.095175] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  104.095176] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  104.095177] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  104.095179] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  104.095180] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  104.095182] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  104.095183] [drm:intel_dump_pipe_config] requested mode:
>[  104.095186] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  104.095187] [drm:intel_dump_pipe_config] adjusted mode:
>[  104.095189] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  104.095191] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  104.095192] [drm:intel_dump_pipe_config] port clock: 540000
>[  104.095193] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  104.095194] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  104.095195] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  104.095197] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  104.095198] [drm:intel_dump_pipe_config] ips: 0
>[  104.095199] [drm:intel_dump_pipe_config] double wide: 0
>[  104.095200] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  104.095201] [drm:intel_dump_pipe_config] planes on this crtc
>[  104.095203] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  104.095205] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  104.095206] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  104.095208] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[  104.095209] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[  104.095211] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[  104.095212] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  104.095215] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d8f800 state to ffff978ee5d8e000
>[  104.095217] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5d8f000 state to ffff978ee5d8e000
>[  104.095218] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[  104.095222] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  104.095224] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[  104.095225] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  104.095227] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  104.095228] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[  104.095230] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  104.095232] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  104.095234] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  104.095239] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[  104.096847] [drm:intel_edp_backlight_off.part.30] 
>[  104.298857] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  104.298943] [drm:intel_disable_pipe] disabling pipe A
>[  104.303313] [drm:edp_panel_off] Turn eDP port A panel power off
>[  104.303351] [drm:edp_panel_off] Wait for panel power off time
>[  104.303427] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[  104.304078] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[  104.304083] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[  104.304106] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[  104.354077] [drm:wait_panel_status] Wait complete
>[  104.354092] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[  104.354112] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  104.354114] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[  104.354131] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  104.354146] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[  104.355769] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  104.355774] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  104.355777] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[  104.358529] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  104.358534] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  104.358537] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  104.358543] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  104.358545] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  104.358548] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  104.358550] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  104.358553] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  104.358556] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  104.358558] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  104.358561] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  104.358564] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  104.358566] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  104.358568] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  104.358571] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  104.358575] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  104.358578] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  104.358580] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  104.358588] [drm:intel_power_well_disable] disabling DDI A/E power well
>[  104.358592] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  104.358596] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  104.358600] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  104.358604] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  104.358612] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[  104.358617] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[  104.947202] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[  104.947222] [drm:wait_panel_status] Wait complete
>[  104.947278] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  104.947292] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  104.996700] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  104.996705] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  104.996709] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[  105.155584] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[  105.156692] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  105.362191] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5656000
>[  105.362197] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee9090240 state to ffff978ee5656000
>[  105.362200] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5653800 state to ffff978ee5656000
>[  105.362202] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee9090240 to [NOCRTC]
>[  105.362205] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee9090240
>[  105.362207] [drm:drm_atomic_check_only] checking ffff978ee5656000
>[  105.362216] [drm:drm_atomic_commit] commiting ffff978ee5656000
>[  105.362225] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5656000
>[  105.362228] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5656000
>[  105.362237] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  105.362241] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[  105.362244] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5656000
>[  105.362246] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5657800 state to ffff978ee5656000
>[  105.362248] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee9090900 state to ffff978ee5656000
>[  105.362251] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5657800
>[  105.362253] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee9090900 to [CRTC:26:pipe A]
>[  105.362255] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffff978ee9090900
>[  105.362257] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5656000
>[  105.362261] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2c440 state to ffff978ee5656000
>[  105.362264] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c440 to [NOCRTC]
>[  105.362266] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c440 to [CRTC:26:pipe A]
>[  105.362268] [drm:drm_atomic_check_only] checking ffff978ee5656000
>[  105.362272] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[  105.362274] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[  105.362276] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  105.362277] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[  105.362279] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5656000
>[  105.362282] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5656000
>[  105.362285] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  105.362287] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  105.362293] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  105.362297] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  105.362305] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  105.362308] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  105.362310] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  105.362313] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5657800 for pipe A
>[  105.362315] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  105.362317] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  105.362319] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  105.362321] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  105.362323] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  105.362325] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  105.362326] [drm:intel_dump_pipe_config] requested mode:
>[  105.362330] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  105.362332] [drm:intel_dump_pipe_config] adjusted mode:
>[  105.362335] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  105.362337] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  105.362339] [drm:intel_dump_pipe_config] port clock: 540000
>[  105.362341] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  105.362343] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  105.362344] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  105.362347] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  105.362348] [drm:intel_dump_pipe_config] ips: 0
>[  105.362349] [drm:intel_dump_pipe_config] double wide: 0
>[  105.362351] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  105.362353] [drm:intel_dump_pipe_config] planes on this crtc
>[  105.362355] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  105.362358] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  105.362360] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  105.362363] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  105.362364] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  105.362369] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5652800 state to ffff978ee5656000
>[  105.362371] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5655800 state to ffff978ee5656000
>[  105.362373] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[  105.362379] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  105.362381] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[  105.362383] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[  105.362387] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  105.362389] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  105.362393] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  105.362401] [drm:drm_atomic_commit] commiting ffff978ee5656000
>[  105.362411] [drm:intel_power_well_enable] enabling DDI A/E power well
>[  105.362415] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  105.362421] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[  105.363824] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  105.363827] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  105.363830] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  105.363834] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  105.363836] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  105.363839] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  105.363841] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  105.363844] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  105.363847] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  105.363849] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  105.363851] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  105.363854] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  105.363856] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  105.363859] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  105.363861] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  105.363865] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  105.363868] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  105.363870] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  105.363875] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[  105.363876] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[  105.363889] [drm:edp_panel_on] Turn eDP port A panel power on
>[  105.363908] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  105.363984] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[  105.363997] [drm:wait_panel_status] Wait complete
>[  105.364030] [drm:edp_panel_on] Wait for panel power on
>[  105.364105] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[  105.565369] [drm:wait_panel_status] Wait complete
>[  105.566514] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  105.566516] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  105.566518] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  105.566521] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[  105.567190] [drm:intel_dp_start_link_train] clock recovery OK
>[  105.567193] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[  105.567194] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[  105.568164] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[  105.568166] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  105.568167] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  105.569127] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[  105.569299] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5657800
>[  105.569397] [drm:intel_enable_pipe] enabling pipe A
>[  105.569407] [drm:intel_edp_backlight_on.part.29] 
>[  105.569410] [drm:intel_panel_enable_backlight] pipe A
>[  105.569491] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  105.569547] [drm:intel_psr_enable] PSR disable by flag
>[  105.569549] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  105.586350] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  105.586361] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  105.586381] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  105.586390] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5656000
>[  105.586396] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5656000
>[  105.586429] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f000
>[  105.586433] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f800 state to ffff978ee5d8f000
>[  105.586435] [drm:drm_atomic_check_only] checking ffff978ee5d8f000
>[  105.586444] [drm:drm_atomic_commit] commiting ffff978ee5d8f000
>[  105.602943] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f000
>[  105.602949] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f000
>[  105.602986] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[  105.602989] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  105.603148] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f000
>[  105.603153] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee87c5600 state to ffff978ee5d8f000
>[  105.603158] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d800 state to ffff978ee5d8f000
>[  105.603161] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee87c5600 to [CRTC:26:pipe A]
>[  105.603164] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee87c5600
>[  105.603166] [drm:drm_atomic_check_only] checking ffff978ee5d8f000
>[  105.603175] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  105.603178] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[  105.603191] [drm:drm_atomic_commit] commiting ffff978ee5d8f000
>[  105.603225] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f000
>[  105.603229] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f000
>[  105.725299] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f800
>[  105.725304] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8e000 state to ffff978ee5d8f800
>[  105.725307] [drm:drm_atomic_check_only] checking ffff978ee5d8f800
>[  105.725311] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  105.725313] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[  105.725316] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8f800
>[  105.725319] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656c500 state to ffff978ee5d8f800
>[  105.725322] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee9178a80 state to ffff978ee5d8f800
>[  105.725324] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee9178e40 state to ffff978ee5d8f800
>[  105.725327] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8f800
>[  105.725330] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  105.725332] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  105.725338] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  105.725342] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  105.725350] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  105.725353] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  105.725355] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  105.725358] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d8e000 for pipe A
>[  105.725360] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  105.725362] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  105.725364] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  105.725366] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  105.725368] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  105.725370] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  105.725371] [drm:intel_dump_pipe_config] requested mode:
>[  105.725376] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  105.725378] [drm:intel_dump_pipe_config] adjusted mode:
>[  105.725381] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  105.725383] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  105.725436] [drm:intel_dump_pipe_config] port clock: 540000
>[  105.725438] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  105.725439] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  105.725441] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  105.725443] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  105.725445] [drm:intel_dump_pipe_config] ips: 0
>[  105.725446] [drm:intel_dump_pipe_config] double wide: 0
>[  105.725448] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  105.725449] [drm:intel_dump_pipe_config] planes on this crtc
>[  105.725452] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  105.725455] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  105.725457] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  105.725459] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[  105.725461] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[  105.725463] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[  105.725465] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  105.725469] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d8d000 state to ffff978ee5d8f800
>[  105.725472] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5d88000 state to ffff978ee5d8f800
>[  105.725473] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[  105.725479] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  105.725481] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[  105.725483] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  105.725485] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  105.725487] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[  105.725491] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  105.725493] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  105.725496] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  105.725504] [drm:drm_atomic_commit] commiting ffff978ee5d8f800
>[  105.726874] [drm:intel_edp_backlight_off.part.30] 
>[  105.930872] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  105.930928] [drm:intel_disable_pipe] disabling pipe A
>[  105.937340] [drm:edp_panel_off] Turn eDP port A panel power off
>[  105.937378] [drm:edp_panel_off] Wait for panel power off time
>[  105.937455] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[  105.937961] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[  105.937965] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[  105.937978] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[  105.988045] [drm:wait_panel_status] Wait complete
>[  105.988061] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[  105.988066] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[  105.988084] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[  105.988127] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  105.988144] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  105.989814] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  105.989819] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  105.989822] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[  105.992408] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  105.992413] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  105.992416] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  105.992422] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  105.992424] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  105.992427] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  105.992429] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  105.992432] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  105.992435] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  105.992437] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  105.992440] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  105.992443] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  105.992445] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  105.992447] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  105.992450] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  105.992454] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  105.992456] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  105.992459] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  105.992467] [drm:intel_power_well_disable] disabling DDI A/E power well
>[  105.992471] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  105.992475] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  105.992478] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  105.992482] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  105.992490] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f800
>[  105.992496] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f800
>[  106.546979] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000
>[  106.565911] [drm:wait_panel_status] Wait complete
>[  106.565971] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  106.565984] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  106.635440] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  106.635444] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  106.635447] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[  106.771373] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[  106.772461] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  106.996642] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d800
>[  106.996647] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee9178900 state to ffff978ee5d8d800
>[  106.996651] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f800 state to ffff978ee5d8d800
>[  106.996653] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee9178900 to [NOCRTC]
>[  106.996655] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee9178900
>[  106.996657] [drm:drm_atomic_check_only] checking ffff978ee5d8d800
>[  106.996667] [drm:drm_atomic_commit] commiting ffff978ee5d8d800
>[  106.996675] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d800
>[  106.996678] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d800
>[  106.996687] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  106.996691] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[  106.996694] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d800
>[  106.996696] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8e000 state to ffff978ee5d8d800
>[  106.996699] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee9178e40 state to ffff978ee5d8d800
>[  106.996702] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5d8e000
>[  106.996704] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee9178e40 to [CRTC:26:pipe A]
>[  106.996706] [drm:drm_atomic_set_fb_for_plane] Set [FB:58] for plane state ffff978ee9178e40
>[  106.996708] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[  106.996711] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656c1e0 state to ffff978ee5d8d800
>[  106.996714] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978ee656c1e0 to [NOCRTC]
>[  106.996716] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978ee656c1e0 to [CRTC:26:pipe A]
>[  106.996718] [drm:drm_atomic_check_only] checking ffff978ee5d8d800
>[  106.996722] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[  106.996724] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[  106.996726] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  106.996727] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[  106.996729] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[  106.996732] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[  106.996735] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  106.996736] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  106.996743] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  106.996747] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  106.996755] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  106.996757] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  106.996759] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  106.996763] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d8e000 for pipe A
>[  106.996765] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  106.996766] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  106.996768] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  106.996771] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  106.996773] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  106.996774] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  106.996776] [drm:intel_dump_pipe_config] requested mode:
>[  106.996780] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  106.996781] [drm:intel_dump_pipe_config] adjusted mode:
>[  106.996784] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  106.996787] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  106.996789] [drm:intel_dump_pipe_config] port clock: 540000
>[  106.996790] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  106.996792] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  106.996794] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  106.996796] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  106.996797] [drm:intel_dump_pipe_config] ips: 0
>[  106.996799] [drm:intel_dump_pipe_config] double wide: 0
>[  106.996801] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  106.996802] [drm:intel_dump_pipe_config] planes on this crtc
>[  106.996810] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  106.996813] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  106.996815] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  106.996817] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  106.996819] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  106.996823] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d8f000 state to ffff978ee5d8d800
>[  106.996826] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee88b8800 state to ffff978ee5d8d800
>[  106.996828] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[  106.996833] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  106.996835] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[  106.996837] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[  106.996840] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  106.996843] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  106.996846] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  106.996855] [drm:drm_atomic_commit] commiting ffff978ee5d8d800
>[  106.996864] [drm:intel_power_well_enable] enabling DDI A/E power well
>[  106.996868] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  106.996873] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[  106.998812] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  106.998815] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  106.998818] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  106.998822] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  106.998824] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  106.998827] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  106.998829] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  106.998832] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  106.998835] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  106.998837] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  106.998840] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  106.998842] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  106.998845] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  106.998847] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  106.998850] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  106.998853] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  106.998856] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  106.998858] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  106.998863] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[  106.998865] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[  106.998877] [drm:edp_panel_on] Turn eDP port A panel power on
>[  106.998895] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  106.998971] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[  106.998984] [drm:wait_panel_status] Wait complete
>[  106.999018] [drm:edp_panel_on] Wait for panel power on
>[  106.999092] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[  107.199980] [drm:wait_panel_status] Wait complete
>[  107.201165] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  107.201168] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  107.201170] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  107.201173] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[  107.201845] [drm:intel_dp_start_link_train] clock recovery OK
>[  107.201848] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[  107.201850] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[  107.202822] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[  107.202824] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  107.202826] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  107.203787] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[  107.203968] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5d8e000
>[  107.204069] [drm:intel_enable_pipe] enabling pipe A
>[  107.204080] [drm:intel_edp_backlight_on.part.29] 
>[  107.204084] [drm:intel_panel_enable_backlight] pipe A
>[  107.204178] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  107.204237] [drm:intel_psr_enable] PSR disable by flag
>[  107.204237] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  107.221040] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  107.221047] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  107.221061] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  107.221067] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d800
>[  107.221071] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d800
>[  107.221095] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88be800
>[  107.221098] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d800 state to ffff978ee88be800
>[  107.221099] [drm:drm_atomic_check_only] checking ffff978ee88be800
>[  107.221104] [drm:drm_atomic_commit] commiting ffff978ee88be800
>[  107.237648] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee88be800
>[  107.237652] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee88be800
>[  107.237679] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[  107.237681] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  107.237800] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[  107.237804] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee9178a80 state to ffff978ee5d8e000
>[  107.237819] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d88000 state to ffff978ee5d8e000
>[  107.237820] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee9178a80 to [CRTC:26:pipe A]
>[  107.237822] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee9178a80
>[  107.237823] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[  107.237829] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  107.237831] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[  107.237838] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[  107.237880] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[  107.237884] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[  107.363063] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d800
>[  107.363066] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d000 state to ffff978ee5d8d800
>[  107.363068] [drm:drm_atomic_check_only] checking ffff978ee5d8d800
>[  107.363071] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  107.363072] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[  107.363074] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[  107.363075] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656ce00 state to ffff978ee5d8d800
>[  107.363077] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee6330600 state to ffff978ee5d8d800
>[  107.363078] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee63303c0 state to ffff978ee5d8d800
>[  107.363080] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[  107.363082] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  107.363082] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  107.363087] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  107.363089] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  107.363094] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  107.363095] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  107.363097] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  107.363099] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d8d000 for pipe A
>[  107.363100] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  107.363101] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  107.363102] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  107.363103] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  107.363104] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  107.363105] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  107.363106] [drm:intel_dump_pipe_config] requested mode:
>[  107.363109] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  107.363109] [drm:intel_dump_pipe_config] adjusted mode:
>[  107.363111] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  107.363113] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  107.363113] [drm:intel_dump_pipe_config] port clock: 540000
>[  107.363114] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  107.363116] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  107.363117] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  107.363118] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  107.363118] [drm:intel_dump_pipe_config] ips: 0
>[  107.363119] [drm:intel_dump_pipe_config] double wide: 0
>[  107.363120] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  107.363121] [drm:intel_dump_pipe_config] planes on this crtc
>[  107.363123] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  107.363124] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  107.363126] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  107.363127] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[  107.363128] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[  107.363129] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[  107.363130] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  107.363133] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d8f800 state to ffff978ee5d8d800
>[  107.363134] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5d8e000 state to ffff978ee5d8d800
>[  107.363135] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[  107.363139] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  107.363140] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 58
>[  107.363141] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  107.363142] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  107.363143] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[  107.363146] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  107.363147] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  107.363149] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  107.363153] [drm:drm_atomic_commit] commiting ffff978ee5d8d800
>[  107.364904] [drm:intel_edp_backlight_off.part.30] 
>[  107.570901] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  107.570955] [drm:intel_disable_pipe] disabling pipe A
>[  107.588417] [drm:edp_panel_off] Turn eDP port A panel power off
>[  107.588456] [drm:edp_panel_off] Wait for panel power off time
>[  107.588533] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[  107.589138] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[  107.589143] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[  107.589166] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[  107.638745] [drm:wait_panel_status] Wait complete
>[  107.638762] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[  107.638781] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  107.638784] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[  107.638801] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  107.638831] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[  107.640914] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  107.640920] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  107.640924] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[  107.647550] [drm:skl_pcode_request] PCODE timeout, retrying with preemption disabled
>[  107.647561] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  107.647566] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  107.647571] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  107.647576] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  107.647579] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  107.647581] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  107.647584] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  107.647587] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  107.647589] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  107.647592] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  107.647595] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  107.647598] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  107.647600] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  107.647603] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  107.647606] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  107.647609] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  107.647612] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  107.647615] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  107.647624] [drm:intel_power_well_disable] disabling DDI A/E power well
>[  107.647628] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  107.647632] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  107.647636] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  107.647640] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  107.647648] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d800
>[  107.647653] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d800
>[  108.210987] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[  108.211007] [drm:wait_panel_status] Wait complete
>[  108.211062] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  108.211075] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  108.260260] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  108.260264] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  108.260268] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[  108.419370] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[  108.420458] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  108.651644] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee67e5800
>[  108.651649] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee65bc600 state to ffff978ee67e5800
>[  108.651653] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee67e3800 state to ffff978ee67e5800
>[  108.651656] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee65bc600 to [NOCRTC]
>[  108.651658] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee65bc600
>[  108.651660] [drm:drm_atomic_check_only] checking ffff978ee67e5800
>[  108.651671] [drm:drm_atomic_commit] commiting ffff978ee67e5800
>[  108.651681] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee67e5800
>[  108.651684] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee67e5800
>[  108.651694] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  108.651699] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[  108.651702] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee67e5800
>[  108.651705] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee67e5000 state to ffff978ee67e5800
>[  108.651707] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee65bc6c0 state to ffff978ee67e5800
>[  108.651711] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee67e5000
>[  108.651713] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee65bc6c0 to [CRTC:26:pipe A]
>[  108.651715] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffff978ee65bc6c0
>[  108.651718] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee67e5800
>[  108.651721] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eeb567e20 state to ffff978ee67e5800
>[  108.651725] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eeb567e20 to [NOCRTC]
>[  108.651728] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eeb567e20 to [CRTC:26:pipe A]
>[  108.651730] [drm:drm_atomic_check_only] checking ffff978ee67e5800
>[  108.651734] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[  108.651737] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[  108.651739] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  108.651741] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[  108.651743] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee67e5800
>[  108.651746] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee67e5800
>[  108.651749] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  108.651751] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  108.651758] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  108.651763] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  108.651771] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  108.651775] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  108.651777] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  108.651781] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee67e5000 for pipe A
>[  108.651783] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  108.651785] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  108.651787] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  108.651790] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  108.651792] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  108.651794] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  108.651796] [drm:intel_dump_pipe_config] requested mode:
>[  108.651800] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  108.651801] [drm:intel_dump_pipe_config] adjusted mode:
>[  108.651805] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  108.651808] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  108.651810] [drm:intel_dump_pipe_config] port clock: 540000
>[  108.651811] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  108.651814] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  108.651816] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  108.651818] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  108.651828] [drm:intel_dump_pipe_config] ips: 0
>[  108.651830] [drm:intel_dump_pipe_config] double wide: 0
>[  108.651832] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  108.651833] [drm:intel_dump_pipe_config] planes on this crtc
>[  108.651837] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  108.651839] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  108.651842] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  108.651844] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  108.651846] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  108.651851] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee67e7800 state to ffff978ee67e5800
>[  108.651854] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee67e3000 state to ffff978ee67e5800
>[  108.651856] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[  108.651862] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  108.651865] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  108.651867] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[  108.651871] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  108.651874] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  108.651877] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  108.651888] [drm:drm_atomic_commit] commiting ffff978ee67e5800
>[  108.651901] [drm:intel_power_well_enable] enabling DDI A/E power well
>[  108.651906] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  108.651912] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[  108.655919] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  108.655923] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  108.655927] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  108.655930] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  108.655933] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  108.655936] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  108.655938] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  108.655941] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  108.655943] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  108.655945] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  108.655948] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  108.655951] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  108.655953] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  108.655955] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  108.655958] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  108.655961] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  108.655964] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  108.655966] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  108.655971] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[  108.655973] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[  108.655985] [drm:edp_panel_on] Turn eDP port A panel power on
>[  108.656004] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  108.656080] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[  108.656094] [drm:wait_panel_status] Wait complete
>[  108.656127] [drm:edp_panel_on] Wait for panel power on
>[  108.656202] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[  108.856749] [drm:wait_panel_status] Wait complete
>[  108.857916] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  108.857919] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  108.857920] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  108.857923] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[  108.858595] [drm:intel_dp_start_link_train] clock recovery OK
>[  108.858598] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[  108.858600] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[  108.859571] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[  108.859573] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  108.859575] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  108.860536] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[  108.860709] [drm:skylake_pfit_enable] for crtc_state = ffff978ee67e5000
>[  108.860811] [drm:intel_enable_pipe] enabling pipe A
>[  108.860821] [drm:intel_edp_backlight_on.part.29] 
>[  108.860827] [drm:intel_panel_enable_backlight] pipe A
>[  108.860909] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  108.860965] [drm:intel_psr_enable] PSR disable by flag
>[  108.860967] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  108.877697] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  108.877709] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  108.877731] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  108.877742] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee67e5800
>[  108.877749] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee67e5800
>[  108.877784] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[  108.877788] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f800 state to ffff978ee5d8e000
>[  108.877791] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[  108.877800] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[  108.894390] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[  108.894397] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[  108.894438] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[  108.894442] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  108.894620] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[  108.894627] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee63300c0 state to ffff978ee5d8e000
>[  108.894633] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d000 state to ffff978ee5d8e000
>[  108.894636] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee63300c0 to [CRTC:26:pipe A]
>[  108.894640] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee63300c0
>[  108.894643] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[  108.894653] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  108.894657] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[  108.894673] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[  108.894711] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[  108.894716] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[  109.019212] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5653000
>[  109.019216] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5652000 state to ffff978ee5653000
>[  109.019218] [drm:drm_atomic_check_only] checking ffff978ee5653000
>[  109.019221] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  109.019223] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[  109.019224] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5653000
>[  109.019226] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2cb20 state to ffff978ee5653000
>[  109.019228] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee6542d80 state to ffff978ee5653000
>[  109.019229] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee6542a80 state to ffff978ee5653000
>[  109.019231] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5653000
>[  109.019233] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  109.019234] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  109.019239] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  109.019242] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  109.019247] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  109.019262] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  109.019264] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  109.019266] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5652000 for pipe A
>[  109.019267] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  109.019268] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  109.019270] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  109.019271] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  109.019273] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  109.019274] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  109.019275] [drm:intel_dump_pipe_config] requested mode:
>[  109.019278] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  109.019279] [drm:intel_dump_pipe_config] adjusted mode:
>[  109.019281] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  109.019282] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  109.019283] [drm:intel_dump_pipe_config] port clock: 540000
>[  109.019284] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  109.019285] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  109.019286] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  109.019288] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  109.019289] [drm:intel_dump_pipe_config] ips: 0
>[  109.019289] [drm:intel_dump_pipe_config] double wide: 0
>[  109.019291] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  109.019291] [drm:intel_dump_pipe_config] planes on this crtc
>[  109.019293] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  109.019295] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  109.019296] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  109.019298] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[  109.019299] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[  109.019301] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[  109.019302] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  109.019305] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5651800 state to ffff978ee5653000
>[  109.019307] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5650800 state to ffff978ee5653000
>[  109.019308] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[  109.019313] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  109.019314] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  109.019315] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  109.019317] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  109.019318] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[  109.019321] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  109.019322] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  109.019324] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  109.019329] [drm:drm_atomic_commit] commiting ffff978ee5653000
>[  109.020899] [drm:intel_edp_backlight_off.part.30] 
>[  109.226986] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  109.227057] [drm:intel_disable_pipe] disabling pipe A
>[  109.229403] [drm:edp_panel_off] Turn eDP port A panel power off
>[  109.229443] [drm:edp_panel_off] Wait for panel power off time
>[  109.229555] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[  109.230130] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[  109.230135] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[  109.230159] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[  109.280217] [drm:wait_panel_status] Wait complete
>[  109.280233] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[  109.280252] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[  109.280256] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  109.280274] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  109.280290] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[  109.281900] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  109.281906] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  109.281909] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[  109.284717] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  109.284723] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  109.284728] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  109.284733] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  109.284736] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  109.284739] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  109.284742] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  109.284745] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  109.284748] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  109.284750] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  109.284753] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  109.284757] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  109.284759] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  109.284762] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  109.284765] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  109.284769] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  109.284773] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  109.284775] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  109.284785] [drm:intel_power_well_disable] disabling DDI A/E power well
>[  109.284789] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  109.284793] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  109.284797] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  109.284801] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  109.284811] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5653000
>[  109.284818] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5653000
>[  109.875083] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[  109.875105] [drm:wait_panel_status] Wait complete
>[  109.875161] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  109.875175] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  109.924487] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  109.924493] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  109.924497] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[  110.083376] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[  110.084452] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  110.289202] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5654000
>[  110.289209] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee6671e40 state to ffff978ee5654000
>[  110.289214] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5651000 state to ffff978ee5654000
>[  110.289217] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee6671e40 to [NOCRTC]
>[  110.289220] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee6671e40
>[  110.289223] [drm:drm_atomic_check_only] checking ffff978ee5654000
>[  110.289235] [drm:drm_atomic_commit] commiting ffff978ee5654000
>[  110.289245] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5654000
>[  110.289249] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5654000
>[  110.289260] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  110.289266] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[  110.289270] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5654000
>[  110.289273] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5652000 state to ffff978ee5654000
>[  110.289276] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee6671480 state to ffff978ee5654000
>[  110.289280] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5652000
>[  110.289282] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee6671480 to [CRTC:26:pipe A]
>[  110.289285] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffff978ee6671480
>[  110.289288] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5654000
>[  110.289292] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2cd40 state to ffff978ee5654000
>[  110.289296] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2cd40 to [NOCRTC]
>[  110.289299] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2cd40 to [CRTC:26:pipe A]
>[  110.289301] [drm:drm_atomic_check_only] checking ffff978ee5654000
>[  110.289306] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[  110.289309] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[  110.289311] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  110.289314] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[  110.289316] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5654000
>[  110.289320] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5654000
>[  110.289324] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  110.289325] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  110.289334] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  110.289340] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  110.289349] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  110.289353] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  110.289356] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  110.289360] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5652000 for pipe A
>[  110.289362] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  110.289364] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  110.289367] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  110.289370] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  110.289373] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  110.289375] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  110.289377] [drm:intel_dump_pipe_config] requested mode:
>[  110.289382] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  110.289384] [drm:intel_dump_pipe_config] adjusted mode:
>[  110.289388] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  110.289392] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  110.289394] [drm:intel_dump_pipe_config] port clock: 540000
>[  110.289396] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  110.289398] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  110.289401] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  110.289403] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  110.289405] [drm:intel_dump_pipe_config] ips: 0
>[  110.289407] [drm:intel_dump_pipe_config] double wide: 0
>[  110.289410] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  110.289411] [drm:intel_dump_pipe_config] planes on this crtc
>[  110.289415] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  110.289418] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  110.289421] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  110.289424] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  110.289426] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  110.289432] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5653000 state to ffff978ee5654000
>[  110.289435] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5656800 state to ffff978ee5654000
>[  110.289437] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[  110.289444] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  110.289446] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  110.289449] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[  110.289454] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  110.289457] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  110.289462] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  110.289473] [drm:drm_atomic_commit] commiting ffff978ee5654000
>[  110.289485] [drm:intel_power_well_enable] enabling DDI A/E power well
>[  110.289490] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  110.289497] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[  110.292910] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  110.292915] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  110.292920] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  110.292925] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  110.292928] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  110.292931] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  110.292934] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  110.292938] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  110.292941] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  110.292943] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  110.292947] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  110.292950] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  110.292953] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  110.292955] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  110.292959] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  110.292963] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  110.292966] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  110.292969] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  110.292976] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[  110.292978] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[  110.292993] [drm:edp_panel_on] Turn eDP port A panel power on
>[  110.293003] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  110.293093] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[  110.293104] [drm:wait_panel_status] Wait complete
>[  110.293128] [drm:edp_panel_on] Wait for panel power on
>[  110.293184] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 0000000b
>[  110.495361] [drm:wait_panel_status] Wait complete
>[  110.496551] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  110.496555] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  110.496557] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  110.496560] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[  110.497237] [drm:intel_dp_start_link_train] clock recovery OK
>[  110.497241] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[  110.497243] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[  110.498220] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[  110.498222] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  110.498224] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  110.499198] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[  110.499375] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5652000
>[  110.499485] [drm:intel_enable_pipe] enabling pipe A
>[  110.499496] [drm:intel_edp_backlight_on.part.29] 
>[  110.499501] [drm:intel_panel_enable_backlight] pipe A
>[  110.499558] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  110.499600] [drm:intel_psr_enable] PSR disable by flag
>[  110.499602] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  110.516452] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  110.516465] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  110.516488] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  110.516500] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5654000
>[  110.516506] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5654000
>[  110.516544] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[  110.516549] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f800 state to ffff978ee5d8e000
>[  110.516552] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[  110.516562] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[  110.533117] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[  110.533125] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[  110.533167] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[  110.533171] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  110.533344] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[  110.533351] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee6598e40 state to ffff978ee5d8e000
>[  110.533356] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d800 state to ffff978ee5d8e000
>[  110.533360] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee6598e40 to [CRTC:26:pipe A]
>[  110.533364] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee6598e40
>[  110.533368] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[  110.533378] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  110.533382] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[  110.533437] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[  110.533475] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[  110.533480] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[  110.658466] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f800
>[  110.658470] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f000 state to ffff978ee5d8f800
>[  110.658472] [drm:drm_atomic_check_only] checking ffff978ee5d8f800
>[  110.658476] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  110.658477] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[  110.658479] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8f800
>[  110.658481] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656ca20 state to ffff978ee5d8f800
>[  110.658483] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee87066c0 state to ffff978ee5d8f800
>[  110.658485] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee8706780 state to ffff978ee5d8f800
>[  110.658486] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8f800
>[  110.658489] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  110.658490] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  110.658495] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  110.658498] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  110.658503] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  110.658505] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  110.658506] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  110.658509] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d8f000 for pipe A
>[  110.658510] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  110.658511] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  110.658512] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  110.658514] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  110.658515] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  110.658516] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  110.658517] [drm:intel_dump_pipe_config] requested mode:
>[  110.658520] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  110.658521] [drm:intel_dump_pipe_config] adjusted mode:
>[  110.658523] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  110.658524] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  110.658525] [drm:intel_dump_pipe_config] port clock: 540000
>[  110.658526] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  110.658528] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  110.658529] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  110.658531] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  110.658532] [drm:intel_dump_pipe_config] ips: 0
>[  110.658533] [drm:intel_dump_pipe_config] double wide: 0
>[  110.658534] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  110.658535] [drm:intel_dump_pipe_config] planes on this crtc
>[  110.658543] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  110.658544] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  110.658546] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  110.658548] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[  110.658550] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[  110.658551] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[  110.658552] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  110.658565] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d88000 state to ffff978ee5d8f800
>[  110.658581] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5d8e000 state to ffff978ee5d8f800
>[  110.658582] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[  110.658587] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  110.658588] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  110.658590] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  110.658591] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  110.658593] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[  110.658596] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  110.658598] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  110.658600] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  110.658606] [drm:drm_atomic_commit] commiting ffff978ee5d8f800
>[  110.659903] [drm:intel_edp_backlight_off.part.30] 
>[  110.866930] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  110.866987] [drm:intel_disable_pipe] disabling pipe A
>[  110.884323] [drm:edp_panel_off] Turn eDP port A panel power off
>[  110.884364] [drm:edp_panel_off] Wait for panel power off time
>[  110.884441] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[  110.884965] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[  110.884972] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[  110.884998] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[  110.934560] [drm:wait_panel_status] Wait complete
>[  110.934579] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[  110.934599] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  110.934602] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[  110.934622] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  110.934639] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[  110.936815] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  110.936823] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  110.936826] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[  110.939173] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  110.939180] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  110.939185] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  110.939191] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  110.939195] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  110.939198] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  110.939202] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  110.939205] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  110.939208] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  110.939212] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  110.939215] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  110.939219] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  110.939222] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  110.939225] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  110.939229] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  110.939234] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  110.939238] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  110.939241] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  110.939252] [drm:intel_power_well_disable] disabling DDI A/E power well
>[  110.939256] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  110.939261] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  110.939266] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  110.939271] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  110.939282] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f800
>[  110.939289] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f800
>[  111.539147] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[  111.539169] [drm:wait_panel_status] Wait complete
>[  111.539226] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  111.539240] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  111.588564] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  111.588571] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  111.588575] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[  111.747651] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[  111.748775] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  111.943012] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5657000
>[  111.943017] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee671af00 state to ffff978ee5657000
>[  111.943021] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5655000 state to ffff978ee5657000
>[  111.943023] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee671af00 to [NOCRTC]
>[  111.943026] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee671af00
>[  111.943028] [drm:drm_atomic_check_only] checking ffff978ee5657000
>[  111.943038] [drm:drm_atomic_commit] commiting ffff978ee5657000
>[  111.943047] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5657000
>[  111.943050] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5657000
>[  111.943059] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  111.943063] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[  111.943066] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5657000
>[  111.943068] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5657800 state to ffff978ee5657000
>[  111.943070] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee671a9c0 state to ffff978ee5657000
>[  111.943073] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5657800
>[  111.943075] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee671a9c0 to [CRTC:26:pipe A]
>[  111.943077] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffff978ee671a9c0
>[  111.943080] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5657000
>[  111.943082] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2c3e0 state to ffff978ee5657000
>[  111.943085] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c3e0 to [NOCRTC]
>[  111.943088] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c3e0 to [CRTC:26:pipe A]
>[  111.943089] [drm:drm_atomic_check_only] checking ffff978ee5657000
>[  111.943093] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[  111.943096] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[  111.943097] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  111.943099] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[  111.943101] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5657000
>[  111.943104] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5657000
>[  111.943107] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  111.943108] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  111.943115] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  111.943119] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  111.943126] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  111.943129] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  111.943131] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  111.943135] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5657800 for pipe A
>[  111.943136] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  111.943138] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  111.943140] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  111.943143] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  111.943145] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  111.943146] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  111.943148] [drm:intel_dump_pipe_config] requested mode:
>[  111.943151] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  111.943153] [drm:intel_dump_pipe_config] adjusted mode:
>[  111.943156] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  111.943159] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  111.943160] [drm:intel_dump_pipe_config] port clock: 540000
>[  111.943162] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  111.943164] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  111.943165] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  111.943167] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  111.943169] [drm:intel_dump_pipe_config] ips: 0
>[  111.943170] [drm:intel_dump_pipe_config] double wide: 0
>[  111.943172] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  111.943173] [drm:intel_dump_pipe_config] planes on this crtc
>[  111.943176] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  111.943178] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  111.943181] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  111.943183] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  111.943185] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  111.943189] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5656000 state to ffff978ee5657000
>[  111.943191] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5653800 state to ffff978ee5657000
>[  111.943193] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[  111.943198] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  111.943200] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  111.943202] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[  111.943205] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  111.943208] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  111.943211] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  111.943220] [drm:drm_atomic_commit] commiting ffff978ee5657000
>[  111.943229] [drm:intel_power_well_enable] enabling DDI A/E power well
>[  111.943232] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  111.943238] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[  111.944881] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  111.944885] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  111.944888] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  111.944891] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  111.944894] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  111.944896] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  111.944898] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  111.944901] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  111.944903] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  111.944906] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  111.944908] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  111.944911] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  111.944913] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  111.944916] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  111.944918] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  111.944922] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  111.944924] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  111.944927] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  111.944931] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[  111.944933] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[  111.944945] [drm:edp_panel_on] Turn eDP port A panel power on
>[  111.944964] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  111.945040] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[  111.945054] [drm:wait_panel_status] Wait complete
>[  111.945087] [drm:edp_panel_on] Wait for panel power on
>[  111.945161] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[  112.146563] [drm:wait_panel_status] Wait complete
>[  112.147712] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  112.147714] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  112.147716] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  112.147719] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[  112.148391] [drm:intel_dp_start_link_train] clock recovery OK
>[  112.148394] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[  112.148396] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[  112.149368] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[  112.149370] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  112.149371] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  112.150332] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[  112.150520] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5657800
>[  112.150592] [drm:intel_enable_pipe] enabling pipe A
>[  112.150599] [drm:intel_edp_backlight_on.part.29] 
>[  112.150600] [drm:intel_panel_enable_backlight] pipe A
>[  112.150680] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  112.150733] [drm:intel_psr_enable] PSR disable by flag
>[  112.150734] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  112.167562] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  112.167569] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  112.167582] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  112.167589] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5657000
>[  112.167592] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5657000
>[  112.167617] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[  112.167619] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d88000 state to ffff978ee5d8e000
>[  112.167620] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[  112.167626] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[  112.184260] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[  112.184265] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[  112.184293] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[  112.184295] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  112.184424] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[  112.184427] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee87063c0 state to ffff978ee5d8e000
>[  112.184430] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d000 state to ffff978ee5d8e000
>[  112.184431] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee87063c0 to [CRTC:26:pipe A]
>[  112.184433] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee87063c0
>[  112.184435] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[  112.184441] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  112.184442] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[  112.184450] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[  112.184497] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[  112.184500] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[  112.315026] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d88000
>[  112.315031] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8e000 state to ffff978ee5d88000
>[  112.315033] [drm:drm_atomic_check_only] checking ffff978ee5d88000
>[  112.315037] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  112.315038] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[  112.315040] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d88000
>[  112.315043] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656ca20 state to ffff978ee5d88000
>[  112.315045] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee8706300 state to ffff978ee5d88000
>[  112.315047] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee87066c0 state to ffff978ee5d88000
>[  112.315049] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d88000
>[  112.315052] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  112.315053] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  112.315059] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  112.315062] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  112.315068] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  112.315071] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  112.315072] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  112.315075] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d8e000 for pipe A
>[  112.315076] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  112.315078] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  112.315079] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  112.315081] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  112.315083] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  112.315084] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  112.315085] [drm:intel_dump_pipe_config] requested mode:
>[  112.315089] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  112.315090] [drm:intel_dump_pipe_config] adjusted mode:
>[  112.315093] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  112.315095] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  112.315096] [drm:intel_dump_pipe_config] port clock: 540000
>[  112.315097] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  112.315099] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  112.315101] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  112.315102] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  112.315103] [drm:intel_dump_pipe_config] ips: 0
>[  112.315104] [drm:intel_dump_pipe_config] double wide: 0
>[  112.315106] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  112.315107] [drm:intel_dump_pipe_config] planes on this crtc
>[  112.315109] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  112.315111] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  112.315113] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  112.315115] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[  112.315116] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[  112.315118] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[  112.315120] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  112.315123] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d8f000 state to ffff978ee5d88000
>[  112.315126] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5d8f800 state to ffff978ee5d88000
>[  112.315127] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[  112.315132] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  112.315133] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  112.315135] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  112.315138] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  112.315139] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[  112.315144] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  112.315146] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  112.315148] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  112.315158] [drm:drm_atomic_commit] commiting ffff978ee5d88000
>[  112.316918] [drm:intel_edp_backlight_off.part.30] 
>[  112.523063] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  112.523121] [drm:intel_disable_pipe] disabling pipe A
>[  112.534300] [drm:edp_panel_off] Turn eDP port A panel power off
>[  112.534340] [drm:edp_panel_off] Wait for panel power off time
>[  112.534417] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[  112.534916] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[  112.534920] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[  112.534935] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[  112.585080] [drm:wait_panel_status] Wait complete
>[  112.585097] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[  112.585116] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  112.585119] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[  112.585136] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  112.585153] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[  112.586755] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  112.586761] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  112.586764] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[  112.587440] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  112.587446] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  112.587451] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  112.587456] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  112.587459] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  112.587462] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  112.587465] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  112.587468] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  112.587471] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  112.587474] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  112.587477] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  112.587480] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  112.587483] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  112.587485] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  112.587488] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  112.587493] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  112.587496] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  112.587499] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  112.587508] [drm:intel_power_well_disable] disabling DDI A/E power well
>[  112.587512] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  112.587517] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  112.587521] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  112.587525] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  112.587534] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d88000
>[  112.587540] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d88000
>[  113.139151] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000
>[  113.145812] [drm:wait_panel_status] Wait complete
>[  113.145891] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  113.145908] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  113.195212] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  113.195218] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  113.195221] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[  113.355550] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[  113.356651] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  113.592118] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee67e7000
>[  113.592125] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee88e3000 state to ffff978ee67e7000
>[  113.592130] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee67e2800 state to ffff978ee67e7000
>[  113.592133] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee88e3000 to [NOCRTC]
>[  113.592135] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee88e3000
>[  113.592138] [drm:drm_atomic_check_only] checking ffff978ee67e7000
>[  113.592150] [drm:drm_atomic_commit] commiting ffff978ee67e7000
>[  113.592161] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee67e7000
>[  113.592165] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee67e7000
>[  113.592176] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  113.592182] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[  113.592186] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee67e7000
>[  113.592189] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee67e1000 state to ffff978ee67e7000
>[  113.592192] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee88e3180 state to ffff978ee67e7000
>[  113.592196] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee67e1000
>[  113.592198] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee88e3180 to [CRTC:26:pipe A]
>[  113.592201] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffff978ee88e3180
>[  113.592204] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee67e7000
>[  113.592208] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eeb5672e0 state to ffff978ee67e7000
>[  113.592211] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eeb5672e0 to [NOCRTC]
>[  113.592214] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eeb5672e0 to [CRTC:26:pipe A]
>[  113.592217] [drm:drm_atomic_check_only] checking ffff978ee67e7000
>[  113.592222] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[  113.592225] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[  113.592227] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  113.592230] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[  113.592232] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee67e7000
>[  113.592236] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee67e7000
>[  113.592240] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  113.592242] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  113.592250] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  113.592256] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  113.592265] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  113.592269] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  113.592272] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  113.592276] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee67e1000 for pipe A
>[  113.592278] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  113.592280] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  113.592283] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  113.592287] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  113.592289] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  113.592292] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  113.592293] [drm:intel_dump_pipe_config] requested mode:
>[  113.592299] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  113.592301] [drm:intel_dump_pipe_config] adjusted mode:
>[  113.592305] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  113.592308] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  113.592310] [drm:intel_dump_pipe_config] port clock: 540000
>[  113.592312] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  113.592315] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  113.592318] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  113.592320] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  113.592322] [drm:intel_dump_pipe_config] ips: 0
>[  113.592324] [drm:intel_dump_pipe_config] double wide: 0
>[  113.592326] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  113.592328] [drm:intel_dump_pipe_config] planes on this crtc
>[  113.592332] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  113.592335] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  113.592338] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  113.592341] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  113.592343] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  113.592348] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee67e3000 state to ffff978ee67e7000
>[  113.592351] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee67e7800 state to ffff978ee67e7000
>[  113.592354] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[  113.592360] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  113.592363] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  113.592365] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[  113.592371] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  113.592374] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  113.592378] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  113.592389] [drm:drm_atomic_commit] commiting ffff978ee67e7000
>[  113.592401] [drm:intel_power_well_enable] enabling DDI A/E power well
>[  113.592406] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  113.592413] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[  113.593875] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  113.593879] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  113.593883] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  113.593887] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  113.593890] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  113.593893] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  113.593896] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  113.593900] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  113.593903] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  113.593906] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  113.593909] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  113.593912] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  113.593915] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  113.593918] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  113.593921] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  113.593925] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  113.593928] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  113.593932] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  113.593937] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[  113.593939] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[  113.593953] [drm:edp_panel_on] Turn eDP port A panel power on
>[  113.593973] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  113.594050] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[  113.594067] [drm:wait_panel_status] Wait complete
>[  113.594101] [drm:edp_panel_on] Wait for panel power on
>[  113.594177] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[  113.794780] [drm:wait_panel_status] Wait complete
>[  113.795931] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  113.795934] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  113.795935] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  113.795938] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[  113.796606] [drm:intel_dp_start_link_train] clock recovery OK
>[  113.796609] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[  113.796610] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[  113.797574] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[  113.797574] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  113.797575] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  113.798519] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[  113.798684] [drm:skylake_pfit_enable] for crtc_state = ffff978ee67e1000
>[  113.798756] [drm:intel_enable_pipe] enabling pipe A
>[  113.798762] [drm:intel_edp_backlight_on.part.29] 
>[  113.798764] [drm:intel_panel_enable_backlight] pipe A
>[  113.798843] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  113.798898] [drm:intel_psr_enable] PSR disable by flag
>[  113.798899] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  113.815730] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  113.815737] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  113.815751] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  113.815757] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee67e7000
>[  113.815761] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee67e7000
>[  113.815785] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f800
>[  113.815788] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f000 state to ffff978ee5d8f800
>[  113.815789] [drm:drm_atomic_check_only] checking ffff978ee5d8f800
>[  113.815794] [drm:drm_atomic_commit] commiting ffff978ee5d8f800
>[  113.832351] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f800
>[  113.832355] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f800
>[  113.832378] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[  113.832379] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  113.832500] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f800
>[  113.832503] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee65510c0 state to ffff978ee5d8f800
>[  113.832507] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8e000 state to ffff978ee5d8f800
>[  113.832508] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee65510c0 to [CRTC:26:pipe A]
>[  113.832510] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee65510c0
>[  113.832512] [drm:drm_atomic_check_only] checking ffff978ee5d8f800
>[  113.832518] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  113.832519] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[  113.832528] [drm:drm_atomic_commit] commiting ffff978ee5d8f800
>[  113.832550] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f800
>[  113.832552] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f800
>[  113.955899] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d800
>[  113.955903] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d88000 state to ffff978ee5d8d800
>[  113.955905] [drm:drm_atomic_check_only] checking ffff978ee5d8d800
>[  113.955908] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  113.955909] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[  113.955912] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[  113.955918] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656ca20 state to ffff978ee5d8d800
>[  113.955924] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978eebbc03c0 state to ffff978ee5d8d800
>[  113.955926] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978eebbc0f00 state to ffff978ee5d8d800
>[  113.955929] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[  113.955932] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  113.955933] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  113.955938] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  113.955941] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  113.955946] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  113.955948] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  113.955950] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  113.955952] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d88000 for pipe A
>[  113.955953] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  113.955955] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  113.955956] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  113.955958] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  113.955959] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  113.955960] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  113.955961] [drm:intel_dump_pipe_config] requested mode:
>[  113.955964] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  113.955965] [drm:intel_dump_pipe_config] adjusted mode:
>[  113.955967] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  113.955969] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  113.955970] [drm:intel_dump_pipe_config] port clock: 540000
>[  113.955971] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  113.955973] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  113.955974] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  113.955975] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  113.955976] [drm:intel_dump_pipe_config] ips: 0
>[  113.955977] [drm:intel_dump_pipe_config] double wide: 0
>[  113.955979] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  113.955980] [drm:intel_dump_pipe_config] planes on this crtc
>[  113.955982] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  113.955983] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  113.955985] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  113.955987] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[  113.955988] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[  113.955990] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[  113.955991] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  113.955994] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d8f800 state to ffff978ee5d8d800
>[  113.955996] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5d8d000 state to ffff978ee5d8d800
>[  113.955997] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[  113.956001] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  113.956002] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  113.956004] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  113.956005] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  113.956007] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[  113.956009] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  113.956011] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  113.956013] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  113.956019] [drm:drm_atomic_commit] commiting ffff978ee5d8d800
>[  113.957939] [drm:intel_edp_backlight_off.part.30] 
>[  114.163098] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  114.163156] [drm:intel_disable_pipe] disabling pipe A
>[  114.167544] [drm:edp_panel_off] Turn eDP port A panel power off
>[  114.167583] [drm:edp_panel_off] Wait for panel power off time
>[  114.167661] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000000
>[  114.168261] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[  114.168267] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[  114.168293] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[  114.218279] [drm:wait_panel_status] Wait complete
>[  114.218296] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[  114.218316] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  114.218318] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[  114.218336] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  114.218352] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[  114.220081] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  114.220087] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  114.220090] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[  114.225052] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  114.225059] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  114.225063] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  114.225069] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  114.225072] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  114.225075] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  114.225079] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  114.225082] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  114.225085] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  114.225088] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  114.225091] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  114.225095] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  114.225098] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  114.225101] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  114.225104] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  114.225109] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  114.225112] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  114.225115] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  114.225126] [drm:intel_power_well_disable] disabling DDI A/E power well
>[  114.225130] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  114.225135] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  114.225140] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  114.225145] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  114.225154] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d800
>[  114.225161] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d800
>[  114.803165] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[  114.803186] [drm:wait_panel_status] Wait complete
>[  114.803244] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  114.803262] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  114.852571] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  114.852578] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  114.852582] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[  115.011570] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[  115.012675] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  115.229719] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5656000
>[  115.229725] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee5d0e300 state to ffff978ee5656000
>[  115.229729] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5653000 state to ffff978ee5656000
>[  115.229731] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5d0e300 to [NOCRTC]
>[  115.229733] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee5d0e300
>[  115.229735] [drm:drm_atomic_check_only] checking ffff978ee5656000
>[  115.229744] [drm:drm_atomic_commit] commiting ffff978ee5656000
>[  115.229754] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5656000
>[  115.229757] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5656000
>[  115.229766] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  115.229770] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[  115.229773] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5656000
>[  115.229776] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5657000 state to ffff978ee5656000
>[  115.229778] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee5d0eb40 state to ffff978ee5656000
>[  115.229781] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5657000
>[  115.229783] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5d0eb40 to [CRTC:26:pipe A]
>[  115.229785] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffff978ee5d0eb40
>[  115.229787] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5656000
>[  115.229790] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2c160 state to ffff978ee5656000
>[  115.229793] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c160 to [NOCRTC]
>[  115.229795] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c160 to [CRTC:26:pipe A]
>[  115.229797] [drm:drm_atomic_check_only] checking ffff978ee5656000
>[  115.229801] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[  115.229803] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[  115.229804] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  115.229806] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[  115.229808] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5656000
>[  115.229811] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5656000
>[  115.229814] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  115.229816] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  115.229822] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  115.229826] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  115.229834] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  115.229837] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  115.229839] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  115.229842] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5657000 for pipe A
>[  115.229844] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  115.229846] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  115.229848] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  115.229850] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  115.229852] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  115.229854] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  115.229855] [drm:intel_dump_pipe_config] requested mode:
>[  115.229859] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  115.229861] [drm:intel_dump_pipe_config] adjusted mode:
>[  115.229864] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  115.229866] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  115.229868] [drm:intel_dump_pipe_config] port clock: 540000
>[  115.229870] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  115.229872] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  115.229873] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  115.229882] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  115.229883] [drm:intel_dump_pipe_config] ips: 0
>[  115.229884] [drm:intel_dump_pipe_config] double wide: 0
>[  115.229886] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  115.229888] [drm:intel_dump_pipe_config] planes on this crtc
>[  115.229890] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  115.229893] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  115.229896] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  115.229898] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  115.229900] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  115.229904] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5655000 state to ffff978ee5656000
>[  115.229906] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5655800 state to ffff978ee5656000
>[  115.229908] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[  115.229913] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  115.229915] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  115.229917] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[  115.229921] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  115.229923] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  115.229926] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  115.229935] [drm:drm_atomic_commit] commiting ffff978ee5656000
>[  115.229945] [drm:intel_power_well_enable] enabling DDI A/E power well
>[  115.229950] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  115.229955] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[  115.231987] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  115.231992] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  115.231995] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  115.231999] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  115.232001] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  115.232004] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  115.232006] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  115.232009] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  115.232011] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  115.232014] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  115.232016] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  115.232019] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  115.232021] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  115.232024] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  115.232026] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  115.232030] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  115.232033] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  115.232035] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  115.232040] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[  115.232042] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[  115.232054] [drm:edp_panel_on] Turn eDP port A panel power on
>[  115.232073] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  115.232149] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[  115.232162] [drm:wait_panel_status] Wait complete
>[  115.232195] [drm:edp_panel_on] Wait for panel power on
>[  115.232270] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[  115.434108] [drm:wait_panel_status] Wait complete
>[  115.435251] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  115.435253] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  115.435255] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  115.435258] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[  115.435930] [drm:intel_dp_start_link_train] clock recovery OK
>[  115.435933] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[  115.435935] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[  115.436902] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[  115.436902] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  115.436903] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  115.437847] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[  115.438013] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5657000
>[  115.438086] [drm:intel_enable_pipe] enabling pipe A
>[  115.438092] [drm:intel_edp_backlight_on.part.29] 
>[  115.438094] [drm:intel_panel_enable_backlight] pipe A
>[  115.438173] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  115.438226] [drm:intel_psr_enable] PSR disable by flag
>[  115.438227] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  115.455040] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  115.455047] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  115.455061] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  115.455067] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5656000
>[  115.455071] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5656000
>[  115.455096] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d000
>[  115.455098] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f800 state to ffff978ee5d8d000
>[  115.455100] [drm:drm_atomic_check_only] checking ffff978ee5d8d000
>[  115.455105] [drm:drm_atomic_commit] commiting ffff978ee5d8d000
>[  115.471611] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d000
>[  115.471616] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d000
>[  115.471646] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[  115.471648] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  115.471775] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d000
>[  115.471779] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978eebbc0180 state to ffff978ee5d8d000
>[  115.471781] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f000 state to ffff978ee5d8d000
>[  115.471783] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eebbc0180 to [CRTC:26:pipe A]
>[  115.471784] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978eebbc0180
>[  115.471786] [drm:drm_atomic_check_only] checking ffff978ee5d8d000
>[  115.471792] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  115.471793] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[  115.471801] [drm:drm_atomic_commit] commiting ffff978ee5d8d000
>[  115.471827] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d000
>[  115.471830] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d000
>[  115.614898] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f800
>[  115.614902] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d000 state to ffff978ee5d8f800
>[  115.614904] [drm:drm_atomic_check_only] checking ffff978ee5d8f800
>[  115.614908] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  115.614909] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[  115.614911] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8f800
>[  115.614913] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656ca20 state to ffff978ee5d8f800
>[  115.614915] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee5c3dd80 state to ffff978ee5d8f800
>[  115.614917] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee5c3dcc0 state to ffff978ee5d8f800
>[  115.614919] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8f800
>[  115.614922] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  115.614923] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  115.614928] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  115.614932] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  115.614937] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  115.614939] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  115.614941] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  115.614943] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d8d000 for pipe A
>[  115.614945] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  115.614946] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  115.614948] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  115.614949] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  115.614951] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  115.614952] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  115.614953] [drm:intel_dump_pipe_config] requested mode:
>[  115.614957] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  115.614958] [drm:intel_dump_pipe_config] adjusted mode:
>[  115.614960] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  115.614962] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  115.614963] [drm:intel_dump_pipe_config] port clock: 540000
>[  115.614965] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  115.614966] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  115.614967] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  115.614969] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  115.614970] [drm:intel_dump_pipe_config] ips: 0
>[  115.614971] [drm:intel_dump_pipe_config] double wide: 0
>[  115.614972] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  115.614973] [drm:intel_dump_pipe_config] planes on this crtc
>[  115.614975] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  115.614977] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  115.614979] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  115.614981] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[  115.614982] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[  115.614984] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[  115.614985] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  115.614989] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d88000 state to ffff978ee5d8f800
>[  115.614990] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5d8d800 state to ffff978ee5d8f800
>[  115.614992] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[  115.614996] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  115.614998] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  115.614999] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  115.615001] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  115.615002] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[  115.615005] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  115.615007] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  115.615009] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  115.615015] [drm:drm_atomic_commit] commiting ffff978ee5d8f800
>[  115.616943] [drm:intel_edp_backlight_off.part.30] 
>[  115.819045] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  115.819100] [drm:intel_disable_pipe] disabling pipe A
>[  115.823698] [drm:edp_panel_off] Turn eDP port A panel power off
>[  115.823738] [drm:edp_panel_off] Wait for panel power off time
>[  115.823815] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[  115.824420] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[  115.824425] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[  115.824449] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[  115.874578] [drm:wait_panel_status] Wait complete
>[  115.874593] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[  115.874612] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  115.874614] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[  115.874631] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  115.874645] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[  115.875960] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  115.875963] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  115.875966] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[  115.876888] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  115.876892] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  115.876896] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  115.876899] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  115.876902] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  115.876905] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  115.876907] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  115.876910] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  115.876913] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  115.876915] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  115.876918] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  115.876921] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  115.876924] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  115.876926] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  115.876929] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  115.876932] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  115.876935] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  115.876938] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  115.876946] [drm:intel_power_well_disable] disabling DDI A/E power well
>[  115.876949] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  115.876954] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  115.876958] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  115.876962] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  115.876970] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f800
>[  115.876975] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f800
>[  116.467174] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[  116.467194] [drm:wait_panel_status] Wait complete
>[  116.467250] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  116.467266] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  116.516560] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  116.516567] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  116.516570] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[  116.675577] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[  116.676677] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  116.881120] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[  116.881127] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee67d5a80 state to ffff978ee5d8e000
>[  116.881132] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f800 state to ffff978ee5d8e000
>[  116.881135] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee67d5a80 to [NOCRTC]
>[  116.881137] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee67d5a80
>[  116.881140] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[  116.881152] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[  116.881162] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[  116.881167] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[  116.881178] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  116.881184] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[  116.881187] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[  116.881190] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d000 state to ffff978ee5d8e000
>[  116.881193] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee67d5d80 state to ffff978ee5d8e000
>[  116.881197] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5d8d000
>[  116.881200] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee67d5d80 to [CRTC:26:pipe A]
>[  116.881202] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffff978ee67d5d80
>[  116.881205] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8e000
>[  116.881209] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656c8a0 state to ffff978ee5d8e000
>[  116.881212] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978ee656c8a0 to [NOCRTC]
>[  116.881215] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978ee656c8a0 to [CRTC:26:pipe A]
>[  116.881218] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[  116.881223] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[  116.881226] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[  116.881228] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  116.881230] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[  116.881233] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8e000
>[  116.881237] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8e000
>[  116.881241] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  116.881243] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  116.881251] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  116.881256] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  116.881266] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  116.881270] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  116.881273] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  116.881277] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d8d000 for pipe A
>[  116.881279] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  116.881281] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  116.881284] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  116.881287] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  116.881290] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  116.881292] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  116.881294] [drm:intel_dump_pipe_config] requested mode:
>[  116.881299] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  116.881301] [drm:intel_dump_pipe_config] adjusted mode:
>[  116.881305] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  116.881309] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  116.881311] [drm:intel_dump_pipe_config] port clock: 540000
>[  116.881313] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  116.881315] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  116.881318] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  116.881320] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  116.881322] [drm:intel_dump_pipe_config] ips: 0
>[  116.881324] [drm:intel_dump_pipe_config] double wide: 0
>[  116.881327] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  116.881328] [drm:intel_dump_pipe_config] planes on this crtc
>[  116.881332] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  116.881335] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  116.881339] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  116.881341] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  116.881343] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  116.881350] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee88b8800 state to ffff978ee5d8e000
>[  116.881353] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee88be800 state to ffff978ee5d8e000
>[  116.881355] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[  116.881361] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  116.881364] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  116.881367] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[  116.881372] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  116.881375] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  116.881379] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  116.881391] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[  116.881402] [drm:intel_power_well_enable] enabling DDI A/E power well
>[  116.881407] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  116.881414] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[  116.882973] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  116.882978] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  116.882982] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  116.882987] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  116.882990] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  116.882993] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  116.882996] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  116.882999] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  116.883002] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  116.883005] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  116.883008] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  116.883012] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  116.883014] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  116.883017] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  116.883020] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  116.883025] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  116.883028] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  116.883031] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  116.883036] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[  116.883039] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[  116.883053] [drm:edp_panel_on] Turn eDP port A panel power on
>[  116.883072] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  116.883150] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[  116.883168] [drm:wait_panel_status] Wait complete
>[  116.883202] [drm:edp_panel_on] Wait for panel power on
>[  116.883278] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[  117.083958] [drm:wait_panel_status] Wait complete
>[  117.085125] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  117.085128] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  117.085130] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  117.085133] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[  117.085806] [drm:intel_dp_start_link_train] clock recovery OK
>[  117.085809] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[  117.085811] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[  117.086786] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[  117.086788] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  117.086790] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  117.087748] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[  117.087914] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5d8d000
>[  117.087988] [drm:intel_enable_pipe] enabling pipe A
>[  117.087994] [drm:intel_edp_backlight_on.part.29] 
>[  117.087996] [drm:intel_panel_enable_backlight] pipe A
>[  117.088075] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  117.088129] [drm:intel_psr_enable] PSR disable by flag
>[  117.088130] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  117.105042] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  117.105050] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  117.105064] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  117.105070] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[  117.105074] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[  117.105099] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[  117.105101] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d800 state to ffff978ee5d8e000
>[  117.105103] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[  117.105109] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[  117.121650] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[  117.121654] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[  117.121683] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[  117.121685] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  117.121826] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[  117.121830] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee67d5c00 state to ffff978ee5d8e000
>[  117.121833] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d000 state to ffff978ee5d8e000
>[  117.121834] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee67d5c00 to [CRTC:26:pipe A]
>[  117.121836] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee67d5c00
>[  117.121838] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[  117.121844] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  117.121846] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[  117.121855] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[  117.121882] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[  117.121884] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[  117.262665] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d800
>[  117.262670] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d88000 state to ffff978ee5d8d800
>[  117.262673] [drm:drm_atomic_check_only] checking ffff978ee5d8d800
>[  117.262676] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  117.262678] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[  117.262680] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[  117.262686] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656ca20 state to ffff978ee5d8d800
>[  117.262696] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee663e840 state to ffff978ee5d8d800
>[  117.262698] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee663e000 state to ffff978ee5d8d800
>[  117.262702] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[  117.262714] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  117.262716] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  117.262730] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  117.262734] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  117.262741] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  117.262743] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  117.262745] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  117.262747] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d88000 for pipe A
>[  117.262749] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  117.262751] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  117.262752] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  117.262754] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  117.262756] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  117.262757] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  117.262758] [drm:intel_dump_pipe_config] requested mode:
>[  117.262762] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  117.262763] [drm:intel_dump_pipe_config] adjusted mode:
>[  117.262766] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  117.262768] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  117.262769] [drm:intel_dump_pipe_config] port clock: 540000
>[  117.262770] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  117.262772] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  117.262773] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  117.262775] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  117.262776] [drm:intel_dump_pipe_config] ips: 0
>[  117.262777] [drm:intel_dump_pipe_config] double wide: 0
>[  117.262793] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  117.262795] [drm:intel_dump_pipe_config] planes on this crtc
>[  117.262797] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  117.262799] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  117.262802] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  117.262804] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[  117.262806] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[  117.262808] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[  117.262810] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  117.262814] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d8f800 state to ffff978ee5d8d800
>[  117.262817] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5d8e000 state to ffff978ee5d8d800
>[  117.262819] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[  117.262824] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  117.262826] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  117.262828] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  117.262830] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  117.262832] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[  117.262835] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  117.262838] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  117.262841] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  117.262848] [drm:drm_atomic_commit] commiting ffff978ee5d8d800
>[  117.263964] [drm:intel_edp_backlight_off.part.30] 
>[  117.467048] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  117.467105] [drm:intel_disable_pipe] disabling pipe A
>[  117.473598] [drm:edp_panel_off] Turn eDP port A panel power off
>[  117.473639] [drm:edp_panel_off] Wait for panel power off time
>[  117.473716] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[  117.474306] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[  117.474312] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[  117.474336] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[  117.524330] [drm:wait_panel_status] Wait complete
>[  117.524347] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[  117.524352] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[  117.524370] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[  117.524414] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  117.524432] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  117.526081] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  117.526086] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  117.526090] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[  117.530868] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  117.530874] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  117.530878] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  117.530884] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  117.530887] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  117.530889] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  117.530892] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  117.530903] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  117.530906] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  117.530909] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  117.530911] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  117.530914] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  117.530917] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  117.530920] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  117.530923] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  117.530926] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  117.530929] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  117.530932] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  117.530940] [drm:intel_power_well_disable] disabling DDI A/E power well
>[  117.530944] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  117.530949] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  117.530953] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  117.530957] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  117.530965] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d800
>[  117.530971] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d800
>[  118.131069] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[  118.131089] [drm:wait_panel_status] Wait complete
>[  118.131144] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  118.131157] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  118.188206] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  118.188211] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  118.188215] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[  118.339655] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[  118.340751] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  118.535687] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d800
>[  118.535693] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee663e3c0 state to ffff978ee5d8d800
>[  118.535697] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d000 state to ffff978ee5d8d800
>[  118.535700] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee663e3c0 to [NOCRTC]
>[  118.535702] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee663e3c0
>[  118.535705] [drm:drm_atomic_check_only] checking ffff978ee5d8d800
>[  118.535716] [drm:drm_atomic_commit] commiting ffff978ee5d8d800
>[  118.535725] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d800
>[  118.535729] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d800
>[  118.535739] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  118.535744] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[  118.535747] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d800
>[  118.535750] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d88000 state to ffff978ee5d8d800
>[  118.535753] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee663e000 state to ffff978ee5d8d800
>[  118.535756] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5d88000
>[  118.535759] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee663e000 to [CRTC:26:pipe A]
>[  118.535761] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffff978ee663e000
>[  118.535764] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[  118.535768] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978ee656c8a0 state to ffff978ee5d8d800
>[  118.535772] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978ee656c8a0 to [NOCRTC]
>[  118.535774] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978ee656c8a0 to [CRTC:26:pipe A]
>[  118.535776] [drm:drm_atomic_check_only] checking ffff978ee5d8d800
>[  118.535781] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[  118.535784] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[  118.535786] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  118.535788] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[  118.535791] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[  118.535794] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5d8d800
>[  118.535798] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  118.535800] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  118.535808] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  118.535813] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  118.535822] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  118.535825] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  118.535828] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  118.535831] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5d88000 for pipe A
>[  118.535834] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  118.535836] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  118.535839] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  118.535841] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  118.535844] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  118.535846] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  118.535848] [drm:intel_dump_pipe_config] requested mode:
>[  118.535852] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  118.535854] [drm:intel_dump_pipe_config] adjusted mode:
>[  118.535858] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  118.535861] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  118.535863] [drm:intel_dump_pipe_config] port clock: 540000
>[  118.535865] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  118.535867] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  118.535869] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  118.535872] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  118.535873] [drm:intel_dump_pipe_config] ips: 0
>[  118.535875] [drm:intel_dump_pipe_config] double wide: 0
>[  118.535877] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  118.535879] [drm:intel_dump_pipe_config] planes on this crtc
>[  118.535882] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  118.535885] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  118.535888] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  118.535891] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  118.535893] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  118.535899] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5d8f000 state to ffff978ee5d8d800
>[  118.535902] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee88be800 state to ffff978ee5d8d800
>[  118.535911] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[  118.535917] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  118.535919] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  118.535922] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[  118.535926] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  118.535929] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  118.535933] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  118.535944] [drm:drm_atomic_commit] commiting ffff978ee5d8d800
>[  118.535956] [drm:intel_power_well_enable] enabling DDI A/E power well
>[  118.535961] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  118.535967] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[  118.537983] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  118.537987] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  118.537991] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  118.537996] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  118.537999] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  118.538001] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  118.538004] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  118.538007] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  118.538010] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  118.538013] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  118.538016] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  118.538019] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  118.538021] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  118.538024] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  118.538027] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  118.538031] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  118.538034] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  118.538037] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  118.538042] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[  118.538044] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[  118.538058] [drm:edp_panel_on] Turn eDP port A panel power on
>[  118.538077] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  118.538154] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[  118.538171] [drm:wait_panel_status] Wait complete
>[  118.538205] [drm:edp_panel_on] Wait for panel power on
>[  118.538280] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[  118.739704] [drm:wait_panel_status] Wait complete
>[  118.740887] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  118.740890] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  118.740892] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  118.740895] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[  118.741576] [drm:intel_dp_start_link_train] clock recovery OK
>[  118.741579] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[  118.741581] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[  118.742556] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[  118.742558] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  118.742559] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  118.743522] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[  118.743697] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5d88000
>[  118.743771] [drm:intel_enable_pipe] enabling pipe A
>[  118.743777] [drm:intel_edp_backlight_on.part.29] 
>[  118.743779] [drm:intel_panel_enable_backlight] pipe A
>[  118.743858] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  118.743913] [drm:intel_psr_enable] PSR disable by flag
>[  118.743914] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  118.760583] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  118.760588] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  118.760601] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  118.760607] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d800
>[  118.760610] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d800
>[  118.760632] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88b8800
>[  118.760635] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d800 state to ffff978ee88b8800
>[  118.760636] [drm:drm_atomic_check_only] checking ffff978ee88b8800
>[  118.760642] [drm:drm_atomic_commit] commiting ffff978ee88b8800
>[  118.777140] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee88b8800
>[  118.777142] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee88b8800
>[  118.777186] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[  118.777188] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  118.777300] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5652800
>[  118.777302] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee9090780 state to ffff978ee5652800
>[  118.777304] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5650000 state to ffff978ee5652800
>[  118.777306] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee9090780 to [CRTC:26:pipe A]
>[  118.777307] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee9090780
>[  118.777309] [drm:drm_atomic_check_only] checking ffff978ee5652800
>[  118.777313] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  118.777314] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[  118.777319] [drm:drm_atomic_commit] commiting ffff978ee5652800
>[  118.777337] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5652800
>[  118.777338] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5652800
>[  118.906221] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5652000
>[  118.906225] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5654000 state to ffff978ee5652000
>[  118.906227] [drm:drm_atomic_check_only] checking ffff978ee5652000
>[  118.906229] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  118.906230] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[  118.906232] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5652000
>[  118.906234] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2ce20 state to ffff978ee5652000
>[  118.906236] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee56e6f00 state to ffff978ee5652000
>[  118.906237] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee56e6540 state to ffff978ee5652000
>[  118.906239] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5652000
>[  118.906241] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  118.906242] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  118.906246] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  118.906249] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  118.906254] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  118.906256] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  118.906258] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  118.906260] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5654000 for pipe A
>[  118.906261] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  118.906262] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  118.906263] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  118.906265] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  118.906266] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  118.906267] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  118.906268] [drm:intel_dump_pipe_config] requested mode:
>[  118.906271] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  118.906272] [drm:intel_dump_pipe_config] adjusted mode:
>[  118.906273] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  118.906275] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  118.906276] [drm:intel_dump_pipe_config] port clock: 540000
>[  118.906277] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  118.906278] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  118.906279] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  118.906281] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  118.906281] [drm:intel_dump_pipe_config] ips: 0
>[  118.906282] [drm:intel_dump_pipe_config] double wide: 0
>[  118.906283] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  118.906284] [drm:intel_dump_pipe_config] planes on this crtc
>[  118.906286] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  118.906288] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  118.906289] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  118.906291] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[  118.906292] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[  118.906293] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[  118.906294] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  118.906298] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5650800 state to ffff978ee5652000
>[  118.906299] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5651800 state to ffff978ee5652000
>[  118.906300] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[  118.906304] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  118.906306] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  118.906307] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  118.906308] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  118.906310] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[  118.906312] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  118.906314] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  118.906316] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  118.906321] [drm:drm_atomic_commit] commiting ffff978ee5652000
>[  118.907985] [drm:intel_edp_backlight_off.part.30] 
>[  119.115069] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  119.115123] [drm:intel_disable_pipe] disabling pipe A
>[  119.128527] [drm:edp_panel_off] Turn eDP port A panel power off
>[  119.128568] [drm:edp_panel_off] Wait for panel power off time
>[  119.128645] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[  119.129252] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[  119.129257] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[  119.129281] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[  119.179310] [drm:wait_panel_status] Wait complete
>[  119.179326] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[  119.179347] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  119.179349] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[  119.179367] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  119.179383] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[  119.180974] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  119.180980] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  119.180983] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[  119.186043] [drm:skl_pcode_request] PCODE timeout, retrying with preemption disabled
>[  119.188299] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  119.188304] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  119.188309] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  119.188314] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  119.188317] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  119.188320] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  119.188323] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  119.188326] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  119.188329] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  119.188332] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  119.188335] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  119.188338] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  119.188341] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  119.188344] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  119.188347] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  119.188351] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  119.188354] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  119.188357] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  119.188366] [drm:intel_power_well_disable] disabling DDI A/E power well
>[  119.188370] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  119.188374] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  119.188379] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  119.188383] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  119.188392] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5652000
>[  119.188399] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5652000
>[  119.731475] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000
>[  119.740363] [drm:wait_panel_status] Wait complete
>[  119.740427] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  119.740444] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  119.789766] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  119.789772] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  119.789775] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[  119.947610] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[  119.948710] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  120.192945] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee67e3800
>[  120.192951] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee663e9c0 state to ffff978ee67e3800
>[  120.192955] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee67e5800 state to ffff978ee67e3800
>[  120.192957] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee663e9c0 to [NOCRTC]
>[  120.192960] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee663e9c0
>[  120.192962] [drm:drm_atomic_check_only] checking ffff978ee67e3800
>[  120.192974] [drm:drm_atomic_commit] commiting ffff978ee67e3800
>[  120.192983] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee67e3800
>[  120.192987] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee67e3800
>[  120.192996] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  120.193002] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[  120.193005] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee67e3800
>[  120.193008] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee67e5000 state to ffff978ee67e3800
>[  120.193010] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee663e840 state to ffff978ee67e3800
>[  120.193014] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee67e5000
>[  120.193016] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee663e840 to [CRTC:26:pipe A]
>[  120.193018] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffff978ee663e840
>[  120.193021] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee67e3800
>[  120.193024] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eeb567cc0 state to ffff978ee67e3800
>[  120.193027] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eeb567cc0 to [NOCRTC]
>[  120.193029] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eeb567cc0 to [CRTC:26:pipe A]
>[  120.193031] [drm:drm_atomic_check_only] checking ffff978ee67e3800
>[  120.193036] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[  120.193038] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[  120.193040] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  120.193042] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[  120.193044] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee67e3800
>[  120.193047] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee67e3800
>[  120.193051] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  120.193053] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  120.193060] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  120.193065] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  120.193073] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  120.193076] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  120.193079] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  120.193082] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee67e5000 for pipe A
>[  120.193084] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  120.193086] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  120.193089] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  120.193091] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  120.193094] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  120.193096] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  120.193097] [drm:intel_dump_pipe_config] requested mode:
>[  120.193102] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  120.193103] [drm:intel_dump_pipe_config] adjusted mode:
>[  120.193107] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  120.193110] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  120.193112] [drm:intel_dump_pipe_config] port clock: 540000
>[  120.193114] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  120.193116] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  120.193118] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  120.193120] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  120.193122] [drm:intel_dump_pipe_config] ips: 0
>[  120.193123] [drm:intel_dump_pipe_config] double wide: 0
>[  120.193125] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  120.193127] [drm:intel_dump_pipe_config] planes on this crtc
>[  120.193130] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  120.193133] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  120.193136] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  120.193138] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  120.193140] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  120.193145] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee67e6000 state to ffff978ee67e3800
>[  120.193148] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee67e7800 state to ffff978ee67e3800
>[  120.193150] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[  120.193155] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  120.193157] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  120.193160] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[  120.193164] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  120.193167] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  120.193170] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  120.193180] [drm:drm_atomic_commit] commiting ffff978ee67e3800
>[  120.193191] [drm:intel_power_well_enable] enabling DDI A/E power well
>[  120.193195] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  120.193201] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[  120.194932] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  120.194935] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  120.194938] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  120.194942] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  120.194945] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  120.194947] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  120.194950] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  120.194953] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  120.194955] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  120.194958] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  120.194960] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  120.194963] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  120.194966] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  120.194968] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  120.194971] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  120.194975] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  120.194978] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  120.194980] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  120.194985] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[  120.194987] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[  120.195000] [drm:edp_panel_on] Turn eDP port A panel power on
>[  120.195018] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  120.195095] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[  120.195112] [drm:wait_panel_status] Wait complete
>[  120.195146] [drm:edp_panel_on] Wait for panel power on
>[  120.195221] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[  120.396770] [drm:wait_panel_status] Wait complete
>[  120.397940] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  120.397943] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  120.397945] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  120.397947] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[  120.398616] [drm:intel_dp_start_link_train] clock recovery OK
>[  120.398618] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[  120.398620] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[  120.399584] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[  120.399585] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  120.399585] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  120.400529] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[  120.400694] [drm:skylake_pfit_enable] for crtc_state = ffff978ee67e5000
>[  120.400767] [drm:intel_enable_pipe] enabling pipe A
>[  120.400773] [drm:intel_edp_backlight_on.part.29] 
>[  120.400775] [drm:intel_panel_enable_backlight] pipe A
>[  120.400854] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  120.400907] [drm:intel_psr_enable] PSR disable by flag
>[  120.400908] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  120.417741] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  120.417748] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  120.417762] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  120.417768] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee67e3800
>[  120.417772] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee67e3800
>[  120.417797] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d000
>[  120.417799] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8e000 state to ffff978ee5d8d000
>[  120.417801] [drm:drm_atomic_check_only] checking ffff978ee5d8d000
>[  120.417806] [drm:drm_atomic_commit] commiting ffff978ee5d8d000
>[  120.434277] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d000
>[  120.434282] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d000
>[  120.434311] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[  120.434313] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  120.434437] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8d000
>[  120.434441] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee504b600 state to ffff978ee5d8d000
>[  120.434444] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f000 state to ffff978ee5d8d000
>[  120.434445] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee504b600 to [CRTC:26:pipe A]
>[  120.434447] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee504b600
>[  120.434448] [drm:drm_atomic_check_only] checking ffff978ee5d8d000
>[  120.434454] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  120.434456] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[  120.434463] [drm:drm_atomic_commit] commiting ffff978ee5d8d000
>[  120.434489] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8d000
>[  120.434492] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8d000
>[  120.578312] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88d9000
>[  120.578315] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee88db000 state to ffff978ee88d9000
>[  120.578317] [drm:drm_atomic_check_only] checking ffff978ee88d9000
>[  120.578320] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  120.578321] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[  120.578322] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88d9000
>[  120.578324] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebbb2200 state to ffff978ee88d9000
>[  120.578326] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee56a2600 state to ffff978ee88d9000
>[  120.578328] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee56a29c0 state to ffff978ee88d9000
>[  120.578329] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88d9000
>[  120.578331] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  120.578332] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  120.578337] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  120.578340] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  120.578345] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  120.578346] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  120.578348] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  120.578350] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee88db000 for pipe A
>[  120.578354] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  120.578355] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  120.578357] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  120.578358] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  120.578359] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  120.578360] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  120.578361] [drm:intel_dump_pipe_config] requested mode:
>[  120.578370] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  120.578371] [drm:intel_dump_pipe_config] adjusted mode:
>[  120.578373] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  120.578375] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  120.578375] [drm:intel_dump_pipe_config] port clock: 540000
>[  120.578376] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  120.578378] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  120.578379] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  120.578380] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  120.578381] [drm:intel_dump_pipe_config] ips: 0
>[  120.578382] [drm:intel_dump_pipe_config] double wide: 0
>[  120.578383] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  120.578384] [drm:intel_dump_pipe_config] planes on this crtc
>[  120.578385] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  120.578387] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  120.578389] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  120.578390] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[  120.578391] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[  120.578393] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[  120.578394] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  120.578397] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee88db800 state to ffff978ee88d9000
>[  120.578398] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee88d8000 state to ffff978ee88d9000
>[  120.578400] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[  120.578404] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  120.578405] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  120.578406] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  120.578407] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  120.578409] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[  120.578411] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  120.578413] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  120.578415] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  120.578419] [drm:drm_atomic_commit] commiting ffff978ee88d9000
>[  120.580061] [drm:intel_edp_backlight_off.part.30] 
>[  120.787161] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  120.787218] [drm:intel_disable_pipe] disabling pipe A
>[  120.802462] [drm:edp_panel_off] Turn eDP port A panel power off
>[  120.802500] [drm:edp_panel_off] Wait for panel power off time
>[  120.802576] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[  120.803177] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[  120.803182] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[  120.803207] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[  120.853339] [drm:wait_panel_status] Wait complete
>[  120.853355] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[  120.853374] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  120.853377] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[  120.853394] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  120.853409] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[  120.854927] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  120.854933] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  120.854936] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[  120.860172] [drm:skl_pcode_request] PCODE timeout, retrying with preemption disabled
>[  120.864674] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  120.864680] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  120.864684] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  120.864690] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  120.864693] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  120.864696] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  120.864699] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  120.864702] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  120.864705] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  120.864708] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  120.864711] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  120.864714] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  120.864717] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  120.864719] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  120.864722] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  120.864726] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  120.864730] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  120.864733] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  120.864742] [drm:intel_power_well_disable] disabling DDI A/E power well
>[  120.864746] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  120.864750] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  120.864755] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  120.864759] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  120.864768] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee88d9000
>[  120.864774] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee88d9000
>[  121.459335] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[  121.459356] [drm:wait_panel_status] Wait complete
>[  121.459417] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  121.459435] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  121.508839] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  121.508845] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  121.508848] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[  121.667739] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[  121.668857] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  121.869458] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5652000
>[  121.869464] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee671a300 state to ffff978ee5652000
>[  121.869469] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5650000 state to ffff978ee5652000
>[  121.869471] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee671a300 to [NOCRTC]
>[  121.869474] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee671a300
>[  121.869477] [drm:drm_atomic_check_only] checking ffff978ee5652000
>[  121.869489] [drm:drm_atomic_commit] commiting ffff978ee5652000
>[  121.869500] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5652000
>[  121.869504] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5652000
>[  121.869515] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  121.869521] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[  121.869524] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5652000
>[  121.869528] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5651800 state to ffff978ee5652000
>[  121.869531] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee671a480 state to ffff978ee5652000
>[  121.869535] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5651800
>[  121.869537] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee671a480 to [CRTC:26:pipe A]
>[  121.869540] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffff978ee671a480
>[  121.869543] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5652000
>[  121.869547] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2ce80 state to ffff978ee5652000
>[  121.869550] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2ce80 to [NOCRTC]
>[  121.869553] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2ce80 to [CRTC:26:pipe A]
>[  121.869555] [drm:drm_atomic_check_only] checking ffff978ee5652000
>[  121.869560] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[  121.869564] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[  121.869566] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  121.869568] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[  121.869571] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5652000
>[  121.869575] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5652000
>[  121.869579] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  121.869581] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  121.869590] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  121.869595] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  121.869605] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  121.869608] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  121.869611] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  121.869615] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5651800 for pipe A
>[  121.869618] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  121.869620] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  121.869623] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  121.869626] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  121.869628] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  121.869631] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  121.869633] [drm:intel_dump_pipe_config] requested mode:
>[  121.869638] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  121.869640] [drm:intel_dump_pipe_config] adjusted mode:
>[  121.869644] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  121.869647] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  121.869649] [drm:intel_dump_pipe_config] port clock: 540000
>[  121.869651] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  121.869654] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  121.869656] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  121.869659] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  121.869661] [drm:intel_dump_pipe_config] ips: 0
>[  121.869663] [drm:intel_dump_pipe_config] double wide: 0
>[  121.869665] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  121.869667] [drm:intel_dump_pipe_config] planes on this crtc
>[  121.869670] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  121.869674] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  121.869677] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  121.869679] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  121.869682] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  121.869687] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5650800 state to ffff978ee5652000
>[  121.869690] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5654000 state to ffff978ee5652000
>[  121.869692] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[  121.869699] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  121.869702] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  121.869704] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[  121.869709] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  121.869712] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  121.869716] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  121.869727] [drm:drm_atomic_commit] commiting ffff978ee5652000
>[  121.869739] [drm:intel_power_well_enable] enabling DDI A/E power well
>[  121.869744] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  121.869751] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[  121.873012] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  121.873017] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  121.873021] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  121.873025] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  121.873028] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  121.873031] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  121.873034] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  121.873037] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  121.873040] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  121.873043] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  121.873046] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  121.873049] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  121.873051] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  121.873054] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  121.873057] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  121.873061] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  121.873064] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  121.873067] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  121.873073] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[  121.873075] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[  121.873089] [drm:edp_panel_on] Turn eDP port A panel power on
>[  121.873140] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  121.873223] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[  121.873240] [drm:wait_panel_status] Wait complete
>[  121.873274] [drm:edp_panel_on] Wait for panel power on
>[  121.873350] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[  122.075262] [drm:wait_panel_status] Wait complete
>[  122.076414] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  122.076417] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  122.076418] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  122.076422] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[  122.077096] [drm:intel_dp_start_link_train] clock recovery OK
>[  122.077099] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[  122.077101] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[  122.078074] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[  122.078076] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  122.078077] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  122.079039] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[  122.079213] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5651800
>[  122.079314] [drm:intel_enable_pipe] enabling pipe A
>[  122.079324] [drm:intel_edp_backlight_on.part.29] 
>[  122.079328] [drm:intel_panel_enable_backlight] pipe A
>[  122.079410] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  122.079466] [drm:intel_psr_enable] PSR disable by flag
>[  122.079468] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  122.096211] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  122.096222] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  122.096242] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  122.096252] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5652000
>[  122.096259] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5652000
>[  122.096292] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[  122.096296] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d000 state to ffff978ee5d8e000
>[  122.096298] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[  122.096307] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[  122.112979] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[  122.112986] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[  122.113022] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[  122.113026] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  122.113196] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8e000
>[  122.113201] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee8a71300 state to ffff978ee5d8e000
>[  122.113205] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d800 state to ffff978ee5d8e000
>[  122.113207] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee8a71300 to [CRTC:26:pipe A]
>[  122.113210] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee8a71300
>[  122.113212] [drm:drm_atomic_check_only] checking ffff978ee5d8e000
>[  122.113220] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  122.113223] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[  122.113233] [drm:drm_atomic_commit] commiting ffff978ee5d8e000
>[  122.113263] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8e000
>[  122.113268] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8e000
>[  122.242205] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5652800
>[  122.242209] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5656800 state to ffff978ee5652800
>[  122.242212] [drm:drm_atomic_check_only] checking ffff978ee5652800
>[  122.242215] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  122.242216] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[  122.242218] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5652800
>[  122.242221] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2c500 state to ffff978ee5652800
>[  122.242223] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee5d0db40 state to ffff978ee5652800
>[  122.242225] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee8700780 state to ffff978ee5652800
>[  122.242227] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5652800
>[  122.242229] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  122.242230] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  122.242236] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  122.242239] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  122.242244] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  122.242246] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  122.242248] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  122.242250] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5656800 for pipe A
>[  122.242252] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  122.242253] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  122.242254] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  122.242270] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  122.242272] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  122.242273] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  122.242274] [drm:intel_dump_pipe_config] requested mode:
>[  122.242277] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  122.242279] [drm:intel_dump_pipe_config] adjusted mode:
>[  122.242281] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  122.242283] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  122.242284] [drm:intel_dump_pipe_config] port clock: 540000
>[  122.242286] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  122.242287] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  122.242289] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  122.242290] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  122.242291] [drm:intel_dump_pipe_config] ips: 0
>[  122.242292] [drm:intel_dump_pipe_config] double wide: 0
>[  122.242294] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  122.242295] [drm:intel_dump_pipe_config] planes on this crtc
>[  122.242297] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  122.242299] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  122.242301] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  122.242303] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[  122.242304] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[  122.242306] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[  122.242308] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  122.242312] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5655800 state to ffff978ee5652800
>[  122.242314] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5655000 state to ffff978ee5652800
>[  122.242315] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[  122.242320] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  122.242322] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  122.242324] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  122.242326] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  122.242327] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[  122.242331] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  122.242333] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  122.242335] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  122.242342] [drm:drm_atomic_commit] commiting ffff978ee5652800
>[  122.243999] [drm:intel_edp_backlight_off.part.30] 
>[  122.451164] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  122.451223] [drm:intel_disable_pipe] disabling pipe A
>[  122.464093] [drm:edp_panel_off] Turn eDP port A panel power off
>[  122.464131] [drm:edp_panel_off] Wait for panel power off time
>[  122.464209] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[  122.464734] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[  122.464740] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[  122.464765] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[  122.516006] [drm:wait_panel_status] Wait complete
>[  122.516023] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[  122.516042] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[  122.516046] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  122.516063] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  122.516079] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[  122.516565] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  122.516571] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  122.516574] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[  122.520519] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  122.520525] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  122.520530] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  122.520536] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  122.520539] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  122.520542] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  122.520545] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  122.520549] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  122.520552] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  122.520554] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  122.520558] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  122.520561] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  122.520564] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  122.520567] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  122.520570] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  122.520575] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  122.520578] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  122.520582] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  122.520591] [drm:intel_power_well_disable] disabling DDI A/E power well
>[  122.520595] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  122.520600] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  122.520605] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  122.520609] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  122.520619] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5652800
>[  122.520626] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5652800
>[  123.123242] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[  123.123263] [drm:wait_panel_status] Wait complete
>[  123.123323] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  123.123337] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  123.172646] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  123.172652] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  123.172655] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[  123.331629] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[  123.332727] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  123.525124] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee67e6800
>[  123.525131] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee623f840 state to ffff978ee67e6800
>[  123.525135] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee67e3000 state to ffff978ee67e6800
>[  123.525138] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee623f840 to [NOCRTC]
>[  123.525141] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee623f840
>[  123.525144] [drm:drm_atomic_check_only] checking ffff978ee67e6800
>[  123.525156] [drm:drm_atomic_commit] commiting ffff978ee67e6800
>[  123.525167] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee67e6800
>[  123.525171] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee67e6800
>[  123.525182] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  123.525187] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[  123.525190] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee67e6800
>[  123.525194] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee67e5000 state to ffff978ee67e6800
>[  123.525197] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee623f600 state to ffff978ee67e6800
>[  123.525200] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee67e5000
>[  123.525203] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee623f600 to [CRTC:26:pipe A]
>[  123.525206] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffff978ee623f600
>[  123.525208] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee67e6800
>[  123.525212] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebaf71c0 state to ffff978ee67e6800
>[  123.525216] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebaf71c0 to [NOCRTC]
>[  123.525219] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebaf71c0 to [CRTC:26:pipe A]
>[  123.525221] [drm:drm_atomic_check_only] checking ffff978ee67e6800
>[  123.525226] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[  123.525229] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[  123.525232] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  123.525234] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[  123.525237] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee67e6800
>[  123.525241] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee67e6800
>[  123.525244] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  123.525246] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  123.525254] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  123.525260] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  123.525269] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  123.525273] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  123.525276] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  123.525280] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee67e5000 for pipe A
>[  123.525283] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  123.525285] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  123.525288] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  123.525291] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  123.525293] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  123.525296] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  123.525298] [drm:intel_dump_pipe_config] requested mode:
>[  123.525303] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  123.525304] [drm:intel_dump_pipe_config] adjusted mode:
>[  123.525309] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  123.525312] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  123.525314] [drm:intel_dump_pipe_config] port clock: 540000
>[  123.525316] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  123.525319] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  123.525321] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  123.525324] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  123.525326] [drm:intel_dump_pipe_config] ips: 0
>[  123.525328] [drm:intel_dump_pipe_config] double wide: 0
>[  123.525330] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  123.525332] [drm:intel_dump_pipe_config] planes on this crtc
>[  123.525335] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  123.525339] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  123.525342] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  123.525344] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  123.525347] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  123.525352] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee67e3800 state to ffff978ee67e6800
>[  123.525355] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee67e5800 state to ffff978ee67e6800
>[  123.525357] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[  123.525364] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  123.525366] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  123.525369] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[  123.525374] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  123.525376] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  123.525381] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  123.525392] [drm:drm_atomic_commit] commiting ffff978ee67e6800
>[  123.525403] [drm:intel_power_well_enable] enabling DDI A/E power well
>[  123.525407] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  123.525414] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[  123.526961] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  123.526965] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  123.526968] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  123.526973] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  123.526976] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  123.526979] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  123.526982] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  123.526985] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  123.526988] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  123.526991] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  123.526994] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  123.526997] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  123.527000] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  123.527003] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  123.527006] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  123.527010] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  123.527014] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  123.527017] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  123.527022] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[  123.527024] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[  123.527039] [drm:edp_panel_on] Turn eDP port A panel power on
>[  123.527058] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  123.527135] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[  123.527153] [drm:wait_panel_status] Wait complete
>[  123.527187] [drm:edp_panel_on] Wait for panel power on
>[  123.527262] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[  123.728684] [drm:wait_panel_status] Wait complete
>[  123.729849] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  123.729852] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  123.729854] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  123.729857] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[  123.730533] [drm:intel_dp_start_link_train] clock recovery OK
>[  123.730536] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[  123.730538] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[  123.731512] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[  123.731514] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  123.731515] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  123.732478] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[  123.732653] [drm:skylake_pfit_enable] for crtc_state = ffff978ee67e5000
>[  123.732758] [drm:intel_enable_pipe] enabling pipe A
>[  123.732769] [drm:intel_edp_backlight_on.part.29] 
>[  123.732773] [drm:intel_panel_enable_backlight] pipe A
>[  123.732855] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  123.732928] [drm:intel_psr_enable] PSR disable by flag
>[  123.732929] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  123.749607] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  123.749613] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  123.749625] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  123.749631] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee67e6800
>[  123.749635] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee67e6800
>[  123.749657] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d8f800
>[  123.749660] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d000 state to ffff978ee5d8f800
>[  123.749661] [drm:drm_atomic_check_only] checking ffff978ee5d8f800
>[  123.749666] [drm:drm_atomic_commit] commiting ffff978ee5d8f800
>[  123.766167] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d8f800
>[  123.766171] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d8f800
>[  123.766194] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[  123.766196] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  123.766294] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88df000
>[  123.766298] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee97d9000 state to ffff978ee88df000
>[  123.766301] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee88de000 state to ffff978ee88df000
>[  123.766303] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee97d9000 to [CRTC:26:pipe A]
>[  123.766305] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee97d9000
>[  123.766307] [drm:drm_atomic_check_only] checking ffff978ee88df000
>[  123.766313] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  123.766315] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[  123.766323] [drm:drm_atomic_commit] commiting ffff978ee88df000
>[  123.766347] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee88df000
>[  123.766349] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee88df000
>[  123.909920] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88da000
>[  123.909927] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee88dd000 state to ffff978ee88da000
>[  123.909930] [drm:drm_atomic_check_only] checking ffff978ee88da000
>[  123.909935] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  123.909938] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[  123.909941] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88da000
>[  123.909945] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebbb2340 state to ffff978ee88da000
>[  123.909948] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee97d90c0 state to ffff978ee88da000
>[  123.909971] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee97d9180 state to ffff978ee88da000
>[  123.909977] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88da000
>[  123.909982] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  123.909984] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  123.909992] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  123.909997] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  123.910006] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  123.910009] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  123.910012] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  123.910016] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee88dd000 for pipe A
>[  123.910018] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  123.910020] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  123.910023] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  123.910026] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  123.910029] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  123.910031] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  123.910032] [drm:intel_dump_pipe_config] requested mode:
>[  123.910038] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  123.910039] [drm:intel_dump_pipe_config] adjusted mode:
>[  123.910043] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  123.910046] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  123.910048] [drm:intel_dump_pipe_config] port clock: 540000
>[  123.910050] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  123.910053] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  123.910055] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  123.910057] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  123.910059] [drm:intel_dump_pipe_config] ips: 0
>[  123.910061] [drm:intel_dump_pipe_config] double wide: 0
>[  123.910063] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  123.910065] [drm:intel_dump_pipe_config] planes on this crtc
>[  123.910068] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  123.910071] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  123.910074] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  123.910077] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[  123.910079] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[  123.910082] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[  123.910085] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  123.910090] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee88df000 state to ffff978ee88da000
>[  123.910093] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee88de800 state to ffff978ee88da000
>[  123.910095] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[  123.910101] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  123.910104] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  123.910106] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  123.910109] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  123.910111] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[  123.910116] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  123.910119] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  123.910123] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  123.910133] [drm:drm_atomic_commit] commiting ffff978ee88da000
>[  123.912021] [drm:intel_edp_backlight_off.part.30] 
>[  124.115044] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  124.115103] [drm:intel_disable_pipe] disabling pipe A
>[  124.117564] [drm:edp_panel_off] Turn eDP port A panel power off
>[  124.117604] [drm:edp_panel_off] Wait for panel power off time
>[  124.117681] [drm:wait_panel_status] mask b0000000 value 00000000 status a0000003 control 00000000
>[  124.118251] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[  124.118256] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[  124.118281] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[  124.168471] [drm:wait_panel_status] Wait complete
>[  124.168489] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[  124.168507] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[  124.168512] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  124.168529] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  124.168545] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[  124.170067] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  124.170073] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  124.170076] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[  124.173105] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  124.173112] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  124.173116] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  124.173122] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  124.173126] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  124.173129] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  124.173132] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  124.173135] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  124.173138] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  124.173141] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  124.173145] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  124.173148] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  124.173151] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  124.173154] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  124.173157] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  124.173162] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  124.173165] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  124.173168] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  124.173178] [drm:intel_power_well_disable] disabling DDI A/E power well
>[  124.173183] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  124.173188] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  124.173192] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  124.173196] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  124.173206] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee88da000
>[  124.173212] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee88da000
>[  124.723511] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000
>[  124.727989] [drm:wait_panel_status] Wait complete
>[  124.728053] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  124.728071] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  124.777308] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  124.777314] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  124.777318] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[  124.931653] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[  124.932766] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  125.177520] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5656000
>[  125.177527] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978eebbc06c0 state to ffff978ee5656000
>[  125.177531] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5653000 state to ffff978ee5656000
>[  125.177534] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eebbc06c0 to [NOCRTC]
>[  125.177537] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978eebbc06c0
>[  125.177540] [drm:drm_atomic_check_only] checking ffff978ee5656000
>[  125.177551] [drm:drm_atomic_commit] commiting ffff978ee5656000
>[  125.177562] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5656000
>[  125.177566] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5656000
>[  125.177578] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  125.177584] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[  125.177587] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5656000
>[  125.177590] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5653800 state to ffff978ee5656000
>[  125.177593] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978eebbc0f00 state to ffff978ee5656000
>[  125.177597] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5653800
>[  125.177600] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978eebbc0f00 to [CRTC:26:pipe A]
>[  125.177603] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffff978eebbc0f00
>[  125.177606] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5656000
>[  125.177609] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2c220 state to ffff978ee5656000
>[  125.177613] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c220 to [NOCRTC]
>[  125.177616] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2c220 to [CRTC:26:pipe A]
>[  125.177618] [drm:drm_atomic_check_only] checking ffff978ee5656000
>[  125.177624] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[  125.177627] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[  125.177629] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  125.177631] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[  125.177634] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5656000
>[  125.177638] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5656000
>[  125.177641] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  125.177643] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  125.177651] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  125.177657] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  125.177666] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  125.177669] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  125.177672] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  125.177676] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5653800 for pipe A
>[  125.177679] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  125.177681] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  125.177684] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  125.177687] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  125.177690] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  125.177692] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  125.177694] [drm:intel_dump_pipe_config] requested mode:
>[  125.177699] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  125.177700] [drm:intel_dump_pipe_config] adjusted mode:
>[  125.177705] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  125.177708] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  125.177710] [drm:intel_dump_pipe_config] port clock: 540000
>[  125.177712] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  125.177715] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  125.177717] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  125.177720] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  125.177722] [drm:intel_dump_pipe_config] ips: 0
>[  125.177724] [drm:intel_dump_pipe_config] double wide: 0
>[  125.177726] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  125.177728] [drm:intel_dump_pipe_config] planes on this crtc
>[  125.177732] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  125.177735] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  125.177738] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  125.177741] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  125.177743] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  125.177748] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5657800 state to ffff978ee5656000
>[  125.177751] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5657000 state to ffff978ee5656000
>[  125.177754] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[  125.177760] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  125.177762] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  125.177765] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[  125.177770] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  125.177773] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  125.177777] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  125.177789] [drm:drm_atomic_commit] commiting ffff978ee5656000
>[  125.177801] [drm:intel_power_well_enable] enabling DDI A/E power well
>[  125.177806] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  125.177813] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[  125.178978] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  125.178983] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  125.178986] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  125.178991] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  125.178995] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  125.178998] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  125.179001] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  125.179005] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  125.179008] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  125.179011] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  125.179015] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  125.179018] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  125.179022] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  125.179025] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  125.179028] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  125.179033] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  125.179036] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  125.179040] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  125.179045] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[  125.179048] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[  125.179063] [drm:edp_panel_on] Turn eDP port A panel power on
>[  125.179081] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  125.179177] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[  125.179195] [drm:wait_panel_status] Wait complete
>[  125.179229] [drm:edp_panel_on] Wait for panel power on
>[  125.179305] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[  125.379564] [drm:wait_panel_status] Wait complete
>[  125.380716] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  125.380718] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  125.380720] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  125.380723] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[  125.381397] [drm:intel_dp_start_link_train] clock recovery OK
>[  125.381400] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[  125.381402] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[  125.382376] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[  125.382379] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  125.382380] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  125.383344] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[  125.383517] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5653800
>[  125.383624] [drm:intel_enable_pipe] enabling pipe A
>[  125.383635] [drm:intel_edp_backlight_on.part.29] 
>[  125.383639] [drm:intel_panel_enable_backlight] pipe A
>[  125.383721] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  125.383777] [drm:intel_psr_enable] PSR disable by flag
>[  125.383779] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  125.400577] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  125.400589] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  125.400611] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  125.400621] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5656000
>[  125.400628] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5656000
>[  125.400663] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d88000
>[  125.400668] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d000 state to ffff978ee5d88000
>[  125.400671] [drm:drm_atomic_check_only] checking ffff978ee5d88000
>[  125.400681] [drm:drm_atomic_commit] commiting ffff978ee5d88000
>[  125.417217] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d88000
>[  125.417224] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d88000
>[  125.417262] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[  125.417266] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  125.417425] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d88000
>[  125.417431] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee8a71600 state to ffff978ee5d88000
>[  125.417435] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f800 state to ffff978ee5d88000
>[  125.417438] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee8a71600 to [CRTC:26:pipe A]
>[  125.417440] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee8a71600
>[  125.417443] [drm:drm_atomic_check_only] checking ffff978ee5d88000
>[  125.417452] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  125.417454] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[  125.417466] [drm:drm_atomic_commit] commiting ffff978ee5d88000
>[  125.417513] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d88000
>[  125.417518] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d88000
>[  125.548442] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88db800
>[  125.548449] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee88db000 state to ffff978ee88db800
>[  125.548452] [drm:drm_atomic_check_only] checking ffff978ee88db800
>[  125.548456] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  125.548458] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[  125.548461] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88db800
>[  125.548464] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebbb2300 state to ffff978ee88db800
>[  125.548467] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee97d9780 state to ffff978ee88db800
>[  125.548469] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee97d9b40 state to ffff978ee88db800
>[  125.548487] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88db800
>[  125.548490] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  125.548491] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  125.548499] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  125.548504] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  125.548512] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  125.548515] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  125.548517] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  125.548520] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee88db000 for pipe A
>[  125.548523] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  125.548524] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  125.548527] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  125.548529] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  125.548532] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  125.548533] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  125.548535] [drm:intel_dump_pipe_config] requested mode:
>[  125.548540] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  125.548541] [drm:intel_dump_pipe_config] adjusted mode:
>[  125.548545] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  125.548547] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  125.548549] [drm:intel_dump_pipe_config] port clock: 540000
>[  125.548551] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  125.548553] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  125.548555] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  125.548557] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  125.548558] [drm:intel_dump_pipe_config] ips: 0
>[  125.548560] [drm:intel_dump_pipe_config] double wide: 0
>[  125.548562] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  125.548563] [drm:intel_dump_pipe_config] planes on this crtc
>[  125.548566] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  125.548569] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  125.548572] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  125.548574] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[  125.548576] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[  125.548579] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[  125.548581] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  125.548586] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee88d9000 state to ffff978ee88db800
>[  125.548588] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee88dc000 state to ffff978ee88db800
>[  125.548590] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[  125.548596] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  125.548599] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  125.548601] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  125.548603] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  125.548605] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[  125.548609] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  125.548612] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  125.548615] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  125.548624] [drm:drm_atomic_commit] commiting ffff978ee88db800
>[  125.550035] [drm:intel_edp_backlight_off.part.30] 
>[  125.755139] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  125.755199] [drm:intel_disable_pipe] disabling pipe A
>[  125.768573] [drm:edp_panel_off] Turn eDP port A panel power off
>[  125.768613] [drm:edp_panel_off] Wait for panel power off time
>[  125.768691] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000000
>[  125.769180] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010
>[  125.769186] [drm:intel_hpd_irq_handler] digital hpd port A - short
>[  125.769203] [drm:intel_dp_hpd_pulse] got hpd irq on port A - short
>[  125.819072] [drm:wait_panel_status] Wait complete
>[  125.819089] [drm:intel_disable_shared_dpll] disable DPLL 0 (active 1, on? 1) for crtc 26
>[  125.819108] [drm:intel_disable_shared_dpll] disabling DPLL 0
>[  125.819113] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  125.819130] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  125.819146] [drm:skl_set_cdclk] Changing CDCLK to 337500 kHz (VCO 8100000 kHz)
>[  125.821112] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  125.821118] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  125.821121] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 0
>[  125.825739] [drm:intel_update_cdclk] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  125.825746] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  125.825751] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  125.825757] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  125.825760] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  125.825763] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  125.825766] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  125.825770] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  125.825773] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  125.825776] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  125.825779] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  125.825782] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  125.825785] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  125.825788] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  125.825791] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  125.825796] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  125.825799] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  125.825802] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  125.825813] [drm:intel_power_well_disable] disabling DDI A/E power well
>[  125.825817] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  125.825822] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  125.825827] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  125.825831] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  125.825841] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee88db800
>[  125.825847] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee88db800
>[  126.387344] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[  126.387365] [drm:wait_panel_status] Wait complete
>[  126.387421] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000008
>[  126.387439] [drm:edp_panel_vdd_on] eDP port A panel power wasn't enabled
>[  126.436870] [drm:intel_get_hpd_pins] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  126.436876] [drm:intel_hpd_irq_handler] digital hpd port A - long
>[  126.436880] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 4 - cnt: 1
>[  126.595738] [drm:intel_dp_read_dpcd] DPCD: 12 14 84 40 00 00 01 01 02 00 00 00 00 0b 00
>[  126.596850] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port A
>[  126.829775] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5656800
>[  126.829781] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee60a9600 state to ffff978ee5656800
>[  126.829785] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5651800 state to ffff978ee5656800
>[  126.829787] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee60a9600 to [NOCRTC]
>[  126.829789] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff978ee60a9600
>[  126.829791] [drm:drm_atomic_check_only] checking ffff978ee5656800
>[  126.829801] [drm:drm_atomic_commit] commiting ffff978ee5656800
>[  126.829810] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5656800
>[  126.829814] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5656800
>[  126.829824] [drm:drm_mode_setcrtc] [CRTC:26:pipe A]
>[  126.829829] [drm:drm_mode_setcrtc] [CONNECTOR:37:eDP-1]
>[  126.829831] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5656800
>[  126.829834] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5652000 state to ffff978ee5656800
>[  126.829836] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee60a96c0 state to ffff978ee5656800
>[  126.829839] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff978ee5652000
>[  126.829841] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee60a96c0 to [CRTC:26:pipe A]
>[  126.829843] [drm:drm_atomic_set_fb_for_plane] Set [FB:61] for plane state ffff978ee60a96c0
>[  126.829846] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5656800
>[  126.829849] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebb2ca60 state to ffff978ee5656800
>[  126.829852] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2ca60 to [NOCRTC]
>[  126.829854] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff978eebb2ca60 to [CRTC:26:pipe A]
>[  126.829856] [drm:drm_atomic_check_only] checking ffff978ee5656800
>[  126.829860] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:37:eDP-1]
>[  126.829862] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:37:eDP-1] keeps [ENCODER:36:DDI A], now on [CRTC:26:pipe A]
>[  126.829864] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  126.829866] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: y
>[  126.829868] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5656800
>[  126.829871] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee5656800
>[  126.829874] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  126.829876] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  126.829883] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  126.829887] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  126.829895] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  126.829898] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  126.829901] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  126.829904] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee5652000 for pipe A
>[  126.829906] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  126.829908] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  126.829910] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  126.829913] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  126.829915] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  126.829917] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  126.829918] [drm:intel_dump_pipe_config] requested mode:
>[  126.829922] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  126.829924] [drm:intel_dump_pipe_config] adjusted mode:
>[  126.829927] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  126.829930] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  126.829932] [drm:intel_dump_pipe_config] port clock: 540000
>[  126.829933] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  126.829935] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  126.829938] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  126.829940] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  126.829941] [drm:intel_dump_pipe_config] ips: 0
>[  126.829943] [drm:intel_dump_pipe_config] double wide: 0
>[  126.829945] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  126.829946] [drm:intel_dump_pipe_config] planes on this crtc
>[  126.829949] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  126.829952] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  126.829954] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  126.829956] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] disabled, scaler_id = -1
>[  126.829958] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  126.829963] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee5650000 state to ffff978ee5656800
>[  126.829965] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee5651000 state to ffff978ee5656800
>[  126.829967] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 450000
>[  126.829973] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  126.829983] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  126.829985] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[  126.829989] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  126.829991] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  126.829995] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  126.830005] [drm:drm_atomic_commit] commiting ffff978ee5656800
>[  126.830014] [drm:intel_power_well_enable] enabling DDI A/E power well
>[  126.830019] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  126.830024] [drm:skl_set_cdclk] Changing CDCLK to 450000 kHz (VCO 8100000 kHz)
>[  126.832009] [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  126.832013] [drm:intel_atomic_commit_tail] [ENCODER:36:DDI A]
>[  126.832016] [drm:intel_atomic_commit_tail] [ENCODER:45:DDI B]
>[  126.832019] [drm:intel_atomic_commit_tail] [ENCODER:47:DP-MST A]
>[  126.832022] [drm:intel_atomic_commit_tail] [ENCODER:48:DP-MST B]
>[  126.832024] [drm:intel_atomic_commit_tail] [ENCODER:49:DP-MST C]
>[  126.832026] [drm:intel_atomic_commit_tail] [ENCODER:52:DDI C]
>[  126.832029] [drm:intel_atomic_commit_tail] [ENCODER:54:DP-MST A]
>[  126.832031] [drm:intel_atomic_commit_tail] [ENCODER:55:DP-MST B]
>[  126.832034] [drm:intel_atomic_commit_tail] [ENCODER:56:DP-MST C]
>[  126.832036] [drm:verify_connector_state] [CONNECTOR:46:DP-1]
>[  126.832039] [drm:verify_connector_state] [CONNECTOR:50:HDMI-A-1]
>[  126.832041] [drm:verify_connector_state] [CONNECTOR:53:DP-2]
>[  126.832043] [drm:verify_connector_state] [CONNECTOR:57:HDMI-A-2]
>[  126.832046] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  126.832049] [drm:verify_single_dpll_state.isra.113] DPLL 1
>[  126.832052] [drm:verify_single_dpll_state.isra.113] DPLL 2
>[  126.832055] [drm:verify_single_dpll_state.isra.113] DPLL 3
>[  126.832059] [drm:intel_enable_shared_dpll] enable DPLL 0 (active 1, on? 0) for crtc 26
>[  126.832061] [drm:intel_enable_shared_dpll] enabling DPLL 0
>[  126.832073] [drm:edp_panel_on] Turn eDP port A panel power on
>[  126.832092] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  126.832168] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000008
>[  126.832181] [drm:wait_panel_status] Wait complete
>[  126.832215] [drm:edp_panel_on] Wait for panel power on
>[  126.832289] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control 0000000b
>[  127.032441] [drm:wait_panel_status] Wait complete
>[  127.033592] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  127.033594] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  127.033596] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  127.033599] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[  127.034274] [drm:intel_dp_start_link_train] clock recovery OK
>[  127.034277] [drm:intel_dp_start_link_train] 5.4 Gbps link rate without sink TPS3 support
>[  127.034279] [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[  127.035254] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
>[  127.035256] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  127.035257] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  127.036221] [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[  127.036395] [drm:skylake_pfit_enable] for crtc_state = ffff978ee5652000
>[  127.036501] [drm:intel_enable_pipe] enabling pipe A
>[  127.036511] [drm:intel_edp_backlight_on.part.29] 
>[  127.036515] [drm:intel_panel_enable_backlight] pipe A
>[  127.036597] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  127.036654] [drm:intel_psr_enable] PSR disable by flag
>[  127.036656] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  127.053374] [drm:verify_connector_state] [CONNECTOR:37:eDP-1]
>[  127.053383] [drm:intel_atomic_commit_tail] [CRTC:26:pipe A]
>[  127.053403] [drm:verify_single_dpll_state.isra.113] DPLL 0
>[  127.053413] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5656800
>[  127.053419] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5656800
>[  127.053451] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d88000
>[  127.053456] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8d000 state to ffff978ee5d88000
>[  127.053458] [drm:drm_atomic_check_only] checking ffff978ee5d88000
>[  127.053467] [drm:drm_atomic_commit] commiting ffff978ee5d88000
>[  127.070093] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d88000
>[  127.070099] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d88000
>[  127.070132] [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=255/937
>[  127.070135] [drm:intel_panel_actually_set_backlight] set backlight PWM = 282
>[  127.070272] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee5d88000
>[  127.070277] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee5fde3c0 state to ffff978ee5d88000
>[  127.070281] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee5d8f000 state to ffff978ee5d88000
>[  127.070283] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff978ee5fde3c0 to [CRTC:26:pipe A]
>[  127.070285] [drm:drm_atomic_set_fb_for_plane] Set [FB:59] for plane state ffff978ee5fde3c0
>[  127.070288] [drm:drm_atomic_check_only] checking ffff978ee5d88000
>[  127.070295] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  127.070298] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>[  127.070307] [drm:drm_atomic_commit] commiting ffff978ee5d88000
>[  127.070335] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff978ee5d88000
>[  127.070338] [drm:drm_atomic_state_free] Freeing atomic state ffff978ee5d88000
>[  127.201209] [drm:drm_atomic_state_init] Allocated atomic state ffff978ee88da800
>[  127.201224] [drm:drm_atomic_get_crtc_state] Added [CRTC:26:pipe A] ffff978ee88d8800 state to ffff978ee88da800
>[  127.201231] [drm:drm_atomic_check_only] checking ffff978ee88da800
>[  127.201234] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] active changed
>[  127.201235] [drm:drm_atomic_helper_check_modeset] [CRTC:26:pipe A] needs all connectors, enable: y, active: n
>[  127.201236] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88da800
>[  127.201238] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:37] ffff978eebbb23c0 state to ffff978ee88da800
>[  127.201240] [drm:drm_atomic_get_plane_state] Added [PLANE:23:plane 1A] ffff978ee97d9000 state to ffff978ee88da800
>[  127.201241] [drm:drm_atomic_get_plane_state] Added [PLANE:25:cursor A] ffff978ee97d90c0 state to ffff978ee88da800
>[  127.201243] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:26:pipe A] to ffff978ee88da800
>[  127.201245] [drm:intel_atomic_check] [CONNECTOR:37:eDP-1] checking for sink bpp constrains
>[  127.201245] [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 24
>[  127.201250] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  127.201253] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 373250KHz
>[  127.201257] [drm:intel_dp_compute_config] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  127.201259] [drm:intel_dp_compute_config] DP link bw required 895800 available 1728000
>[  127.201260] [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  127.201262] [drm:intel_dump_pipe_config] [CRTC:26:pipe A][modeset] config ffff978ee88d8800 for pipe A
>[  127.201263] [drm:intel_dump_pipe_config] cpu_transcoder: EDP
>[  127.201264] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  127.201265] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  127.201266] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 4348677, gmch_n: 8388608, link_m: 724779, link_n: 1048576, tu: 64
>[  127.201267] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  127.201268] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  127.201269] [drm:intel_dump_pipe_config] requested mode:
>[  127.201271] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x0 0xa
>[  127.201272] [drm:intel_dump_pipe_config] adjusted mode:
>[  127.201274] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
>[  127.201275] [drm:intel_dump_pipe_config] crtc timings: 373250 3200 3248 3280 3360 1800 1803 1808 1852, type: 0x48 flags: 0xa
>[  127.201276] [drm:intel_dump_pipe_config] port clock: 540000
>[  127.201276] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  127.201277] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  127.201278] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  127.201279] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  127.201280] [drm:intel_dump_pipe_config] ips: 0
>[  127.201281] [drm:intel_dump_pipe_config] double wide: 0
>[  127.201282] [drm:intel_dump_pipe_config] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  127.201282] [drm:intel_dump_pipe_config] planes on this crtc
>[  127.201284] [drm:intel_dump_pipe_config] [PLANE:23:plane 1A] enabled
>[  127.201285] [drm:intel_dump_pipe_config] 	FB:61, fb = 3200x1800 format = XR24 little-endian (0x34325258)
>[  127.201286] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+3200+1800 dst 0x0+3200+1800
>[  127.201288] [drm:intel_dump_pipe_config] [PLANE:25:cursor A] enabled
>[  127.201289] [drm:intel_dump_pipe_config] 	FB:59, fb = 64x64 format = AR24 little-endian (0x34325241)
>[  127.201290] [drm:intel_dump_pipe_config] 	scaler:-1 src 0x0+64+64 dst 1599x899+64+64
>[  127.201291] [drm:intel_dump_pipe_config] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  127.201293] [drm:drm_atomic_get_crtc_state] Added [CRTC:30:pipe B] ffff978ee88dd800 state to ffff978ee88da800
>[  127.201295] [drm:drm_atomic_get_crtc_state] Added [CRTC:34:pipe C] ffff978ee88d9800 state to ffff978ee88da800
>[  127.201296] [drm:intel_atomic_check] New cdclk calculated to be atomic 450000, actual 337500
>[  127.201300] [drm:intel_plane_atomic_calc_changes] Updating scaler for [PLANE:23:plane 1A] scaler_user index 0.0
>[  127.201301] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:23:plane 1A] with fb 61
>[  127.201302] [drm:intel_plane_atomic_calc_changes] [PLANE:23:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  127.201303] [drm:intel_plane_atomic_calc_changes] [CRTC:26:pipe A] has [PLANE:25:cursor A] with fb 59
>[  127.201304] [drm:intel_plane_atomic_calc_changes] [PLANE:25:cursor A] visible 1 -> 0, off 1, on 0, ms 1
>[  127.201307] [drm:intel_find_shared_dpll] [CRTC:26:pipe A] allocated DPLL 0
>[  127.201308] [drm:intel_reference_shared_dpll] using DPLL 0 for pipe A
>[  127.201310] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:26:pipe A] scaler_user index 0.31
>[  127.201314] [drm:drm_atomic_commit] commiting ffff978ee88da800
>[  127.203075] [drm:intel_edp_backlight_off.part.30]

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Attachments on bug 99345: 128854 | 128855 | 128856 | 128859 | 128863

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