Attachment 128987 Details for Bug 99430 – kms_pipe_crc_basic@suspend-read-crc-pipe-A

kms_pipe_crc_basic@suspend-read-crc-pipe-A

dmesg.log (text/plain), 250.62 KB, created by Jairo Miramontes on 2017-01-16 19:24:19 UTC

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Creator: Jairo Miramontes

Created: 2017-01-16 19:24:19 UTC

Size: 250.62 KB

patch

obsolete

>[  245.618811] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  245.618867] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  245.618923] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  245.618985] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  245.619044] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  245.619494] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  245.619895] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[  245.619915] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:51:eDP-1] probed modes :
>[  245.619951] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  245.619983] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:59:DP-1]
>[  245.620044] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  245.620518] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  245.621292] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  245.621350] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  245.621406] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  245.621461] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  245.621911] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.1 SW-rev 1.39
>[  245.622269] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  245.624077] [drm:drm_add_edid_modes [drm]] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  245.624113] [drm:drm_edid_to_eld [drm]] ELD monitor VX279
>[  245.624150] [drm:drm_edid_to_eld [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  245.624183] [drm:drm_edid_to_eld [drm]] ELD size 28, SAD count 1
>[  245.624256] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:59:DP-1] probed modes :
>[  245.624292] [drm:drm_mode_debug_printmodeline [drm]] Modeline 74:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  245.624328] [drm:drm_mode_debug_printmodeline [drm]] Modeline 109:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  245.624363] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  245.624398] [drm:drm_mode_debug_printmodeline [drm]] Modeline 111:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  245.624433] [drm:drm_mode_debug_printmodeline [drm]] Modeline 106:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  245.624468] [drm:drm_mode_debug_printmodeline [drm]] Modeline 103:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  245.624503] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  245.624538] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  245.624573] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  245.624607] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  245.624642] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  245.624677] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  245.624713] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  245.624748] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  245.624783] [drm:drm_mode_debug_printmodeline [drm]] Modeline 112:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  245.624818] [drm:drm_mode_debug_printmodeline [drm]] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  245.624853] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  245.624888] [drm:drm_mode_debug_printmodeline [drm]] Modeline 94:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  245.624923] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  245.624957] [drm:drm_mode_debug_printmodeline [drm]] Modeline 96:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  245.624994] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  245.625029] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  245.625064] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  245.625099] [drm:drm_mode_debug_printmodeline [drm]] Modeline 104:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  245.625134] [drm:drm_mode_debug_printmodeline [drm]] Modeline 113:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  245.625168] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  245.625203] [drm:drm_mode_debug_printmodeline [drm]] Modeline 88:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  245.625238] [drm:drm_mode_debug_printmodeline [drm]] Modeline 89:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  245.625273] [drm:drm_mode_debug_printmodeline [drm]] Modeline 114:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  245.625308] [drm:drm_mode_debug_printmodeline [drm]] Modeline 90:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  245.625342] [drm:drm_mode_debug_printmodeline [drm]] Modeline 91:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  245.625396] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:63:HDMI-A-1]
>[  245.625461] [drm:intel_hdmi_detect [i915]] [CONNECTOR:63:HDMI-A-1]
>[  245.627554] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  245.627612] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  245.629710] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  245.629752] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb
>[  245.631811] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  245.631840] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  245.633932] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  245.633964] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  245.633987] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:63:HDMI-A-1] disconnected
>[  245.634059] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:66:DP-2]
>[  245.634094] [drm:intel_dp_detect [i915]] [CONNECTOR:66:DP-2]
>[  245.635009] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[  245.635784] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  245.635815] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  245.635844] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  245.635874] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  245.636745] [drm:intel_dp_read_desc [i915]] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  245.636773] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  245.637633] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[  245.637667] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:66:DP-2] probed modes :
>[  245.637686] [drm:drm_mode_debug_printmodeline [drm]] Modeline 92:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  245.637705] [drm:drm_mode_debug_printmodeline [drm]] Modeline 135:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  245.637723] [drm:drm_mode_debug_printmodeline [drm]] Modeline 137:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  245.637742] [drm:drm_mode_debug_printmodeline [drm]] Modeline 131:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  245.637760] [drm:drm_mode_debug_printmodeline [drm]] Modeline 130:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  245.637779] [drm:drm_mode_debug_printmodeline [drm]] Modeline 134:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  245.637797] [drm:drm_mode_debug_printmodeline [drm]] Modeline 107:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  245.637815] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  245.637834] [drm:drm_mode_debug_printmodeline [drm]] Modeline 133:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  245.637852] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  245.637870] [drm:drm_mode_debug_printmodeline [drm]] Modeline 127:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  245.637889] [drm:drm_mode_debug_printmodeline [drm]] Modeline 129:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
>[  245.637907] [drm:drm_mode_debug_printmodeline [drm]] Modeline 128:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  245.637926] [drm:drm_mode_debug_printmodeline [drm]] Modeline 126:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  245.637944] [drm:drm_mode_debug_printmodeline [drm]] Modeline 125:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  245.637962] [drm:drm_mode_debug_printmodeline [drm]] Modeline 98:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  245.637981] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x6
>[  245.637999] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  245.638017] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  245.638036] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  245.638054] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  245.638073] [drm:drm_mode_debug_printmodeline [drm]] Modeline 115:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  245.638091] [drm:drm_mode_debug_printmodeline [drm]] Modeline 136:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  245.638109] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  245.638128] [drm:drm_mode_debug_printmodeline [drm]] Modeline 119:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  245.638146] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  245.638164] [drm:drm_mode_debug_printmodeline [drm]] Modeline 118:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  245.638183] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  245.638201] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  245.638219] [drm:drm_mode_debug_printmodeline [drm]] Modeline 117:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  245.638237] [drm:drm_mode_debug_printmodeline [drm]] Modeline 102:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  245.638256] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  245.638301] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[  245.638335] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[  245.640438] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  245.640467] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  245.642415] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  245.642451] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[  245.644566] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  245.644635] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  245.646377] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  245.646396] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  245.646413] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[  245.647263] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:51:eDP-1]
>[  245.647307] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  245.647347] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  245.647386] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  245.647421] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  245.647460] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  245.647886] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  245.648249] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[  245.648263] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:51:eDP-1] probed modes :
>[  245.648286] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  245.648361] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:59:DP-1]
>[  245.648403] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  245.648841] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  245.649573] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  245.649611] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  245.649646] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  245.649683] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  245.650100] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.1 SW-rev 1.39
>[  245.650440] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  245.650947] [drm:drm_add_edid_modes [drm]] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  245.650969] [drm:drm_edid_to_eld [drm]] ELD monitor VX279
>[  245.650994] [drm:drm_edid_to_eld [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  245.651016] [drm:drm_edid_to_eld [drm]] ELD size 28, SAD count 1
>[  245.651063] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:59:DP-1] probed modes :
>[  245.651087] [drm:drm_mode_debug_printmodeline [drm]] Modeline 74:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  245.651110] [drm:drm_mode_debug_printmodeline [drm]] Modeline 109:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  245.651135] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  245.651158] [drm:drm_mode_debug_printmodeline [drm]] Modeline 111:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  245.651183] [drm:drm_mode_debug_printmodeline [drm]] Modeline 106:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  245.651206] [drm:drm_mode_debug_printmodeline [drm]] Modeline 103:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  245.651231] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  245.651254] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  245.651278] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  245.651301] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  245.651325] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  245.651349] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  245.651372] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  245.651395] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  245.651420] [drm:drm_mode_debug_printmodeline [drm]] Modeline 112:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  245.651443] [drm:drm_mode_debug_printmodeline [drm]] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  245.651466] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  245.651490] [drm:drm_mode_debug_printmodeline [drm]] Modeline 94:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  245.651514] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  245.651538] [drm:drm_mode_debug_printmodeline [drm]] Modeline 96:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  245.651562] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  245.651586] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  245.651609] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  245.651633] [drm:drm_mode_debug_printmodeline [drm]] Modeline 104:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  245.651656] [drm:drm_mode_debug_printmodeline [drm]] Modeline 113:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  245.651679] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  245.651704] [drm:drm_mode_debug_printmodeline [drm]] Modeline 88:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  245.651727] [drm:drm_mode_debug_printmodeline [drm]] Modeline 89:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  245.651751] [drm:drm_mode_debug_printmodeline [drm]] Modeline 114:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  245.651775] [drm:drm_mode_debug_printmodeline [drm]] Modeline 90:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  245.651801] [drm:drm_mode_debug_printmodeline [drm]] Modeline 91:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  245.651884] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:63:HDMI-A-1]
>[  245.651924] [drm:intel_hdmi_detect [i915]] [CONNECTOR:63:HDMI-A-1]
>[  245.653987] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  245.654028] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  245.656112] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  245.656140] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb
>[  245.658234] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  245.658299] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  245.660405] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  245.660420] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  245.660431] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:63:HDMI-A-1] disconnected
>[  245.660500] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:66:DP-2]
>[  245.660541] [drm:intel_dp_detect [i915]] [CONNECTOR:66:DP-2]
>[  245.661453] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[  245.662250] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  245.662291] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  245.662329] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  245.662395] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  245.663301] [drm:intel_dp_read_desc [i915]] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  245.663339] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  245.664207] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[  245.664247] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:66:DP-2] probed modes :
>[  245.664272] [drm:drm_mode_debug_printmodeline [drm]] Modeline 92:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  245.664296] [drm:drm_mode_debug_printmodeline [drm]] Modeline 135:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  245.664320] [drm:drm_mode_debug_printmodeline [drm]] Modeline 137:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  245.664345] [drm:drm_mode_debug_printmodeline [drm]] Modeline 131:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  245.664369] [drm:drm_mode_debug_printmodeline [drm]] Modeline 130:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  245.664393] [drm:drm_mode_debug_printmodeline [drm]] Modeline 134:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  245.664417] [drm:drm_mode_debug_printmodeline [drm]] Modeline 107:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  245.664441] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  245.664465] [drm:drm_mode_debug_printmodeline [drm]] Modeline 133:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  245.664489] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  245.664513] [drm:drm_mode_debug_printmodeline [drm]] Modeline 127:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  245.664538] [drm:drm_mode_debug_printmodeline [drm]] Modeline 129:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
>[  245.664562] [drm:drm_mode_debug_printmodeline [drm]] Modeline 128:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  245.664586] [drm:drm_mode_debug_printmodeline [drm]] Modeline 126:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  245.664610] [drm:drm_mode_debug_printmodeline [drm]] Modeline 125:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  245.664634] [drm:drm_mode_debug_printmodeline [drm]] Modeline 98:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  245.664658] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x6
>[  245.664682] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  245.664706] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  245.664730] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  245.664754] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  245.664778] [drm:drm_mode_debug_printmodeline [drm]] Modeline 115:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  245.664802] [drm:drm_mode_debug_printmodeline [drm]] Modeline 136:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  245.664826] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  245.664851] [drm:drm_mode_debug_printmodeline [drm]] Modeline 119:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  245.664875] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  245.664899] [drm:drm_mode_debug_printmodeline [drm]] Modeline 118:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  245.664923] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  245.664947] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  245.664971] [drm:drm_mode_debug_printmodeline [drm]] Modeline 117:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  245.664995] [drm:drm_mode_debug_printmodeline [drm]] Modeline 102:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  245.665019] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  245.665107] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[  245.665148] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[  245.666428] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  245.666473] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  245.668533] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  245.668561] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[  245.670393] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  245.670434] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  245.672490] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  245.672505] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  245.672517] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[  245.672667] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-C
>[  245.730309] PM: Syncing filesystems ... done.
>[  245.737826] PM: Preparing system for sleep (mem)
>[  245.741806] Freezing user space processes ... (elapsed 0.003 seconds) done.
>[  245.745164] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  245.746300] PM: Suspending system (mem)
>[  245.746318] Suspending console(s) (use no_console_suspend to debug)
>[  246.654849] hpet_rtc_timer_reinit: 60 callbacks suppressed
>[  246.654850] hpet1: lost 7160 rtc interrupts
>[  247.598101] hpet1: lost 7160 rtc interrupts
>[  248.103384] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  248.287765] sd 0:0:0:0: [sda] Stopping disk
>[  248.294855] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  248.294995] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  248.336818] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  248.336845] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  248.336877] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  248.336908] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  248.336933] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  248.336962] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  248.336990] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  248.337019] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  248.337047] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  248.337073] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  248.337099] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  248.337122] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  248.337149] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  248.337165] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  248.337192] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  248.337219] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  248.337246] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  248.337272] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  248.337299] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  248.337328] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  248.337354] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  248.337384] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:141, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  248.337411] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  248.337438] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  248.337464] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  248.337491] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  248.337520] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains
>[  248.337547] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  248.337573] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[  248.337599] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  248.337625] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  248.337651] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  248.337678] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  248.337704] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  248.337731] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  248.337758] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  248.337784] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  248.337800] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  248.337826] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  248.337842] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  248.337870] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  248.337896] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080
>[  248.337923] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  248.337949] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  248.337976] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  248.338003] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  248.338029] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  248.338057] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:141, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  248.338084] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  248.338110] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  248.338137] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  248.338163] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  248.338191] [drm:intel_atomic_check [i915]] [CONNECTOR:66:DP-2] checking for sink bpp constrains
>[  248.338217] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  248.338245] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  248.338271] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  248.338296] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  248.338323] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  248.338367] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  248.338394] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  248.338421] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  248.338447] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  248.338473] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  248.338490] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  248.338516] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  248.338532] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  248.338560] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  248.338586] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080
>[  248.338613] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  248.338640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  248.338666] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  248.338693] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  248.338720] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  248.338747] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:141, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  248.338774] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  248.338801] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  248.338827] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  248.338857] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  248.338892] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  248.338919] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  248.338947] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL B
>[  248.338973] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  248.339000] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  248.339026] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  248.339080] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  248.345825] igb 0000:01:00.0: System wakeup enabled by ACPI
>[  248.514462] ACPI : EC: event blocked
>[  248.535881] hpet1: lost 7161 rtc interrupts
>[  248.546383] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  248.546424] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  248.562543] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  248.562579] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  248.562748] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  248.562774] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  248.562803] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  248.613094] [drm:wait_panel_status [i915]] Wait complete
>[  248.613121] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  248.613152] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  248.613197] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  248.613237] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  248.613268] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  248.615162] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  248.615189] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  248.615216] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  248.615247] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  248.619487] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 42
>[  248.619526] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  248.619563] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  248.628013] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  248.628051] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  248.628088] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  248.632149] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  248.632178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  248.632206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  248.632234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  248.632260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  248.632287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  248.632314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  248.632340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  248.632367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  248.632394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  248.632424] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  248.632451] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  248.632478] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  248.632511] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:51:eDP-1]
>[  248.632542] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  248.632573] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  248.632601] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:59:DP-1]
>[  248.632630] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  248.632660] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  248.632687] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:66:DP-2]
>[  248.632715] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  248.632744] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  248.633116] PM: suspend of devices complete after 530.920 msecs
>[  248.723080] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  248.723106] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  248.723130] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  248.723163] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  248.723187] [drm:intel_power_well_disable [i915]] disabling DC off
>[  248.723216] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  248.723242] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  248.723267] [drm:intel_power_well_disable [i915]] disabling always-on
>[  248.723771] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  248.723814] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 19200 kHz (VCO 0 kHz)
>[  248.727884] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  248.727908] [drm:intel_power_well_disable [i915]] disabling power well 1
>[  248.727936] [drm:skl_set_power_well [i915]] Disabling power well 1
>[  248.727964] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC
>[  248.727995] [drm:bxt_enable_dc9 [i915]] Enabling DC9
>[  248.728022] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08
>[  248.746509] PM: late suspend of devices complete after 113.390 msecs
>[  248.747721] ACPI : EC: interrupt blocked
>[  248.748472] xhci_hcd 0000:00:15.0: System wakeup enabled by ACPI
>[  248.766444] acpi device:0a: Cannot transition from D3cold to D3hot
>[  248.770345] PM: noirq suspend of devices complete after 23.829 msecs
>[  248.770556] ACPI: Preparing to enter system sleep state S3
>[  248.771019] ACPI : EC: EC stopped
>[  248.771020] PM: Saving platform NVS memory
>[  248.771024] Disabling non-boot CPUs ...
>[  248.771975] Cannot set affinity for irq 350
>[  248.771980] Broke affinity for irq 367
>[  248.773019] smpboot: CPU 1 is now offline
>[  248.788230] Broke affinity for irq 367
>[  248.788233] Broke affinity for irq 373
>[  248.789512] smpboot: CPU 2 is now offline
>[  248.820381] Broke affinity for irq 1
>[  248.820412] Broke affinity for irq 8
>[  248.820421] Broke affinity for irq 9
>[  248.820474] Broke affinity for irq 30
>[  248.820569] Broke affinity for irq 121
>[  248.820643] Broke affinity for irq 367
>[  248.820647] Broke affinity for irq 373
>[  248.821724] smpboot: CPU 3 is now offline
>[  248.843457] ACPI: Low-level resume complete
>[  248.843792] ACPI : EC: EC started
>[  248.843795] PM: Restoring platform NVS memory
>[  248.844864] Suspended for 11.640 seconds
>[  248.845125] Enabling non-boot CPUs ...
>[  248.856514] x86: Booting SMP configuration:
>[  248.856520] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  248.857636] Skipped synchronization checks as TSC is reliable.
>[  248.858981]  cache: parent cpu1 should not be sleeping
>[  248.860156] CPU1 is up
>[  248.876110] smpboot: Booting Node 0 Processor 2 APIC 0x4
>[  248.876806] Skipped synchronization checks as TSC is reliable.
>[  248.877733]  cache: parent cpu2 should not be sleeping
>[  248.878566] CPU2 is up
>[  248.892033] smpboot: Booting Node 0 Processor 3 APIC 0x6
>[  248.892641] Skipped synchronization checks as TSC is reliable.
>[  248.893404]  cache: parent cpu3 should not be sleeping
>[  248.894287] CPU3 is up
>[  248.897659] ACPI: Waking up from system sleep state S3
>[  248.907863] ACPI : button: The lid device is not compliant to SW_LID.
>[  248.910727] acpi LNXPOWER:15: Turning OFF
>[  248.947068] acpi LNXPOWER:14: Turning OFF
>[  248.947148] acpi LNXPOWER:12: Turning OFF
>[  248.947786] acpi LNXPOWER:09: Turning OFF
>[  248.948088] acpi LNXPOWER:07: Turning OFF
>[  248.948362] acpi LNXPOWER:06: Turning OFF
>[  248.949656] ACPI : EC: interrupt unblocked
>[  248.968300] xhci_hcd 0000:00:15.0: System wakeup disabled by ACPI
>[  249.015586] PM: noirq resume of devices complete after 66.138 msecs
>[  249.016090] [drm:gen9_sanitize_dc_state [i915]] Resetting DC state tracking from 08 to 00
>[  249.016153] [drm:bxt_disable_dc9 [i915]] Disabling DC9
>[  249.016215] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  249.016373] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 4
>[  249.016559] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  249.016623] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  249.016703] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  249.017133] [drm:intel_power_well_enable [i915]] enabling always-on
>[  249.017193] [drm:intel_power_well_enable [i915]] enabling DC off
>[  249.017254] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  249.017319] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  249.017381] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  249.017520] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  249.017675] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  249.017812] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 1 already enabled, won't reprogram it
>[  249.017924] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>[  249.024472] PM: early resume of devices complete after 8.703 msecs
>[  249.024644] ACPI : EC: event unblocked
>[  249.025853] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x79cff018
>[  249.025971] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  249.026037] [drm:intel_opregion_setup [i915]] ASLE supported
>[  249.026109] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  249.026229] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  249.026300] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  249.026724] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  249.026835] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  249.026931] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  249.027136] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  249.027176] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[  249.027179] [drm] GuC firmware load skipped
>[  249.027218] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  249.027255] [drm:bxt_hpd_irq_setup [i915]] Invert bit setting: hp_ctl:10001010 hp_port:38
>[  249.027298] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:33:pipe A] hw state readout: disabled
>[  249.027332] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:42:pipe B] hw state readout: disabled
>[  249.027367] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:49:pipe C] hw state readout: disabled
>[  249.027400] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0
>[  249.027459] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0
>[  249.027490] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0
>[  249.027525] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI A] hw state readout: disabled, pipe A
>[  249.027557] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI B] hw state readout: disabled, pipe A
>[  249.027590] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A
>[  249.027621] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B
>[  249.027651] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C
>[  249.027684] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DDI C] hw state readout: disabled, pipe A
>[  249.027714] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:67:DP-MST A] hw state readout: disabled, pipe A
>[  249.027745] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:68:DP-MST B] hw state readout: disabled, pipe B
>[  249.027776] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:69:DP-MST C] hw state readout: disabled, pipe C
>[  249.027778] igb 0000:01:00.0: System wakeup disabled by ACPI
>[  249.027809] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:eDP-1] hw state readout: disabled
>[  249.027841] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-1] hw state readout: disabled
>[  249.027872] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:63:HDMI-A-1] hw state readout: disabled
>[  249.027904] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:66:DP-2] hw state readout: disabled
>[  249.027936] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:70:HDMI-A-2] hw state readout: disabled
>[  249.027970] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][setup_hw_state]
>[  249.028000] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  249.028031] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  249.028061] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  249.028086] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  249.028116] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  249.028119] rtc_cmos 00:04: System wakeup disabled by ACPI
>[  249.028137] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  249.028168] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  249.028199] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  249.028229] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  249.028260] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  249.028290] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  249.028322] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  249.028352] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  249.028386] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:141, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  249.028417] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  249.028448] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  249.028479] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  249.028509] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  249.028541] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][setup_hw_state]
>[  249.028572] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  249.028602] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  249.028632] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  249.028650] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  249.028680] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  249.028699] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  249.028730] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  249.028761] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  249.028762] sd 0:0:0:0: [sda] Starting disk
>[  249.028793] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  249.028824] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  249.028857] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  249.028888] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  249.028918] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  249.028950] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:141, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  249.028981] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  249.029011] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  249.029041] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  249.029072] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  249.029103] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][setup_hw_state]
>[  249.029133] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  249.029164] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  249.029194] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  249.029215] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  249.029246] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  249.029264] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  249.029295] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  249.029326] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  249.029356] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  249.029386] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  249.029416] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  249.029449] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  249.029479] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  249.029512] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:141, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  249.029543] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  249.029574] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  249.029604] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  249.029681] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  249.029709] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  249.029761] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  249.029791] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  249.029826] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  249.029861] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  249.029890] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  249.029921] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  249.029952] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  249.029983] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  249.030022] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  249.030053] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  249.030080] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  249.030110] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  249.030136] [drm:intel_power_well_disable [i915]] disabling DC off
>[  249.030166] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  249.030192] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  249.030211] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  249.030238] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  249.030268] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  249.030296] [drm:intel_power_well_disable [i915]] disabling always-on
>[  249.030315] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  249.030346] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  249.030376] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  249.030407] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  249.030437] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  249.030467] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  249.030499] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  249.030529] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  249.030560] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:141, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  249.030591] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  249.030622] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  249.030652] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  249.030682] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  249.030714] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains
>[  249.030744] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  249.030774] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[  249.030804] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  249.030833] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  249.030863] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  249.030894] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  249.030924] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  249.030955] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  249.030985] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  249.031015] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  249.031033] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  249.031063] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  249.031082] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  249.031113] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  249.031143] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080
>[  249.031174] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  249.031204] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  249.031234] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  249.031266] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  249.031295] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  249.031327] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:141, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  249.031358] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  249.031388] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  249.031432] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  249.031462] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  249.031494] [drm:intel_atomic_check [i915]] [CONNECTOR:66:DP-2] checking for sink bpp constrains
>[  249.031524] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  249.031555] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  249.031585] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  249.031614] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  249.031644] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  249.031675] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  249.031705] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  249.031736] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  249.031766] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  249.031796] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  249.031814] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  249.031844] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  249.031862] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  249.031894] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  249.031924] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080
>[  249.031954] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  249.031985] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  249.032015] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  249.032046] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  249.032076] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  249.032108] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:141, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  249.032139] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  249.032169] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  249.032199] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  249.032232] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  249.032271] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  249.032302] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  249.032333] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL B
>[  249.032363] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  249.032393] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  249.032423] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  249.032475] [drm:intel_power_well_enable [i915]] enabling always-on
>[  249.032501] [drm:intel_power_well_enable [i915]] enabling DC off
>[  249.032690] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  249.032722] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  249.032820] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  249.032847] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  249.032882] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  249.032997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  249.033028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  249.033058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  249.033090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  249.033121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  249.033151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  249.033182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  249.033212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  249.033243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  249.033277] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:63:HDMI-A-1]
>[  249.033309] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:70:HDMI-A-2]
>[  249.033341] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  249.033372] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  249.033403] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  249.033448] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  249.033478] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  249.033604] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  249.033634] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  249.033669] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000062
>[  249.033698] [drm:wait_panel_status [i915]] Wait complete
>[  249.033727] [drm:edp_panel_on [i915]] Wait for panel power on
>[  249.033758] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  249.141062] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  249.141102] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  249.141143] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  249.141206] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  249.234911] [drm:wait_panel_status [i915]] Wait complete
>[  249.234969] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  249.235022] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  249.236169] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  249.236221] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  249.236276] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  249.236975] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  249.237026] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  249.237954] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  249.238157] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8ab2736a0800
>[  249.238380] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  249.238468] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  249.238517] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  249.238571] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  249.243497] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  249.243547] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  249.243608] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  249.243660] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  249.243761] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 42
>[  249.243812] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  249.245039] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  249.245089] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  249.245139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  249.251413] atkbd serio0: Failed to deactivate keyboard on isa0060/serio0
>[  249.278602] [drm:drm_dp_dpcd_access [drm_kms_helper]] Too many retries, giving up. First error: -5
>[  249.278657] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to enable link training
>[  249.278703] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  249.312174] [drm:drm_dp_dpcd_access [drm_kms_helper]] Too many retries, giving up. First error: -5
>[  249.312219] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to start channel equalization
>[  249.312418] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8ab2736a7800
>[  249.312627] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  249.312730] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B]
>[  249.312778] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 28 bytes ELD
>[  249.312826] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  249.312926] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  249.312970] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  249.314876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  249.314918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  249.314962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  249.317443] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  249.317486] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  249.319212] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  249.319255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  249.320874] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  249.323374] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8ab2736a1800
>[  249.323543] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  249.340312] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:51:eDP-1]
>[  249.340360] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  249.340450] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  249.340545] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:59:DP-1]
>[  249.340591] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  249.340663] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  249.340736] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:66:DP-2]
>[  249.340783] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  249.340861] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  249.340936] [drm:bxt_hpd_irq_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  249.340981] [drm:intel_opregion_register [i915]] 5 outputs detected
>[  249.341026] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  249.341068] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  249.341111] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  249.341151] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  249.341192] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  249.344160] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  249.344505] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:51:eDP-1] status updated from connected to connected
>[  249.344555] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  249.344575] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:59:DP-1] status updated from connected to disconnected
>[  249.344629] [drm:intel_hdmi_detect [i915]] [CONNECTOR:63:HDMI-A-1]
>[  249.346072] PM: resume of devices complete after 321.593 msecs
>[  249.346571] PM: Finishing wakeup.
>[  249.346573] Restarting tasks ... 
>[  249.347593] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  249.347671] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  249.347688] done.
>[  249.349743] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  249.349771] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb
>[  249.351560] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  249.351588] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  249.353656] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  249.353674] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  249.353684] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:63:HDMI-A-1] status updated from disconnected to disconnected
>[  249.353713] [drm:intel_dp_detect [i915]] [CONNECTOR:66:DP-2]
>[  249.354670] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[  249.355496] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  249.355525] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  249.355551] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  249.355577] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  249.356493] [drm:intel_dp_read_desc [i915]] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  249.356520] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  249.357350] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:66:DP-2] status updated from connected to connected
>[  249.357388] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[  249.359455] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  249.359482] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  249.361597] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  249.361623] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[  249.363459] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  249.363485] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  249.365542] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  249.365556] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  249.365567] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] status updated from disconnected to disconnected
>[  249.366344] [drm:drm_mode_addfb2 [drm]] [FB:53]
>[  249.507437] atkbd serio0: Failed to enable keyboard on isa0060/serio0
>[  249.551448] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  250.267969] ata1.00: configured for UDMA/133
>[  250.282061] [drm:drm_mode_setcrtc [drm]] [CRTC:33:pipe A]
>[  250.282118] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  250.282179] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  250.487520] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  250.487629] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  250.489929] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  250.489957] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  250.489989] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  250.541875] [drm:wait_panel_status [i915]] Wait complete
>[  250.541906] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  250.541938] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  250.541983] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  250.542030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  250.542060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  250.542088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  250.542115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  250.542142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  250.542169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  250.542195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  250.542222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  250.542249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  250.542279] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:51:eDP-1]
>[  250.542307] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  250.542334] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  250.542378] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  250.542402] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  250.542429] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  250.542456] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  250.542506] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  250.557025] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  250.557143] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  250.557235] [drm:drm_mode_setcrtc [drm]] [CRTC:42:pipe B]
>[  250.557280] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  250.557339] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  250.557370] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  250.557418] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  250.563729] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 42
>[  250.563786] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  250.563847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  250.563892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  250.563938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  250.563981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  250.564024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  250.564067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  250.564110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  250.564153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  250.564196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  250.564242] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:59:DP-1]
>[  250.564286] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  250.564330] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  250.564375] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  250.573707] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  250.573831] [drm:drm_mode_setcrtc [drm]] [CRTC:49:pipe C]
>[  250.573867] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:51:eDP-1]
>[  250.574083] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  250.574132] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  250.574186] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  250.574244] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  250.574290] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  250.574341] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  250.574394] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  250.574445] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  250.574495] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  250.574544] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  250.574593] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  250.574627] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  250.574675] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  250.574705] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  250.574756] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  250.574805] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  250.574855] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  250.574904] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  250.574953] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  250.575007] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  250.575056] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  250.575111] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:141, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  250.575161] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  250.575210] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  250.575260] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  250.575317] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  250.575379] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  250.575471] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  250.575818] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  250.575955] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  250.591989] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  250.592055] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  250.592114] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  250.595461] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  250.595520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  250.595575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  250.595630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  250.595681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  250.595732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  250.595783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  250.595836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  250.595888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  250.595939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  250.595991] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:66:DP-2]
>[  250.596044] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  250.596095] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  250.596148] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  250.596216] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  250.596265] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  250.596417] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  250.596466] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  250.827743] [drm] RC6 on
>[  251.019521] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  251.130270] [drm:wait_panel_status [i915]] Wait complete
>[  251.130351] [drm:edp_panel_on [i915]] Wait for panel power on
>[  251.130432] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  251.237705] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  251.237790] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  251.237868] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  251.237979] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  251.331969] [drm:wait_panel_status [i915]] Wait complete
>[  251.332057] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  251.332139] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  251.333318] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  251.333393] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  251.333471] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  251.334141] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  251.334218] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  251.335184] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  251.335417] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8ab274f67000
>[  251.335754] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  251.335844] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  251.335922] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  251.336004] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  251.343506] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  251.343561] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  251.352604] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  251.352698] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:51:eDP-1]
>[  251.352769] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  251.352885] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  251.436060] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  251.436176] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  251.643533] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  251.643619] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  251.653902] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  251.653972] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  251.654048] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  251.705832] [drm:wait_panel_status [i915]] Wait complete
>[  251.705911] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  251.706002] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  251.706090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  251.706165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  251.706239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  251.706310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  251.706374] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  251.706445] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  251.706515] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  251.706594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  251.706675] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  251.706747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  251.706821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  251.706892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  251.706963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  251.707037] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:51:eDP-1]
>[  251.707110] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  251.707183] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  251.707254] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  251.707323] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  251.707396] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  251.707508] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  251.707599] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  251.707668] [drm:intel_power_well_disable [i915]] disabling DC off
>[  251.707744] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  251.707811] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  251.707879] [drm:intel_power_well_disable [i915]] disabling always-on
>[  251.708757] [drm:drm_mode_addfb2 [drm]] [FB:53]
>[  251.720016] [drm:drm_mode_setcrtc [drm]] [CRTC:49:pipe C]
>[  251.720037] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:51:eDP-1]
>[  251.720092] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  251.720119] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  251.720152] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  251.720185] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  251.720210] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  251.720239] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  251.720268] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  251.720297] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  251.720325] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  251.720351] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  251.720377] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  251.720394] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  251.720421] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  251.720437] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  251.720465] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  251.720491] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  251.720518] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  251.720545] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  251.720571] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  251.720603] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  251.720629] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  251.720659] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  251.720686] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  251.720714] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  251.720743] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  251.720780] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  251.720807] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  251.721058] [drm:intel_power_well_enable [i915]] enabling always-on
>[  251.721081] [drm:intel_power_well_enable [i915]] enabling DC off
>[  251.721355] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  251.721384] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  251.721412] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  251.721444] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  251.721540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  251.721568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  251.721596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  251.721624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  251.721652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  251.721679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  251.721707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  251.721734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  251.721761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  251.721791] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  251.721819] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  251.721846] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  251.721889] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  251.721915] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  251.722033] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  251.722060] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  252.016142] igb 0000:01:00.0 enp1s0: igb: enp1s0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX/TX
>[  252.171536] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  252.232123] [drm:wait_panel_status [i915]] Wait complete
>[  252.232195] [drm:edp_panel_on [i915]] Wait for panel power on
>[  252.232267] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  252.339614] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  252.339688] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  252.339758] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  252.339911] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  252.434390] [drm:wait_panel_status [i915]] Wait complete
>[  252.434486] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  252.434567] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  252.435929] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  252.436005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  252.436084] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  252.436757] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  252.436833] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  252.437798] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  252.438032] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8ab2736d6000
>[  252.438322] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  252.438428] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  252.438504] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  252.438583] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  252.443483] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  252.443534] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  252.455201] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:51:eDP-1]
>[  252.455263] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  252.455372] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  252.538645] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  252.538773] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  252.743521] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  252.743618] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  252.755755] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  252.755834] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  252.755918] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  252.807818] [drm:wait_panel_status [i915]] Wait complete
>[  252.807907] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  252.808008] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  252.808109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  252.808194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  252.808268] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  252.808346] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  252.808425] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  252.808517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  252.808605] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  252.808686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  252.808767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  252.808847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  252.808928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  252.809008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  252.809088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  252.809171] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:51:eDP-1]
>[  252.809254] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  252.809335] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  252.809415] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  252.809496] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  252.809576] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  252.809648] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  252.809737] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  252.809809] [drm:intel_power_well_disable [i915]] disabling DC off
>[  252.809884] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  252.809955] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  252.810027] [drm:intel_power_well_disable [i915]] disabling always-on
>[  252.810972] [drm:drm_mode_addfb2 [drm]] [FB:53]
>[  252.824599] [drm:drm_mode_setcrtc [drm]] [CRTC:49:pipe C]
>[  252.824621] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:66:DP-2]
>[  252.824675] [drm:intel_atomic_check [i915]] [CONNECTOR:66:DP-2] checking for sink bpp constrains
>[  252.824702] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  252.824735] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  252.824764] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  252.824789] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  252.824817] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  252.824847] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  252.824876] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  252.824903] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  252.824930] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  252.824956] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  252.824973] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  252.824999] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  252.825015] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  252.825043] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  252.825070] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080
>[  252.825098] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  252.825125] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  252.825153] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  252.825184] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  252.825211] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  252.825239] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  252.825266] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  252.825294] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  252.825327] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  252.825363] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  252.825392] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  252.825640] [drm:intel_power_well_enable [i915]] enabling always-on
>[  252.825663] [drm:intel_power_well_enable [i915]] enabling DC off
>[  252.825937] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  252.825966] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  252.825993] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  252.826026] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  252.826221] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  252.829486] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  252.829516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  252.829547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  252.829580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  252.829607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  252.829634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  252.829662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  252.829689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  252.829716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  252.829861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  252.829890] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  252.829919] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  252.829946] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  252.829994] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  252.830020] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  252.831909] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  252.831934] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  252.831961] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  252.833364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  252.833389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  252.834692] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  252.834717] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  252.836427] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  252.836457] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  252.838066] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  252.839892] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8ab2736d2000
>[  252.840058] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  252.856853] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:66:DP-2]
>[  252.856892] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  252.856969] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  252.940323] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  252.940417] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  252.959055] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  252.959138] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  252.959217] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  252.963349] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  252.963417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  252.963520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  252.963591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  252.963656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  252.963726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  252.963790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  252.963858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  252.963925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  252.963991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  252.964060] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:66:DP-2]
>[  252.964127] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  252.964195] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  252.964262] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  252.964331] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  252.964390] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  252.964459] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  252.964532] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  252.964591] [drm:intel_power_well_disable [i915]] disabling DC off
>[  252.964655] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  252.964714] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  252.964772] [drm:intel_power_well_disable [i915]] disabling always-on
>[  252.965605] [drm:drm_mode_addfb2 [drm]] [FB:53]
>[  252.975954] [drm:drm_mode_setcrtc [drm]] [CRTC:49:pipe C]
>[  252.975975] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:66:DP-2]
>[  252.976031] [drm:intel_atomic_check [i915]] [CONNECTOR:66:DP-2] checking for sink bpp constrains
>[  252.976058] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  252.976089] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  252.976117] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  252.976142] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  252.976171] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  252.976201] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  252.976230] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  252.976257] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  252.976284] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  252.976310] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  252.976326] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  252.976352] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  252.976369] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  252.976397] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  252.976423] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080
>[  252.976452] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  252.976478] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  252.976505] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  252.976537] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  252.976563] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  252.976593] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  252.976620] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  252.976648] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  252.976679] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  252.976717] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  252.976746] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  252.976994] [drm:intel_power_well_enable [i915]] enabling always-on
>[  252.977017] [drm:intel_power_well_enable [i915]] enabling DC off
>[  252.977292] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  252.977321] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  252.977348] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  252.977380] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  252.977571] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  252.981663] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  252.981693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  252.981724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  252.981755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  252.981782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  252.981808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  252.981837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  252.981863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  252.981890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  252.981917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  252.981947] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  252.981975] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  252.982002] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  252.982044] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  252.982070] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  252.985021] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  252.985046] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  252.985075] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  252.986481] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  252.986506] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  252.987829] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  252.987855] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  252.989558] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  252.989583] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  252.991192] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  252.993711] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8ab2736d7800
>[  252.993866] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  253.010706] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:66:DP-2]
>[  253.010757] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  253.010849] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  253.094104] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  253.094184] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  253.111887] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  253.111948] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  253.112005] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  253.115579] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  253.115626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  253.115674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  253.115726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  253.115771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  253.115815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  253.115860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  253.115904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  253.115949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  253.115995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  253.116040] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:66:DP-2]
>[  253.116084] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  253.116131] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  253.116174] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  253.116222] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  253.116263] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  253.116311] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  253.116361] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  253.116401] [drm:intel_power_well_disable [i915]] disabling DC off
>[  253.116443] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  253.116483] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  253.116523] [drm:intel_power_well_disable [i915]] disabling always-on
>[  253.117262] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  253.149017] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  253.149060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  253.149107] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  253.149157] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  253.149197] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  253.149242] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  253.149287] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  253.149332] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  253.149376] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  253.149418] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  253.149460] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  253.149493] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  253.149535] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  253.149560] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  253.149604] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  253.149646] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  253.149690] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  253.149732] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  253.149775] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  253.149823] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  253.149864] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  253.149910] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  253.149953] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  253.149995] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  253.150038] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  253.150083] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains
>[  253.150126] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  253.150170] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[  253.150213] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  253.150252] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  253.150295] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  253.150338] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  253.150380] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  253.150423] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  253.150465] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  253.150507] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  253.150533] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  253.150574] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  253.150600] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  253.150643] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  253.150686] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080
>[  253.150730] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  253.150772] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  253.150814] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  253.150858] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  253.150900] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  253.150942] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  253.150984] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  253.151027] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  253.151069] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  253.151112] [drm:intel_atomic_check [i915]] [CONNECTOR:66:DP-2] checking for sink bpp constrains
>[  253.151155] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  253.151198] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  253.151240] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  253.151280] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  253.151322] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  253.151365] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  253.151407] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  253.151496] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  253.151538] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  253.151580] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  253.151605] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  253.151647] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  253.151673] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  253.151716] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  253.151759] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080
>[  253.151802] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  253.151845] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  253.151887] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  253.151930] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  253.151972] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  253.152154] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  253.152197] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  253.152240] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  253.152287] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  253.152343] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  253.152386] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  253.152430] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL B
>[  253.152472] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  253.152514] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  253.152556] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  253.152625] [drm:intel_power_well_enable [i915]] enabling always-on
>[  253.152661] [drm:intel_power_well_enable [i915]] enabling DC off
>[  253.152950] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  253.152995] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  253.153104] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  253.153145] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  253.153192] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  253.153347] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  253.157433] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  253.157477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  253.157521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  253.157565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  253.157608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  253.157651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  253.157693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  253.157736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  253.157778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  253.157820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  253.157867] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  253.157911] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  253.157954] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  253.158014] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  253.158057] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  253.158196] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  253.158237] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  253.263538] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  253.330104] [drm:wait_panel_status [i915]] Wait complete
>[  253.330174] [drm:edp_panel_on [i915]] Wait for panel power on
>[  253.330245] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  253.437478] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  253.437548] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  253.437618] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  253.437723] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  253.531498] [drm:wait_panel_status [i915]] Wait complete
>[  253.531578] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  253.531660] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  253.532823] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  253.532890] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  253.532960] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  253.533615] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  253.533682] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  253.534634] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  253.534857] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8ab26e40e800
>[  253.535131] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  253.535225] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  253.535293] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  253.535363] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  253.543526] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  253.543592] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  253.543673] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  253.543744] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  253.543871] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 42
>[  253.543940] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  253.545223] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  253.545290] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  253.545357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  253.579284] [drm:drm_dp_dpcd_access [drm_kms_helper]] Too many retries, giving up. First error: -5
>[  253.579329] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to enable link training
>[  253.579371] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  253.613284] [drm:drm_dp_dpcd_access [drm_kms_helper]] Too many retries, giving up. First error: -5
>[  253.613329] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to start channel equalization
>[  253.613525] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8ab26e40f000
>[  253.613732] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  253.613871] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  253.613916] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  253.615833] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  253.615876] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  253.615919] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  253.617341] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  253.617372] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  253.618694] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  253.618726] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  253.620440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  253.620471] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  253.622100] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  253.624615] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8ab26e409800
>[  253.624783] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  253.641657] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:51:eDP-1]
>[  253.641712] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  253.641821] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  253.641908] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:59:DP-1]
>[  253.641958] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  253.642035] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  253.642123] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:66:DP-2]
>[  253.642172] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  253.642260] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  253.642429] Console: switching to colour frame buffer device 240x67
>[  253.668561] [drm:drm_fb_helper_hotplug_event [drm_kms_helper]] 
>[  253.668570] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[  253.668579] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:51:eDP-1]
>[  253.668615] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  253.668648] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  253.668678] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  253.668706] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  253.668734] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  253.669133] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  253.669487] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[  253.669499] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:51:eDP-1] probed modes :
>[  253.669517] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  253.669525] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:59:DP-1]
>[  253.669557] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  253.669568] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:59:DP-1] disconnected
>[  253.669580] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:63:HDMI-A-1]
>[  253.669608] [drm:intel_hdmi_detect [i915]] [CONNECTOR:63:HDMI-A-1]
>[  253.671485] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  253.671536] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  253.673610] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  253.673645] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb
>[  253.675526] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  253.675570] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  253.677684] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  253.677702] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  253.677716] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:63:HDMI-A-1] disconnected
>[  253.677729] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:66:DP-2]
>[  253.677778] [drm:intel_dp_detect [i915]] [CONNECTOR:66:DP-2]
>[  253.678697] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[  253.679518] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  253.679566] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  253.679611] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  253.679658] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  253.680551] [drm:intel_dp_read_desc [i915]] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  253.680594] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  253.681477] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[  253.681524] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:66:DP-2] probed modes :
>[  253.681553] [drm:drm_mode_debug_printmodeline [drm]] Modeline 92:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  253.681581] [drm:drm_mode_debug_printmodeline [drm]] Modeline 135:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  253.681609] [drm:drm_mode_debug_printmodeline [drm]] Modeline 137:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  253.681636] [drm:drm_mode_debug_printmodeline [drm]] Modeline 131:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  253.681664] [drm:drm_mode_debug_printmodeline [drm]] Modeline 130:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  253.681691] [drm:drm_mode_debug_printmodeline [drm]] Modeline 134:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  253.681719] [drm:drm_mode_debug_printmodeline [drm]] Modeline 107:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  253.681746] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  253.681774] [drm:drm_mode_debug_printmodeline [drm]] Modeline 133:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  253.681802] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  253.681829] [drm:drm_mode_debug_printmodeline [drm]] Modeline 127:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  253.681857] [drm:drm_mode_debug_printmodeline [drm]] Modeline 129:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
>[  253.681884] [drm:drm_mode_debug_printmodeline [drm]] Modeline 128:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  253.681912] [drm:drm_mode_debug_printmodeline [drm]] Modeline 126:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  253.681940] [drm:drm_mode_debug_printmodeline [drm]] Modeline 125:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  253.681967] [drm:drm_mode_debug_printmodeline [drm]] Modeline 98:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  253.681995] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x6
>[  253.682022] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  253.682050] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  253.682077] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  253.682105] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  253.682133] [drm:drm_mode_debug_printmodeline [drm]] Modeline 115:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  253.682160] [drm:drm_mode_debug_printmodeline [drm]] Modeline 136:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  253.682188] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  253.682215] [drm:drm_mode_debug_printmodeline [drm]] Modeline 119:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  253.682245] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  253.682272] [drm:drm_mode_debug_printmodeline [drm]] Modeline 118:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  253.682300] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  253.682327] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  253.682355] [drm:drm_mode_debug_printmodeline [drm]] Modeline 117:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  253.682382] [drm:drm_mode_debug_printmodeline [drm]] Modeline 102:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  253.682410] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  253.682424] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[  253.682473] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[  253.684554] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  253.684595] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  253.686658] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  253.686691] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[  253.688755] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  253.688796] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  253.690889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  253.690933] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  253.690945] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[  253.690960] [drm:drm_setup_crtcs [drm_kms_helper]] connector 51 enabled? yes
>[  253.690971] [drm:drm_setup_crtcs [drm_kms_helper]] connector 59 enabled? no
>[  253.690982] [drm:drm_setup_crtcs [drm_kms_helper]] connector 63 enabled? no
>[  253.690993] [drm:drm_setup_crtcs [drm_kms_helper]] connector 66 enabled? yes
>[  253.691004] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[  253.691048] [drm:intel_fb_initial_config [i915]] looking for cmdline mode on connector eDP-1
>[  253.691089] [drm:intel_fb_initial_config [i915]] looking for preferred mode on connector eDP-1 0
>[  253.691133] [drm:intel_fb_initial_config [i915]] connector eDP-1 on [CRTC:33:pipe A]: 1920x1080
>[  253.691175] [drm:intel_fb_initial_config [i915]] connector DP-1 not enabled, skipping
>[  253.691215] [drm:intel_fb_initial_config [i915]] connector HDMI-A-1 not enabled, skipping
>[  253.691259] [drm:intel_fb_initial_config [i915]] looking for cmdline mode on connector DP-2
>[  253.691299] [drm:intel_fb_initial_config [i915]] looking for preferred mode on connector DP-2 0
>[  253.691342] [drm:intel_fb_initial_config [i915]] connector DP-2 on [CRTC:49:pipe C]: 1920x1080
>[  253.691382] [drm:intel_fb_initial_config [i915]] connector HDMI-A-2 not enabled, skipping
>[  253.691434] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 33 (0,0)
>[  253.691452] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 49 (0,0)
>[  253.691549] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  253.691645] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  253.697642] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 42
>[  253.697708] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  253.697773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  253.697823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  253.697876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  253.697926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  253.697976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  253.698027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  253.698077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  253.698126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  253.698175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  253.698228] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:59:DP-1]
>[  253.698279] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  253.698362] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  253.698412] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  253.708263] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  256.235539] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  256.235614] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  273.811926] Console: switching to colour dummy device 80x25
>[  273.812045] [IGT] kms_pipe_crc_basic: executing
>[  273.855723] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:51:eDP-1]
>[  273.855812] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  273.855893] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  273.855974] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  273.856050] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  273.856128] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  273.856213] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  273.856295] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  273.856823] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  273.857256] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[  273.857286] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:51:eDP-1] probed modes :
>[  273.857338] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  273.857390] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:59:DP-1]
>[  273.857467] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  273.857493] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:59:DP-1] disconnected
>[  273.857532] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:63:HDMI-A-1]
>[  273.857777] [drm:intel_hdmi_detect [i915]] [CONNECTOR:63:HDMI-A-1]
>[  273.859518] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  273.859607] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  273.861745] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  273.861800] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb
>[  273.863508] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  273.863592] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  273.865696] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  273.865725] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  273.865748] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:63:HDMI-A-1] disconnected
>[  273.865794] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:66:DP-2]
>[  273.865877] [drm:intel_dp_detect [i915]] [CONNECTOR:66:DP-2]
>[  273.866849] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[  273.867712] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  273.867798] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  273.867875] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  273.867956] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  273.868944] [drm:intel_dp_read_desc [i915]] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  273.869011] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  273.869950] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[  273.870022] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:66:DP-2] probed modes :
>[  273.870068] [drm:drm_mode_debug_printmodeline [drm]] Modeline 92:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  273.870111] [drm:drm_mode_debug_printmodeline [drm]] Modeline 135:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  273.870154] [drm:drm_mode_debug_printmodeline [drm]] Modeline 137:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  273.870197] [drm:drm_mode_debug_printmodeline [drm]] Modeline 131:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  273.870240] [drm:drm_mode_debug_printmodeline [drm]] Modeline 130:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  273.870283] [drm:drm_mode_debug_printmodeline [drm]] Modeline 134:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  273.870325] [drm:drm_mode_debug_printmodeline [drm]] Modeline 107:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  273.870368] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  273.870411] [drm:drm_mode_debug_printmodeline [drm]] Modeline 133:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  273.870454] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  273.870497] [drm:drm_mode_debug_printmodeline [drm]] Modeline 127:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  273.870540] [drm:drm_mode_debug_printmodeline [drm]] Modeline 129:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
>[  273.870583] [drm:drm_mode_debug_printmodeline [drm]] Modeline 128:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  273.870625] [drm:drm_mode_debug_printmodeline [drm]] Modeline 126:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  273.870668] [drm:drm_mode_debug_printmodeline [drm]] Modeline 125:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  273.870711] [drm:drm_mode_debug_printmodeline [drm]] Modeline 98:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  273.870754] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x6
>[  273.870797] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  273.870839] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  273.870882] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  273.870925] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  273.870968] [drm:drm_mode_debug_printmodeline [drm]] Modeline 115:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  273.871011] [drm:drm_mode_debug_printmodeline [drm]] Modeline 136:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  273.871053] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  273.871096] [drm:drm_mode_debug_printmodeline [drm]] Modeline 119:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  273.871139] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  273.871182] [drm:drm_mode_debug_printmodeline [drm]] Modeline 118:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  273.871225] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  273.871269] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  273.871312] [drm:drm_mode_debug_printmodeline [drm]] Modeline 117:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  273.871355] [drm:drm_mode_debug_printmodeline [drm]] Modeline 102:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  273.871398] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  273.871522] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[  273.871575] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[  273.873659] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  273.873855] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  273.875463] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  273.875498] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[  273.877608] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  273.877675] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  273.879452] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  273.879472] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  273.879485] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[  273.880443] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:51:eDP-1]
>[  273.880496] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  273.880539] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  273.880583] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  273.880624] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  273.880666] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  273.881102] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  273.881475] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[  273.881492] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:51:eDP-1] probed modes :
>[  273.881518] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  273.881606] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:59:DP-1]
>[  273.881651] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  273.881670] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:59:DP-1] disconnected
>[  273.881728] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:63:HDMI-A-1]
>[  273.881769] [drm:intel_hdmi_detect [i915]] [CONNECTOR:63:HDMI-A-1]
>[  273.883517] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  273.883574] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  273.885657] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  273.885698] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb
>[  273.887474] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  273.887531] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  273.889639] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  273.889661] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  273.889678] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:63:HDMI-A-1] disconnected
>[  273.889959] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:66:DP-2]
>[  273.890023] [drm:intel_dp_detect [i915]] [CONNECTOR:66:DP-2]
>[  273.890964] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[  273.891786] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  273.891846] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  273.891901] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  273.891957] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  273.892865] [drm:intel_dp_read_desc [i915]] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  273.892919] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  273.893829] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[  273.893889] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:66:DP-2] probed modes :
>[  273.893927] [drm:drm_mode_debug_printmodeline [drm]] Modeline 92:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  273.893962] [drm:drm_mode_debug_printmodeline [drm]] Modeline 135:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  273.893997] [drm:drm_mode_debug_printmodeline [drm]] Modeline 137:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  273.894032] [drm:drm_mode_debug_printmodeline [drm]] Modeline 131:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  273.894067] [drm:drm_mode_debug_printmodeline [drm]] Modeline 130:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  273.894104] [drm:drm_mode_debug_printmodeline [drm]] Modeline 134:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  273.894139] [drm:drm_mode_debug_printmodeline [drm]] Modeline 107:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  273.894174] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  273.894209] [drm:drm_mode_debug_printmodeline [drm]] Modeline 133:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  273.894244] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  273.894279] [drm:drm_mode_debug_printmodeline [drm]] Modeline 127:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  273.894313] [drm:drm_mode_debug_printmodeline [drm]] Modeline 129:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
>[  273.894348] [drm:drm_mode_debug_printmodeline [drm]] Modeline 128:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  273.894383] [drm:drm_mode_debug_printmodeline [drm]] Modeline 126:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  273.894418] [drm:drm_mode_debug_printmodeline [drm]] Modeline 125:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  273.894453] [drm:drm_mode_debug_printmodeline [drm]] Modeline 98:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  273.894488] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x6
>[  273.894523] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  273.894558] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  273.894593] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  273.894628] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  273.894663] [drm:drm_mode_debug_printmodeline [drm]] Modeline 115:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  273.894698] [drm:drm_mode_debug_printmodeline [drm]] Modeline 136:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  273.894733] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  273.894768] [drm:drm_mode_debug_printmodeline [drm]] Modeline 119:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  273.894803] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  273.894837] [drm:drm_mode_debug_printmodeline [drm]] Modeline 118:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  273.894872] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  273.894907] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  273.894942] [drm:drm_mode_debug_printmodeline [drm]] Modeline 117:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  273.894977] [drm:drm_mode_debug_printmodeline [drm]] Modeline 102:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  273.895012] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  273.895150] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[  273.895212] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[  273.897298] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  273.897349] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  273.899451] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  273.899523] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[  273.901644] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  273.901702] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  273.903453] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  273.903469] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  273.903483] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[  273.903650] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-A
>[  273.961473] PM: Syncing filesystems ... done.
>[  273.969446] PM: Preparing system for sleep (mem)
>[  273.977328] Freezing user space processes ... (elapsed 0.009 seconds) done.
>[  273.987129] Freezing remaining freezable tasks ... (elapsed 0.007 seconds) done.
>[  273.994988] PM: Suspending system (mem)
>[  273.995810] Suspending console(s) (use no_console_suspend to debug)
>[  274.840991] hpet1: lost 7161 rtc interrupts
>[  275.763790] hpet1: lost 7161 rtc interrupts
>[  276.382342] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  276.459999] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  276.460154] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  276.566981] sd 0:0:0:0: [sda] Stopping disk
>[  276.620404] igb 0000:01:00.0: System wakeup enabled by ACPI
>[  276.621898] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  276.622038] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  276.622288] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  276.622538] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  276.622675] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  276.622931] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  276.623065] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  276.623210] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  276.623343] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  276.623595] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  276.623727] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  276.623865] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  276.623996] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  276.624129] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  276.624263] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  276.624407] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  276.624541] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  276.624683] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  276.624815] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  276.624958] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  276.625094] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  276.625229] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:141, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  276.625368] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  276.625500] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  276.625631] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  276.625761] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  276.625906] [drm:intel_atomic_check [i915]] [CONNECTOR:66:DP-2] checking for sink bpp constrains
>[  276.626037] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  276.626176] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  276.626323] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  276.626452] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  276.626589] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  276.626721] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  276.626869] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  276.627001] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  276.627151] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  276.627281] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  276.627407] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  276.627538] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  276.627659] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  276.627791] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  276.627922] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080
>[  276.628054] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  276.628185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  276.628333] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  276.628465] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  276.628607] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  276.628741] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:141, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  276.628892] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  276.629025] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  276.629279] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  276.629531] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  276.630005] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  276.630142] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  276.630288] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  276.630420] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  276.631267] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  276.651570] ACPI : EC: event blocked
>[  276.692375] hpet1: lost 7161 rtc interrupts
>[  276.840031] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  276.840293] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  276.856031] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  276.856281] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  276.856795] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  276.856932] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  276.857069] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  276.907668] [drm:wait_panel_status [i915]] Wait complete
>[  276.907802] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  276.908056] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  276.908980] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  276.909347] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  276.909373] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  276.909400] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  276.909438] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  276.909649] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  276.932350] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  276.932708] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  276.932960] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  276.935566] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  276.935703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  276.935839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  276.935976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  276.936110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  276.936243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  276.936378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  276.936510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  276.936643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  276.936775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  276.936910] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  276.937045] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  276.937178] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  276.937424] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:51:eDP-1]
>[  276.937561] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  276.937806] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  276.937939] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:66:DP-2]
>[  276.938074] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  276.938209] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  276.941105] PM: suspend of devices complete after 561.792 msecs
>[  276.945487] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  276.945514] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  276.945538] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  276.945569] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  276.945593] [drm:intel_power_well_disable [i915]] disabling DC off
>[  276.945618] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  276.945644] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  276.945671] [drm:intel_power_well_disable [i915]] disabling always-on
>[  276.946174] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  276.946218] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 19200 kHz (VCO 0 kHz)
>[  276.950279] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  276.950302] [drm:intel_power_well_disable [i915]] disabling power well 1
>[  276.950330] [drm:skl_set_power_well [i915]] Disabling power well 1
>[  276.950356] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC
>[  276.950387] [drm:bxt_enable_dc9 [i915]] Enabling DC9
>[  276.950414] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08
>[  276.967554] PM: late suspend of devices complete after 26.442 msecs
>[  276.968278] ACPI : EC: interrupt blocked
>[  276.969255] xhci_hcd 0000:00:15.0: System wakeup enabled by ACPI
>[  276.969258] pcieport 0000:00:13.0: invalid power transition (from state 4 to 3)
>[  276.991287] PM: noirq suspend of devices complete after 23.727 msecs
>[  276.991554] ACPI: Preparing to enter system sleep state S3
>[  276.992013] ACPI : EC: EC stopped
>[  276.992015] PM: Saving platform NVS memory
>[  276.992018] Disabling non-boot CPUs ...
>[  276.992923] Broke affinity for irq 367
>[  276.993973] smpboot: CPU 1 is now offline
>[  277.009139] Broke affinity for irq 367
>[  277.009143] Broke affinity for irq 373
>[  277.010202] smpboot: CPU 2 is now offline
>[  277.033200] Broke affinity for irq 1
>[  277.033229] Broke affinity for irq 8
>[  277.033238] Broke affinity for irq 9
>[  277.033248] Broke affinity for irq 14
>[  277.033290] Broke affinity for irq 30
>[  277.033373] Broke affinity for irq 50
>[  277.033385] Broke affinity for irq 121
>[  277.033454] Broke affinity for irq 367
>[  277.033458] Broke affinity for irq 373
>[  277.034523] smpboot: CPU 3 is now offline
>[  277.056099] ACPI: Low-level resume complete
>[  277.056979] ACPI : EC: EC started
>[  277.056982] PM: Restoring platform NVS memory
>[  277.058063] Suspended for 13.792 seconds
>[  277.058319] Enabling non-boot CPUs ...
>[  277.070122] x86: Booting SMP configuration:
>[  277.070127] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  277.071219] Skipped synchronization checks as TSC is reliable.
>[  277.072620]  cache: parent cpu1 should not be sleeping
>[  277.073804] CPU1 is up
>[  277.089692] smpboot: Booting Node 0 Processor 2 APIC 0x4
>[  277.090414] Skipped synchronization checks as TSC is reliable.
>[  277.091360]  cache: parent cpu2 should not be sleeping
>[  277.092189] CPU2 is up
>[  277.105619] smpboot: Booting Node 0 Processor 3 APIC 0x6
>[  277.106223] Skipped synchronization checks as TSC is reliable.
>[  277.107012]  cache: parent cpu3 should not be sleeping
>[  277.107894] CPU3 is up
>[  277.111267] ACPI: Waking up from system sleep state S3
>[  277.120701] acpi LNXPOWER:04: Turning ON
>[  277.146400] acpi LNXPOWER:15: Turning OFF
>[  277.183186] acpi LNXPOWER:12: Turning OFF
>[  277.183700] acpi LNXPOWER:09: Turning OFF
>[  277.183952] acpi LNXPOWER:07: Turning OFF
>[  277.184173] acpi LNXPOWER:06: Turning OFF
>[  277.185232] ACPI : EC: interrupt unblocked
>[  277.205560] xhci_hcd 0000:00:15.0: System wakeup disabled by ACPI
>[  277.217327] PM: noirq resume of devices complete after 32.261 msecs
>[  277.217642] [drm:gen9_sanitize_dc_state [i915]] Resetting DC state tracking from 08 to 00
>[  277.217683] [drm:bxt_disable_dc9 [i915]] Disabling DC9
>[  277.217723] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  277.217772] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 4
>[  277.217971] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  277.218013] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  277.218068] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  277.218401] [drm:intel_power_well_enable [i915]] enabling always-on
>[  277.218440] [drm:intel_power_well_enable [i915]] enabling DC off
>[  277.218480] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  277.218523] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  277.218563] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  277.218678] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  277.218800] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  277.218903] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 1 already enabled, won't reprogram it
>[  277.218988] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>[  277.225596] PM: early resume of devices complete after 8.140 msecs
>[  277.225759] ACPI : EC: event unblocked
>[  277.226298] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x79cff018
>[  277.226437] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  277.226492] [drm:intel_opregion_setup [i915]] ASLE supported
>[  277.226551] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  277.226654] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  277.226712] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  277.227052] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  277.227190] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  277.227313] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  277.227436] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  277.227504] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[  277.227509] [drm] GuC firmware load skipped
>[  277.227575] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  277.227636] [drm:bxt_hpd_irq_setup [i915]] Invert bit setting: hp_ctl:10001010 hp_port:38
>[  277.227712] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:33:pipe A] hw state readout: disabled
>[  277.227775] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:42:pipe B] hw state readout: disabled
>[  277.227838] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:49:pipe C] hw state readout: disabled
>[  277.227922] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0
>[  277.227966] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0
>[  277.228010] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0
>[  277.228055] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI A] hw state readout: disabled, pipe A
>[  277.228099] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI B] hw state readout: disabled, pipe A
>[  277.228144] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A
>[  277.228187] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B
>[  277.228230] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C
>[  277.228274] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DDI C] hw state readout: disabled, pipe A
>[  277.228317] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:67:DP-MST A] hw state readout: disabled, pipe A
>[  277.228359] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:68:DP-MST B] hw state readout: disabled, pipe B
>[  277.228402] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:69:DP-MST C] hw state readout: disabled, pipe C
>[  277.228447] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:eDP-1] hw state readout: disabled
>[  277.228491] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-1] hw state readout: disabled
>[  277.228535] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:63:HDMI-A-1] hw state readout: disabled
>[  277.228580] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:66:DP-2] hw state readout: disabled
>[  277.228624] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:70:HDMI-A-2] hw state readout: disabled
>[  277.228671] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][setup_hw_state]
>[  277.228716] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  277.228758] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  277.228800] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  277.228832] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  277.228875] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  277.228900] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  277.228943] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  277.228986] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  277.229071] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  277.229114] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  277.229156] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  277.229204] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  277.229246] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  277.229291] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:141, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  277.229335] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  277.229378] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  277.229420] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  277.229464] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  277.229508] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][setup_hw_state]
>[  277.229551] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  277.229593] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  277.229635] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  277.229664] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  277.229706] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  277.229731] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  277.229774] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  277.229816] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  277.229859] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  277.229901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  277.229943] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  277.229987] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  277.230029] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  277.230072] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  277.230114] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  277.230157] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  277.230199] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  277.230243] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][setup_hw_state]
>[  277.230285] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  277.230327] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  277.230369] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  277.230401] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  277.230443] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  277.230468] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  277.230511] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  277.230556] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  277.230598] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  277.230640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  277.230682] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  277.230728] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  277.230770] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  277.230816] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:141, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  277.230859] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  277.230901] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  277.230944] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  277.231031] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  277.231069] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  277.231107] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  277.231151] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  277.231189] [drm:intel_power_well_disable [i915]] disabling DC off
>[  277.231228] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  277.231265] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  277.231634] [drm:intel_power_well_disable [i915]] disabling always-on
>[  277.231698] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  277.231741] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  277.231789] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  277.231838] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  277.231878] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  277.231923] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  277.231968] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  277.232010] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  277.232053] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  277.232095] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  277.232137] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  277.232169] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  277.232213] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  277.232239] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  277.232282] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  277.232325] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  277.232368] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  277.232410] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  277.232452] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  277.232498] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  277.232540] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  277.232587] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:141, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  277.232630] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  277.232672] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  277.232715] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  277.232757] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  277.232802] [drm:intel_atomic_check [i915]] [CONNECTOR:66:DP-2] checking for sink bpp constrains
>[  277.232845] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  277.232886] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  277.232928] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  277.232969] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  277.233025] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  277.233068] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  277.233110] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  277.233153] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  277.233195] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  277.233237] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  277.233265] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  277.233307] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  277.233332] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  277.233377] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  277.233419] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080
>[  277.233462] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  277.233504] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  277.233546] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  277.233590] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  277.233632] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  277.233677] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:141, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  277.233720] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  277.233762] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  277.233805] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  277.233850] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  277.233904] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  277.233947] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  277.233992] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  277.234035] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  277.234108] [drm:intel_power_well_enable [i915]] enabling always-on
>[  277.234110] igb 0000:01:00.0: System wakeup disabled by ACPI
>[  277.234114] rtc_cmos 00:04: System wakeup disabled by ACPI
>[  277.234151] [drm:intel_power_well_enable [i915]] enabling DC off
>[  277.234350] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  277.234393] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  277.236336] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  277.236374] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  277.236421] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  277.236555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  277.236599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  277.236644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  277.236688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  277.236730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  277.236773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  277.236816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  277.236859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  277.236901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  277.236946] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:59:DP-1]
>[  277.236990] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:63:HDMI-A-1]
>[  277.237062] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:70:HDMI-A-2]
>[  277.237108] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  277.237152] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  277.237194] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  277.237255] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  277.237296] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  277.237439] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  277.237480] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  277.237528] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000062
>[  277.237569] [drm:wait_panel_status [i915]] Wait complete
>[  277.237611] [drm:edp_panel_on [i915]] Wait for panel power on
>[  277.237654] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  277.241524] sd 0:0:0:0: [sda] Starting disk
>[  277.344887] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  277.344933] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  277.344979] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  277.345036] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  277.438772] [drm:wait_panel_status [i915]] Wait complete
>[  277.438843] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  277.438909] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  277.440044] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  277.440104] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  277.440168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  277.440810] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  277.440870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  277.441815] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  277.442029] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8ab26e40b800
>[  277.442279] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  277.442368] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  277.442428] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  277.442491] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  277.449100] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  277.449160] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  277.449231] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  277.449294] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  277.449406] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  277.449468] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  277.451498] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  277.451558] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  277.451619] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  277.454128] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  277.454190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  277.455946] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  277.456005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  277.456987] atkbd serio0: Failed to deactivate keyboard on isa0060/serio0
>[  277.457634] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  277.460138] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8ab26e40a800
>[  277.460314] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  277.477119] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:51:eDP-1]
>[  277.477162] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  277.477245] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  277.477302] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  277.477361] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:66:DP-2]
>[  277.477404] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  277.477479] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  277.477560] [drm:bxt_hpd_irq_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  277.477597] [drm:intel_opregion_register [i915]] 5 outputs detected
>[  277.477637] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  277.477673] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  277.477711] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  277.477747] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  277.477783] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  277.480786] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  277.481129] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:51:eDP-1] status updated from connected to connected
>[  277.481180] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  277.481197] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:59:DP-1] status updated from disconnected to disconnected
>[  277.481248] [drm:intel_hdmi_detect [i915]] [CONNECTOR:63:HDMI-A-1]
>[  277.482704] PM: resume of devices complete after 257.100 msecs
>[  277.483115] PM: Finishing wakeup.
>[  277.483118] Restarting tasks ... 
>[  277.483340] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  277.483401] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  277.484508] done.
>[  277.486973] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  277.487016] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb
>[  277.489102] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  277.489157] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  277.491218] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  277.491234] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  277.491243] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:63:HDMI-A-1] status updated from disconnected to disconnected
>[  277.491271] [drm:intel_dp_detect [i915]] [CONNECTOR:66:DP-2]
>[  277.492225] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[  277.493064] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  277.493093] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  277.493119] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  277.493145] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  277.494090] [drm:intel_dp_read_desc [i915]] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  277.494118] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  277.494955] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:66:DP-2] status updated from connected to connected
>[  277.494992] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[  277.497024] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  277.497050] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  277.499113] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  277.499140] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[  277.501057] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  277.501084] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  277.503122] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  277.503136] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  277.503146] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] status updated from disconnected to disconnected
>[  277.503320] [drm:drm_mode_addfb2 [drm]] [FB:53]
>[  277.510343] [drm:drm_mode_setcrtc [drm]] [CRTC:33:pipe A]
>[  277.510364] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:51:eDP-1]
>[  277.542455] [drm:drm_mode_setcrtc [drm]] [CRTC:42:pipe B]
>[  277.542586] [drm:drm_mode_setcrtc [drm]] [CRTC:49:pipe C]
>[  277.542684] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  277.542760] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  277.542824] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  277.542925] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  277.713014] atkbd serio0: Failed to enable keyboard on isa0060/serio0
>[  277.749117] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  277.749216] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  277.759332] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  277.759411] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  277.759493] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  277.765027] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  277.811106] [drm:wait_panel_status [i915]] Wait complete
>[  277.811192] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  277.811279] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  277.811380] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  277.811486] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  277.811755] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  277.811833] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  277.811913] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  277.812029] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  277.817329] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000010, dig 0x1800181a, pins 0x00000020
>[  277.817410] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - long
>[  277.817489] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 5 - cnt: 0
>[  277.817585] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - long
>[  277.827594] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  277.827698] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  277.827798] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  277.831129] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  277.831212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  277.831294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  277.831379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  277.831460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  277.831540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  277.831620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  277.831702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  277.831783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  277.831863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  277.831943] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:66:DP-2]
>[  277.832026] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  277.832108] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  277.832188] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  277.832292] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  277.832370] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  277.832601] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  277.832678] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  277.903299] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000010, dig 0x18001819, pins 0x00000020
>[  277.903383] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  277.903489] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  278.289125] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  278.343428] [drm:wait_panel_status [i915]] Wait complete
>[  278.343509] [drm:edp_panel_on [i915]] Wait for panel power on
>[  278.343592] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  278.386988] ata1.00: configured for UDMA/133
>[  278.450761] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  278.450790] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  278.450818] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  278.543953] [drm:wait_panel_status [i915]] Wait complete
>[  278.544009] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  278.544054] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  278.544675] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  278.545401] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  278.545457] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  278.545516] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  278.546632] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  278.546688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  278.547620] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  278.547828] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8ab26e23c800
>[  278.548130] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  278.548198] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  278.548253] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  278.548311] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  278.553107] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  278.553163] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  278.553234] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  278.553293] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  278.581700] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:51:eDP-1]
>[  278.581775] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  278.581900] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  278.581990] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  278.582453] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  278.582512] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  278.582577] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  278.582669] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  278.582734] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[  278.582798] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[  278.582861] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  278.582918] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  278.582976] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  278.583042] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  278.583603] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  278.584374] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  278.584440] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  278.584501] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  278.584564] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  278.585044] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.1 SW-rev 1.39
>[  278.585599] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  278.586052] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.587257] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.588486] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.589755] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.590980] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.592159] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.593333] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.594539] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.595703] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.597025] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.598325] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.599621] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.600950] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.602269] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.603589] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.604889] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.606187] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.607350] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.608525] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.609715] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.610884] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.612195] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.613506] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.614809] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.616111] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.617475] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.618777] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.620107] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.621476] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  278.622242] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support
>[  278.622590] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  278.622626] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  278.622668] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  278.622711] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:59:DP-1] status updated from disconnected to connected
>[  278.622750] [drm:i915_hotplug_work_func [i915]] Connector HDMI-A-1 (pin 5) received hotplug event.
>[  278.622786] [drm:intel_hdmi_detect [i915]] [CONNECTOR:63:HDMI-A-1]
>[  278.622818] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  278.622851] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  278.624995] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  278.625089] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  278.627148] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  278.627178] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb
>[  278.629031] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  278.629068] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  278.631164] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  278.631191] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  278.631246] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  278.631287] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  278.648437] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  278.648515] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  278.833355] [drm] RC6 on
>[  278.853347] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  278.853447] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  278.865374] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  278.865452] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  278.865538] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  278.917451] [drm:wait_panel_status [i915]] Wait complete
>[  278.917534] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  278.917622] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  278.917727] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  278.917830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  278.917912] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  278.917993] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  278.918075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  278.918158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  278.918236] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  278.918319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  278.918399] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  278.918489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  278.918584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  278.918673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  278.918764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  278.918854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  278.918947] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:51:eDP-1]
>[  278.919034] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  278.919120] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  278.919203] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  278.919290] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  278.919380] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  278.919460] [drm:intel_power_well_disable [i915]] disabling DC off
>[  278.919535] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  278.919609] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  278.919682] [drm:intel_power_well_disable [i915]] disabling always-on
>[  278.920597] [drm:drm_mode_addfb2 [drm]] [FB:53]
>[  278.931907] [drm:drm_mode_setcrtc [drm]] [CRTC:33:pipe A]
>[  278.931928] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:51:eDP-1]
>[  278.931984] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  278.932011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  278.932043] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  278.932076] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  278.932101] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  278.932129] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  278.932159] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  278.932188] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  278.932216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  278.932243] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  278.932269] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  278.932286] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  278.932312] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  278.932328] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  278.932472] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  278.932499] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  278.932527] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  278.932554] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  278.932580] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  278.932612] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  278.932638] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  278.932668] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  278.932695] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  278.932723] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  278.932751] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  278.932783] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  278.932820] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  278.932847] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  278.933199] [drm:intel_power_well_enable [i915]] enabling always-on
>[  278.933223] [drm:intel_power_well_enable [i915]] enabling DC off
>[  278.933498] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  278.933529] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  278.933625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  278.933653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  278.933683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  278.933712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  278.933739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  278.933769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  278.933796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  278.933825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  278.933852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  278.933881] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  278.933909] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  278.933939] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  278.933980] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  278.934007] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  278.934125] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  278.934152] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  279.377115] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  279.443554] [drm:wait_panel_status [i915]] Wait complete
>[  279.443635] [drm:edp_panel_on [i915]] Wait for panel power on
>[  279.443718] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  279.551019] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  279.551101] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  279.551180] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  279.551286] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  279.645764] [drm:wait_panel_status [i915]] Wait complete
>[  279.645855] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  279.645937] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  279.647113] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  279.647188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  279.647267] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  279.647961] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  279.648036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  279.648693] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  279.648770] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  279.649755] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  279.649992] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8ab273636800
>[  279.650323] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  279.650417] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  279.650492] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  279.650571] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  279.657104] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  279.657149] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  279.657204] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  279.657250] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  279.667214] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:51:eDP-1]
>[  279.667287] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  279.667410] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  279.750629] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  279.750753] [drm:intel_edp_backlight_off.part.28 [i915]] 
>[  279.957105] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  279.957200] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  279.967438] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  279.967516] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  279.967599] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  280.019602] [drm:wait_panel_status [i915]] Wait complete
>[  280.019685] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  280.019771] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  280.019885] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  280.019963] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  280.020043] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  280.020124] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  280.020225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  280.020305] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  280.020402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  280.020495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  280.020583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  280.020672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  280.020753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  280.020838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  280.020921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  280.021006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  280.021143] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:51:eDP-1]
>[  280.021232] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  280.021315] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  280.021401] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  280.021484] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  280.021576] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  280.021657] [drm:intel_power_well_disable [i915]] disabling DC off
>[  280.021733] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  280.021807] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  280.021879] [drm:intel_power_well_disable [i915]] disabling always-on
>[  280.027932] [IGT] kms_pipe_crc_basic: exiting, ret=99
>[  280.073384] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  280.073435] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  280.073489] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  280.073547] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  280.073593] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  280.073645] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  280.073697] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  280.073748] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  280.073799] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  280.073847] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  280.073896] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  280.073934] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  280.073982] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  280.074012] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  280.074062] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  280.074111] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  280.074161] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  280.074210] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  280.074259] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  280.074314] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  280.074362] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  280.074415] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  280.074463] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  280.074512] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  280.074561] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  280.074614] [drm:intel_atomic_check [i915]] [CONNECTOR:66:DP-2] checking for sink bpp constrains
>[  280.074663] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  280.074712] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  280.074761] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  280.074807] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  280.074856] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  280.074906] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  280.074954] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  280.075004] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  280.075053] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  280.075101] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  280.075131] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  280.075179] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  280.075209] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  280.075259] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  280.075308] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080
>[  280.075359] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  280.075407] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  280.075456] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  280.075508] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  280.075557] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  280.075605] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  280.075654] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  280.075703] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  280.075756] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  280.075819] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  280.075868] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  280.075919] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  280.075967] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  280.076041] [drm:intel_power_well_enable [i915]] enabling always-on
>[  280.076083] [drm:intel_power_well_enable [i915]] enabling DC off
>[  280.076378] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  280.076555] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  280.076691] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  280.076750] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  280.076816] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  280.076973] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  280.081100] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  280.081168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  280.081233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  280.081301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  280.081365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  280.081430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  280.081494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  280.081559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  280.081623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  280.081687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  280.081754] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  280.081818] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  280.081883] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  280.081968] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  280.082030] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  280.082224] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  280.082288] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  280.249699] igb 0000:01:00.0 enp1s0: igb: enp1s0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX/TX
>[  280.497122] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  280.543536] [drm:wait_panel_status [i915]] Wait complete
>[  280.543616] [drm:edp_panel_on [i915]] Wait for panel power on
>[  280.543827] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  280.650902] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  280.650982] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  280.651060] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  280.651159] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  280.745342] [drm:wait_panel_status [i915]] Wait complete
>[  280.745431] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  280.745512] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  280.746731] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  280.746807] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  280.746887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  280.747570] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  280.747645] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  280.748623] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  280.748861] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8ab272753000
>[  280.749200] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  280.749315] [drm:intel_edp_backlight_on.part.27 [i915]] 
>[  280.749390] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  280.749468] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  280.757094] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  280.757149] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  280.757218] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  280.757276] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  280.757386] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  280.757443] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  280.759366] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  280.759421] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  280.759476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  280.761981] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  280.762035] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  280.763775] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  280.766321] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8ab272752000
>[  280.766549] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  280.783365] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:51:eDP-1]
>[  280.783444] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  280.783571] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  280.783685] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:66:DP-2]
>[  280.783762] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  280.783877] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  280.784123] Console: switching to colour frame buffer device 240x67
>[  280.799928] [drm:drm_fb_helper_hotplug_event [drm_kms_helper]] 
>[  280.799937] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[  280.799946] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:51:eDP-1]
>[  280.799981] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  280.800011] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  280.800041] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  280.800067] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  280.800094] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  280.800498] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  280.800850] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[  280.800862] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:51:eDP-1] probed modes :
>[  280.800879] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  280.800887] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:59:DP-1]
>[  280.800912] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  280.801672] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  280.802385] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  280.802412] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  280.802438] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  280.802465] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  280.802863] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.1 SW-rev 1.39
>[  280.803175] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  280.803637] [drm:drm_add_edid_modes [drm]] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  280.803653] [drm:drm_edid_to_eld [drm]] ELD monitor VX279
>[  280.803669] [drm:drm_edid_to_eld [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  280.803684] [drm:drm_edid_to_eld [drm]] ELD size 28, SAD count 1
>[  280.803720] [drm:drm_mode_debug_printmodeline [drm]] Modeline 88:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  280.803735] [drm:drm_mode_prune_invalid [drm]] Not using 1600x1200 mode: VIRTUAL_Y
>[  280.803750] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:59:DP-1] probed modes :
>[  280.803766] [drm:drm_mode_debug_printmodeline [drm]] Modeline 74:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  280.803783] [drm:drm_mode_debug_printmodeline [drm]] Modeline 145:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  280.803799] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  280.803815] [drm:drm_mode_debug_printmodeline [drm]] Modeline 147:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  280.803831] [drm:drm_mode_debug_printmodeline [drm]] Modeline 142:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  280.803847] [drm:drm_mode_debug_printmodeline [drm]] Modeline 138:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  280.803863] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  280.803879] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  280.803895] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  280.803911] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  280.803928] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  280.803944] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  280.803960] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  280.803976] [drm:drm_mode_debug_printmodeline [drm]] Modeline 148:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  280.803992] [drm:drm_mode_debug_printmodeline [drm]] Modeline 144:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  280.804008] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  280.804024] [drm:drm_mode_debug_printmodeline [drm]] Modeline 103:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  280.804040] [drm:drm_mode_debug_printmodeline [drm]] Modeline 104:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  280.804056] [drm:drm_mode_debug_printmodeline [drm]] Modeline 106:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  280.804072] [drm:drm_mode_debug_printmodeline [drm]] Modeline 108:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  280.804088] [drm:drm_mode_debug_printmodeline [drm]] Modeline 89:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  280.804104] [drm:drm_mode_debug_printmodeline [drm]] Modeline 90:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  280.804120] [drm:drm_mode_debug_printmodeline [drm]] Modeline 139:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  280.804136] [drm:drm_mode_debug_printmodeline [drm]] Modeline 149:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  280.804152] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  280.804168] [drm:drm_mode_debug_printmodeline [drm]] Modeline 91:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  280.804184] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  280.804201] [drm:drm_mode_debug_printmodeline [drm]] Modeline 150:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  280.804217] [drm:drm_mode_debug_printmodeline [drm]] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  280.804233] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  280.804241] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:63:HDMI-A-1]
>[  280.804268] [drm:intel_hdmi_detect [i915]] [CONNECTOR:63:HDMI-A-1]
>[  280.806333] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  280.806360] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  280.808464] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  280.808519] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb
>[  280.810573] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  280.810599] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  280.812694] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  280.812722] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  280.812746] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:63:HDMI-A-1] disconnected
>[  280.812786] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:66:DP-2]
>[  280.812815] [drm:intel_dp_detect [i915]] [CONNECTOR:66:DP-2]
>[  280.813725] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[  280.814527] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  280.814569] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  280.814608] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  280.814646] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  280.815531] [drm:intel_dp_read_desc [i915]] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  280.815569] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  280.816451] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[  280.816494] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:66:DP-2] probed modes :
>[  280.816520] [drm:drm_mode_debug_printmodeline [drm]] Modeline 92:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  280.816544] [drm:drm_mode_debug_printmodeline [drm]] Modeline 135:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  280.816568] [drm:drm_mode_debug_printmodeline [drm]] Modeline 137:"1680x945" 60 131481 1680 1784 1960 2240 945 946 949 978 0x0 0x6
>[  280.816593] [drm:drm_mode_debug_printmodeline [drm]] Modeline 131:"1400x1050" 75 156000 1400 1504 1648 1896 1050 1053 1057 1099 0x40 0x6
>[  280.816617] [drm:drm_mode_debug_printmodeline [drm]] Modeline 130:"1400x1050" 60 121750 1400 1488 1632 1864 1050 1053 1057 1089 0x40 0x6
>[  280.816641] [drm:drm_mode_debug_printmodeline [drm]] Modeline 134:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  280.816665] [drm:drm_mode_debug_printmodeline [drm]] Modeline 107:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  280.816689] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  280.816713] [drm:drm_mode_debug_printmodeline [drm]] Modeline 133:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  280.816738] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  280.816762] [drm:drm_mode_debug_printmodeline [drm]] Modeline 127:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  280.816786] [drm:drm_mode_debug_printmodeline [drm]] Modeline 129:"1366x768" 60 85500 1366 1436 1579 1792 768 771 774 798 0x40 0x5
>[  280.816810] [drm:drm_mode_debug_printmodeline [drm]] Modeline 128:"1360x768" 60 85500 1360 1424 1536 1792 768 771 777 795 0x40 0x5
>[  280.816834] [drm:drm_mode_debug_printmodeline [drm]] Modeline 126:"1280x800" 75 106500 1280 1360 1488 1696 800 803 809 838 0x40 0x6
>[  280.816860] [drm:drm_mode_debug_printmodeline [drm]] Modeline 125:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  280.816885] [drm:drm_mode_debug_printmodeline [drm]] Modeline 98:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  280.816909] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"1280x768" 75 102250 1280 1360 1488 1696 768 771 778 805 0x40 0x6
>[  280.816933] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"1280x768" 60 79500 1280 1344 1472 1664 768 771 778 798 0x40 0x6
>[  280.816957] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  280.816981] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  280.817054] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  280.817084] [drm:drm_mode_debug_printmodeline [drm]] Modeline 115:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  280.817110] [drm:drm_mode_debug_printmodeline [drm]] Modeline 136:"1024x576" 60 46970 1024 1064 1168 1312 576 577 580 597 0x0 0x6
>[  280.817140] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  280.817167] [drm:drm_mode_debug_printmodeline [drm]] Modeline 119:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  280.817194] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  280.817222] [drm:drm_mode_debug_printmodeline [drm]] Modeline 118:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  280.817250] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"848x480" 60 33750 848 864 976 1088 480 486 494 517 0x40 0x5
>[  280.817278] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  280.817302] [drm:drm_mode_debug_printmodeline [drm]] Modeline 117:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  280.817327] [drm:drm_mode_debug_printmodeline [drm]] Modeline 102:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  280.817351] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  280.817367] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[  280.817418] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[  280.819551] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  280.819590] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  280.821066] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  280.821100] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[  280.823208] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  280.823266] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  280.825037] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  280.825055] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  280.825068] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[  280.825083] [drm:drm_setup_crtcs [drm_kms_helper]] connector 51 enabled? yes
>[  280.825095] [drm:drm_setup_crtcs [drm_kms_helper]] connector 59 enabled? yes
>[  280.825106] [drm:drm_setup_crtcs [drm_kms_helper]] connector 63 enabled? no
>[  280.825116] [drm:drm_setup_crtcs [drm_kms_helper]] connector 66 enabled? yes
>[  280.825127] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[  280.825170] [drm:intel_fb_initial_config [i915]] looking for cmdline mode on connector eDP-1
>[  280.825209] [drm:intel_fb_initial_config [i915]] looking for preferred mode on connector eDP-1 0
>[  280.825251] [drm:intel_fb_initial_config [i915]] connector eDP-1 on [CRTC:33:pipe A]: 1920x1080
>[  280.825290] [drm:intel_fb_initial_config [i915]] connector DP-1 has no encoder or crtc, skipping
>[  280.825330] [drm:intel_fb_initial_config [i915]] connector HDMI-A-1 not enabled, skipping
>[  280.825370] [drm:intel_fb_initial_config [i915]] looking for cmdline mode on connector DP-2
>[  280.825410] [drm:intel_fb_initial_config [i915]] looking for preferred mode on connector DP-2 0
>[  280.825450] [drm:intel_fb_initial_config [i915]] connector DP-2 on [CRTC:49:pipe C]: 1920x1080
>[  280.825489] [drm:intel_fb_initial_config [i915]] connector HDMI-A-2 not enabled, skipping
>[  280.825528] [drm:intel_fb_initial_config [i915]] fallback: Not all outputs enabled
>[  280.825568] [drm:intel_fb_initial_config [i915]] Enabled: 2, detected: 3
>[  280.825606] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  280.825619] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 51
>[  280.825630] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 51 0
>[  280.825640] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[  280.825650] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 59
>[  280.825662] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 59 0
>[  280.825672] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[  280.825682] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 66
>[  280.825693] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 66 0
>[  280.825705] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[  280.825715] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1080 config
>[  280.825740] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 33 (0,0)
>[  280.825754] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 42 (0,0)
>[  280.825765] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 49 (0,0)
>[  280.825856] [drm:intel_atomic_check [i915]] [CONNECTOR:59:DP-1] checking for sink bpp constrains
>[  280.825897] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  280.825941] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[  280.825984] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  280.826023] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  280.826065] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  280.826108] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  280.826151] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  280.826193] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  280.826234] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  280.826275] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  280.826303] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  280.826344] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  280.826369] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  280.826412] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  280.826453] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080
>[  280.826495] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  280.826537] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  280.826579] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  280.826624] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  280.826665] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  280.826709] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  280.826751] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  280.826791] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  280.826833] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  280.826878] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  280.826932] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL B
>[  280.826975] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  280.827054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  280.827095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  280.827137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  280.827178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  280.827220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  280.827260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DDI C]
>[  280.827302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST A]
>[  280.827342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST B]
>[  280.827385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST C]
>[  280.827427] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL A
>[  280.827488] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  280.827530] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL C
>[  280.833315] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 42
>[  280.833357] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  280.834576] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  280.834616] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  280.834660] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  280.837470] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  280.837508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  280.840612] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  280.842823] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8ab272752000
>[  280.843022] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  280.843088] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:59:DP-1], [ENCODER:58:DDI B]
>[  280.843130] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 28 bytes ELD
>[  280.843173] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  280.859883] [drm:verify_connector_state.isra.84 [i915]] [CONNECTOR:59:DP-1]
>[  280.859949] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  280.860063] [drm:verify_single_dpll_state.isra.114 [i915]] PORT PLL B
>[  283.377118] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  283.377202] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067

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