Attachment 129407 Details for Bug 99710 – DDEBUG_DUMP_#1

DDEBUG_DUMP_#1

ne.exe_4668_00000000 (text/plain), 17.94 KB, created by Garth Theisen on 2017-02-08 05:50:11 UTC

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Creator: Garth Theisen

Created: 2017-02-08 05:50:11 UTC

Size: 17.94 KB

patch

obsolete

>Command: hearthstone.exe                                       
>Driver vendor: X.Org
>Device vendor: AMD
>Device name: AMD HAWAII (DRM 3.8.0 / 4.9.8-gentoo, LLVM 3.9.1)
>
>Draw call sequence # = 1
>HW reached sequence # = 0
>Elapsed time = 1004 ms
>
>clear_render_target:
>
>
>*****************************************************************************
>Driver-specific state:
>
>[1;32mRW buffers slot 0 (CPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 1 (CPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 2 (CPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 3 (CPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 4 (CPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 5 (CPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 6 (CPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 7 (CPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 8 (CPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 9 (CPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x00040a00
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 16 (0x00000010)
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 10 (CPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x00040a00
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 16 (0x00000010)
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 11 (CPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x00040a00
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 16 (0x00000010)
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 12 (CPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x00580000
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 8
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>
>Memory-mapped registers:
>        [1;33mGRBM_STATUS[0m <- ME0PIPE0_CMDFIFO_AVAIL = 8
>                       SRBM_RQ_PENDING = 1
>                       ME0PIPE0_CF_RQ_PENDING = 0
>                       ME0PIPE0_PF_RQ_PENDING = 0
>                       GDS_DMA_RQ_PENDING = 0
>                       DB_CLEAN = 1
>                       CB_CLEAN = 1
>                       TA_BUSY = 0
>                       GDS_BUSY = 0
>                       WD_BUSY_NO_DMA = 0
>                       VGT_BUSY = 0
>                       IA_BUSY_NO_DMA = 0
>                       IA_BUSY = 0
>                       SX_BUSY = 0
>                       WD_BUSY = 0
>                       SPI_BUSY = 0
>                       BCI_BUSY = 0
>                       SC_BUSY = 0
>                       PA_BUSY = 0
>                       DB_BUSY = 0
>                       CP_COHERENCY_BUSY = 0
>                       CP_BUSY = 0
>                       CB_BUSY = 0
>                       GUI_ACTIVE = 0
>
>
>Last 60 lines of dmesg:
>
>[    4.216368] amdgpu 0000:01:00.0: fence driver on ring 8 use gpu addr 0x0000000200000090, cpu addr 0xffff880226614090
>[    4.219151] amdgpu 0000:01:00.0: fence driver on ring 9 use gpu addr 0x00000002000000a0, cpu addr 0xffff8802266140a0
>[    4.219195] amdgpu 0000:01:00.0: fence driver on ring 10 use gpu addr 0x00000002000000b0, cpu addr 0xffff8802266140b0
>[    4.222884] [drm] Found UVD firmware Version: 1.64 Family ID: 9
>[    4.223177] amdgpu 0000:01:00.0: fence driver on ring 11 use gpu addr 0x0000000000853d30, cpu addr 0xffffc90004838d30
>[    4.226075] [drm] Found VCE firmware Version: 50.10 Binary ID: 2
>[    4.226259] amdgpu 0000:01:00.0: fence driver on ring 12 use gpu addr 0x00000002000000d0, cpu addr 0xffff8802266140d0
>[    4.226306] amdgpu 0000:01:00.0: fence driver on ring 13 use gpu addr 0x00000002000000e0, cpu addr 0xffff8802266140e0
>[    4.226356] [drm] PCIE gen 2 link speeds already enabled
>[    4.235589] [drm] ring test on 0 succeeded in 10 usecs
>[    4.235808] [drm] ring test on 1 succeeded in 2 usecs
>[    4.235817] [drm] ring test on 2 succeeded in 3 usecs
>[    4.235823] [drm] ring test on 3 succeeded in 2 usecs
>[    4.235829] [drm] ring test on 4 succeeded in 1 usecs
>[    4.235837] [drm] ring test on 5 succeeded in 2 usecs
>[    4.235843] [drm] ring test on 6 succeeded in 2 usecs
>[    4.235849] [drm] ring test on 7 succeeded in 2 usecs
>[    4.235855] [drm] ring test on 8 succeeded in 2 usecs
>[    4.235966] [drm] ring test on 9 succeeded in 5 usecs
>[    4.235972] [drm] ring test on 10 succeeded in 4 usecs
>[    4.282624] [drm] ring test on 11 succeeded in 1 usecs
>[    4.302667] [drm] UVD initialized successfully.
>[    4.530602] [drm] ring test on 12 succeeded in 6 usecs
>[    4.530639] [drm] ring test on 13 succeeded in 1 usecs
>[    4.530641] [drm] VCE initialized successfully.
>[    4.627250] [drm] fb mappable at 0xD09EF000
>[    4.627251] [drm] vram apper at 0xD0000000
>[    4.627251] [drm] size 8294400
>[    4.627252] [drm] fb depth is 24
>[    4.627252] [drm]    pitch is 7680
>[    4.627315] fbcon: amdgpudrmfb (fb0) is primary device
>[    4.739067] Console: switching to colour frame buffer device 240x67
>[    4.742944] amdgpu 0000:01:00.0: fb0: amdgpudrmfb frame buffer device
>[    4.748927] [drm] ib test on ring 0 succeeded
>[    4.748951] [drm] ib test on ring 1 succeeded
>[    4.748967] [drm] ib test on ring 2 succeeded
>[    4.749096] [drm] ib test on ring 3 succeeded
>[    4.749139] [drm] ib test on ring 4 succeeded
>[    4.749239] [drm] ib test on ring 5 succeeded
>[    4.749271] [drm] ib test on ring 6 succeeded
>[    4.749302] [drm] ib test on ring 7 succeeded
>[    4.749329] [drm] ib test on ring 8 succeeded
>[    4.749353] [drm] ib test on ring 9 succeeded
>[    4.749375] [drm] ib test on ring 10 succeeded
>[    4.750351] [drm] ib test on ring 11 succeeded
>[    4.750684] [drm] ib test on ring 12 succeeded
>[    4.752599] [drm] Initialized amdgpu 3.8.0 20150101 for 0000:01:00.0 on minor 0
>[    4.764304] systemd-udevd (1877) used greatest stack depth: 11480 bytes left
>[    5.302443] EXT4-fs (sda3): re-mounted. Opts: (null)
>[    5.427285] Adding 4200992k swap on /dev/sda2.  Priority:-1 extents:1 across:4200992k SS
>[    5.478633] EXT4-fs (sda1): mounting ext2 file system using the ext4 subsystem
>[    5.482537] EXT4-fs (sda1): mounted filesystem without journal. Opts: (null)
>[    5.492738] EXT4-fs (sdb1): mounted filesystem with ordered data mode. Opts: (null)
>[    7.316516] r8169 0000:03:00.0 eth0: link down
>[    7.316519] r8169 0000:03:00.0 eth0: link down
>[    7.316572] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
>[    7.316775] ip (2921) used greatest stack depth: 11328 bytes left
>[    9.215789] r8169 0000:03:00.0 eth0: link up
>[    9.215802] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
>[   11.043518] random: crng init done

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Attachments on bug 99710: 129407 | 129408 | 129409

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