Attachment 129446 Details for Bug 99738 – dmesg during tests

dmesg during tests

dmesg-during.log (text/plain), 4.97 MB, created by Jani Saarinen on 2017-02-09 18:46:18 UTC

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Creator: Jani Saarinen

Created: 2017-02-09 18:46:18 UTC

Size: 4.97 MB

patch

obsolete

>[   37.096383] Console: switching to colour dummy device 80x25
>[   37.096723] [IGT] core_auth: executing
>[   37.117534] [IGT] core_auth: starting subtest basic-auth
>[   37.118846] [IGT] core_auth: exiting, ret=0
>[   37.157914] Console: switching to colour frame buffer device 240x67
>[   37.285037] Console: switching to colour dummy device 80x25
>[   37.285645] [IGT] core_prop_blob: executing
>[   37.311160] [IGT] core_prop_blob: starting subtest basic
>[   37.311479] [IGT] core_prop_blob: exiting, ret=0
>[   37.358012] Console: switching to colour frame buffer device 240x67
>[   37.476532] Console: switching to colour dummy device 80x25
>[   37.476760] [IGT] drv_getparams_basic: executing
>[   37.501749] [IGT] drv_getparams_basic: starting subtest basic-eu-total
>[   37.501973] [IGT] drv_getparams_basic: exiting, ret=0
>[   37.541315] Console: switching to colour frame buffer device 240x67
>[   37.679064] Console: switching to colour dummy device 80x25
>[   37.679476] [IGT] drv_getparams_basic: executing
>[   37.703649] [IGT] drv_getparams_basic: starting subtest basic-subslice-total
>[   37.703842] [IGT] drv_getparams_basic: exiting, ret=0
>[   37.741406] Console: switching to colour frame buffer device 240x67
>[   37.871599] Console: switching to colour dummy device 80x25
>[   37.871942] [IGT] drv_hangman: executing
>[   37.901022] [IGT] drv_hangman: starting subtest error-state-basic
>[   37.909825] [drm] GPU HANG: ecode 9:-1:0x00000000, reason: Manually setting wedged to 1, action: reset
>[   37.909838] [drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.
>[   37.909840] [drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel
>[   37.909842] [drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue.
>[   37.909843] [drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it.
>[   37.909845] [drm] GPU crash dump saved to /sys/class/drm/card0/error
>[   37.911051] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[   37.911372] drm/i915: Resetting chip after gpu hang
>[   37.914466] [drm] RC6 on
>[   37.914718] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[   37.914863] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[   37.914982] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[   37.915095] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[   37.915212] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[   37.915231] [drm] GuC firmware load skipped
>[   37.945030] [IGT] drv_hangman: exiting, ret=0
>[   37.974617] Console: switching to colour frame buffer device 240x67
>[   38.094143] Console: switching to colour dummy device 80x25
>[   38.094371] [IGT] gem_basic: executing
>[   38.121475] [IGT] gem_basic: starting subtest bad-close
>[   38.121609] [IGT] gem_basic: exiting, ret=0
>[   38.141355] Console: switching to colour frame buffer device 240x67
>[   38.247377] Console: switching to colour dummy device 80x25
>[   38.247599] [IGT] gem_basic: executing
>[   38.270497] [IGT] gem_basic: starting subtest create-close
>[   38.270697] [IGT] gem_basic: exiting, ret=0
>[   38.307999] Console: switching to colour frame buffer device 240x67
>[   38.411464] Console: switching to colour dummy device 80x25
>[   38.411686] [IGT] gem_basic: executing
>[   38.436649] [IGT] gem_basic: starting subtest create-fd-close
>[   38.437634] [IGT] gem_basic: exiting, ret=0
>[   38.491455] Console: switching to colour frame buffer device 240x67
>[   38.609219] Console: switching to colour dummy device 80x25
>[   38.609522] [IGT] gem_busy: executing
>[   38.634028] [IGT] gem_busy: starting subtest basic-busy-default
>[   38.652982] [IGT] gem_busy: exiting, ret=0
>[   38.708188] Console: switching to colour frame buffer device 240x67
>[   38.830627] Console: switching to colour dummy device 80x25
>[   38.830845] [IGT] gem_busy: executing
>[   38.853120] [IGT] gem_busy: starting subtest basic-hang-default
>[   56.768233] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[   56.768440] drm/i915: Resetting chip after gpu hang
>[   56.770552] [drm:i915_gem_reset_finish [i915]] context gem_busy[6260]/0 marked guilty (score 10) banned? no
>[   56.770588] [drm:i915_gem_reset_finish [i915]] resetting render ring to restart from tail of request 0x378
>[   56.770879] [drm] RC6 on
>[   56.771217] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[   56.771255] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x378, 0x0]
>[   56.771473] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[   56.771650] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[   56.771779] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[   56.771866] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[   56.771878] [drm] GuC firmware load skipped
>[   56.772916] [IGT] gem_busy: exiting, ret=0
>[   56.827543] Console: switching to colour frame buffer device 240x67
>[   56.945221] Console: switching to colour dummy device 80x25
>[   56.945473] [IGT] gem_close_race: executing
>[   56.970235] [IGT] gem_close_race: starting subtest basic-process
>[   56.992225] [IGT] gem_close_race: exiting, ret=0
>[   57.044272] Console: switching to colour frame buffer device 240x67
>[   57.161804] Console: switching to colour dummy device 80x25
>[   57.162068] [IGT] gem_close_race: executing
>[   57.187834] [IGT] gem_close_race: starting subtest basic-threads
>[   58.269471] [IGT] gem_close_race: exiting, ret=0
>[   58.327689] Console: switching to colour frame buffer device 240x67
>[   58.450477] Console: switching to colour dummy device 80x25
>[   58.450699] [IGT] gem_cpu_reloc: executing
>[   58.473511] [IGT] gem_cpu_reloc: starting subtest basic
>[   58.488979] [IGT] gem_cpu_reloc: exiting, ret=0
>[   58.544459] Console: switching to colour frame buffer device 240x67
>[   58.660337] Console: switching to colour dummy device 80x25
>[   58.660564] [IGT] gem_cs_tlb: executing
>[   58.685652] [IGT] gem_cs_tlb: starting subtest basic-default
>[   65.184977] [IGT] gem_cs_tlb: exiting, ret=0
>[   65.240645] Console: switching to colour frame buffer device 240x67
>[   65.353894] Console: switching to colour dummy device 80x25
>[   65.354185] [IGT] gem_ctx_basic: executing
>[   71.886200] [IGT] gem_ctx_basic: exiting, ret=0
>[   75.657378] Console: switching to colour frame buffer device 240x67
>[   75.831227] Console: switching to colour dummy device 80x25
>[   75.831512] [IGT] gem_ctx_create: executing
>[   75.860314] [IGT] gem_ctx_create: starting subtest basic
>[   75.863375] [IGT] gem_ctx_create: exiting, ret=0
>[   75.913730] Console: switching to colour frame buffer device 240x67
>[   76.031720] Console: switching to colour dummy device 80x25
>[   76.031941] [IGT] gem_ctx_create: executing
>[   76.060269] [IGT] gem_ctx_create: starting subtest basic-files
>[   82.119544] [IGT] gem_ctx_create: exiting, ret=0
>[   82.198004] Console: switching to colour frame buffer device 240x67
>[   82.315867] Console: switching to colour dummy device 80x25
>[   82.316146] [IGT] gem_ctx_exec: executing
>[   82.339762] [IGT] gem_ctx_exec: starting subtest basic
>[   82.342693] [IGT] gem_ctx_exec: exiting, ret=0
>[   82.381334] Console: switching to colour frame buffer device 240x67
>[   82.512061] Console: switching to colour dummy device 80x25
>[   82.512422] [IGT] gem_ctx_param: executing
>[   82.537562] [IGT] gem_ctx_param: starting subtest basic
>[   82.537931] [IGT] gem_ctx_param: exiting, ret=0
>[   82.581563] Console: switching to colour frame buffer device 240x67
>[   82.704445] Console: switching to colour dummy device 80x25
>[   82.704730] [IGT] gem_ctx_param: executing
>[   82.731621] [IGT] gem_ctx_param: starting subtest basic-default
>[   82.732039] [IGT] gem_ctx_param: exiting, ret=0
>[   82.790802] Console: switching to colour frame buffer device 240x67
>[   82.910816] Console: switching to colour dummy device 80x25
>[   82.911163] [IGT] gem_ctx_switch: executing
>[   82.947487] [IGT] gem_ctx_switch: starting subtest basic-default
>[   88.737784] [IGT] gem_ctx_switch: exiting, ret=0
>[   89.040667] Console: switching to colour frame buffer device 240x67
>[   89.164417] Console: switching to colour dummy device 80x25
>[   89.164648] [IGT] gem_ctx_switch: executing
>[   89.198650] [IGT] gem_ctx_switch: starting subtest basic-default-heavy
>[  117.055841] [IGT] gem_ctx_switch: exiting, ret=0
>[  117.124155] Console: switching to colour frame buffer device 240x67
>[  117.244016] Console: switching to colour dummy device 80x25
>[  117.244448] [IGT] gem_exec_basic: executing
>[  117.270433] [IGT] gem_exec_basic: starting subtest basic-blt
>[  117.274005] [IGT] gem_exec_basic: exiting, ret=0
>[  117.323985] Console: switching to colour frame buffer device 240x67
>[  117.456504] Console: switching to colour dummy device 80x25
>[  117.456726] [IGT] gem_exec_basic: executing
>[  117.484871] [IGT] gem_exec_basic: starting subtest basic-bsd
>[  117.489043] [IGT] gem_exec_basic: exiting, ret=0
>[  117.540683] Console: switching to colour frame buffer device 240x67
>[  117.666242] Console: switching to colour dummy device 80x25
>[  117.666578] [IGT] gem_exec_basic: executing
>[  117.694866] [IGT] gem_exec_basic: starting subtest basic-bsd1
>[  117.698285] [IGT] gem_exec_basic: exiting, ret=77
>[  117.753471] Console: switching to colour frame buffer device 240x67
>[  117.870722] Console: switching to colour dummy device 80x25
>[  117.870949] [IGT] gem_exec_basic: executing
>[  117.899861] [IGT] gem_exec_basic: starting subtest basic-bsd2
>[  117.902804] [IGT] gem_exec_basic: exiting, ret=77
>[  117.957530] Console: switching to colour frame buffer device 240x67
>[  118.096684] Console: switching to colour dummy device 80x25
>[  118.096988] [IGT] gem_exec_basic: executing
>[  118.124898] [IGT] gem_exec_basic: starting subtest basic-default
>[  118.128798] [IGT] gem_exec_basic: exiting, ret=0
>[  118.190709] Console: switching to colour frame buffer device 240x67
>[  118.310240] Console: switching to colour dummy device 80x25
>[  118.310497] [IGT] gem_exec_basic: executing
>[  118.335813] [IGT] gem_exec_basic: starting subtest basic-render
>[  118.339483] [IGT] gem_exec_basic: exiting, ret=0
>[  118.390794] Console: switching to colour frame buffer device 240x67
>[  118.516635] Console: switching to colour dummy device 80x25
>[  118.516956] [IGT] gem_exec_basic: executing
>[  118.543786] [IGT] gem_exec_basic: starting subtest basic-vebox
>[  118.548192] [IGT] gem_exec_basic: exiting, ret=0
>[  118.607526] Console: switching to colour frame buffer device 240x67
>[  118.732856] Console: switching to colour dummy device 80x25
>[  118.733075] [IGT] gem_exec_basic: executing
>[  118.749725] [IGT] gem_exec_basic: starting subtest gtt-blt
>[  118.753514] [IGT] gem_exec_basic: exiting, ret=0
>[  118.807496] Console: switching to colour frame buffer device 240x67
>[  118.923862] Console: switching to colour dummy device 80x25
>[  118.924302] [IGT] gem_exec_basic: executing
>[  118.940744] [IGT] gem_exec_basic: starting subtest gtt-bsd
>[  118.943902] [IGT] gem_exec_basic: exiting, ret=0
>[  118.990656] Console: switching to colour frame buffer device 240x67
>[  119.127520] Console: switching to colour dummy device 80x25
>[  119.127860] [IGT] gem_exec_basic: executing
>[  119.154846] [IGT] gem_exec_basic: starting subtest gtt-bsd1
>[  119.157783] [IGT] gem_exec_basic: exiting, ret=77
>[  119.207385] Console: switching to colour frame buffer device 240x67
>[  119.326300] Console: switching to colour dummy device 80x25
>[  119.326574] [IGT] gem_exec_basic: executing
>[  119.354993] [IGT] gem_exec_basic: starting subtest gtt-bsd2
>[  119.358150] [IGT] gem_exec_basic: exiting, ret=77
>[  119.407418] Console: switching to colour frame buffer device 240x67
>[  119.541032] Console: switching to colour dummy device 80x25
>[  119.541385] [IGT] gem_exec_basic: executing
>[  119.569009] [IGT] gem_exec_basic: starting subtest gtt-default
>[  119.573052] [IGT] gem_exec_basic: exiting, ret=0
>[  119.624059] Console: switching to colour frame buffer device 240x67
>[  119.742555] Console: switching to colour dummy device 80x25
>[  119.742840] [IGT] gem_exec_basic: executing
>[  119.771048] [IGT] gem_exec_basic: starting subtest gtt-render
>[  119.775163] [IGT] gem_exec_basic: exiting, ret=0
>[  119.824055] Console: switching to colour frame buffer device 240x67
>[  119.945146] Console: switching to colour dummy device 80x25
>[  119.945371] [IGT] gem_exec_basic: executing
>[  119.970998] [IGT] gem_exec_basic: starting subtest gtt-vebox
>[  119.974982] [IGT] gem_exec_basic: exiting, ret=0
>[  120.024189] Console: switching to colour frame buffer device 240x67
>[  120.143712] Console: switching to colour dummy device 80x25
>[  120.143933] [IGT] gem_exec_basic: executing
>[  120.171965] [IGT] gem_exec_basic: starting subtest readonly-blt
>[  120.175650] [IGT] gem_exec_basic: exiting, ret=0
>[  120.224184] Console: switching to colour frame buffer device 240x67
>[  120.351469] Console: switching to colour dummy device 80x25
>[  120.351765] [IGT] gem_exec_basic: executing
>[  120.368603] [IGT] gem_exec_basic: starting subtest readonly-bsd
>[  120.371498] [IGT] gem_exec_basic: exiting, ret=0
>[  120.424017] Console: switching to colour frame buffer device 240x67
>[  120.544984] Console: switching to colour dummy device 80x25
>[  120.545487] [IGT] gem_exec_basic: executing
>[  120.574828] [IGT] gem_exec_basic: starting subtest readonly-bsd1
>[  120.577921] [IGT] gem_exec_basic: exiting, ret=77
>[  120.637415] Console: switching to colour frame buffer device 240x67
>[  120.759968] Console: switching to colour dummy device 80x25
>[  120.760595] [IGT] gem_exec_basic: executing
>[  120.788276] [IGT] gem_exec_basic: starting subtest readonly-bsd2
>[  120.791802] [IGT] gem_exec_basic: exiting, ret=77
>[  120.840720] Console: switching to colour frame buffer device 240x67
>[  120.956560] Console: switching to colour dummy device 80x25
>[  120.956824] [IGT] gem_exec_basic: executing
>[  120.974710] [IGT] gem_exec_basic: starting subtest readonly-default
>[  120.977743] [IGT] gem_exec_basic: exiting, ret=0
>[  121.037261] Console: switching to colour frame buffer device 240x67
>[  121.166275] Console: switching to colour dummy device 80x25
>[  121.166509] [IGT] gem_exec_basic: executing
>[  121.194861] [IGT] gem_exec_basic: starting subtest readonly-render
>[  121.198758] [IGT] gem_exec_basic: exiting, ret=0
>[  121.257442] Console: switching to colour frame buffer device 240x67
>[  121.389635] Console: switching to colour dummy device 80x25
>[  121.389971] [IGT] gem_exec_basic: executing
>[  121.417905] [IGT] gem_exec_basic: starting subtest readonly-vebox
>[  121.421602] [IGT] gem_exec_basic: exiting, ret=0
>[  121.474046] Console: switching to colour frame buffer device 240x67
>[  121.605181] Console: switching to colour dummy device 80x25
>[  121.605484] [IGT] gem_exec_create: executing
>[  121.626509] [IGT] gem_exec_create: starting subtest basic
>[  126.698211] [IGT] gem_exec_create: exiting, ret=0
>[  126.757483] Console: switching to colour frame buffer device 240x67
>[  126.883530] Console: switching to colour dummy device 80x25
>[  126.883753] [IGT] gem_exec_fence: executing
>[  126.899179] [IGT] gem_exec_fence: starting subtest basic-busy-default
>[  126.950641] [IGT] gem_exec_fence: exiting, ret=0
>[  127.007472] Console: switching to colour frame buffer device 240x67
>[  127.125438] Console: switching to colour dummy device 80x25
>[  127.125664] [IGT] gem_exec_fence: executing
>[  127.150934] [IGT] gem_exec_fence: starting subtest basic-wait-default
>[  127.191672] [IGT] gem_exec_fence: exiting, ret=0
>[  127.240795] Console: switching to colour frame buffer device 240x67
>[  127.368377] Console: switching to colour dummy device 80x25
>[  127.368607] [IGT] gem_exec_fence: executing
>[  127.392895] [IGT] gem_exec_fence: starting subtest basic-await-default
>[  128.409269] [IGT] gem_exec_fence: exiting, ret=0
>[  128.457501] Console: switching to colour frame buffer device 240x67
>[  128.583899] Console: switching to colour dummy device 80x25
>[  128.584293] [IGT] gem_exec_fence: executing
>[  128.609853] [IGT] gem_exec_fence: starting subtest await-hang-default
>[  136.768598] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  136.769634] drm/i915: Resetting chip after gpu hang
>[  136.771694] [drm:i915_gem_reset_finish [i915]] context gem_exec_fence[6438]/0 marked guilty (score 10) banned? no
>[  136.771774] [drm:i915_gem_reset_finish [i915]] resetting render ring to restart from tail of request 0x1d51d
>[  136.772459] [drm] RC6 on
>[  136.774999] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  136.775080] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x1d51f, 0x0]
>[  136.775491] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  136.775742] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  136.775991] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  136.776176] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[  136.776280] [drm] GuC firmware load skipped
>[  136.777543] [IGT] gem_exec_fence: exiting, ret=0
>[  136.823935] Console: switching to colour frame buffer device 240x67
>[  136.955802] Console: switching to colour dummy device 80x25
>[  136.956068] [IGT] gem_exec_fence: executing
>[  136.981838] [IGT] gem_exec_fence: starting subtest nb-await-default
>[  137.987359] [IGT] gem_exec_fence: exiting, ret=0
>[  138.040832] Console: switching to colour frame buffer device 240x67
>[  138.162381] Console: switching to colour dummy device 80x25
>[  138.162644] [IGT] gem_exec_flush: executing
>[  138.193432] [IGT] gem_exec_flush: starting subtest basic-batch-kernel-default-cmd
>[  138.197471] [IGT] gem_exec_flush: exiting, ret=77
>[  138.257481] Console: switching to colour frame buffer device 240x67
>[  138.378616] Console: switching to colour dummy device 80x25
>[  138.378901] [IGT] gem_exec_flush: executing
>[  138.408089] [IGT] gem_exec_flush: starting subtest basic-batch-kernel-default-uc
>[  144.067891] [IGT] gem_exec_flush: exiting, ret=0
>[  144.124263] Console: switching to colour frame buffer device 240x67
>[  144.246706] Console: switching to colour dummy device 80x25
>[  144.246930] [IGT] gem_exec_flush: executing
>[  144.275480] [IGT] gem_exec_flush: starting subtest basic-batch-kernel-default-wb
>[  149.820021] [IGT] gem_exec_flush: exiting, ret=0
>[  149.874993] Console: switching to colour frame buffer device 240x67
>[  149.993308] Console: switching to colour dummy device 80x25
>[  149.993568] [IGT] gem_exec_flush: executing
>[  150.021181] [IGT] gem_exec_flush: starting subtest basic-uc-pro-default
>[  155.406438] [IGT] gem_exec_flush: exiting, ret=0
>[  155.459083] Console: switching to colour frame buffer device 240x67
>[  155.581184] Console: switching to colour dummy device 80x25
>[  155.581504] [IGT] gem_exec_flush: executing
>[  155.613217] [IGT] gem_exec_flush: starting subtest basic-uc-prw-default
>[  160.999648] [IGT] gem_exec_flush: exiting, ret=0
>[  161.043323] Console: switching to colour frame buffer device 240x67
>[  161.160242] Console: switching to colour dummy device 80x25
>[  161.160499] [IGT] gem_exec_flush: executing
>[  161.187984] [IGT] gem_exec_flush: starting subtest basic-uc-ro-default
>[  166.574703] [IGT] gem_exec_flush: exiting, ret=0
>[  166.627519] Console: switching to colour frame buffer device 240x67
>[  166.762288] Console: switching to colour dummy device 80x25
>[  166.762512] [IGT] gem_exec_flush: executing
>[  166.777150] [IGT] gem_exec_flush: starting subtest basic-uc-rw-default
>[  172.165140] [IGT] gem_exec_flush: exiting, ret=0
>[  172.211692] Console: switching to colour frame buffer device 240x67
>[  172.331913] Console: switching to colour dummy device 80x25
>[  172.332251] [IGT] gem_exec_flush: executing
>[  172.360518] [IGT] gem_exec_flush: starting subtest basic-uc-set-default
>[  177.746513] [IGT] gem_exec_flush: exiting, ret=0
>[  177.795867] Console: switching to colour frame buffer device 240x67
>[  177.922249] Console: switching to colour dummy device 80x25
>[  177.922472] [IGT] gem_exec_flush: executing
>[  177.938958] [IGT] gem_exec_flush: starting subtest basic-wb-pro-default
>[  183.324813] [IGT] gem_exec_flush: exiting, ret=0
>[  183.373922] Console: switching to colour frame buffer device 240x67
>[  183.490606] Console: switching to colour dummy device 80x25
>[  183.490828] [IGT] gem_exec_flush: executing
>[  183.520672] [IGT] gem_exec_flush: starting subtest basic-wb-prw-default
>[  188.907431] [IGT] gem_exec_flush: exiting, ret=0
>[  188.964155] Console: switching to colour frame buffer device 240x67
>[  189.089290] Console: switching to colour dummy device 80x25
>[  189.089578] [IGT] gem_exec_flush: executing
>[  189.117002] [IGT] gem_exec_flush: starting subtest basic-wb-ro-before-default
>[  194.503869] [IGT] gem_exec_flush: exiting, ret=0
>[  194.557398] Console: switching to colour frame buffer device 240x67
>[  194.684565] Console: switching to colour dummy device 80x25
>[  194.684788] [IGT] gem_exec_flush: executing
>[  194.712154] [IGT] gem_exec_flush: starting subtest basic-wb-ro-default
>[  200.100976] [IGT] gem_exec_flush: exiting, ret=0
>[  200.157455] Console: switching to colour frame buffer device 240x67
>[  200.282517] Console: switching to colour dummy device 80x25
>[  200.282743] [IGT] gem_exec_flush: executing
>[  200.309136] [IGT] gem_exec_flush: starting subtest basic-wb-rw-before-default
>[  205.694742] [IGT] gem_exec_flush: exiting, ret=0
>[  205.750021] Console: switching to colour frame buffer device 240x67
>[  205.883484] Console: switching to colour dummy device 80x25
>[  205.883711] [IGT] gem_exec_flush: executing
>[  205.901121] [IGT] gem_exec_flush: starting subtest basic-wb-rw-default
>[  211.288672] [IGT] gem_exec_flush: exiting, ret=0
>[  211.340665] Console: switching to colour frame buffer device 240x67
>[  211.473797] Console: switching to colour dummy device 80x25
>[  211.474016] [IGT] gem_exec_flush: executing
>[  211.500076] [IGT] gem_exec_flush: starting subtest basic-wb-set-default
>[  216.887898] [IGT] gem_exec_flush: exiting, ret=0
>[  216.934818] Console: switching to colour frame buffer device 240x67
>[  217.048276] Console: switching to colour dummy device 80x25
>[  217.048498] [IGT] gem_exec_gttfill: executing
>[  217.074035] [IGT] gem_exec_gttfill: starting subtest basic
>[  217.074419] gem_exec_gttfil (6569): drop_caches: 4
>[  217.580610] [IGT] gem_exec_gttfill: exiting, ret=77
>[  217.635174] Console: switching to colour frame buffer device 240x67
>[  217.807769] Console: switching to colour dummy device 80x25
>[  217.808010] [IGT] gem_exec_nop: executing
>[  217.835995] [IGT] gem_exec_nop: starting subtest basic-parallel
>[  227.178367] [IGT] gem_exec_nop: exiting, ret=0
>[  227.236575] Console: switching to colour frame buffer device 240x67
>[  227.363176] Console: switching to colour dummy device 80x25
>[  227.363426] [IGT] gem_exec_nop: executing
>[  227.391660] [IGT] gem_exec_nop: starting subtest basic-series
>[  237.041717] [IGT] gem_exec_nop: exiting, ret=0
>[  237.090714] Console: switching to colour frame buffer device 240x67
>[  237.223659] Console: switching to colour dummy device 80x25
>[  237.223991] [IGT] gem_exec_parallel: executing
>[  237.250881] [IGT] gem_exec_parallel: starting subtest basic
>[  239.736368] [IGT] gem_exec_parallel: exiting, ret=0
>[  239.790634] Console: switching to colour frame buffer device 240x67
>[  239.911059] Console: switching to colour dummy device 80x25
>[  239.911418] [IGT] gem_exec_parse: executing
>[  239.937842] [IGT] gem_exec_parse: exiting, ret=77
>[  239.971909] Console: switching to colour frame buffer device 240x67
>[  240.079157] Console: switching to colour dummy device 80x25
>[  240.079383] [IGT] gem_exec_parse: executing
>[  240.103804] [IGT] gem_exec_parse: exiting, ret=77
>[  240.123926] Console: switching to colour frame buffer device 240x67
>[  240.246519] Console: switching to colour dummy device 80x25
>[  240.246792] [IGT] gem_exec_reloc: executing
>[  240.271558] [IGT] gem_exec_reloc: starting subtest basic-cpu
>[  240.272957] [IGT] gem_exec_reloc: exiting, ret=0
>[  240.323931] Console: switching to colour frame buffer device 240x67
>[  240.442418] Console: switching to colour dummy device 80x25
>[  240.442671] [IGT] gem_exec_reloc: executing
>[  240.466679] [IGT] gem_exec_reloc: starting subtest basic-gtt
>[  240.468562] [IGT] gem_exec_reloc: exiting, ret=0
>[  240.523996] Console: switching to colour frame buffer device 240x67
>[  240.646319] Console: switching to colour dummy device 80x25
>[  240.646614] [IGT] gem_exec_reloc: executing
>[  240.671713] [IGT] gem_exec_reloc: starting subtest basic-softpin
>[  240.673489] [IGT] gem_exec_reloc: exiting, ret=0
>[  240.723990] Console: switching to colour frame buffer device 240x67
>[  240.850761] Console: switching to colour dummy device 80x25
>[  240.851174] [IGT] gem_exec_store: executing
>[  240.878912] [IGT] gem_exec_store: starting subtest basic-all
>[  240.931421] [IGT] gem_exec_store: exiting, ret=0
>[  240.990709] Console: switching to colour frame buffer device 240x67
>[  241.114080] Console: switching to colour dummy device 80x25
>[  241.114433] [IGT] gem_exec_store: executing
>[  241.143027] [IGT] gem_exec_store: starting subtest basic-blt
>[  241.189313] [IGT] gem_exec_store: exiting, ret=0
>[  241.240706] Console: switching to colour frame buffer device 240x67
>[  241.357250] Console: switching to colour dummy device 80x25
>[  241.357483] [IGT] gem_exec_store: executing
>[  241.384860] [IGT] gem_exec_store: starting subtest basic-bsd
>[  241.429838] [IGT] gem_exec_store: exiting, ret=0
>[  241.490727] Console: switching to colour frame buffer device 240x67
>[  241.619939] Console: switching to colour dummy device 80x25
>[  241.620350] [IGT] gem_exec_store: executing
>[  241.647876] [IGT] gem_exec_store: starting subtest basic-bsd1
>[  241.651010] [IGT] gem_exec_store: exiting, ret=77
>[  241.707611] Console: switching to colour frame buffer device 240x67
>[  241.837347] Console: switching to colour dummy device 80x25
>[  241.837637] [IGT] gem_exec_store: executing
>[  241.868817] [IGT] gem_exec_store: starting subtest basic-bsd2
>[  241.871818] [IGT] gem_exec_store: exiting, ret=77
>[  241.924231] Console: switching to colour frame buffer device 240x67
>[  242.050461] Console: switching to colour dummy device 80x25
>[  242.050734] [IGT] gem_exec_store: executing
>[  242.077954] [IGT] gem_exec_store: starting subtest basic-default
>[  242.121972] [IGT] gem_exec_store: exiting, ret=0
>[  242.174086] Console: switching to colour frame buffer device 240x67
>[  242.303469] Console: switching to colour dummy device 80x25
>[  242.303693] [IGT] gem_exec_store: executing
>[  242.331855] [IGT] gem_exec_store: starting subtest basic-render
>[  242.373646] [IGT] gem_exec_store: exiting, ret=0
>[  242.423983] Console: switching to colour frame buffer device 240x67
>[  242.550223] Console: switching to colour dummy device 80x25
>[  242.550510] [IGT] gem_exec_store: executing
>[  242.577054] [IGT] gem_exec_store: starting subtest basic-vebox
>[  242.621613] [IGT] gem_exec_store: exiting, ret=0
>[  242.674229] Console: switching to colour frame buffer device 240x67
>[  242.807485] Console: switching to colour dummy device 80x25
>[  242.807711] [IGT] gem_exec_suspend: executing
>[  242.833691] [IGT] gem_exec_suspend: starting subtest basic
>[  243.131276] [IGT] gem_exec_suspend: exiting, ret=0
>[  243.173944] Console: switching to colour frame buffer device 240x67
>[  243.315482] Console: switching to colour dummy device 80x25
>[  243.315786] [IGT] gem_exec_suspend: executing
>[  243.342909] [IGT] gem_exec_suspend: starting subtest basic-S3
>[  244.995722] PM: Syncing filesystems ... done.
>[  244.999048] PM: Preparing system for sleep (mem)
>[  245.014426] Freezing user space processes ... (elapsed 0.015 seconds) done.
>[  245.030380] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  245.032168] PM: Suspending system (mem)
>[  245.032354] Suspending console(s) (use no_console_suspend to debug)
>[  245.424447] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  245.426873] sd 0:0:0:0: [sda] Stopping disk
>[  245.636416] ACPI : EC: event blocked
>[  245.667893] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  245.667928] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  245.667965] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  245.668008] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  245.668040] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  245.668077] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  245.668110] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  245.668174] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  245.668207] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  245.668242] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  245.668274] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  245.668280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  245.668314] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  245.668318] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  245.668351] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  245.668383] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  245.668415] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  245.668447] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  245.668479] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  245.668514] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  245.668546] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  245.668580] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  245.668612] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  245.668645] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  245.668677] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  245.668710] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  245.668750] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  245.668782] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  245.668817] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  245.668848] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  245.668881] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  245.668914] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  245.668946] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  245.668978] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  245.669009] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  245.669013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  245.669044] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  245.669047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  245.669080] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  245.669112] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  245.669194] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  245.669227] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  245.669259] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  245.669292] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  245.669324] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  245.669359] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  245.669392] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  245.669426] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  245.669459] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  245.669493] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  245.669538] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  245.669581] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  245.669614] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  245.669652] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  245.669685] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  245.670827] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  245.676603] igb 0000:01:00.0: System wakeup enabled by ACPI
>[  245.879220] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  245.879394] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  245.889714] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  245.889757] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  245.901333] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  245.901383] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  245.901423] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  245.910018] hpet1: lost 7161 rtc interrupts
>[  245.952159] [drm:wait_panel_status [i915]] Wait complete
>[  245.952218] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  245.952319] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  245.952451] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  245.952580] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  245.952658] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  245.953906] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  245.953940] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  245.953973] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  245.954244] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  245.958809] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  245.958910] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  245.958998] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  245.963241] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  245.963277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  245.963314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  245.963357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  245.963390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  245.963425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  245.963460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  245.963493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  245.963528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  245.963562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  245.963597] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  245.963633] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  245.963669] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  245.963764] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  245.963807] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  245.963855] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  245.963902] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  245.963943] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  245.963990] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  245.965206] PM: suspend of devices complete after 545.307 msecs
>[  245.972354] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  245.972416] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  245.972448] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  245.972574] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  245.972606] [drm:intel_power_well_disable [i915]] disabling DC off
>[  245.972640] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  245.972673] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  245.973232] [drm:intel_power_well_disable [i915]] disabling always-on
>[  245.973266] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  245.973322] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 19200 kHz (VCO 0 kHz)
>[  245.977549] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  245.977581] [drm:intel_power_well_disable [i915]] disabling power well 1
>[  245.977620] [drm:skl_set_power_well [i915]] Disabling power well 1
>[  245.977655] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC
>[  245.977692] [drm:bxt_enable_dc9 [i915]] Enabling DC9
>[  245.977727] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08
>[  245.989325] PM: late suspend of devices complete after 24.113 msecs
>[  245.997658] xhci_hcd 0000:00:15.0: System wakeup enabled by ACPI
>[  245.998405] ACPI : EC: interrupt blocked
>[  246.009313] acpi device:0a: Cannot transition from D3cold to D3hot
>[  246.022224] PM: noirq suspend of devices complete after 32.888 msecs
>[  246.022414] ACPI: Preparing to enter system sleep state S3
>[  246.029317] ACPI : EC: EC stopped
>[  246.029320] PM: Saving platform NVS memory
>[  246.029364] Disabling non-boot CPUs ...
>[  246.050102] Broke affinity for irq 123
>[  246.050307] Cannot set affinity for irq 352
>[  246.050322] Broke affinity for irq 374
>[  246.051664] smpboot: CPU 1 is now offline
>[  246.071484] Broke affinity for irq 122
>[  246.071491] Broke affinity for irq 123
>[  246.071758] Broke affinity for irq 374
>[  246.072981] smpboot: CPU 2 is now offline
>[  246.084718] Broke affinity for irq 1
>[  246.084733] Broke affinity for irq 8
>[  246.084744] Broke affinity for irq 9
>[  246.084774] Broke affinity for irq 122
>[  246.084778] Broke affinity for irq 123
>[  246.084965] Broke affinity for irq 374
>[  246.086172] smpboot: CPU 3 is now offline
>[  246.091197] ACPI: Low-level resume complete
>[  246.091813] ACPI : EC: EC started
>[  246.091820] PM: Restoring platform NVS memory
>[  246.093370] Suspended for 14.054 seconds
>[  246.097890] Enabling non-boot CPUs ...
>[  246.102353] x86: Booting SMP configuration:
>[  246.102363] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  246.103608] Skipped synchronization checks as TSC is reliable.
>[  246.115140]  cache: parent cpu1 should not be sleeping
>[  246.122574] CPU1 is up
>[  246.123215] smpboot: Booting Node 0 Processor 2 APIC 0x4
>[  246.123942] Skipped synchronization checks as TSC is reliable.
>[  246.129552]  cache: parent cpu2 should not be sleeping
>[  246.135408] CPU2 is up
>[  246.135949] smpboot: Booting Node 0 Processor 3 APIC 0x6
>[  246.136557] Skipped synchronization checks as TSC is reliable.
>[  246.140987]  cache: parent cpu3 should not be sleeping
>[  246.146441] CPU3 is up
>[  246.150382] ACPI: Waking up from system sleep state S3
>[  246.166531] ACPI : button: The lid device is not compliant to SW_LID.
>[  246.204539] acpi LNXPOWER:14: Turning OFF
>[  246.243197] acpi LNXPOWER:13: Turning OFF
>[  246.244154] acpi LNXPOWER:11: Turning OFF
>[  246.250244] acpi LNXPOWER:09: Turning OFF
>[  246.253904] acpi LNXPOWER:07: Turning OFF
>[  246.257379] acpi LNXPOWER:06: Turning OFF
>[  246.273150] ACPI : EC: interrupt unblocked
>[  246.287915] xhci_hcd 0000:00:15.0: System wakeup disabled by ACPI
>[  246.327007] PM: noirq resume of devices complete after 55.745 msecs
>[  246.327954] [drm:gen9_sanitize_dc_state [i915]] Resetting DC state tracking from 08 to 00
>[  246.328006] [drm:bxt_disable_dc9 [i915]] Disabling DC9
>[  246.328056] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  246.328222] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 4
>[  246.328619] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  246.328720] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  246.328799] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  246.331992] [drm:intel_power_well_enable [i915]] enabling always-on
>[  246.332048] [drm:intel_power_well_enable [i915]] enabling DC off
>[  246.332106] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  246.332182] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  246.332245] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  246.333754] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  246.333984] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  246.334204] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 1 already enabled, won't reprogram it
>[  246.334360] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>[  246.348358] PM: early resume of devices complete after 20.765 msecs
>[  246.349425] ACPI : EC: event unblocked
>[  246.349911] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x79df2018
>[  246.350207] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  246.350249] [drm:intel_opregion_setup [i915]] ASLE supported
>[  246.350589] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA)
>[  246.350758] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001010 hp_port:38
>[  246.350875] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  246.350919] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  246.352592] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 15.10
>[  246.354112] igb 0000:01:00.0: System wakeup disabled by ACPI
>[  246.359480] sd 0:0:0:0: [sda] Starting disk
>[  246.362252] rtc_cmos 00:04: System wakeup disabled by ACPI
>[  246.588750] atkbd serio0: Failed to deactivate keyboard on isa0060/serio0
>[  246.852777] atkbd serio0: Failed to enable keyboard on isa0060/serio0
>[  246.983895] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 632 ms
>[  246.984499] [drm:drm_dp_i2c_do_msg] native defer
>[  246.987316] [drm:drm_dp_i2c_do_msg] native defer
>[  246.988821] [drm:drm_dp_i2c_do_msg] native defer
>[  246.990304] [drm:drm_dp_i2c_do_msg] native defer
>[  246.991818] [drm:drm_dp_i2c_do_msg] native defer
>[  246.993324] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  246.994436] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  246.994805] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  246.995076] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  246.995348] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  246.995519] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[  246.995542] [drm] GuC firmware load skipped
>[  246.996624] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  246.996820] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:1800181a hp_port:38
>[  246.997272] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:33:pipe A] hw state readout: disabled
>[  246.997403] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:42:pipe B] hw state readout: disabled
>[  246.997533] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:49:pipe C] hw state readout: disabled
>[  246.997644] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0
>[  246.997859] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0
>[  246.997968] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0
>[  246.998080] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI A] hw state readout: disabled, pipe A
>[  246.998194] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI B] hw state readout: disabled, pipe A
>[  246.998295] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A
>[  246.998396] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B
>[  246.998496] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C
>[  246.998608] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:63:DDI C] hw state readout: disabled, pipe A
>[  246.998708] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST A] hw state readout: disabled, pipe A
>[  246.998868] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST B] hw state readout: disabled, pipe B
>[  246.998969] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:67:DP-MST C] hw state readout: disabled, pipe C
>[  246.999089] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:eDP-1] hw state readout: disabled
>[  246.999205] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-1] hw state readout: disabled
>[  246.999321] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:64:DP-2] hw state readout: disabled
>[  246.999438] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:68:HDMI-A-1] hw state readout: disabled
>[  246.999589] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][setup_hw_state]
>[  246.999686] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  246.999836] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  246.999931] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  246.999945] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  247.000040] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  247.000050] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  247.000148] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  247.000244] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  247.000342] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  247.000440] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  247.000536] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  247.000639] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  247.000794] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  247.000898] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  247.000996] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  247.001095] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  247.001193] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  247.001291] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  247.001399] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][setup_hw_state]
>[  247.001495] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  247.001591] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  247.001685] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  247.001760] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  247.001855] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  247.001865] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  247.001961] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  247.001993] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  247.002025] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  247.002057] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  247.002089] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  247.002122] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  247.002154] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  247.002190] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  247.002223] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  247.002257] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  247.002291] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  247.002323] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  247.002362] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][setup_hw_state]
>[  247.002394] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  247.002426] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  247.002457] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  247.002462] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  247.002494] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  247.002497] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  247.002529] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  247.002561] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  247.002595] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  247.002627] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  247.002679] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  247.002712] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  247.002744] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  247.002776] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  247.002809] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  247.002841] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  247.003021] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  247.003100] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  247.003132] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  247.003270] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  247.003303] [drm:intel_power_well_disable [i915]] disabling DC off
>[  247.003339] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  247.003371] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  247.003760] [drm:intel_power_well_disable [i915]] disabling always-on
>[  247.003854] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  247.003887] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  247.003926] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  247.003964] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  247.003996] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  247.004031] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  247.004063] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  247.004097] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  247.004130] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  247.004162] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  247.004193] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  247.004197] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  247.004228] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  247.004232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  247.004264] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  247.004296] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  247.004328] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  247.004360] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  247.004392] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  247.004426] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  247.004457] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  247.004492] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  247.004525] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  247.004557] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  247.004589] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  247.004621] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  247.004683] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  247.004716] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  247.004751] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  247.004783] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  247.004816] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  247.004848] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  247.004880] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  247.004912] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  247.004943] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  247.004946] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  247.004978] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  247.004981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  247.005014] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  247.005046] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  247.005078] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  247.005110] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  247.005142] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  247.005176] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  247.005207] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  247.005240] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  247.005273] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  247.005305] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  247.005336] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  247.005370] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  247.005405] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  247.005447] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  247.005481] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  247.005520] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  247.005553] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  247.005585] [drm:skl_update_scaler [i915]] scaler_user index 2.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  247.006565] [drm:intel_power_well_enable [i915]] enabling always-on
>[  247.006594] [drm:intel_power_well_enable [i915]] enabling DC off
>[  247.006838] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  247.006891] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  247.007761] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  247.007796] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  247.008415] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  247.009280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  247.009314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  247.009355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  247.009388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  247.009421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  247.009499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  247.009533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  247.009566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  247.009599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  247.009632] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:59:DP-1]
>[  247.009702] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:64:DP-2]
>[  247.009743] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  247.009780] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  247.009816] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  247.009908] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  247.009940] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  247.010995] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  247.011033] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  247.011089] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000062
>[  247.011124] [drm:wait_panel_status [i915]] Wait complete
>[  247.011161] [drm:edp_panel_on [i915]] Wait for panel power on
>[  247.011201] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  247.108772] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  247.110996] ata1.00: supports DRM functions and may not be fully accessible
>[  247.111475] ata1.00: NCQ Send/Recv Log not supported
>[  247.112907] ata1.00: supports DRM functions and may not be fully accessible
>[  247.113411] ata1.00: NCQ Send/Recv Log not supported
>[  247.113425] ata1.00: configured for UDMA/133
>[  247.119662] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  247.119788] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  247.119821] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  247.119883] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  247.211492] [drm:wait_panel_status [i915]] Wait complete
>[  247.211716] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  247.211760] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  247.213510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  247.213544] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  247.213581] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  247.214353] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  247.214385] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  247.215459] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  247.215699] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016eba6fc8
>[  247.216861] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  247.216986] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  247.217018] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  247.217072] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  247.217119] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  247.217151] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  247.217279] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  247.217312] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  247.217528] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  247.217561] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  247.218367] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016eba53d8
>[  247.219498] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  247.220043] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  247.220078] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  247.220150] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  247.220183] [drm:hsw_audio_config_update [i915]] using automatic N
>[  247.237134] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  247.237182] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  247.237357] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  247.237542] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  247.237588] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  247.237812] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  247.237920] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  247.238164] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  247.238226] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  247.238285] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  247.238319] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  247.238351] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  247.238384] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  247.239238] [drm:intel_opregion_register [i915]] 4 outputs detected
>[  247.241607] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  247.242557] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:eDP-1] status updated from connected to connected
>[  247.242560] PM: resume of devices complete after 894.191 msecs
>[  247.242608] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  247.243195] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  247.243573] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-1] status updated from disconnected to disconnected
>[  247.243607] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  247.244838] PM: Finishing wakeup.
>[  247.244840] Restarting tasks ... done.
>[  247.253542] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.262479] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.271189] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.280391] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.283577] [drm] RC6 on
>[  247.289995] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.300121] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.308814] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.317437] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.326059] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.334758] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.348096] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.356790] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.365464] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.374156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.383350] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.392020] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.402419] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.412182] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.420841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.429472] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.438147] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.446817] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.455450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.464078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.473338] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.481999] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.490715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.499333] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.507967] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.516827] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.525484] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.535119] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  247.535151] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  247.535158] [drm:drm_helper_hpd_irq_event] [CONNECTOR:64:DP-2] status updated from disconnected to disconnected
>[  247.535194] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  247.612719] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  247.616726] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  247.616774] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  247.616780] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  247.616786] [drm:drm_helper_hpd_irq_event] [CONNECTOR:68:HDMI-A-1] status updated from connected to connected
>[  248.603756] [IGT] gem_exec_suspend: exiting, ret=0
>[  248.653992] Console: switching to colour frame buffer device 240x67
>[  248.993947] Console: switching to colour dummy device 80x25
>[  248.994174] [IGT] gem_exec_suspend: executing
>[  249.020492] [IGT] gem_exec_suspend: starting subtest basic-S4-devices
>[  249.203389] igb 0000:01:00.0 enp1s0: igb: enp1s0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX
>[  249.796779] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  249.796830] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  250.552810] PM: Syncing filesystems ... 
>[  250.587528] done.
>[  250.587536] Freezing user space processes ... (elapsed 0.002 seconds) done.
>[  250.590131] PM: Marking nosave pages: [mem 0x00000000-0x00000fff]
>[  250.590135] PM: Marking nosave pages: [mem 0x00058000-0x00058fff]
>[  250.590137] PM: Marking nosave pages: [mem 0x0009e000-0x000fffff]
>[  250.590142] PM: Marking nosave pages: [mem 0x0f000000-0x12151fff]
>[  250.590443] PM: Marking nosave pages: [mem 0x77ff9000-0x79e38fff]
>[  250.590661] PM: Marking nosave pages: [mem 0x7ac2c000-0x7ac56fff]
>[  250.590665] PM: Marking nosave pages: [mem 0x7b000000-0xffffffff]
>[  250.593680] PM: Basic memory bitmaps created
>[  250.594149] PM: Preallocating image memory... done (allocated 150318 pages)
>[  250.856770] PM: Allocated 601272 kbytes in 0.26 seconds (2312.58 MB/s)
>[  250.856772] Freezing remaining freezable tasks ... (elapsed 0.002 seconds) done.
>[  251.250018] Suspending console(s) (use no_console_suspend to debug)
>[  251.275528] ACPI : EC: event blocked
>[  251.286534] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  251.286576] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  251.286620] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  251.286742] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  251.286781] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  251.286825] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  251.286867] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  251.286907] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  251.286947] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  251.286986] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  251.287023] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  251.287032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  251.287070] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  251.287074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  251.287113] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  251.287151] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  251.287191] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  251.287229] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  251.287267] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  251.287312] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  251.287350] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  251.287394] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  251.287433] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  251.287473] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  251.287513] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  251.287554] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  251.287603] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  251.287642] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  251.287738] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  251.287777] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  251.287816] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  251.287857] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  251.287895] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  251.287933] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  251.287971] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  251.287975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  251.288013] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  251.288017] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  251.288056] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  251.288097] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  251.288136] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  251.288174] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  251.288212] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  251.288255] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  251.288293] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  251.288334] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  251.288373] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  251.288414] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  251.288454] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  251.288494] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  251.288549] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  251.288600] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  251.288641] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  251.288737] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  251.288778] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  251.288971] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  251.308515] igb 0000:01:00.0: System wakeup enabled by ACPI
>[  251.492837] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  251.492932] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  251.501365] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  251.501445] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  251.501792] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  251.501856] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  251.501932] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  251.553766] [drm:wait_panel_status [i915]] Wait complete
>[  251.553839] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  251.553907] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  251.554050] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  251.554215] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  251.554264] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  251.554321] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  251.554377] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  251.554434] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  251.554560] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  251.571047] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  251.571184] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  251.571331] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  251.575567] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  251.575629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  251.575741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  251.575810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  251.575868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  251.575926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  251.575983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  251.576042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  251.576100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  251.576158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  251.576216] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  251.576278] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  251.576339] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  251.576460] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  251.576530] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  251.576611] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  251.576724] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  251.576794] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  251.576873] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  251.580114] PM: freeze of devices complete after 329.951 msecs
>[  251.580118] hibernation debug: Waiting for 5 seconds.
>[  256.983878] usb usb1: root hub lost power or was reset
>[  256.983881] usb usb2: root hub lost power or was reset
>[  256.984477] ACPI : EC: event unblocked
>[  256.984845] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x79df2018
>[  256.984924] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  256.984957] [drm:intel_opregion_setup [i915]] ASLE supported
>[  256.985241] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA)
>[  256.985390] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  256.985447] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  256.987492] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  256.987528] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  256.988007] [drm:drm_dp_i2c_do_msg] native defer
>[  256.990065] [drm:drm_dp_i2c_do_msg] native defer
>[  256.990360] rtc_cmos 00:04: System wakeup disabled by ACPI
>[  256.991373] [drm:drm_dp_i2c_do_msg] native defer
>[  256.992676] [drm:drm_dp_i2c_do_msg] native defer
>[  256.993942] [drm:drm_dp_i2c_do_msg] native defer
>[  256.994787] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  256.994932] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  256.995068] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  256.995071] sd 0:0:0:0: [sda] Starting disk
>[  256.995183] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  256.995296] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  256.995355] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[  256.995364] [drm] GuC firmware load skipped
>[  256.996143] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  256.996202] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  256.996291] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:33:pipe A] hw state readout: disabled
>[  256.996337] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:42:pipe B] hw state readout: disabled
>[  256.996382] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:49:pipe C] hw state readout: disabled
>[  256.996420] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0
>[  256.996457] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0
>[  256.996494] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0
>[  256.996532] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI A] hw state readout: disabled, pipe A
>[  256.996570] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI B] hw state readout: disabled, pipe A
>[  256.996604] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A
>[  256.996637] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B
>[  256.996697] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C
>[  256.996749] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:63:DDI C] hw state readout: disabled, pipe A
>[  256.996786] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST A] hw state readout: disabled, pipe A
>[  256.996819] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST B] hw state readout: disabled, pipe B
>[  256.996853] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:67:DP-MST C] hw state readout: disabled, pipe C
>[  256.996892] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:eDP-1] hw state readout: disabled
>[  256.996932] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-1] hw state readout: disabled
>[  256.996971] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:64:DP-2] hw state readout: disabled
>[  256.997010] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:68:HDMI-A-1] hw state readout: disabled
>[  256.997049] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][setup_hw_state]
>[  256.997082] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  256.997114] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  256.997145] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  256.997151] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  256.997183] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  256.997186] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  256.997219] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  256.997251] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  256.997283] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  256.997315] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  256.997347] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  256.997385] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  256.997416] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  256.997451] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  256.997483] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  256.997518] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  256.997550] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  256.997583] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  256.997620] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][setup_hw_state]
>[  256.997652] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  256.997717] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  256.997749] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  256.997752] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  256.997783] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  256.997786] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  256.997819] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  256.997851] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  256.997883] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  256.997915] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  256.997947] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  256.997980] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  256.998012] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  256.998045] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  256.998078] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  256.998110] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  256.998142] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  256.998175] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  256.998211] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][setup_hw_state]
>[  256.998243] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  256.998275] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  256.998306] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  256.998310] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  256.998341] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  256.998344] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  256.998377] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  256.998409] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  256.998441] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  256.998473] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  256.998505] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  256.998538] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  256.998570] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  256.998602] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  256.998634] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  256.998707] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  256.998883] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  256.998917] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  256.998920] igb 0000:01:00.0: System wakeup disabled by ACPI
>[  256.998951] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  256.999001] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  256.999033] [drm:intel_power_well_disable [i915]] disabling DC off
>[  256.999068] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  256.999097] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  256.999637] [drm:intel_power_well_disable [i915]] disabling always-on
>[  256.999762] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  256.999799] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  256.999839] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  256.999880] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  256.999915] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  256.999952] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  256.999987] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  257.000022] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  257.000058] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  257.000093] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  257.000127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  257.000131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  257.000165] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  257.000169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  257.000205] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  257.000240] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  257.000275] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  257.000310] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  257.000344] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  257.000381] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  257.000416] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  257.000452] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  257.000487] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  257.000522] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  257.000557] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  257.000591] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  257.000633] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  257.000692] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  257.000731] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  257.000765] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  257.000801] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  257.000836] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  257.000871] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  257.000905] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  257.000940] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  257.000943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  257.000978] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  257.000981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  257.001017] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  257.001052] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  257.001087] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  257.001122] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  257.001157] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  257.001194] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  257.001228] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  257.001264] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  257.001299] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  257.001334] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  257.001369] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  257.001403] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  257.001441] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  257.001487] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  257.001524] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  257.001565] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  257.001601] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  257.001780] [drm:intel_power_well_enable [i915]] enabling always-on
>[  257.001810] [drm:intel_power_well_enable [i915]] enabling DC off
>[  257.002094] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  257.002148] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  257.002299] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  257.002334] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  257.002393] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  257.002617] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  257.007066] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  257.007102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  257.007138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  257.007181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  257.007216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  257.007251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  257.007286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  257.007321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  257.007353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  257.007389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  257.007424] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:59:DP-1]
>[  257.007465] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:64:DP-2]
>[  257.007506] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  257.007543] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  257.007578] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  257.007647] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  257.007733] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  257.007965] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  257.008000] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  257.008045] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  257.008081] [drm:wait_panel_status [i915]] Wait complete
>[  257.008117] [drm:edp_panel_on [i915]] Wait for panel power on
>[  257.008156] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  257.116598] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  257.116655] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  257.116709] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  257.116832] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  257.209474] [drm:wait_panel_status [i915]] Wait complete
>[  257.209557] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  257.209628] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  257.211120] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  257.211175] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  257.211235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  257.212214] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  257.212269] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  257.213503] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  257.213816] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016ce48958
>[  257.215617] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  257.215734] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  257.215789] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  257.215852] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  257.215931] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  257.215987] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  257.216066] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  257.216124] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  257.216368] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  257.216424] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  257.216816] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016ce4efc8
>[  257.218594] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  257.219225] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  257.219282] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  257.219368] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  257.219423] [drm:hsw_audio_config_update [i915]] using automatic N
>[  257.220715] atkbd serio0: Failed to deactivate keyboard on isa0060/serio0
>[  257.236259] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  257.236347] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  257.236616] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  257.236968] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  257.237058] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  257.237313] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  257.237473] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  257.237889] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  257.237982] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  257.238053] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  257.238120] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  257.238185] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  257.238251] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  257.238407] [drm:intel_opregion_register [i915]] 4 outputs detected
>[  257.241901] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  257.242459] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:eDP-1] status updated from connected to connected
>[  257.242527] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  257.243215] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  257.243626] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-1] status updated from disconnected to disconnected
>[  257.243699] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  257.252372] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.261128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.269996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.278871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.287778] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.296647] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.305567] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.314499] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.323351] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.332270] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.341128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.349989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.358857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.365076] usb 1-7: reset full-speed USB device number 2 using xhci_hcd
>[  257.367788] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.376623] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.385557] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.394424] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.403280] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.412134] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.421003] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.429873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.438746] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.447603] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.456518] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.465371] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.474241] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.483110] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.484716] atkbd serio0: Failed to enable keyboard on isa0060/serio0
>[  257.491976] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.500841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.509758] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.518623] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.527543] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  257.527580] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  257.527590] [drm:drm_helper_hpd_irq_event] [CONNECTOR:64:DP-2] status updated from disconnected to disconnected
>[  257.527671] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  257.540022] PM: restore of devices complete after 557.103 msecs
>[  257.544270] PM: Image restored successfully.
>[  257.544710] PM: Basic memory bitmaps freed
>[  257.544715] Restarting tasks ... done.
>[  257.597084] [drm] RC6 on
>[  257.623691] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  257.627669] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  257.627720] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  257.627726] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  257.627733] [drm:drm_helper_hpd_irq_event] [CONNECTOR:68:HDMI-A-1] status updated from connected to connected
>[  258.909508] [IGT] gem_exec_suspend: exiting, ret=0
>[  258.986819] Console: switching to colour frame buffer device 240x67
>[  259.780908] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  259.781027] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  259.878470] igb 0000:01:00.0 enp1s0: igb: enp1s0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX
>[  260.084775] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  260.087744] ata1.00: supports DRM functions and may not be fully accessible
>[  260.088220] ata1.00: NCQ Send/Recv Log not supported
>[  260.090211] ata1.00: supports DRM functions and may not be fully accessible
>[  260.090806] ata1.00: NCQ Send/Recv Log not supported
>[  260.090822] ata1.00: configured for UDMA/133
>[  260.212548] Console: switching to colour dummy device 80x25
>[  260.212984] [IGT] gem_flink_basic: executing
>[  260.238237] [IGT] gem_flink_basic: starting subtest bad-flink
>[  260.238425] [IGT] gem_flink_basic: exiting, ret=0
>[  260.269893] Console: switching to colour frame buffer device 240x67
>[  260.401424] Console: switching to colour dummy device 80x25
>[  260.401705] [IGT] gem_flink_basic: executing
>[  260.415371] [IGT] gem_flink_basic: starting subtest bad-open
>[  260.415525] [IGT] gem_flink_basic: exiting, ret=0
>[  260.453171] Console: switching to colour frame buffer device 240x67
>[  260.581588] Console: switching to colour dummy device 80x25
>[  260.581993] [IGT] gem_flink_basic: executing
>[  260.605141] [IGT] gem_flink_basic: starting subtest basic
>[  260.605403] [IGT] gem_flink_basic: exiting, ret=0
>[  260.636420] Console: switching to colour frame buffer device 240x67
>[  260.764365] Console: switching to colour dummy device 80x25
>[  260.764678] [IGT] gem_flink_basic: executing
>[  260.779326] [IGT] gem_flink_basic: starting subtest double-flink
>[  260.779525] [IGT] gem_flink_basic: exiting, ret=0
>[  260.819913] Console: switching to colour frame buffer device 240x67
>[  260.945233] Console: switching to colour dummy device 80x25
>[  260.945478] [IGT] gem_flink_basic: executing
>[  260.971205] [IGT] gem_flink_basic: starting subtest flink-lifetime
>[  260.972252] [IGT] gem_flink_basic: exiting, ret=0
>[  261.003128] Console: switching to colour frame buffer device 240x67
>[  261.126363] Console: switching to colour dummy device 80x25
>[  261.126581] [IGT] gem_linear_blits: executing
>[  261.150207] [IGT] gem_linear_blits: starting subtest basic
>[  261.177153] [IGT] gem_linear_blits: exiting, ret=0
>[  261.219877] Console: switching to colour frame buffer device 240x67
>[  261.352470] Console: switching to colour dummy device 80x25
>[  261.352791] [IGT] gem_mmap: executing
>[  261.380185] [IGT] gem_mmap: starting subtest basic
>[  261.381122] [IGT] gem_mmap: exiting, ret=0
>[  261.436486] Console: switching to colour frame buffer device 240x67
>[  261.564355] Console: switching to colour dummy device 80x25
>[  261.564576] [IGT] gem_mmap: executing
>[  261.591182] [IGT] gem_mmap: starting subtest basic-small-bo
>[  262.063582] [IGT] gem_mmap: exiting, ret=0
>[  262.103177] Console: switching to colour frame buffer device 240x67
>[  262.268369] Console: switching to colour dummy device 80x25
>[  262.268604] [IGT] gem_mmap_gtt: executing
>[  262.293202] [IGT] gem_mmap_gtt: starting subtest basic
>[  262.293936] [IGT] gem_mmap_gtt: exiting, ret=0
>[  262.319782] Console: switching to colour frame buffer device 240x67
>[  262.445897] Console: switching to colour dummy device 80x25
>[  262.446125] [IGT] gem_mmap_gtt: executing
>[  262.473156] [IGT] gem_mmap_gtt: starting subtest basic-copy
>[  263.275536] [IGT] gem_mmap_gtt: exiting, ret=0
>[  263.351006] Console: switching to colour frame buffer device 240x67
>[  263.483820] Console: switching to colour dummy device 80x25
>[  263.484109] [IGT] gem_mmap_gtt: executing
>[  263.510104] [IGT] gem_mmap_gtt: starting subtest basic-read
>[  263.564268] [IGT] gem_mmap_gtt: exiting, ret=0
>[  263.636490] Console: switching to colour frame buffer device 240x67
>[  263.763138] Console: switching to colour dummy device 80x25
>[  263.763367] [IGT] gem_mmap_gtt: executing
>[  263.779419] [IGT] gem_mmap_gtt: starting subtest basic-read-no-prefault
>[  263.779619] Setting dangerous option prefault_disable - tainting kernel
>[  263.829782] Setting dangerous option prefault_disable - tainting kernel
>[  263.830013] [IGT] gem_mmap_gtt: exiting, ret=0
>[  263.830177] Setting dangerous option prefault_disable - tainting kernel
>[  263.903085] Console: switching to colour frame buffer device 240x67
>[  264.030173] Console: switching to colour dummy device 80x25
>[  264.030393] [IGT] gem_mmap_gtt: executing
>[  264.053222] [IGT] gem_mmap_gtt: starting subtest basic-read-write
>[  264.079174] [IGT] gem_mmap_gtt: exiting, ret=0
>[  264.119605] Console: switching to colour frame buffer device 240x67
>[  264.247402] Console: switching to colour dummy device 80x25
>[  264.247726] [IGT] gem_mmap_gtt: executing
>[  264.260496] [IGT] gem_mmap_gtt: starting subtest basic-read-write-distinct
>[  264.286258] [IGT] gem_mmap_gtt: exiting, ret=0
>[  264.353160] Console: switching to colour frame buffer device 240x67
>[  264.496961] Console: switching to colour dummy device 80x25
>[  264.497305] [IGT] gem_mmap_gtt: executing
>[  264.522262] [IGT] gem_mmap_gtt: starting subtest basic-short
>[  264.560072] [IGT] gem_mmap_gtt: exiting, ret=0
>[  264.619889] Console: switching to colour frame buffer device 240x67
>[  264.748996] Console: switching to colour dummy device 80x25
>[  264.749275] [IGT] gem_mmap_gtt: executing
>[  264.776309] [IGT] gem_mmap_gtt: starting subtest basic-small-bo
>[  264.987928] [IGT] gem_mmap_gtt: exiting, ret=0
>[  265.153108] Console: switching to colour frame buffer device 240x67
>[  265.317894] Console: switching to colour dummy device 80x25
>[  265.318129] [IGT] gem_mmap_gtt: executing
>[  265.343203] [IGT] gem_mmap_gtt: starting subtest basic-small-bo-tiledX
>[  265.546591] [IGT] gem_mmap_gtt: exiting, ret=0
>[  265.719603] Console: switching to colour frame buffer device 240x67
>[  265.881915] Console: switching to colour dummy device 80x25
>[  265.882158] [IGT] gem_mmap_gtt: executing
>[  265.906045] [IGT] gem_mmap_gtt: starting subtest basic-small-bo-tiledY
>[  266.108728] [IGT] gem_mmap_gtt: exiting, ret=0
>[  266.269804] Console: switching to colour frame buffer device 240x67
>[  266.438238] Console: switching to colour dummy device 80x25
>[  266.438512] [IGT] gem_mmap_gtt: executing
>[  266.464281] [IGT] gem_mmap_gtt: starting subtest basic-small-copy
>[  268.975303] [IGT] gem_mmap_gtt: exiting, ret=0
>[  269.036284] Console: switching to colour frame buffer device 240x67
>[  269.215457] Console: switching to colour dummy device 80x25
>[  269.216051] [IGT] gem_mmap_gtt: executing
>[  269.241221] [IGT] gem_mmap_gtt: starting subtest basic-small-copy-XY
>[  272.148616] [IGT] gem_mmap_gtt: exiting, ret=0
>[  272.202939] Console: switching to colour frame buffer device 240x67
>[  272.366195] Console: switching to colour dummy device 80x25
>[  272.366447] [IGT] gem_mmap_gtt: executing
>[  272.380555] [IGT] gem_mmap_gtt: starting subtest basic-wc
>[  273.010771] [IGT] gem_mmap_gtt: exiting, ret=0
>[  273.069810] Console: switching to colour frame buffer device 240x67
>[  273.206304] Console: switching to colour dummy device 80x25
>[  273.206550] [IGT] gem_mmap_gtt: executing
>[  273.233089] [IGT] gem_mmap_gtt: starting subtest basic-write
>[  273.656047] [IGT] gem_mmap_gtt: exiting, ret=0
>[  273.719672] Console: switching to colour frame buffer device 240x67
>[  273.856049] Console: switching to colour dummy device 80x25
>[  273.856389] [IGT] gem_mmap_gtt: executing
>[  273.881180] [IGT] gem_mmap_gtt: starting subtest basic-write-cpu-read-gtt
>[  273.881447] [IGT] gem_mmap_gtt: exiting, ret=77
>[  273.919870] Console: switching to colour frame buffer device 240x67
>[  274.060543] Console: switching to colour dummy device 80x25
>[  274.060866] [IGT] gem_mmap_gtt: executing
>[  274.084083] [IGT] gem_mmap_gtt: starting subtest basic-write-gtt
>[  274.850004] [IGT] gem_mmap_gtt: exiting, ret=0
>[  274.903069] Console: switching to colour frame buffer device 240x67
>[  275.030096] Console: switching to colour dummy device 80x25
>[  275.030370] [IGT] gem_mmap_gtt: executing
>[  275.055193] [IGT] gem_mmap_gtt: starting subtest basic-write-gtt-no-prefault
>[  275.055461] Setting dangerous option prefault_disable - tainting kernel
>[  275.821037] Setting dangerous option prefault_disable - tainting kernel
>[  275.821356] [IGT] gem_mmap_gtt: exiting, ret=0
>[  275.821524] Setting dangerous option prefault_disable - tainting kernel
>[  275.886430] Console: switching to colour frame buffer device 240x67
>[  276.015487] Console: switching to colour dummy device 80x25
>[  276.015953] [IGT] gem_mmap_gtt: executing
>[  276.031516] [IGT] gem_mmap_gtt: starting subtest basic-write-no-prefault
>[  276.031728] Setting dangerous option prefault_disable - tainting kernel
>[  276.454744] Setting dangerous option prefault_disable - tainting kernel
>[  276.455067] [IGT] gem_mmap_gtt: exiting, ret=0
>[  276.455235] Setting dangerous option prefault_disable - tainting kernel
>[  276.536397] Console: switching to colour frame buffer device 240x67
>[  276.666540] Console: switching to colour dummy device 80x25
>[  276.666889] [IGT] gem_mmap_gtt: executing
>[  276.692180] [IGT] gem_mmap_gtt: starting subtest basic-write-read
>[  276.719208] [IGT] gem_mmap_gtt: exiting, ret=0
>[  276.769745] Console: switching to colour frame buffer device 240x67
>[  276.903258] Console: switching to colour dummy device 80x25
>[  276.903524] [IGT] gem_mmap_gtt: executing
>[  276.927197] [IGT] gem_mmap_gtt: starting subtest basic-write-read-distinct
>[  276.954226] [IGT] gem_mmap_gtt: exiting, ret=0
>[  277.003097] Console: switching to colour frame buffer device 240x67
>[  277.133719] Console: switching to colour dummy device 80x25
>[  277.133948] [IGT] gem_pread: executing
>[  277.157325] [IGT] gem_pread: starting subtest basic
>[  279.343122] [IGT] gem_pread: exiting, ret=0
>[  279.403104] Console: switching to colour frame buffer device 240x67
>[  279.530356] Console: switching to colour dummy device 80x25
>[  279.530572] [IGT] gem_pwrite: executing
>[  279.544822] [IGT] gem_pwrite: starting subtest basic
>[  282.289839] [IGT] gem_pwrite: exiting, ret=0
>[  282.336617] Console: switching to colour frame buffer device 240x67
>[  282.464826] Console: switching to colour dummy device 80x25
>[  282.465081] [IGT] gem_render_linear_blits: executing
>[  282.489181] [IGT] gem_render_linear_blits: starting subtest basic
>[  282.520800] [IGT] gem_render_linear_blits: exiting, ret=0
>[  282.553336] Console: switching to colour frame buffer device 240x67
>[  282.665211] Console: switching to colour dummy device 80x25
>[  282.665460] [IGT] gem_render_tiled_blits: executing
>[  282.689189] [IGT] gem_render_tiled_blits: starting subtest basic
>[  282.717165] [IGT] gem_render_tiled_blits: exiting, ret=0
>[  282.753279] Console: switching to colour frame buffer device 240x67
>[  282.896816] Console: switching to colour dummy device 80x25
>[  282.897066] [IGT] gem_ringfill: executing
>[  282.922204] [IGT] gem_ringfill: starting subtest basic-default
>[  283.454883] [IGT] gem_ringfill: exiting, ret=0
>[  283.503467] Console: switching to colour frame buffer device 240x67
>[  283.638141] Console: switching to colour dummy device 80x25
>[  283.638387] [IGT] gem_ringfill: executing
>[  283.666217] [IGT] gem_ringfill: starting subtest basic-default-interruptible
>[  284.278990] [IGT] gem_ringfill: exiting, ret=0
>[  284.337008] Console: switching to colour frame buffer device 240x67
>[  284.467689] Console: switching to colour dummy device 80x25
>[  284.467987] [IGT] gem_ringfill: executing
>[  284.491044] [IGT] gem_ringfill: starting subtest basic-default-forked
>[  286.492915] [IGT] gem_ringfill: exiting, ret=0
>[  286.537292] Console: switching to colour frame buffer device 240x67
>[  286.672190] Console: switching to colour dummy device 80x25
>[  286.672473] [IGT] gem_ringfill: executing
>[  286.699240] [IGT] gem_ringfill: starting subtest basic-default-fd
>[  290.118003] [IGT] gem_ringfill: exiting, ret=0
>[  290.171182] Console: switching to colour frame buffer device 240x67
>[  290.304534] Console: switching to colour dummy device 80x25
>[  290.304991] [IGT] gem_ringfill: executing
>[  290.330142] [IGT] gem_ringfill: starting subtest basic-default-hang
>[  299.781783] drm/i915: Resetting chip after gpu hang
>[  299.782162] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  299.786430] [drm:i915_gem_reset_finish [i915]] context gem_ringfill[7900]/0 marked guilty (score 10) banned? no
>[  299.786566] [drm:i915_gem_reset_finish [i915]] resetting render ring to restart from tail of request 0x1206ac
>[  299.787343] [drm] RC6 on
>[  299.789313] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  299.789370] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x120728, 0x0]
>[  299.789514] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  299.789641] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  299.789813] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  299.789889] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[  299.789909] [drm] GuC firmware load skipped
>[  300.291301] [IGT] gem_ringfill: exiting, ret=0
>[  300.339409] Console: switching to colour frame buffer device 240x67
>[  300.480878] Console: switching to colour dummy device 80x25
>[  300.481214] [IGT] gem_sync: executing
>[  300.509334] [IGT] gem_sync: starting subtest basic-all
>[  305.743300] [IGT] gem_sync: exiting, ret=0
>[  305.803202] Console: switching to colour frame buffer device 240x67
>[  305.947073] Console: switching to colour dummy device 80x25
>[  305.947296] [IGT] gem_sync: executing
>[  305.971989] [IGT] gem_sync: starting subtest basic-each
>[  311.095409] [IGT] gem_sync: exiting, ret=0
>[  311.153226] Console: switching to colour frame buffer device 240x67
>[  311.287785] Console: switching to colour dummy device 80x25
>[  311.288062] [IGT] gem_sync: executing
>[  311.317488] [IGT] gem_sync: starting subtest basic-many-each
>[  316.891417] [IGT] gem_sync: exiting, ret=0
>[  316.942020] Console: switching to colour frame buffer device 240x67
>[  317.086667] Console: switching to colour dummy device 80x25
>[  317.086893] [IGT] gem_sync: executing
>[  317.113938] [IGT] gem_sync: starting subtest basic-store-all
>[  322.331802] [IGT] gem_sync: exiting, ret=0
>[  322.392762] Console: switching to colour frame buffer device 240x67
>[  322.530161] Console: switching to colour dummy device 80x25
>[  322.530389] [IGT] gem_sync: executing
>[  322.561298] [IGT] gem_sync: starting subtest basic-store-each
>[  328.011216] [IGT] gem_sync: exiting, ret=0
>[  328.069979] Console: switching to colour frame buffer device 240x67
>[  328.197407] Console: switching to colour dummy device 80x25
>[  328.197690] [IGT] gem_tiled_blits: executing
>[  328.221443] [IGT] gem_tiled_blits: starting subtest basic
>[  328.252385] [IGT] gem_tiled_blits: exiting, ret=0
>[  328.310300] Console: switching to colour frame buffer device 240x67
>[  328.443992] Console: switching to colour dummy device 80x25
>[  328.444227] [IGT] gem_tiled_fence_blits: executing
>[  328.468127] [IGT] gem_tiled_fence_blits: starting subtest basic
>[  328.487787] [IGT] gem_tiled_fence_blits: exiting, ret=0
>[  328.543688] Console: switching to colour frame buffer device 240x67
>[  328.694406] Console: switching to colour dummy device 80x25
>[  328.694804] [IGT] gem_tiled_pread_basic: executing
>[  328.950282] [IGT] gem_tiled_pread_basic: exiting, ret=0
>[  329.003171] Console: switching to colour frame buffer device 240x67
>[  329.132985] Console: switching to colour dummy device 80x25
>[  329.133208] [IGT] gem_wait: executing
>[  329.150843] [IGT] gem_wait: starting subtest basic-busy-all
>[  329.175828] [IGT] gem_wait: exiting, ret=0
>[  329.227133] Console: switching to colour frame buffer device 240x67
>[  329.369911] Console: switching to colour dummy device 80x25
>[  329.370139] [IGT] gem_wait: executing
>[  329.387482] [IGT] gem_wait: starting subtest basic-wait-all
>[  330.412045] [IGT] gem_wait: exiting, ret=0
>[  330.469970] Console: switching to colour frame buffer device 240x67
>[  330.599058] Console: switching to colour dummy device 80x25
>[  330.599278] [IGT] gem_workarounds: executing
>[  330.636029] [IGT] gem_workarounds: starting subtest basic-read
>[  330.653255] [IGT] gem_workarounds: exiting, ret=0
>[  330.694152] Console: switching to colour frame buffer device 240x67
>[  330.860912] Console: switching to colour dummy device 80x25
>[  330.861243] [IGT] kms_addfb_basic: executing
>[  330.887390] [drm:drm_mode_addfb2] [FB:89]
>[  330.888189] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
>[  330.888286] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  330.904994] [drm:drm_mode_addfb2] [FB:89]
>[  330.905164] [IGT] kms_addfb_basic: exiting, ret=0
>[  330.960497] Console: switching to colour frame buffer device 240x67
>[  331.097270] Console: switching to colour dummy device 80x25
>[  331.097525] [IGT] kms_addfb_basic: executing
>[  331.121250] [drm:drm_mode_addfb2] [FB:91]
>[  331.121862] [IGT] kms_addfb_basic: starting subtest addfb25-framebuffer-vs-set-tiling
>[  331.121939] [drm:drm_mode_addfb2] [FB:91]
>[  331.138056] [drm:drm_mode_addfb2] [FB:91]
>[  331.138262] [IGT] kms_addfb_basic: exiting, ret=0
>[  331.194193] Console: switching to colour frame buffer device 240x67
>[  331.328906] Console: switching to colour dummy device 80x25
>[  331.329146] [IGT] kms_addfb_basic: executing
>[  331.353267] [drm:drm_mode_addfb2] [FB:89]
>[  331.353821] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
>[  331.353891] [drm:drm_internal_framebuffer_create] bad fb modifier 72057594037927937 for plane 0
>[  331.370724] [drm:drm_mode_addfb2] [FB:89]
>[  331.370896] [IGT] kms_addfb_basic: exiting, ret=0
>[  331.410768] Console: switching to colour frame buffer device 240x67
>[  331.546810] Console: switching to colour dummy device 80x25
>[  331.547083] [IGT] kms_addfb_basic: executing
>[  331.572236] [drm:drm_mode_addfb2] [FB:91]
>[  331.572854] [IGT] kms_addfb_basic: starting subtest addfb25-X-tiled
>[  331.572928] [drm:drm_mode_addfb2] [FB:91]
>[  331.589006] [drm:drm_mode_addfb2] [FB:91]
>[  331.589179] [IGT] kms_addfb_basic: exiting, ret=0
>[  331.644140] Console: switching to colour frame buffer device 240x67
>[  331.788037] Console: switching to colour dummy device 80x25
>[  331.788269] [IGT] kms_addfb_basic: executing
>[  331.811180] [drm:drm_mode_addfb2] [FB:89]
>[  331.811828] [IGT] kms_addfb_basic: starting subtest addfb25-X-tiled-mismatch
>[  331.811909] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  331.828114] [drm:drm_mode_addfb2] [FB:89]
>[  331.828283] [IGT] kms_addfb_basic: exiting, ret=0
>[  331.877328] Console: switching to colour frame buffer device 240x67
>[  332.008798] Console: switching to colour dummy device 80x25
>[  332.009051] [IGT] kms_addfb_basic: executing
>[  332.035259] [drm:drm_mode_addfb2] [FB:91]
>[  332.036042] [IGT] kms_addfb_basic: starting subtest addfb25-Yf-tiled
>[  332.036129] [drm:drm_mode_addfb2] [FB:91]
>[  332.051906] [drm:drm_mode_addfb2] [FB:91]
>[  332.052078] [IGT] kms_addfb_basic: exiting, ret=0
>[  332.103209] Console: switching to colour frame buffer device 240x67
>[  332.241149] Console: switching to colour dummy device 80x25
>[  332.241369] [IGT] kms_addfb_basic: executing
>[  332.255452] [drm:drm_mode_addfb2] [FB:89]
>[  332.256004] [IGT] kms_addfb_basic: starting subtest addfb25-Y-tiled
>[  332.256067] [drm:drm_mode_addfb2] [FB:89]
>[  332.271839] [drm:drm_mode_addfb2] [FB:89]
>[  332.272012] [IGT] kms_addfb_basic: exiting, ret=0
>[  332.327493] Console: switching to colour frame buffer device 240x67
>[  332.460014] Console: switching to colour dummy device 80x25
>[  332.460241] [IGT] kms_addfb_basic: executing
>[  332.476720] [drm:drm_mode_addfb2] [FB:91]
>[  332.477360] [IGT] kms_addfb_basic: starting subtest addfb25-Y-tiled-small
>[  332.477443] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  332.491858] [drm:drm_mode_addfb2] [FB:91]
>[  332.492027] [IGT] kms_addfb_basic: exiting, ret=0
>[  332.544280] Console: switching to colour frame buffer device 240x67
>[  332.686203] Console: switching to colour dummy device 80x25
>[  332.686424] [IGT] kms_addfb_basic: executing
>[  332.712312] [drm:drm_mode_addfb2] [FB:89]
>[  332.712593] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
>[  332.712726] [drm:drm_internal_framebuffer_create] bad pitch 0 for plane 0
>[  332.730089] [drm:drm_mode_addfb2] [FB:89]
>[  332.730280] [IGT] kms_addfb_basic: exiting, ret=0
>[  332.777761] Console: switching to colour frame buffer device 240x67
>[  332.932204] Console: switching to colour dummy device 80x25
>[  332.932424] [IGT] kms_addfb_basic: executing
>[  332.958054] [drm:drm_mode_addfb2] [FB:91]
>[  332.958229] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
>[  332.958266] [drm:drm_internal_framebuffer_create] bad pitch 1024 for plane 0
>[  332.974843] [drm:drm_mode_addfb2] [FB:91]
>[  332.975015] [IGT] kms_addfb_basic: exiting, ret=0
>[  333.027753] Console: switching to colour frame buffer device 240x67
>[  333.159201] Console: switching to colour dummy device 80x25
>[  333.159460] [IGT] kms_addfb_basic: executing
>[  333.184252] [drm:drm_mode_addfb2] [FB:89]
>[  333.184508] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
>[  333.184566] [drm:drm_internal_framebuffer_create] bad pitch 128 for plane 0
>[  333.201055] [drm:drm_mode_addfb2] [FB:89]
>[  333.201229] [IGT] kms_addfb_basic: exiting, ret=0
>[  333.253198] Console: switching to colour frame buffer device 240x67
>[  333.410607] Console: switching to colour dummy device 80x25
>[  333.411004] [IGT] kms_addfb_basic: executing
>[  333.436271] [drm:drm_mode_addfb2] [FB:91]
>[  333.436529] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
>[  333.436586] [drm:drm_internal_framebuffer_create] bad pitch 256 for plane 0
>[  333.454300] [drm:drm_mode_addfb2] [FB:91]
>[  333.454472] [IGT] kms_addfb_basic: exiting, ret=0
>[  333.494363] Console: switching to colour frame buffer device 240x67
>[  333.636007] Console: switching to colour dummy device 80x25
>[  333.636251] [IGT] kms_addfb_basic: executing
>[  333.665262] [drm:drm_mode_addfb2] [FB:89]
>[  333.665525] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
>[  333.665580] [drm:drm_internal_framebuffer_create] bad pitch 32 for plane 0
>[  333.682391] [drm:drm_mode_addfb2] [FB:89]
>[  333.682566] [IGT] kms_addfb_basic: exiting, ret=0
>[  333.736426] Console: switching to colour frame buffer device 240x67
>[  333.874410] Console: switching to colour dummy device 80x25
>[  333.874734] [IGT] kms_addfb_basic: executing
>[  333.901259] [drm:drm_mode_addfb2] [FB:91]
>[  333.901514] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
>[  333.901569] [drm:drm_internal_framebuffer_create] bad pitch 63 for plane 0
>[  333.917859] [drm:drm_mode_addfb2] [FB:91]
>[  333.918029] [IGT] kms_addfb_basic: exiting, ret=0
>[  333.969697] Console: switching to colour frame buffer device 240x67
>[  334.108215] Console: switching to colour dummy device 80x25
>[  334.108443] [IGT] kms_addfb_basic: executing
>[  334.134140] [drm:drm_mode_addfb2] [FB:89]
>[  334.134337] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
>[  334.134390] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  334.149744] [drm:drm_mode_addfb2] [FB:89]
>[  334.149914] [IGT] kms_addfb_basic: exiting, ret=0
>[  334.203196] Console: switching to colour frame buffer device 240x67
>[  334.339299] Console: switching to colour dummy device 80x25
>[  334.339518] [IGT] kms_addfb_basic: executing
>[  334.364269] [drm:drm_mode_addfb2] [FB:91]
>[  334.364523] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
>[  334.364579] [drm:drm_internal_framebuffer_create] bad pitch 999 for plane 0
>[  334.380952] [drm:drm_mode_addfb2] [FB:91]
>[  334.381120] [IGT] kms_addfb_basic: exiting, ret=0
>[  334.436532] Console: switching to colour frame buffer device 240x67
>[  334.573245] Console: switching to colour dummy device 80x25
>[  334.573496] [IGT] kms_addfb_basic: executing
>[  334.603233] [drm:drm_mode_addfb2] [FB:89]
>[  334.603477] [IGT] kms_addfb_basic: starting subtest basic
>[  334.603547] [drm:drm_mode_addfb2] [FB:89]
>[  334.619554] [drm:drm_mode_addfb2] [FB:89]
>[  334.619854] [IGT] kms_addfb_basic: exiting, ret=0
>[  334.669922] Console: switching to colour frame buffer device 240x67
>[  334.802562] Console: switching to colour dummy device 80x25
>[  334.802904] [IGT] kms_addfb_basic: executing
>[  334.830300] [drm:drm_mode_addfb2] [FB:91]
>[  334.846545] [IGT] kms_addfb_basic: starting subtest basic-X-tiled
>[  334.846629] [drm:drm_mode_addfb2] [FB:91]
>[  334.847308] [drm:drm_mode_addfb2] [FB:91]
>[  334.847466] [IGT] kms_addfb_basic: exiting, ret=0
>[  334.903168] Console: switching to colour frame buffer device 240x67
>[  335.041082] Console: switching to colour dummy device 80x25
>[  335.041302] [IGT] kms_addfb_basic: executing
>[  335.066314] [drm:drm_mode_addfb2] [FB:89]
>[  335.082409] [IGT] kms_addfb_basic: starting subtest basic-Y-tiled
>[  335.082489] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  335.082627] [drm:drm_mode_addfb2] [FB:89]
>[  335.083035] [IGT] kms_addfb_basic: exiting, ret=0
>[  335.136515] Console: switching to colour frame buffer device 240x67
>[  335.288333] Console: switching to colour dummy device 80x25
>[  335.288573] [IGT] kms_addfb_basic: executing
>[  335.316166] [drm:drm_mode_addfb2] [FB:91]
>[  335.316560] [IGT] kms_addfb_basic: starting subtest bo-too-small
>[  335.316707] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  335.334149] [drm:drm_mode_addfb2] [FB:91]
>[  335.334325] [IGT] kms_addfb_basic: exiting, ret=0
>[  335.377988] Console: switching to colour frame buffer device 240x67
>[  335.513047] Console: switching to colour dummy device 80x25
>[  335.513285] [IGT] kms_addfb_basic: executing
>[  335.532759] [drm:drm_mode_addfb2] [FB:89]
>[  335.533136] [IGT] kms_addfb_basic: starting subtest bo-too-small-due-to-tiling
>[  335.533233] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  335.548383] [drm:drm_mode_addfb2] [FB:89]
>[  335.548553] [IGT] kms_addfb_basic: exiting, ret=0
>[  335.611409] Console: switching to colour frame buffer device 240x67
>[  335.762216] Console: switching to colour dummy device 80x25
>[  335.762549] [IGT] kms_addfb_basic: executing
>[  335.795175] [drm:drm_mode_addfb2] [FB:91]
>[  335.795317] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
>[  335.795415] [drm:drm_mode_addfb2] [FB:91]
>[  335.811855] [drm:drm_mode_addfb2] [FB:91]
>[  335.812028] [IGT] kms_addfb_basic: exiting, ret=0
>[  335.861494] Console: switching to colour frame buffer device 240x67
>[  336.002246] Console: switching to colour dummy device 80x25
>[  336.002504] [IGT] kms_addfb_basic: executing
>[  336.019569] [drm:drm_mode_addfb2] [FB:89]
>[  336.034493] [IGT] kms_addfb_basic: starting subtest framebuffer-vs-set-tiling
>[  336.034596] [drm:drm_mode_addfb2] [FB:89]
>[  336.034808] [drm:drm_mode_addfb2] [FB:89]
>[  336.034935] [IGT] kms_addfb_basic: exiting, ret=0
>[  336.078070] Console: switching to colour frame buffer device 240x67
>[  336.214456] Console: switching to colour dummy device 80x25
>[  336.214840] [IGT] kms_addfb_basic: executing
>[  336.240275] [drm:drm_mode_addfb2] [FB:91]
>[  336.257478] [drm:drm_mode_addfb2] [FB:91]
>[  336.257586] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
>[  336.258110] [IGT] kms_addfb_basic: exiting, ret=0
>[  336.303094] Console: switching to colour frame buffer device 240x67
>[  336.434832] Console: switching to colour dummy device 80x25
>[  336.435099] [IGT] kms_addfb_basic: executing
>[  336.461144] [drm:drm_mode_addfb2] [FB:89]
>[  336.478447] [drm:drm_mode_addfb2] [FB:89]
>[  336.478555] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
>[  336.478863] [IGT] kms_addfb_basic: exiting, ret=0
>[  336.519913] Console: switching to colour frame buffer device 240x67
>[  336.657100] Console: switching to colour dummy device 80x25
>[  336.657322] [IGT] kms_addfb_basic: executing
>[  336.684278] [drm:drm_mode_addfb2] [FB:91]
>[  336.701860] [drm:drm_mode_addfb2] [FB:91]
>[  336.701967] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
>[  336.702223] [IGT] kms_addfb_basic: exiting, ret=0
>[  336.745109] Console: switching to colour frame buffer device 240x67
>[  336.879451] Console: switching to colour dummy device 80x25
>[  336.879752] [IGT] kms_addfb_basic: executing
>[  336.903254] [drm:drm_mode_addfb2] [FB:89]
>[  336.918758] [drm:drm_mode_addfb2] [FB:89]
>[  336.918872] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
>[  336.919146] [IGT] kms_addfb_basic: exiting, ret=0
>[  336.970091] Console: switching to colour frame buffer device 240x67
>[  337.114341] Console: switching to colour dummy device 80x25
>[  337.114737] [IGT] kms_addfb_basic: executing
>[  337.140278] [drm:drm_mode_addfb2] [FB:91]
>[  337.140526] [IGT] kms_addfb_basic: starting subtest no-handle
>[  337.140582] [drm:drm_internal_framebuffer_create] no buffer object handle for plane 0
>[  337.158174] [drm:drm_mode_addfb2] [FB:91]
>[  337.158344] [IGT] kms_addfb_basic: exiting, ret=0
>[  337.211697] Console: switching to colour frame buffer device 240x67
>[  337.353534] Console: switching to colour dummy device 80x25
>[  337.353851] [IGT] kms_addfb_basic: executing
>[  337.366539] [drm:drm_mode_addfb2] [FB:89]
>[  337.366925] [IGT] kms_addfb_basic: starting subtest size-max
>[  337.366987] [drm:drm_mode_addfb2] [FB:89]
>[  337.367015] [drm:drm_mode_addfb2] [FB:89]
>[  337.367041] [drm:drm_mode_addfb2] [FB:89]
>[  337.382445] [drm:drm_mode_addfb2] [FB:89]
>[  337.382731] [IGT] kms_addfb_basic: exiting, ret=0
>[  337.436510] Console: switching to colour frame buffer device 240x67
>[  337.576313] Console: switching to colour dummy device 80x25
>[  337.576532] [IGT] kms_addfb_basic: executing
>[  337.592397] [drm:drm_mode_addfb2] [FB:91]
>[  337.592769] [IGT] kms_addfb_basic: starting subtest small-bo
>[  337.592836] [drm:drm_mode_addfb2] [FB:91]
>[  337.608124] [drm:drm_mode_addfb2] [FB:91]
>[  337.608294] [IGT] kms_addfb_basic: exiting, ret=0
>[  337.661680] Console: switching to colour frame buffer device 240x67
>[  337.801305] Console: switching to colour dummy device 80x25
>[  337.801544] [IGT] kms_addfb_basic: executing
>[  337.826263] [drm:drm_mode_addfb2] [FB:89]
>[  337.842968] [IGT] kms_addfb_basic: starting subtest tile-pitch-mismatch
>[  337.843054] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  337.843183] [drm:drm_mode_addfb2] [FB:89]
>[  337.843300] [IGT] kms_addfb_basic: exiting, ret=0
>[  337.895078] Console: switching to colour frame buffer device 240x67
>[  338.027364] Console: switching to colour dummy device 80x25
>[  338.027613] [IGT] kms_addfb_basic: executing
>[  338.051256] [drm:drm_mode_addfb2] [FB:91]
>[  338.051840] [IGT] kms_addfb_basic: starting subtest too-high
>[  338.051926] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  338.051950] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  338.051972] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  338.068088] [drm:drm_mode_addfb2] [FB:91]
>[  338.068260] [IGT] kms_addfb_basic: exiting, ret=0
>[  338.119887] Console: switching to colour frame buffer device 240x67
>[  338.267465] Console: switching to colour dummy device 80x25
>[  338.267745] [IGT] kms_addfb_basic: executing
>[  338.291247] [drm:drm_mode_addfb2] [FB:89]
>[  338.291720] [IGT] kms_addfb_basic: starting subtest too-wide
>[  338.291785] [drm:drm_internal_framebuffer_create] bad pitch 4096 for plane 0
>[  338.291796] [drm:drm_internal_framebuffer_create] bad pitch 2048 for plane 0
>[  338.291806] [drm:drm_internal_framebuffer_create] bad pitch 2048 for plane 0
>[  338.307584] [drm:drm_mode_addfb2] [FB:89]
>[  338.307918] [IGT] kms_addfb_basic: exiting, ret=0
>[  338.361913] Console: switching to colour frame buffer device 240x67
>[  338.508006] Console: switching to colour dummy device 80x25
>[  338.508234] [IGT] kms_addfb_basic: executing
>[  338.532060] [drm:drm_mode_addfb2] [FB:91]
>[  338.532157] [IGT] kms_addfb_basic: starting subtest unused-handle
>[  338.532203] [drm:drm_internal_framebuffer_create] buffer object handle for unused plane 1
>[  338.544815] [drm:drm_mode_addfb2] [FB:91]
>[  338.544985] [IGT] kms_addfb_basic: exiting, ret=0
>[  338.595147] Console: switching to colour frame buffer device 240x67
>[  338.731602] Console: switching to colour dummy device 80x25
>[  338.731924] [IGT] kms_addfb_basic: executing
>[  338.756224] [drm:drm_mode_addfb2] [FB:89]
>[  338.756356] [IGT] kms_addfb_basic: starting subtest unused-modifier
>[  338.756419] [drm:drm_internal_framebuffer_create] non-zero modifier for unused plane 1
>[  338.772322] [drm:drm_mode_addfb2] [FB:89]
>[  338.772492] [IGT] kms_addfb_basic: exiting, ret=0
>[  338.828488] Console: switching to colour frame buffer device 240x67
>[  338.957076] Console: switching to colour dummy device 80x25
>[  338.957325] [IGT] kms_addfb_basic: executing
>[  338.973556] [drm:drm_mode_addfb2] [FB:91]
>[  338.973742] [IGT] kms_addfb_basic: starting subtest unused-offsets
>[  338.973799] [drm:drm_internal_framebuffer_create] non-zero offset for unused plane 1
>[  338.988890] [drm:drm_mode_addfb2] [FB:91]
>[  338.989060] [IGT] kms_addfb_basic: exiting, ret=0
>[  339.036519] Console: switching to colour frame buffer device 240x67
>[  339.176069] Console: switching to colour dummy device 80x25
>[  339.176296] [IGT] kms_addfb_basic: executing
>[  339.201303] [drm:drm_mode_addfb2] [FB:89]
>[  339.201443] [IGT] kms_addfb_basic: starting subtest unused-pitches
>[  339.201507] [drm:drm_internal_framebuffer_create] non-zero pitch for unused plane 1
>[  339.217691] [drm:drm_mode_addfb2] [FB:89]
>[  339.217864] [IGT] kms_addfb_basic: exiting, ret=0
>[  339.270031] Console: switching to colour frame buffer device 240x67
>[  339.401738] Console: switching to colour dummy device 80x25
>[  339.401979] [IGT] kms_busy: executing
>[  339.439277] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  339.439326] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  339.439390] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  339.439425] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  339.439457] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  339.439492] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  339.439625] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  339.439717] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  339.440830] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  339.442022] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  339.442036] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  339.442040] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  339.442760] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  339.442807] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  339.443373] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  339.443782] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  339.444205] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  339.444249] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  339.452939] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.461687] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.470499] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.479239] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.487995] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.496739] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.505565] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.514559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.523547] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.532445] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.541362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.550323] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.559324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.568315] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.577320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.586297] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.595312] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.604266] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.613190] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.622123] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.631050] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.639980] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.648923] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.657885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.666830] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.675863] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.684817] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.693822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.702832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.711843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.720832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.729843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.729891] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  339.729906] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  339.731046] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  339.731156] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  339.811117] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  339.815313] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  339.815426] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  339.815439] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  339.816765] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  339.816777] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  339.816786] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  339.816792] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  339.818781] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  339.818797] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  339.818807] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  339.818816] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  339.818825] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  339.818835] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  339.818844] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  339.818854] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  339.818863] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  339.818872] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  339.818882] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  339.818891] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  339.818901] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  339.818910] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  339.818919] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  339.818928] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  339.818938] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  339.818947] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  339.818956] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  339.818965] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  339.818974] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  339.818984] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  339.818993] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  339.819002] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  339.822152] [IGT] kms_busy: starting subtest basic-flip-default-A
>[  339.837327] [drm:drm_mode_addfb2] [FB:71]
>[  340.036548] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  340.036596] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  340.062135] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  340.062317] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  340.062384] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  340.062438] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  340.063258] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  340.268926] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  340.269408] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  340.281800] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  340.281918] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  340.282013] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  340.332268] [drm:wait_panel_status [i915]] Wait complete
>[  340.332416] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  340.332683] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  340.333264] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  340.333424] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  340.333676] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  340.334356] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  340.334451] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  340.334539] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  340.334876] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  340.335456] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  340.337734] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  340.338022] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  340.338300] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  340.342574] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  340.342619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  340.342660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  340.342773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  340.342814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  340.342855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  340.342896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  340.342942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  340.342983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  340.343024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  340.343065] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  340.343112] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  340.343157] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  340.343202] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  340.343327] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  340.343368] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  340.344644] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  340.344742] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  340.788971] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  340.903418] [drm:wait_panel_status [i915]] Wait complete
>[  340.903531] [drm:edp_panel_on [i915]] Wait for panel power on
>[  340.903648] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  341.012079] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  341.012187] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  341.012286] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  341.012489] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  341.104031] [drm:wait_panel_status [i915]] Wait complete
>[  341.104276] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  341.104397] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  341.106251] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.106351] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.106456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.107696] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.107873] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.109438] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.110449] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  341.113082] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  341.113235] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  341.113331] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  341.113439] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  341.113573] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  341.113669] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  341.114054] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  341.114154] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  341.146903] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  341.146967] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  341.147165] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  341.147283] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  341.147401] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  341.147602] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  341.147994] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  341.148522] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  341.164149] [drm:drm_mode_addfb2] [FB:89]
>[  341.872094] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  341.872348] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  341.873166] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  342.076879] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  342.077017] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  342.081696] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  342.081888] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  342.081994] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  342.132151] [drm:wait_panel_status [i915]] Wait complete
>[  342.132257] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  342.132366] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  342.132552] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  342.132951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  342.133061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  342.133156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  342.133248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  342.133340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  342.133432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  342.133531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  342.133622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  342.134258] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  342.134353] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  342.134446] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  342.134671] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  342.135253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  342.135355] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  342.135474] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  342.135581] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  342.135687] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  342.135894] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  342.136036] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  342.136168] [drm:intel_power_well_disable [i915]] disabling DC off
>[  342.136270] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  342.136360] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  342.137570] [drm:intel_power_well_disable [i915]] disabling always-on
>[  342.138797] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  342.139834] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  342.140993] [IGT] kms_busy: exiting, ret=0
>[  342.178809] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  342.178850] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  342.178896] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  342.178942] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  342.178980] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  342.179022] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.179064] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  342.179105] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  342.179144] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  342.179182] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  342.179220] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.179229] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  342.179266] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.179270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  342.179310] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  342.179348] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  342.179387] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  342.179426] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.179464] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.179508] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  342.179546] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.179588] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  342.179628] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  342.179717] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  342.179758] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  342.179806] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  342.179846] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  342.179891] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  342.179929] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  342.179970] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.180010] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  342.180049] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  342.180087] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  342.180125] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.180129] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  342.180166] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.180170] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  342.180210] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  342.180248] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  342.180288] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  342.180326] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.180364] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.180405] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  342.180443] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.180483] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  342.180523] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  342.180563] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  342.180601] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  342.180644] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  342.180713] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  342.180753] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  342.180798] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  342.180837] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  342.181028] [drm:intel_power_well_enable [i915]] enabling always-on
>[  342.181061] [drm:intel_power_well_enable [i915]] enabling DC off
>[  342.181408] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  342.181470] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  342.182467] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  342.182518] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  342.182808] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  342.183069] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  342.186888] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  342.186943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  342.186994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  342.187056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  342.187108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  342.187159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  342.187210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  342.187261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  342.187312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  342.187363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  342.187414] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  342.187469] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  342.187522] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  342.187646] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  342.187737] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  342.189157] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  342.189230] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  342.588952] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  342.702363] [drm:wait_panel_status [i915]] Wait complete
>[  342.702481] [drm:edp_panel_on [i915]] Wait for panel power on
>[  342.702600] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  342.810988] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  342.811089] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  342.811188] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  342.811373] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  342.903193] [drm:wait_panel_status [i915]] Wait complete
>[  342.903636] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  342.903864] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  342.906946] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.907043] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.907148] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.908501] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.908597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  342.910240] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.910688] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  342.914120] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  342.914288] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  342.914384] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  342.914551] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  342.914690] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  342.914845] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  342.915263] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  342.915361] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  342.915814] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  342.915912] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  342.916681] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  342.918095] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  342.918627] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  342.918682] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  342.918759] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  342.918791] [drm:hsw_audio_config_update [i915]] using automatic N
>[  342.935759] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  342.935834] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  342.936071] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  342.936331] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  342.936403] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  342.936631] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  342.937177] Console: switching to colour frame buffer device 240x67
>[  343.081889] Console: switching to colour dummy device 80x25
>[  343.082114] [IGT] kms_busy: executing
>[  343.119981] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  343.120028] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  343.120066] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  343.120100] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  343.120133] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  343.120167] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  343.120744] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  343.121206] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  343.121218] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  343.121222] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  343.121770] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  343.121817] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  343.122356] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  343.122734] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  343.123133] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  343.123178] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  343.131835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.140418] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.149033] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.157656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.166287] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.175027] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.183750] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.192464] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.201184] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.209919] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.218645] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.227486] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.236225] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.244976] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.253727] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.262453] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.271199] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.279959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.288691] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.297475] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.306236] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.314963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.323753] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.332488] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.341235] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.349976] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.358720] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.367469] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.376201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.384934] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.393755] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.402524] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  343.402556] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  343.402566] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  343.403681] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  343.403755] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  343.483576] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  343.487767] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  343.487863] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  343.487871] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  343.488259] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  343.488265] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  343.488270] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  343.488274] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  343.488494] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  343.488501] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  343.488507] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  343.488512] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  343.488518] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  343.488523] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  343.488528] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  343.488534] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  343.488539] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  343.488544] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  343.488550] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  343.488555] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  343.488561] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  343.488566] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  343.488571] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  343.488576] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  343.488582] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  343.488587] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  343.488592] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  343.488597] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  343.488603] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  343.488608] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  343.488613] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  343.488618] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  343.490106] [IGT] kms_busy: starting subtest basic-flip-default-B
>[  343.507775] [drm:drm_mode_addfb2] [FB:70]
>[  343.579302] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  343.579412] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  343.579623] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  343.788955] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  343.789083] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  343.799534] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  343.799637] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  343.800409] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  343.850159] [drm:wait_panel_status [i915]] Wait complete
>[  343.850279] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  343.850400] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  343.850610] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  343.851156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  343.851283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  343.851396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  343.851500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  343.851603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  343.851705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  343.852057] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  343.852163] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  343.852267] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  343.852473] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  343.852579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  343.852680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  343.853084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  343.853185] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  343.853305] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  343.853413] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  343.853527] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  343.868998] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  343.869146] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  343.869940] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  343.869990] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  343.870281] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  343.870386] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.870497] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  343.870612] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  343.870708] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  343.870910] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.871015] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  343.871122] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  343.871227] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  343.871334] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  343.871437] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.871461] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  343.871558] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.871580] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  343.871688] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  343.871842] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  343.871944] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  343.872051] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.872157] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.872271] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  343.872373] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.872493] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  343.872598] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  343.872705] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  343.872860] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  343.872966] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  343.873113] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  343.873235] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  343.873337] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  343.874141] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  343.876102] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  343.876232] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  343.876429] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  343.886775] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  343.886886] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  343.886939] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  343.891095] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  343.891138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  343.891180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  343.891228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  343.891270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  343.891312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  343.891353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  343.891399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  343.891441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  343.891482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  343.891523] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  343.891569] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  343.891613] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  343.891655] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  343.891848] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  343.891913] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  343.892332] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  343.892399] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  344.308858] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  344.401893] [drm:wait_panel_status [i915]] Wait complete
>[  344.401993] [drm:edp_panel_on [i915]] Wait for panel power on
>[  344.402098] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  344.510466] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  344.510570] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  344.510670] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  344.510873] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  344.603345] [drm:wait_panel_status [i915]] Wait complete
>[  344.603489] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  344.603609] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  344.605485] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.605582] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.605687] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.606966] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.607067] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  344.608815] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.609228] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  344.612036] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  344.612191] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  344.612287] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  344.612396] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  344.612529] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  344.612626] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  344.629064] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  344.629336] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  344.629489] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  344.630292] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  344.645762] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  344.662754] [drm:drm_mode_addfb2] [FB:91]
>[  345.369054] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  345.370013] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  345.370214] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  345.370513] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  345.572892] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  345.573030] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  345.579897] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  345.580012] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  345.580130] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  345.631099] [drm:wait_panel_status [i915]] Wait complete
>[  345.631229] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  345.631430] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  345.631662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  345.631946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  345.632055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  345.632162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  345.632264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  345.632350] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  345.632451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  345.632552] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  345.632654] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  345.632756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  345.632923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  345.633027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  345.633130] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  345.633250] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  345.633362] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  345.633473] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  345.633619] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  345.633820] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  345.633925] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  345.634072] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  345.634182] [drm:intel_power_well_disable [i915]] disabling DC off
>[  345.634284] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  345.634378] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  345.635044] [drm:intel_power_well_disable [i915]] disabling always-on
>[  345.635726] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  345.636183] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  345.638067] [IGT] kms_busy: exiting, ret=0
>[  345.667560] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  345.667595] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.667632] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  345.667730] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  345.667764] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  345.667801] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.667838] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  345.667872] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  345.667905] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  345.667937] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  345.667968] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.667976] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  345.668008] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.668011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  345.668044] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  345.668076] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  345.668109] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  345.668141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.668172] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.668210] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  345.668242] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.668277] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  345.668311] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  345.668345] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  345.668379] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  345.668420] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  345.668453] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.668490] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  345.668522] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  345.668556] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.668590] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  345.668622] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  345.668653] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  345.668706] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.668710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  345.668741] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.668744] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  345.668777] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  345.668809] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  345.668842] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  345.668874] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.668906] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.668941] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  345.668973] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.669007] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  345.669041] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  345.669074] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  345.669108] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  345.669145] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  345.669188] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  345.669222] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  345.669260] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  345.669293] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  345.669455] [drm:intel_power_well_enable [i915]] enabling always-on
>[  345.669483] [drm:intel_power_well_enable [i915]] enabling DC off
>[  345.669790] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  345.669844] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  345.670586] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  345.670621] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  345.670779] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  345.670941] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  345.674757] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  345.674794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  345.674829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  345.674871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  345.674906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  345.674941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  345.674976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  345.675011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  345.675045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  345.675080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  345.675114] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  345.675151] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  345.675187] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  345.675256] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  345.675288] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  345.676040] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  345.676077] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  346.084891] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  346.202655] [drm:wait_panel_status [i915]] Wait complete
>[  346.202862] [drm:edp_panel_on [i915]] Wait for panel power on
>[  346.202982] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  346.311365] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  346.311466] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  346.311564] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  346.311862] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  346.403994] [drm:wait_panel_status [i915]] Wait complete
>[  346.404137] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  346.404259] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  346.406279] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.406376] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.406480] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.407809] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.407905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.409487] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.409938] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  346.413258] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  346.413413] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  346.413510] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  346.413618] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  346.413822] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  346.413911] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  346.413960] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  346.413993] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  346.414163] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  346.414196] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  346.414488] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  346.415739] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  346.416269] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  346.416304] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  346.416358] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  346.416390] [drm:hsw_audio_config_update [i915]] using automatic N
>[  346.433353] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  346.433428] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  346.433665] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  346.433978] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  346.434051] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  346.434277] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  346.434821] Console: switching to colour frame buffer device 240x67
>[  346.585717] Console: switching to colour dummy device 80x25
>[  346.585939] [IGT] kms_busy: executing
>[  346.622975] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  346.623021] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  346.623060] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  346.623094] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  346.623127] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  346.623159] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  346.623848] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  346.624298] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  346.624310] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  346.624314] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  346.624924] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  346.624969] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  346.625494] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  346.625939] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  346.626320] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  346.626364] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  346.635014] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.643753] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.652447] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.661311] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.670071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.678831] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.687681] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.696593] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.705578] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.714598] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.723726] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.732871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.741854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.750843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.759839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.768875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.777834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.786871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.795882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.804859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.813820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.822844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.831866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.840813] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.849832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.858865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.867823] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.876835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.885861] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.894817] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.903856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.912837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  346.912883] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  346.912900] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  346.914422] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  346.914542] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  346.995317] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  346.999493] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  346.999605] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  346.999618] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  347.000400] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  347.000411] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  347.000419] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  347.000426] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  347.000919] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  347.000932] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  347.000942] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  347.000952] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  347.000961] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  347.000971] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  347.000981] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  347.000997] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  347.001006] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  347.001015] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  347.001025] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  347.001034] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  347.001044] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  347.001054] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  347.001063] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  347.001076] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  347.001085] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  347.001097] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  347.001107] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  347.001116] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  347.001125] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  347.001134] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  347.001144] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  347.001153] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  347.003350] [IGT] kms_busy: starting subtest basic-flip-default-C
>[  347.019015] [drm:drm_mode_addfb2] [FB:89]
>[  347.090464] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  347.090572] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  347.090835] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  347.292846] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  347.292937] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  347.297505] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  347.297574] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  347.297649] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  347.347843] [drm:wait_panel_status [i915]] Wait complete
>[  347.347919] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  347.348001] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  347.348153] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  347.348314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  347.348390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  347.348465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  347.348533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  347.348599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  347.348666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  347.348861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  347.348954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  347.349041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  347.349130] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  347.349232] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  347.349327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  347.349420] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  347.349870] [drm:intel_pipe_update_end [i915]] *ERROR* Atomic update failure on pipe B (start=56 end=57) time 112 us, min 1073, max 1079, scanline start 1072, end 1081
>[  347.350031] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  347.350114] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  347.350195] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  347.350327] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  347.366602] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  347.366972] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  347.367581] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  347.367949] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  347.368265] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  347.368379] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  347.368557] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  347.383255] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  347.383441] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  347.383645] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  347.388063] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  347.388170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  347.388282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  347.388394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  347.388496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  347.388597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  347.388698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  347.388934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  347.389043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  347.389150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  347.389256] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  347.389373] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  347.389484] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  347.389592] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  347.389817] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  347.389894] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  347.389997] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  347.390104] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  347.390181] [drm:intel_power_well_disable [i915]] disabling DC off
>[  347.390256] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  347.390323] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  347.390955] [drm:intel_power_well_disable [i915]] disabling always-on
>[  347.391933] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  347.391972] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  347.392185] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  347.392258] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.392338] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  347.392419] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  347.392489] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  347.392564] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.392637] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  347.392785] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  347.392861] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  347.392938] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  347.393015] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.393031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  347.393102] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.393118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  347.393192] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  347.393272] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  347.393350] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  347.393430] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.393505] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.393586] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  347.393663] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.393778] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  347.393857] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  347.393936] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  347.394017] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  347.394104] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  347.394185] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  347.394836] [drm:intel_power_well_enable [i915]] enabling always-on
>[  347.394887] [drm:intel_power_well_enable [i915]] enabling DC off
>[  347.395189] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  347.395270] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  347.395327] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  347.395559] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  347.396648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  347.396738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  347.396801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  347.396859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  347.396915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  347.396974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  347.397035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  347.397093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  347.397152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  347.397210] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  347.397273] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  347.397333] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  347.397430] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  347.397487] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  347.398543] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  347.398606] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  347.804942] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  347.902685] [drm:wait_panel_status [i915]] Wait complete
>[  347.902885] [drm:edp_panel_on [i915]] Wait for panel power on
>[  347.903003] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  348.011371] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  348.011477] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  348.011577] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  348.011836] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  348.103286] [drm:wait_panel_status [i915]] Wait complete
>[  348.103438] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  348.103560] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  348.105298] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.105400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.105504] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.106715] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.106868] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.108456] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.108938] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  348.111569] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.111721] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  348.111912] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  348.112023] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  348.112163] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  348.112262] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  348.128694] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  348.128928] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  348.129259] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  348.162015] [drm:drm_mode_addfb2] [FB:91]
>[  348.870399] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  348.871204] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  348.871957] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  348.872198] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  348.872569] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  349.076895] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  349.077046] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  349.079706] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  349.079933] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  349.080052] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  349.131807] [drm:wait_panel_status [i915]] Wait complete
>[  349.131939] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  349.132141] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  349.132348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  349.132447] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  349.132547] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  349.132646] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  349.132829] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  349.132950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  349.133065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  349.133170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  349.133283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  349.133389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  349.133505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  349.133613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  349.133722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  349.133884] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  349.134008] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  349.134120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  349.134238] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  349.134385] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  349.134526] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  349.134630] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  349.135004] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  349.135116] [drm:intel_power_well_disable [i915]] disabling DC off
>[  349.135220] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  349.135313] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  349.136013] [drm:intel_power_well_disable [i915]] disabling always-on
>[  349.137751] [IGT] kms_busy: exiting, ret=0
>[  349.169568] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  349.169602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  349.169639] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  349.169730] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  349.169762] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  349.169800] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.169837] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  349.169871] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  349.169904] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  349.169936] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  349.169967] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.169975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  349.170007] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.170010] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  349.170043] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  349.170075] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  349.170108] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  349.170140] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.170172] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.170209] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  349.170241] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.170276] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  349.170310] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  349.170344] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  349.170378] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  349.170419] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  349.170452] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  349.170489] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  349.170520] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  349.170554] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.170588] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  349.170620] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  349.170652] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  349.170704] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.170708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  349.170739] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.170743] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  349.170776] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  349.170807] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  349.170841] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  349.170873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.170905] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.170939] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  349.170971] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.171004] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  349.171038] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  349.171072] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  349.171104] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  349.171142] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  349.171184] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  349.171219] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  349.171257] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  349.171290] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  349.171453] [drm:intel_power_well_enable [i915]] enabling always-on
>[  349.171481] [drm:intel_power_well_enable [i915]] enabling DC off
>[  349.171788] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  349.171842] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  349.172578] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  349.172613] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  349.172707] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  349.172887] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  349.176774] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  349.176816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  349.176858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  349.176908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  349.176949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  349.176990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  349.177032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  349.177073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  349.177114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  349.177155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  349.177196] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  349.177240] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  349.177283] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  349.177361] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  349.177402] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  349.178212] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  349.178257] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  349.588776] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  349.702888] [drm:wait_panel_status [i915]] Wait complete
>[  349.702958] [drm:edp_panel_on [i915]] Wait for panel power on
>[  349.703032] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  349.811478] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  349.811560] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  349.811639] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  349.811789] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  349.903281] [drm:wait_panel_status [i915]] Wait complete
>[  349.903396] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  349.903494] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  349.905180] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  349.905258] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.905343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  349.906584] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  349.906662] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  349.908122] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  349.908505] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  349.911236] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  349.911362] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  349.911440] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  349.911527] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  349.911639] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  349.911767] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  349.911877] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  349.911954] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  349.912285] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  349.912364] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  349.912892] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  349.915218] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  349.915773] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  349.915807] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  349.915862] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  349.915894] [drm:hsw_audio_config_update [i915]] using automatic N
>[  349.932907] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  349.932983] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  349.933229] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  349.933493] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  349.933570] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  349.933844] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  349.934406] Console: switching to colour frame buffer device 240x67
>[  350.092519] Console: switching to colour dummy device 80x25
>[  350.093070] [IGT] kms_cursor_legacy: executing
>[  350.132217] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  350.132264] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  350.132305] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  350.132339] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  350.132371] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  350.132406] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  350.133155] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  350.133621] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  350.133698] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  350.133702] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  350.134199] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  350.134246] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  350.134836] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  350.135212] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  350.135600] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  350.135641] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  350.144394] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.153012] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.161718] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.170444] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.179181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.187927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.196765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.205580] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.214516] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.223379] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.232225] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.241090] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.250073] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.259084] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.268034] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.276980] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.285929] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.294906] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.303901] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.312936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.321941] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.330943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.339959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.348964] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.357972] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.366977] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.375987] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.385001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.394020] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.403124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.412136] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.421146] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.421206] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  350.421223] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  350.422634] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  350.422808] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  350.503204] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  350.507389] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  350.507506] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  350.507519] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  350.508346] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  350.508357] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  350.508366] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  350.508372] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  350.508857] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  350.508874] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  350.508884] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  350.508893] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  350.508903] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  350.508913] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  350.508925] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  350.508935] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  350.508944] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  350.508954] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  350.508966] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  350.508976] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  350.508986] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  350.508995] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  350.509007] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  350.509016] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  350.509026] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  350.509035] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  350.509044] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  350.509053] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  350.509063] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  350.509076] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  350.509089] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  350.509098] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  350.510991] [IGT] kms_cursor_legacy: starting subtest basic-busy-flip-before-cursor-atomic
>[  350.511355] [IGT] kms_cursor_legacy: exiting, ret=77
>[  350.545391] Console: switching to colour frame buffer device 240x67
>[  350.696409] Console: switching to colour dummy device 80x25
>[  350.696705] [IGT] kms_cursor_legacy: executing
>[  350.732732] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  350.732779] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  350.732819] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  350.732854] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  350.732886] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  350.732920] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  350.733438] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  350.733947] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  350.733960] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  350.733964] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  350.734465] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  350.734511] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  350.735055] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  350.735420] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  350.735897] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  350.735941] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  350.744602] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.753387] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.762097] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.770896] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.779658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.788463] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.797369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.806261] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.815132] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.824056] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.833107] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.842079] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.851066] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.860109] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.869124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.878111] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.887090] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.896071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.905056] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.914138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.923121] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.932108] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.941087] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.950062] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.959124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.968093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.977081] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.986076] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  350.995089] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  351.004074] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  351.013053] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  351.022097] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  351.022145] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  351.022161] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  351.023433] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  351.023551] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  351.104760] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  351.108952] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  351.109069] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  351.109082] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  351.109874] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  351.109884] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  351.109894] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  351.109901] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  351.110286] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  351.110299] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  351.110309] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  351.110318] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  351.110327] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  351.110337] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  351.110346] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  351.110356] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  351.110365] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  351.110375] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  351.110384] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  351.110394] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  351.110403] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  351.110412] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  351.110422] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  351.110431] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  351.110440] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  351.110450] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  351.110462] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  351.110472] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  351.110481] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  351.110490] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  351.110499] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  351.110509] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  351.112585] [IGT] kms_cursor_legacy: starting subtest basic-busy-flip-before-cursor-legacy
>[  351.114443] [drm:drm_mode_addfb2] [FB:70]
>[  351.196479] [drm:drm_mode_addfb2] [FB:91]
>[  351.198487] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  351.198507] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  351.228322] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  351.228516] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  351.228586] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  351.228643] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  351.228997] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  351.436843] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  351.436931] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  351.445670] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  351.445834] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  351.445921] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  351.495997] [drm:wait_panel_status [i915]] Wait complete
>[  351.496084] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  351.496171] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  351.496335] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  351.496440] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  351.496529] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  351.496679] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  351.498256] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  351.498352] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  351.498440] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  351.498588] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  351.501293] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  351.501479] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  351.501687] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  351.505862] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  351.505958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  351.506047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  351.506151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  351.506242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  351.506332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  351.506422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  351.506521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  351.506611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  351.506699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  351.506906] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  351.507012] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  351.507113] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  351.507212] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  351.507384] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  351.507475] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  351.507902] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  351.507998] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  351.948885] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  352.002690] [drm:wait_panel_status [i915]] Wait complete
>[  352.002879] [drm:edp_panel_on [i915]] Wait for panel power on
>[  352.002997] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  352.111377] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  352.111484] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  352.111584] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  352.111837] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  352.204334] [drm:wait_panel_status [i915]] Wait complete
>[  352.204476] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  352.204598] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  352.206925] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.207028] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.207132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.208835] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.208937] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  352.210961] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.211373] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  352.214676] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.214889] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  352.214962] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  352.215001] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  352.215054] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  352.215088] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  352.215137] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.215169] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.248441] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  352.248527] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  352.249194] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  352.249350] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  352.249407] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.249482] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  352.249563] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  352.250282] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  352.304213] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  352.304415] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  352.304868] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  352.508876] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  352.509016] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.515855] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  352.515957] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  352.516063] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  352.566126] [drm:wait_panel_status [i915]] Wait complete
>[  352.566230] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.566339] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  352.566525] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  352.566857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  352.566964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  352.567061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  352.567155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  352.567246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  352.567340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  352.567435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  352.567529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  352.567620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  352.567777] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  352.567880] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  352.567976] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  352.568076] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  352.568210] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  352.568339] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  352.568433] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  352.568525] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  352.568647] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  352.568751] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  352.568869] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.568959] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  352.569038] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  352.569645] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.571420] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  352.572358] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  352.573602] [IGT] kms_cursor_legacy: exiting, ret=0
>[  352.599861] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  352.599909] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.599960] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  352.600013] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  352.600058] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  352.600106] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.600153] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  352.600198] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  352.600244] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  352.600289] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  352.600334] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.600342] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  352.600386] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.600391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  352.600437] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  352.600483] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  352.600528] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.600574] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.600619] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.600667] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  352.600740] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.600797] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  352.600830] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  352.600862] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  352.600894] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  352.600933] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  352.600966] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.601000] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  352.601032] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  352.601065] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.601097] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  352.601129] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  352.601161] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  352.601192] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.601196] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  352.601227] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.601231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  352.601263] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  352.601295] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  352.601329] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.601361] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.601393] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.601430] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  352.601462] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.601497] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  352.601531] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  352.601565] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  352.601598] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  352.601633] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  352.601736] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  352.601769] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  352.601808] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  352.601841] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  352.602004] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.602031] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.602316] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  352.602369] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  352.603145] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  352.603180] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  352.603236] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  352.603411] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  352.606736] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  352.606771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  352.606804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  352.606846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  352.606881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  352.606916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  352.606951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  352.606985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  352.607020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  352.607055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  352.607089] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  352.607126] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  352.607162] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  352.607230] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  352.607264] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  352.607473] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  352.607508] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  353.020847] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  353.102994] [drm:wait_panel_status [i915]] Wait complete
>[  353.103058] [drm:edp_panel_on [i915]] Wait for panel power on
>[  353.103128] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  353.211516] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  353.211576] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  353.211633] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  353.211814] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  353.304083] [drm:wait_panel_status [i915]] Wait complete
>[  353.304200] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  353.304300] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  353.305951] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  353.306027] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.306111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  353.307209] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  353.307286] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  353.308689] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  353.309142] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  353.311855] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  353.311991] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  353.312069] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  353.312156] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  353.312267] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  353.312343] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  353.312449] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  353.312529] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  353.312902] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  353.312980] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  353.313437] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  353.316009] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  353.316539] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  353.316573] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  353.316627] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  353.316679] [drm:hsw_audio_config_update [i915]] using automatic N
>[  353.333631] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  353.333763] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  353.334016] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  353.334285] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  353.334361] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  353.334596] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  353.335182] Console: switching to colour frame buffer device 240x67
>[  353.499106] Console: switching to colour dummy device 80x25
>[  353.499327] [IGT] kms_cursor_legacy: executing
>[  353.522620] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  353.522673] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  353.522763] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  353.522806] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  353.522850] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  353.522890] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  353.523484] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  353.524145] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  353.524163] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  353.524170] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  353.524982] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  353.525028] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  353.525608] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  353.525990] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  353.526440] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  353.526483] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  353.535079] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.543770] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.552481] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.561233] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.570006] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.578806] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.587576] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.596503] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.605400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.614347] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.623267] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.632185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.641143] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.650125] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.659129] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.668126] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.677111] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.686104] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.695103] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.704090] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.713078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.722050] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.731101] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.740094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.749089] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.758074] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.767051] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.776151] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.785137] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.794126] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.803113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.812077] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  353.812125] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  353.812141] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  353.813412] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  353.813530] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  353.894768] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  353.898954] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  353.899069] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  353.899082] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  353.899878] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  353.899891] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  353.899900] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  353.899906] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  353.900301] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  353.900314] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  353.900324] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  353.900336] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  353.900346] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  353.900355] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  353.900368] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  353.900378] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  353.900387] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  353.900396] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  353.900406] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  353.900415] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  353.900428] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  353.900438] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  353.900451] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  353.900460] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  353.900469] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  353.900478] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  353.900488] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  353.900497] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  353.900507] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  353.900516] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  353.900533] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  353.900542] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  353.902507] [IGT] kms_cursor_legacy: starting subtest basic-flip-after-cursor-atomic
>[  353.903098] [IGT] kms_cursor_legacy: exiting, ret=77
>[  353.933948] Console: switching to colour frame buffer device 240x67
>[  354.100890] Console: switching to colour dummy device 80x25
>[  354.101117] [IGT] kms_cursor_legacy: executing
>[  354.126448] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  354.126507] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  354.126560] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  354.126608] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  354.126654] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  354.127018] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  354.127543] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  354.128051] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  354.128063] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  354.128068] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  354.128579] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  354.128624] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  354.129227] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  354.129602] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  354.130029] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  354.130071] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  354.138761] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.147504] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.156219] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.164955] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.173670] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.182438] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.191180] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.199909] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.208635] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.217518] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.226373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.235258] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.244092] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.252988] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.261822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.270760] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.279586] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.288518] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.297353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.306253] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.315084] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.324071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.333059] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.342060] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.351057] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.360052] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.369047] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.378036] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.386974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.395907] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.404837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.413838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  354.413879] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  354.413893] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  354.415029] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  354.415131] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  354.496322] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  354.499886] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  354.500003] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  354.500016] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  354.500817] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  354.500827] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  354.500837] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  354.500843] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  354.501227] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  354.501240] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  354.501251] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  354.501260] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  354.501273] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  354.501282] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  354.501291] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  354.501301] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  354.501310] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  354.501320] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.501330] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  354.501347] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  354.501357] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  354.501366] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  354.501376] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  354.501385] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  354.501394] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  354.501404] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.501414] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  354.501427] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  354.501436] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.501446] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  354.501458] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  354.501467] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  354.503420] [IGT] kms_cursor_legacy: starting subtest basic-flip-after-cursor-legacy
>[  354.505234] [drm:drm_mode_addfb2] [FB:71]
>[  354.586537] [drm:drm_mode_addfb2] [FB:91]
>[  354.588491] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  354.588511] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  354.612295] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  354.612469] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  354.612533] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  354.612586] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  354.612883] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  354.820888] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  354.821003] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  354.829802] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  354.829886] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  354.829972] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  354.880105] [drm:wait_panel_status [i915]] Wait complete
>[  354.880198] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  354.880295] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  354.880469] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  354.880589] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  354.880687] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  354.881037] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  354.882351] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  354.882451] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  354.882539] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  354.882714] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  354.884863] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  354.885045] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  354.885253] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  354.888798] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  354.888893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  354.888983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  354.889085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  354.889175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  354.889265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  354.889355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  354.889454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  354.889543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  354.889631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  354.889811] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  354.889921] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  354.890027] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  354.890130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  354.890301] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  354.890395] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  354.890946] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  354.891043] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  355.332908] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  355.403351] [drm:wait_panel_status [i915]] Wait complete
>[  355.403462] [drm:edp_panel_on [i915]] Wait for panel power on
>[  355.403577] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  355.511969] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  355.512077] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  355.512176] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  355.512370] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  355.604470] [drm:wait_panel_status [i915]] Wait complete
>[  355.604611] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  355.604876] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  355.606651] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.606815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.606921] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.608597] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.608698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  355.610508] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.611067] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  355.613600] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  355.613843] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  355.613945] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  355.614053] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  355.614189] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  355.614287] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  355.614422] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  355.614523] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  355.647428] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  355.647550] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  355.648136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  355.648308] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  355.648392] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  355.648505] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  355.648628] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  355.649365] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  355.705333] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  355.705589] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  355.706294] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  355.908883] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  355.909040] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  355.915906] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  355.916021] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  355.916137] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  355.967950] [drm:wait_panel_status [i915]] Wait complete
>[  355.968066] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  355.968186] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  355.968389] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  355.968488] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  355.968589] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  355.968688] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  355.968893] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  355.969661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  355.969839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  355.969962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  355.970066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  355.970176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  355.970279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  355.970395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  355.970502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  355.970608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  355.970710] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  355.971083] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  355.971195] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  355.971309] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  355.971452] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  355.971599] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  355.971978] [drm:intel_power_well_disable [i915]] disabling DC off
>[  355.972082] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  355.972170] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  355.973351] [drm:intel_power_well_disable [i915]] disabling always-on
>[  355.974242] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  355.975026] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  355.975954] [IGT] kms_cursor_legacy: exiting, ret=0
>[  356.007976] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  356.008031] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  356.008088] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  356.008148] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  356.008199] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  356.008253] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  356.008310] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  356.008363] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  356.008416] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  356.008467] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  356.008517] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  356.008527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  356.008578] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  356.008583] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  356.008636] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  356.008720] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  356.008773] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  356.008825] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  356.008875] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  356.008934] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  356.008985] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  356.009040] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  356.009093] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  356.009146] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  356.009198] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  356.009263] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  356.009315] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  356.009372] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  356.009422] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  356.009476] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  356.009529] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  356.009581] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  356.009631] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  356.009756] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  356.009764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  356.009815] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  356.009820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  356.009872] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  356.009923] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  356.009975] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  356.010027] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  356.010078] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  356.010133] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  356.010184] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  356.010237] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  356.010290] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  356.010343] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  356.010396] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  356.010453] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  356.010517] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  356.010571] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  356.010631] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  356.010717] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  356.010942] [drm:intel_power_well_enable [i915]] enabling always-on
>[  356.010986] [drm:intel_power_well_enable [i915]] enabling DC off
>[  356.011287] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  356.011368] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  356.011523] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  356.011574] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  356.011656] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  356.011939] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  356.015777] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  356.015833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  356.015887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  356.015950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  356.016005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  356.016059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  356.016113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  356.016168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  356.016222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  356.016276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  356.016330] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  356.016388] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  356.016446] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  356.016540] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  356.016592] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  356.016908] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  356.016964] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  356.420858] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  356.501617] [drm:wait_panel_status [i915]] Wait complete
>[  356.501676] [drm:edp_panel_on [i915]] Wait for panel power on
>[  356.501793] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  356.610216] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  356.610272] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  356.610325] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  356.610432] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  356.702529] [drm:wait_panel_status [i915]] Wait complete
>[  356.702610] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  356.702677] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  356.704236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  356.704287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  356.704344] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  356.705271] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  356.705323] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  356.706553] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  356.706858] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  356.708649] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  356.708782] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  356.708834] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  356.708892] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  356.708966] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  356.709016] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  356.709091] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  356.709145] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  356.709370] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  356.709422] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  356.709800] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  356.711590] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  356.712199] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  356.712253] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  356.712336] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  356.712387] [drm:hsw_audio_config_update [i915]] using automatic N
>[  356.729261] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  356.729337] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  356.729581] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  356.729901] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  356.729975] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  356.730198] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  356.730759] Console: switching to colour frame buffer device 240x67
>[  356.888833] Console: switching to colour dummy device 80x25
>[  356.889054] [IGT] kms_cursor_legacy: executing
>[  356.925147] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  356.925193] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  356.925233] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  356.925268] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  356.925300] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  356.925334] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  356.925902] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  356.926371] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  356.926382] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  356.926386] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  356.926986] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  356.927031] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  356.927554] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  356.927930] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  356.928296] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  356.928336] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  356.936962] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  356.945647] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  356.954453] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  356.963191] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  356.971904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  356.980642] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  356.989401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  356.998123] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.006912] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.015794] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.024634] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.033535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.042410] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.051296] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.060176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.069047] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.077926] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.086806] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.095705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.104590] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.113273] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.121943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.130671] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.139500] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.148280] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.157081] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.165911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.174789] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.183665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.192640] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.201617] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.210714] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  357.210859] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  357.210876] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  357.212155] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  357.212271] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  357.293710] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  357.297894] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  357.298008] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  357.298020] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  357.299173] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  357.299184] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  357.299194] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  357.299200] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  357.299580] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  357.299593] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  357.299603] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  357.299612] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  357.299621] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  357.299631] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  357.300587] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  357.300597] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  357.300607] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  357.300616] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  357.300626] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  357.301201] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  357.301211] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  357.301220] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  357.301229] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  357.301243] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  357.301252] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  357.301262] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  357.301271] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  357.301280] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  357.301290] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  357.301299] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  357.301308] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  357.301317] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  357.304396] [IGT] kms_cursor_legacy: starting subtest basic-flip-after-cursor-varying-size
>[  357.305849] [drm:drm_mode_addfb2] [FB:70]
>[  357.386081] [drm:drm_mode_addfb2] [FB:91]
>[  357.386346] [drm:drm_mode_addfb2] [FB:101]
>[  357.388846] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  357.388867] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  357.409035] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  357.409217] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  357.409282] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  357.409335] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  357.409547] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  357.612790] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  357.612879] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  357.627803] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  357.627864] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  357.627928] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  357.679603] [drm:wait_panel_status [i915]] Wait complete
>[  357.679667] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  357.679810] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  357.679954] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  357.680039] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  357.680314] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  357.680370] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  357.680424] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  357.680595] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  357.680692] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  357.680948] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  357.697646] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  357.697879] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  357.698053] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  357.702312] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  357.702391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  357.702465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  357.702553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  357.702627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  357.702807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  357.702882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  357.702968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  357.703043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  357.703119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  357.703194] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  357.703281] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  357.703364] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  357.703444] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  357.703589] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  357.703664] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  357.704912] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  357.704999] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  358.132944] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  358.203334] [drm:wait_panel_status [i915]] Wait complete
>[  358.203444] [drm:edp_panel_on [i915]] Wait for panel power on
>[  358.203561] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  358.311981] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  358.312089] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  358.312189] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  358.312384] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  358.405307] [drm:wait_panel_status [i915]] Wait complete
>[  358.405451] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  358.405575] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  358.407910] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  358.408012] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  358.408117] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  358.409729] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  358.409921] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  358.411971] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  358.412392] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  358.415125] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  358.415186] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  358.415221] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  358.415262] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  358.415313] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  358.415347] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  358.415399] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  358.415433] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  358.448914] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  358.449001] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  358.449240] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  358.449380] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  358.449444] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  358.449531] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  358.449623] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  358.450468] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  358.505190] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  358.505395] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  358.505812] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  358.708918] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  358.709071] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  358.717507] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  358.717624] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  358.717821] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  358.769549] [drm:wait_panel_status [i915]] Wait complete
>[  358.769664] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  358.769924] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  358.770048] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  358.770153] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  358.770253] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  358.770448] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  358.770553] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  358.770857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  358.770978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  358.771092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  358.771199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  358.771304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  358.771410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  358.771522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  358.771624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  358.771875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  358.771982] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  358.772102] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  358.772215] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  358.772325] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  358.772472] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  358.772619] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  358.773016] [drm:intel_power_well_disable [i915]] disabling DC off
>[  358.773120] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  358.773212] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  358.774439] [drm:intel_power_well_disable [i915]] disabling always-on
>[  358.776259] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  358.777260] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  358.778760] [IGT] kms_cursor_legacy: exiting, ret=0
>[  358.806987] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  358.807037] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.807092] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  358.807149] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  358.807196] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  358.807248] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.807299] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  358.807349] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  358.807398] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  358.807446] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  358.807494] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.807503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  358.807550] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.807556] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  358.807605] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  358.807653] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  358.807747] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  358.807795] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.807843] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.807898] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  358.807945] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.807997] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  358.808047] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  358.808097] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  358.808147] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  358.808207] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  358.808256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.808310] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  358.808358] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  358.808408] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.808458] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  358.808506] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  358.808553] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  358.808601] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.808606] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  358.808653] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.808684] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  358.808733] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  358.808781] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  358.808830] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  358.808878] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.808926] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.808976] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  358.809024] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.809074] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  358.809124] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  358.809174] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  358.809224] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  358.809275] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  358.809337] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  358.809388] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  358.809444] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  358.809493] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  358.809741] [drm:intel_power_well_enable [i915]] enabling always-on
>[  358.809783] [drm:intel_power_well_enable [i915]] enabling DC off
>[  358.810082] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  358.810158] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  358.810303] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  358.810355] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  358.810433] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  358.810652] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  358.814769] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  358.814820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  358.814869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  358.814928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  358.814980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  358.815031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  358.815082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  358.815133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  358.815183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  358.815234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  358.815285] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  358.815339] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  358.815393] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  358.815483] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  358.815532] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  358.815836] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  358.815887] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  359.220851] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  359.302586] [drm:wait_panel_status [i915]] Wait complete
>[  359.302643] [drm:edp_panel_on [i915]] Wait for panel power on
>[  359.302749] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  359.411114] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  359.411167] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  359.411217] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  359.411312] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  359.504331] [drm:wait_panel_status [i915]] Wait complete
>[  359.504406] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  359.504470] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  359.505895] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.505943] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.505997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.507088] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.507157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  359.508488] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.508844] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  359.511080] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  359.511187] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  359.511252] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  359.511326] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  359.511422] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  359.511487] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  359.511577] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  359.511642] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  359.512003] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  359.512069] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  359.512471] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  359.514749] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  359.515387] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  359.515453] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  359.515555] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  359.515618] [drm:hsw_audio_config_update [i915]] using automatic N
>[  359.532459] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  359.532543] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  359.532880] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  359.533170] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  359.533252] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  359.533493] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  359.534114] Console: switching to colour frame buffer device 240x67
>[  359.712556] Console: switching to colour dummy device 80x25
>[  359.713071] [IGT] kms_cursor_legacy: executing
>[  359.746672] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  359.746719] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  359.746759] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  359.746794] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  359.746827] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  359.746859] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  359.747431] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  359.748114] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  359.748127] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  359.748132] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  359.748724] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  359.748769] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  359.749319] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  359.749799] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  359.750188] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  359.750233] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  359.758835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.767545] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.776249] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.785010] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.793758] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.802485] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.811231] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.820037] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.828923] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.837812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.846800] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.855878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.864887] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.873883] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.882876] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.891865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.900852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.909848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.918838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.927857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.936849] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.945865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.954875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.963881] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.972873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.981873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.990859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  359.999852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.008866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.017861] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.026856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.035865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.035915] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  360.035930] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  360.037224] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  360.037339] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  360.118453] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  360.122632] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  360.122817] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  360.122830] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  360.123491] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  360.123500] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  360.123509] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  360.123515] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  360.124007] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  360.124020] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  360.124034] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  360.124043] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  360.124052] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  360.124062] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  360.124074] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  360.124084] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  360.124093] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  360.124103] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  360.124112] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  360.124122] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  360.124131] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  360.124141] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  360.124154] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  360.124163] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  360.124175] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  360.124184] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  360.124193] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  360.124203] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  360.124212] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  360.124221] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  360.124234] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  360.124243] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  360.126189] [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-atomic
>[  360.126571] [IGT] kms_cursor_legacy: exiting, ret=77
>[  360.149214] Console: switching to colour frame buffer device 240x67
>[  360.304280] Console: switching to colour dummy device 80x25
>[  360.304544] [IGT] kms_cursor_legacy: executing
>[  360.341050] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  360.341099] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  360.341139] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  360.341173] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  360.341206] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  360.341256] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  360.341860] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  360.342323] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  360.342336] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  360.342340] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  360.342895] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  360.342942] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  360.343481] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  360.343894] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  360.344275] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  360.344320] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  360.352997] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.361739] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.370455] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.379205] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.387937] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.396759] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.405591] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.414564] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.423479] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.432424] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.441403] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.450399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.459392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.468391] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.477397] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.486398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.495393] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.504403] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.513398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.522383] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.531380] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.540385] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.549374] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.558369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.567355] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.576338] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.585324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.594332] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.603335] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.612337] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.621340] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.630333] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  360.630381] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  360.630396] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  360.631807] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  360.631926] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  360.713359] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  360.717550] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  360.717667] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  360.717803] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  360.718469] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  360.718479] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  360.718487] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  360.718493] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  360.718964] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  360.718978] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  360.718988] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  360.718998] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  360.719007] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  360.719020] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  360.719029] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  360.719039] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  360.719048] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  360.719061] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  360.719070] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  360.719080] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  360.719090] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  360.719102] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  360.719112] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  360.719121] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  360.719130] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  360.719139] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  360.719153] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  360.719162] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  360.719172] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  360.719185] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  360.719194] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  360.719203] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  360.721036] [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-legacy
>[  360.722872] [drm:drm_mode_addfb2] [FB:71]
>[  360.805211] [drm:drm_mode_addfb2] [FB:91]
>[  360.807167] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  360.807187] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  360.828176] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  360.828353] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  360.828417] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  360.828471] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  360.828765] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  361.036860] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  361.036966] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  361.045812] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  361.045899] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  361.045985] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  361.096095] [drm:wait_panel_status [i915]] Wait complete
>[  361.096183] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  361.096273] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  361.096435] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  361.096554] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  361.096644] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  361.096957] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  361.098355] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  361.098439] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  361.098518] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  361.098709] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  361.098984] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  361.099171] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  361.099381] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  361.102834] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  361.102923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  361.103004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  361.103099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  361.103180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  361.103262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  361.103343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  361.103432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  361.103513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  361.103594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  361.103674] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  361.103844] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  361.103937] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  361.104026] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  361.104183] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  361.104266] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  361.105811] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  361.105900] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  361.548870] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  361.602423] [drm:wait_panel_status [i915]] Wait complete
>[  361.602535] [drm:edp_panel_on [i915]] Wait for panel power on
>[  361.602650] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  361.711064] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  361.711173] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  361.711272] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  361.711472] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  361.804499] [drm:wait_panel_status [i915]] Wait complete
>[  361.804645] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  361.805013] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  361.806729] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  361.806891] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  361.806996] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  361.808574] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  361.808677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  361.810488] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  361.810917] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  361.813664] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  361.813868] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  361.813965] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  361.814073] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  361.814207] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  361.814304] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  361.814432] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  361.814530] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  361.847360] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  361.847434] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  361.847655] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  361.847883] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  361.847940] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  361.848018] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  361.848102] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  361.848628] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  361.905444] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  361.905701] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  361.906171] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  362.108858] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  362.108984] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  362.115715] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  362.115915] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  362.116033] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  362.167836] [drm:wait_panel_status [i915]] Wait complete
>[  362.167948] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  362.168067] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  362.168267] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  362.168366] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  362.168467] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  362.168565] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  362.168838] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  362.168956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  362.169081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  362.169199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  362.169305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  362.169413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  362.169522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  362.169636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  362.169798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  362.169902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  362.170009] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  362.170130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  362.170240] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  362.170349] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  362.170491] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  362.170635] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  362.170833] [drm:intel_power_well_disable [i915]] disabling DC off
>[  362.170943] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  362.171034] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  362.171645] [drm:intel_power_well_disable [i915]] disabling always-on
>[  362.173073] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  362.173884] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  362.174891] [IGT] kms_cursor_legacy: exiting, ret=0
>[  362.213975] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  362.214029] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  362.214087] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  362.214148] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  362.214198] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  362.214253] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  362.214307] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  362.214361] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  362.214413] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  362.214464] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  362.214514] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  362.214524] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  362.214575] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  362.214580] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  362.214632] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  362.214717] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  362.214769] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  362.214821] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  362.214872] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  362.214930] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  362.214980] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  362.215036] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  362.215089] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  362.215141] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  362.215194] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  362.215258] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  362.215311] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  362.215367] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  362.215417] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  362.215471] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  362.215524] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  362.215575] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  362.215626] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  362.215704] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  362.215710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  362.215761] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  362.215766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  362.215818] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  362.215869] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  362.215922] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  362.215973] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  362.216024] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  362.216078] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  362.216128] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  362.216181] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  362.216235] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  362.216288] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  362.216341] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  362.216398] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  362.216462] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  362.216515] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  362.216575] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  362.216628] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  362.216910] [drm:intel_power_well_enable [i915]] enabling always-on
>[  362.216954] [drm:intel_power_well_enable [i915]] enabling DC off
>[  362.217256] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  362.217336] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  362.217488] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  362.217539] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  362.217622] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  362.217904] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  362.221771] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  362.221821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  362.221870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  362.221925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  362.221973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  362.222022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  362.222070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  362.222118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  362.222166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  362.222214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  362.222262] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  362.222314] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  362.222364] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  362.222451] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  362.222499] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  362.222786] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  362.222835] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  362.620898] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  362.701743] [drm:wait_panel_status [i915]] Wait complete
>[  362.701831] [drm:edp_panel_on [i915]] Wait for panel power on
>[  362.701924] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  362.810323] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  362.810405] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  362.810485] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  362.810644] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  362.903507] [drm:wait_panel_status [i915]] Wait complete
>[  362.903622] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  362.903793] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  362.905424] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  362.905501] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  362.905585] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  362.906825] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  362.906903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  362.908376] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  362.908831] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  362.911479] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  362.911606] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  362.911682] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  362.911817] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  362.911927] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  362.912003] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  362.912109] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  362.912187] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  362.912515] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  362.912593] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  362.913094] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  362.914771] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  362.915301] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  362.915336] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  362.915390] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  362.915422] [drm:hsw_audio_config_update [i915]] using automatic N
>[  362.932393] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  362.932466] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  362.932771] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  362.933036] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  362.933109] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  362.933340] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  362.933892] Console: switching to colour frame buffer device 240x67
>[  363.099046] Console: switching to colour dummy device 80x25
>[  363.099370] [IGT] kms_cursor_legacy: executing
>[  363.126180] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  363.126242] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  363.126298] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  363.126350] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  363.126398] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  363.126449] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  363.127223] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  363.127810] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  363.127848] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  363.127852] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  363.128353] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  363.128398] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  363.129011] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  363.129394] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  363.129844] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  363.129888] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  363.138530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.147273] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.156000] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.164741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.173491] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.182237] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.191005] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.199837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.208773] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.217709] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.226701] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.235692] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.244706] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.253829] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.262882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.271867] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.280867] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.289869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.298884] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.307877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.316873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.325875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.334880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.343890] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.352891] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.361888] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.370878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.379881] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.388875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.397870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.406885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.415875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  363.415923] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  363.415939] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  363.417728] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  363.417847] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  363.499112] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  363.503304] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  363.503420] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  363.503432] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  363.504762] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  363.504774] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  363.504783] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  363.504789] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  363.505170] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  363.505182] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  363.505192] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  363.505201] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  363.505211] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  363.505220] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  363.505229] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  363.505239] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  363.505248] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  363.505257] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  363.505267] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  363.505276] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  363.505285] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  363.505295] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  363.505304] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  363.505313] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  363.505322] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  363.505332] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  363.505341] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  363.505350] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  363.505359] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  363.505368] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  363.505378] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  363.505387] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  363.508280] [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-varying-size
>[  363.510106] [drm:drm_mode_addfb2] [FB:70]
>[  363.592997] [drm:drm_mode_addfb2] [FB:91]
>[  363.593256] [drm:drm_mode_addfb2] [FB:101]
>[  363.595561] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  363.595580] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  363.628481] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  363.628658] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  363.628804] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  363.628860] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  363.629101] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  363.836957] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  363.837098] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  363.845879] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  363.845963] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  363.846049] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  363.897668] [drm:wait_panel_status [i915]] Wait complete
>[  363.897822] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  363.897911] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  363.898072] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  363.898176] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  363.898266] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  363.898327] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  363.898400] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  363.898474] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  363.898544] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  363.898893] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  363.899845] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  363.900031] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  363.900241] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  363.904492] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  363.904586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  363.904675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  363.904894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  363.904984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  363.905078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  363.905170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  363.905275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  363.905367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  363.905462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  363.905553] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  363.905659] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  363.905835] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  363.905904] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  363.906034] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  363.906097] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  363.906395] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  363.906463] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  364.348942] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  364.402824] [drm:wait_panel_status [i915]] Wait complete
>[  364.402936] [drm:edp_panel_on [i915]] Wait for panel power on
>[  364.403053] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  364.511462] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  364.511568] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  364.511668] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  364.511874] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  364.603592] [drm:wait_panel_status [i915]] Wait complete
>[  364.603854] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  364.603979] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  364.605691] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  364.605877] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  364.605982] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  364.607232] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  364.607332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  364.608807] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  364.609128] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  364.610892] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  364.610999] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  364.611063] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  364.611135] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  364.611225] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  364.611289] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  364.611381] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  364.611446] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  364.644632] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  364.644797] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  364.645047] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  364.645194] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  364.645263] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  364.645355] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  364.645453] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  364.646606] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  364.702758] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  364.703021] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  364.703425] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  364.908869] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  364.909025] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  364.911682] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  364.911994] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  364.912112] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  364.963274] [drm:wait_panel_status [i915]] Wait complete
>[  364.963392] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  364.963510] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  364.963710] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  364.964077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  364.964194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  364.964304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  364.964394] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  364.964493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  364.964592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  364.964695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  364.964796] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  364.964895] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  364.965156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  364.965260] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  364.965364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  364.965470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  364.965573] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  364.965695] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  364.966071] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  364.966181] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  364.966331] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  364.966482] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  364.966617] [drm:intel_power_well_disable [i915]] disabling DC off
>[  364.966817] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  364.966917] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  364.967537] [drm:intel_power_well_disable [i915]] disabling always-on
>[  364.969400] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  364.970393] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  364.971408] [IGT] kms_cursor_legacy: exiting, ret=0
>[  364.997753] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  364.997793] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  364.997836] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  364.997879] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  364.997916] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  364.997956] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  364.997996] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  364.998035] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  364.998072] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  364.998109] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  364.998145] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  364.998153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  364.998189] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  364.998193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  364.998231] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  364.998267] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  364.998305] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  364.998341] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  364.998377] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  364.998420] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  364.998456] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  364.998497] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  364.998535] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  364.998573] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  364.998611] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  364.998657] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  364.998720] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  364.998762] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  364.998798] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  364.998836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  364.998875] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  364.998911] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  364.998947] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  364.998985] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  364.998989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  364.999025] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  364.999029] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  364.999066] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  364.999103] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  364.999141] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  364.999178] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  364.999214] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  364.999252] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  364.999289] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  364.999327] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  364.999365] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  364.999404] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  364.999442] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  364.999483] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  364.999531] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  364.999570] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  364.999614] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  364.999651] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  364.999849] [drm:intel_power_well_enable [i915]] enabling always-on
>[  364.999881] [drm:intel_power_well_enable [i915]] enabling DC off
>[  365.000170] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  365.000230] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  365.000348] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  365.000386] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  365.000447] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  365.000629] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  365.004746] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  365.004786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  365.004826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  365.004871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  365.004911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  365.004950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  365.004989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  365.005044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  365.005082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  365.005121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  365.005160] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  365.005202] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  365.005243] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  365.005317] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  365.005354] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  365.005581] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  365.005622] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  365.420889] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  365.502298] [drm:wait_panel_status [i915]] Wait complete
>[  365.502396] [drm:edp_panel_on [i915]] Wait for panel power on
>[  365.502502] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  365.610868] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  365.610959] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  365.611047] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  365.611231] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  365.702796] [drm:wait_panel_status [i915]] Wait complete
>[  365.702923] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  365.703034] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  365.704801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  365.704886] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  365.704979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  365.706149] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  365.706235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  365.707701] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  365.708186] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  365.711016] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  365.711107] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  365.711143] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  365.711185] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  365.711239] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  365.711274] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  365.711328] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  365.711363] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  365.711541] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  365.711577] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  365.711880] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  365.713182] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  365.713739] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  365.713776] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  365.713835] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  365.713870] [drm:hsw_audio_config_update [i915]] using automatic N
>[  365.730877] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  365.730955] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  365.731211] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  365.731482] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  365.731558] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  365.731827] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  365.732381] Console: switching to colour frame buffer device 240x67
>[  365.900990] Console: switching to colour dummy device 80x25
>[  365.901244] [IGT] kms_flip: executing
>[  365.925203] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  365.925255] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  365.925299] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  365.925339] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  365.925376] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  365.925414] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  365.926279] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  365.926921] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  365.926940] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  365.926946] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  365.926996] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  365.927061] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  365.927661] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  365.928530] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  365.928581] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  365.928647] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  365.937413] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  365.946216] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  365.955053] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  365.963953] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  365.972835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  365.981776] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  365.990687] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  365.999681] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.008676] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.017683] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.026721] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.035722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.044830] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.053917] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.062930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.071923] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.080936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.089943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.098957] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.107963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.116954] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.125944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.134938] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.143936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.152936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.161920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.170915] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.179918] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.188907] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.197904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.206910] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.215904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  366.215958] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  366.215974] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  366.216048] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  366.216151] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  366.297524] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  366.299727] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  366.299846] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  366.299858] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  366.300527] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  366.300537] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  366.300546] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  366.300552] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  366.301043] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  366.301056] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  366.301070] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  366.301079] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  366.301088] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  366.301097] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  366.301107] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  366.301116] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  366.301126] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  366.301135] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  366.301144] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  366.301154] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  366.301166] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  366.301176] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  366.301185] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  366.301194] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  366.301203] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  366.301213] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  366.301222] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  366.301231] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  366.301241] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  366.301250] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  366.301263] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  366.301272] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  366.302911] [IGT] kms_flip: starting subtest basic-flip-vs-dpms
>[  366.305983] [drm:drm_mode_addfb2] [FB:89]
>[  366.306145] [drm:drm_mode_addfb2] [FB:91]
>[  366.415443] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  366.415552] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  366.415802] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  366.620843] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  366.620933] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  366.629586] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  366.629646] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  366.630015] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  366.681720] [drm:wait_panel_status [i915]] Wait complete
>[  366.681827] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  366.681892] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  366.682026] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  366.682071] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  366.682126] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  366.682182] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  366.682349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  366.682424] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  366.682512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  366.682600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  366.682682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  366.682803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  366.682882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  366.682961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  366.683038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  366.683119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  366.683196] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  366.683290] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  366.684132] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  366.684213] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  366.697381] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  366.697494] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  366.698164] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  366.698377] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  366.698642] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  366.698817] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  366.699276] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  366.715994] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  366.716179] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  366.716383] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  366.720683] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  366.720862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  366.720962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  366.721062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  366.721152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  366.721241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  366.721331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  366.721429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  366.721518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  366.721608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  366.721697] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  366.721885] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  366.721993] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  366.722094] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  366.722232] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  366.722754] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  366.723201] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  366.723335] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  366.723435] [drm:intel_power_well_disable [i915]] disabling DC off
>[  366.723526] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  366.723609] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  366.724303] [drm:intel_power_well_disable [i915]] disabling always-on
>[  366.725069] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  366.725820] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  366.725869] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  366.726119] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  366.726209] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  366.726305] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  366.726408] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  366.726493] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  366.726584] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  366.726674] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  366.726867] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  366.726956] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  366.727039] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  366.727126] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  366.727145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  366.727225] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  366.727242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  366.727326] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  366.727410] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  366.727495] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  366.727582] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  366.727667] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  366.727800] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  366.727886] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  366.727970] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  366.728054] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  366.728144] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  366.728229] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  366.728318] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  366.728412] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  366.728503] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  366.729170] [drm:intel_power_well_enable [i915]] enabling always-on
>[  366.729242] [drm:intel_power_well_enable [i915]] enabling DC off
>[  366.729565] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  366.729677] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  366.729975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  366.730058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  366.730149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  366.730229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  366.730313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  366.730395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  366.730484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  366.730565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  366.730650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  366.730811] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  366.730905] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  366.731000] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  366.731131] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  366.731212] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  366.731577] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  366.731613] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  367.132955] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  367.201653] [drm:wait_panel_status [i915]] Wait complete
>[  367.201796] [drm:edp_panel_on [i915]] Wait for panel power on
>[  367.201882] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  367.310333] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  367.310410] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  367.310483] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  367.310697] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  367.403961] [drm:wait_panel_status [i915]] Wait complete
>[  367.404094] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  367.404202] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  367.405936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  367.406035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  367.406139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  367.407288] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  367.407387] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  367.408951] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  367.409363] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  367.412098] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  367.412270] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  367.412369] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  367.412476] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  367.412607] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  367.412704] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  367.412928] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  367.413036] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  367.429236] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  367.429342] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  367.429629] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  367.463221] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  367.463325] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  367.463432] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  367.463544] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  367.463640] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  367.463834] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  367.463942] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  367.464047] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  367.464149] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  367.464249] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  367.464351] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  367.464371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  367.464475] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  367.464491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  367.464599] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  367.464699] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  367.464856] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  367.464957] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  367.465062] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  367.465171] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  367.465275] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  367.465384] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  367.465488] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  367.465591] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  367.465694] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  367.465847] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  367.465951] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  367.466067] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  367.466167] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  367.480078] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  367.684885] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  367.685038] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  367.697995] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  367.698108] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  367.698225] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  367.749983] [drm:wait_panel_status [i915]] Wait complete
>[  367.750101] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  367.750223] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  367.750425] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  367.750508] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  367.750611] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  367.750712] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  367.751609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  367.751688] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  367.751798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  367.751886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  367.751968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  367.752048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  367.752129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  367.752213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  367.752294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  367.752374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  367.752454] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  367.752541] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  367.752626] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  367.753453] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  367.753550] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  367.753639] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  367.754206] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  367.754303] [drm:intel_power_well_disable [i915]] disabling DC off
>[  367.754385] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  367.754461] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  367.755662] [drm:intel_power_well_disable [i915]] disabling always-on
>[  367.757222] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  367.757308] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  367.757395] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  367.757485] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  367.757561] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  367.757643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  367.757815] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  367.757898] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  367.757988] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  367.758070] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  367.758159] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  367.758181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  367.758263] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  367.758277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  367.758359] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  367.758445] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  367.758527] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  367.758613] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  367.758696] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  367.758847] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  367.758953] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  367.758991] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  367.759027] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  367.759062] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  367.759096] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  367.759131] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  367.759169] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  367.759213] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  367.759248] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  367.759411] [drm:intel_power_well_enable [i915]] enabling always-on
>[  367.759442] [drm:intel_power_well_enable [i915]] enabling DC off
>[  367.759759] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  367.759813] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  367.760016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  367.760051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  367.760089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  367.760124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  367.760157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  367.760190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  367.760225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  367.760260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  367.760295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  367.760330] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  367.760367] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  367.760403] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  367.760469] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  367.760503] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  367.760757] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  367.760794] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  368.204867] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  368.302783] [drm:wait_panel_status [i915]] Wait complete
>[  368.302875] [drm:edp_panel_on [i915]] Wait for panel power on
>[  368.302969] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  368.411349] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  368.411444] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  368.411533] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  368.411855] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  368.503349] [drm:wait_panel_status [i915]] Wait complete
>[  368.503499] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  368.503620] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  368.505507] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  368.505608] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  368.505712] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  368.506992] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  368.507094] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  368.508555] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  368.509086] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  368.511731] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  368.511943] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  368.512039] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  368.512147] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  368.512279] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  368.512374] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  368.512508] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  368.512606] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  368.529027] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  368.529159] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  368.529490] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  368.530628] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  368.530769] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  368.530854] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  368.530944] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  368.531021] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  368.531102] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  368.531182] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  368.531262] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  368.531341] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  368.531418] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  368.531494] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  368.531510] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  368.531586] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  368.531595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  368.531673] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  368.531831] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  368.531914] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  368.532003] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  368.532088] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  368.532180] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  368.532262] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  368.532353] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  368.532439] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  368.532526] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  368.532610] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  368.532698] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  368.532826] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  368.532922] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  368.533009] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  368.545622] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  368.748861] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  368.749017] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  368.764049] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  368.764161] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  368.764279] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  368.816274] [drm:wait_panel_status [i915]] Wait complete
>[  368.816392] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  368.816510] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  368.816609] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  368.816710] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  368.816810] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  368.816982] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  368.817193] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  368.817431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  368.817535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  368.817649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  368.817834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  368.817945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  368.818050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  368.818164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  368.818272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  368.818381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  368.818489] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  368.818606] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  368.818717] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  368.818940] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  368.819058] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  368.819169] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  368.819302] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  368.819420] [drm:intel_power_well_disable [i915]] disabling DC off
>[  368.819531] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  368.819628] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  368.820301] [drm:intel_power_well_disable [i915]] disabling always-on
>[  368.822144] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  368.822251] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  368.822356] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  368.822468] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  368.822564] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  368.822665] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  368.822873] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  368.822975] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  368.823084] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  368.823187] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  368.823292] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  368.823316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  368.823417] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  368.823438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  368.823545] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  368.823651] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  368.823804] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  368.823911] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  368.824011] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  368.824129] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  368.824234] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  368.824342] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  368.824451] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  368.824553] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  368.824657] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  368.824834] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  368.824940] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  368.825059] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  368.825167] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  368.825553] [drm:intel_power_well_enable [i915]] enabling always-on
>[  368.825640] [drm:intel_power_well_enable [i915]] enabling DC off
>[  368.826030] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  368.826091] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  368.826225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  368.826268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  368.826313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  368.826355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  368.826400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  368.826441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  368.826485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  368.826526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  368.826569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  368.826611] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  368.826658] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  368.826779] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  368.826848] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  368.826883] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  368.827118] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  368.827155] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  369.268852] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  369.402075] [drm:wait_panel_status [i915]] Wait complete
>[  369.402139] [drm:edp_panel_on [i915]] Wait for panel power on
>[  369.402205] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  369.510627] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  369.510699] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  369.510768] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  369.510976] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  369.604118] [drm:wait_panel_status [i915]] Wait complete
>[  369.604236] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  369.604334] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  369.606156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  369.606244] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  369.606337] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  369.607521] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  369.607613] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  369.609161] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  369.609547] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  369.611959] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  369.612108] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  369.612194] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  369.612289] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  369.612407] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  369.612492] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  369.612605] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  369.612692] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  369.629116] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  369.629235] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  369.629541] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  369.630878] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  369.630981] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  369.631087] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  369.631199] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  369.631295] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  369.631397] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  369.631497] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  369.631596] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  369.631695] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  369.631890] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  369.631992] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  369.632017] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  369.632115] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  369.632132] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  369.632239] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  369.632339] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  369.632446] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  369.632549] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  369.632655] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  369.632815] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  369.632922] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  369.633030] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  369.633140] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  369.633243] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  369.633354] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  369.633460] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  369.633571] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  369.633685] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  369.633840] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  369.645929] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  369.852928] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  369.853085] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  369.863970] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  369.864082] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  369.864199] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  369.916135] [drm:wait_panel_status [i915]] Wait complete
>[  369.916252] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  369.916369] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  369.916452] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  369.916555] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  369.916655] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  369.916753] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  369.916946] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  369.917049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  369.917151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  369.917265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  369.917373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  369.917486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  369.917591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  369.917707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  369.917869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  369.917974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  369.918085] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  369.918202] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  369.918313] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  369.918460] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  369.918580] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  369.918698] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  369.918914] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  369.919036] [drm:intel_power_well_disable [i915]] disabling DC off
>[  369.919140] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  369.919232] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  369.919933] [drm:intel_power_well_disable [i915]] disabling always-on
>[  369.921613] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  369.921715] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  369.921924] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  369.922043] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  369.922145] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  369.922250] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  369.922353] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  369.922458] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  369.922561] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  369.922664] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  369.922836] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  369.922857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  369.922962] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  369.922982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  369.923087] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  369.923190] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  369.923299] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  369.923403] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  369.923509] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  369.923622] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  369.923749] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  369.923858] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  369.923970] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  369.924074] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  369.924186] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  369.924290] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  369.924401] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  369.924521] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  369.924627] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  369.925058] [drm:intel_power_well_enable [i915]] enabling always-on
>[  369.925146] [drm:intel_power_well_enable [i915]] enabling DC off
>[  369.925489] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  369.925629] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  369.925959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  369.926067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  369.926177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  369.926284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  369.926386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  369.926492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  369.926601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  369.926707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  369.926918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  369.927029] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  369.927148] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  369.927263] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  369.927420] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  369.927522] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  369.927943] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  369.927981] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  370.372887] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  370.501866] [drm:wait_panel_status [i915]] Wait complete
>[  370.501949] [drm:edp_panel_on [i915]] Wait for panel power on
>[  370.502035] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  370.610449] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  370.610546] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  370.610636] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  370.610887] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  370.703381] [drm:wait_panel_status [i915]] Wait complete
>[  370.703527] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  370.703648] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  370.705528] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  370.705626] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  370.705842] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  370.707328] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  370.707433] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  370.709318] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  370.709862] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  370.712467] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  370.712644] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  370.712839] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  370.712950] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  370.713088] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  370.713188] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  370.713323] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  370.713425] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  370.729532] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  370.729615] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  370.730165] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  370.731099] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  370.731163] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  370.731232] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  370.731301] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  370.731360] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  370.731423] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  370.731484] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  370.731546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  370.731607] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  370.731666] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  370.731876] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  370.731893] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  370.731972] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  370.731983] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  370.732064] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  370.732150] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  370.732235] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  370.732321] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  370.732407] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  370.732497] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  370.732578] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  370.732667] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  370.732795] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  370.732883] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  370.732964] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  370.733047] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  370.733136] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  370.733232] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  370.733316] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  370.746321] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  370.948874] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  370.949029] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  370.963845] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  370.963962] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  370.964080] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  371.015050] [drm:wait_panel_status [i915]] Wait complete
>[  371.015165] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  371.015283] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  371.015486] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  371.015718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  371.015953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  371.016065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  371.016174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  371.016282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  371.016391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  371.016478] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  371.016589] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  371.016694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  371.016796] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  371.016902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  371.017009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  371.017112] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  371.017233] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  371.017344] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  371.017495] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  371.017618] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  371.017804] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  371.017939] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  371.018059] [drm:intel_power_well_disable [i915]] disabling DC off
>[  371.018163] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  371.018254] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  371.018520] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  371.018929] [drm:intel_power_well_disable [i915]] disabling always-on
>[  371.021111] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  371.022870] [drm:intel_power_well_enable [i915]] enabling always-on
>[  371.022958] [drm:intel_power_well_enable [i915]] enabling DC off
>[  371.023398] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  371.023552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  371.023662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  371.023880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  371.023988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  371.024096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  371.024207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  371.024320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  371.024430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  371.024530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  371.024631] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  371.024813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  371.024969] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  371.025078] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  371.025327] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  371.025483] [drm:intel_power_well_disable [i915]] disabling DC off
>[  371.025592] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  371.025683] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  371.026340] [drm:intel_power_well_disable [i915]] disabling always-on
>[  371.026886] [drm:drm_mode_addfb2] [FB:89]
>[  371.026942] [drm:drm_mode_addfb2] [FB:91]
>[  371.082883] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  371.083321] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  371.083978] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  371.084537] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  371.084558] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  371.084662] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  371.084735] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  371.084776] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  371.084821] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  371.084854] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  371.084889] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  371.084923] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  371.084957] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  371.084993] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  371.085027] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  371.085062] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  371.085068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  371.085101] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  371.085107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  371.085140] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  371.085175] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  371.085208] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  371.085241] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  371.085275] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  371.085313] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  371.085346] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  371.085382] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  371.085418] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  371.085453] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  371.085487] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  371.085523] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  371.085565] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  371.085600] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  371.085999] [drm:intel_power_well_enable [i915]] enabling always-on
>[  371.086028] [drm:intel_power_well_enable [i915]] enabling DC off
>[  371.086311] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  371.086359] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  371.086393] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  371.086446] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  371.086592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  371.086627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  371.086721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  371.086754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  371.086789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  371.086822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  371.086860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  371.086895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  371.086930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  371.086965] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  371.087005] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  371.087043] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  371.087110] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  371.087145] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  371.087377] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  371.087415] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  371.468848] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  371.601413] [drm:wait_panel_status [i915]] Wait complete
>[  371.601504] [drm:edp_panel_on [i915]] Wait for panel power on
>[  371.601598] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  371.710035] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  371.710115] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  371.710187] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  371.710412] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  371.802904] [drm:wait_panel_status [i915]] Wait complete
>[  371.803032] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  371.803140] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  371.804897] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  371.804996] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  371.805100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  371.806906] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  371.807009] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  371.808872] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  371.809323] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  371.811623] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  371.811793] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  371.811861] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  371.811937] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  371.812031] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  371.812097] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  371.828912] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  371.829028] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  371.829338] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  371.862689] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  371.862869] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  371.862964] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  371.863066] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  371.863151] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  371.863243] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  371.863330] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  371.863419] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  371.863506] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  371.863592] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  371.863676] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  371.863813] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  371.863915] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  371.863936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  371.864037] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  371.864143] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  371.864250] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  371.864358] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  371.864466] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  371.864578] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  371.864686] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  371.864846] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  371.864954] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  371.865059] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  371.865165] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  371.865274] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  371.865385] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  371.865503] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  371.865609] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  371.878981] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  372.084894] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  372.085049] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  372.095937] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  372.096049] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  372.096165] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  372.147659] [drm:wait_panel_status [i915]] Wait complete
>[  372.147897] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  372.148098] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  372.148331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  372.148433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  372.148514] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  372.148615] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  372.148715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  372.148815] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  372.148921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  372.149028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  372.149136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  372.149248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  372.149359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  372.149465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  372.149574] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  372.149692] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  372.149855] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  372.150011] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  372.150198] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  372.150977] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  372.151085] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  372.151205] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  372.151317] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  372.151431] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  372.151549] [drm:intel_power_well_disable [i915]] disabling DC off
>[  372.151652] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  372.151840] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  372.152461] [drm:intel_power_well_disable [i915]] disabling always-on
>[  372.154218] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  372.154320] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  372.154427] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  372.154539] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  372.154635] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  372.154843] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  372.154946] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  372.155056] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  372.155165] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  372.155276] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  372.155381] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  372.155405] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  372.155504] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  372.155517] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  372.155624] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  372.155748] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  372.155850] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  372.155957] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  372.156055] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  372.156165] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  372.156264] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  372.156373] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  372.156480] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  372.156581] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  372.156679] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  372.156851] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  372.156963] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  372.157086] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  372.157192] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  372.157568] [drm:intel_power_well_enable [i915]] enabling always-on
>[  372.157656] [drm:intel_power_well_enable [i915]] enabling DC off
>[  372.158059] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  372.158111] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  372.158149] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  372.158224] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  372.158353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  372.158393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  372.158433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  372.158473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  372.158510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  372.158550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  372.158589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  372.158629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  372.158709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  372.158750] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  372.158800] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  372.158843] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  372.158915] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  372.158953] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  372.159153] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  372.159193] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  372.604843] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  372.702781] [drm:wait_panel_status [i915]] Wait complete
>[  372.702875] [drm:edp_panel_on [i915]] Wait for panel power on
>[  372.702969] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  372.811359] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  372.811466] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  372.811566] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  372.811860] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  372.903861] [drm:wait_panel_status [i915]] Wait complete
>[  372.904008] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  372.904131] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  372.905909] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  372.906008] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  372.906112] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  372.907433] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  372.907534] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  372.909167] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  372.909580] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  372.912408] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  372.912580] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  372.912677] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  372.913024] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  372.913164] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  372.913264] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  372.929497] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  372.929586] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  372.929936] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  372.930853] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  372.930924] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  372.931000] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  372.931078] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  372.931145] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  372.931218] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  372.931287] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  372.931356] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  372.931426] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  372.931495] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  372.931558] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  372.931573] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  372.931637] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  372.931694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  372.931761] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  372.931834] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  372.931903] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  372.931979] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  372.932050] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  372.932129] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  372.932200] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  372.932278] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  372.932351] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  372.932422] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  372.932489] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  372.932561] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  372.932636] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  372.932749] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  372.932821] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  372.946197] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  373.148878] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  373.149013] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  373.164007] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  373.164121] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  373.164239] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  373.215148] [drm:wait_panel_status [i915]] Wait complete
>[  373.215276] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  373.215475] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  373.215706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  373.215964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  373.216075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  373.216179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  373.216282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  373.216387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  373.216494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  373.216579] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  373.216680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  373.216777] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  373.216879] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  373.216981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  373.217082] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  373.217199] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  373.217306] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  373.217455] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  373.217596] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  373.217701] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  373.217873] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  373.217987] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  373.218102] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  373.218217] [drm:intel_power_well_disable [i915]] disabling DC off
>[  373.218321] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  373.218414] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  373.219080] [drm:intel_power_well_disable [i915]] disabling always-on
>[  373.219938] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  373.220805] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  373.220907] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  373.221017] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  373.221133] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  373.221230] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  373.221336] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  373.221436] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  373.221538] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  373.221637] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  373.221837] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  373.221909] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  373.221923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  373.221965] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  373.221975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  373.222021] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  373.222066] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  373.222112] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  373.222154] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  373.222200] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  373.222248] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  373.222293] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  373.222342] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  373.222391] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  373.222434] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  373.222481] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  373.222527] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  373.222574] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  373.222627] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  373.222794] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  373.222973] [drm:intel_power_well_enable [i915]] enabling always-on
>[  373.223009] [drm:intel_power_well_enable [i915]] enabling DC off
>[  373.223301] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  373.223361] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  373.223404] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  373.223469] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  373.223631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  373.223833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  373.223880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  373.223922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  373.223965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  373.224006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  373.224050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  373.224095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  373.224137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  373.224181] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  373.224228] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  373.224273] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  373.224351] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  373.224392] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  373.224612] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  373.224655] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  373.668888] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  373.790142] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x18001a18, pins 0x00000040
>[  373.790248] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - long
>[  373.790347] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 6 - cnt: 0
>[  373.790541] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - long
>[  373.803490] [drm:wait_panel_status [i915]] Wait complete
>[  373.803606] [drm:edp_panel_on [i915]] Wait for panel power on
>[  373.803723] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  373.912062] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  373.912168] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  373.912268] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  373.912455] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  373.987850] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x18001a18, pins 0x00000040
>[  373.987956] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - long
>[  373.988054] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 6 - cnt: 1
>[  373.988233] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - long
>[  374.005382] [drm:wait_panel_status [i915]] Wait complete
>[  374.005527] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  374.005648] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  374.007544] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  374.007643] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  374.007892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  374.009540] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  374.009642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  374.011522] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  374.011966] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  374.014619] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  374.014874] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  374.014974] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  374.015088] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  374.015229] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  374.015329] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  374.031945] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  374.032078] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  374.032413] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  374.033136] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[  374.033324] [drm:i915_hotplug_work_func [i915]] Connector DP-2 (pin 6) received hotplug event.
>[  374.033425] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  374.033585] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  374.045913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.054792] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.063646] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.072589] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.081686] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.090892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.099938] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.108961] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.117991] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.127115] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.136149] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.145204] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.154221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.163247] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.172373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.181393] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.190470] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.199489] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.208595] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.217786] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.226877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.235875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.244938] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.253948] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.262942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.271948] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.280992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.290124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.299128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.308137] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.317134] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.326142] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  374.326194] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  374.326284] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  374.326401] [drm:i915_hotplug_work_func [i915]] Connector HDMI-A-1 (pin 6) received hotplug event.
>[  374.326499] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  374.408253] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  374.412443] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  374.412557] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  374.412569] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  374.412718] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[  374.414043] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  374.414148] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  374.414253] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  374.414367] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  374.414463] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  374.414564] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  374.414666] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  374.414875] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  374.414986] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  374.415092] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  374.415198] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  374.415219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  374.415321] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  374.415343] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  374.415448] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  374.415552] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  374.415662] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  374.415818] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  374.415929] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  374.416036] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  374.416145] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  374.416256] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  374.416362] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  374.416473] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  374.416581] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  374.416682] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  374.417058] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  374.417175] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  374.417281] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  374.417698] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  374.620878] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  374.621033] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  374.634015] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  374.634130] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  374.634247] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  374.685732] [drm:wait_panel_status [i915]] Wait complete
>[  374.685952] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  374.686155] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  374.686387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  374.686488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  374.686570] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  374.686671] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  374.686770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  374.686870] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  374.687071] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  374.687888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  374.687991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  374.688096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  374.688210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  374.688316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  374.688418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  374.688523] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  374.688642] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  374.688860] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  374.689014] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  374.689157] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  374.689260] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  374.689380] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  374.689490] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  374.689603] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  374.689780] [drm:intel_power_well_disable [i915]] disabling DC off
>[  374.689881] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  374.689974] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  374.690591] [drm:intel_power_well_disable [i915]] disabling always-on
>[  374.692285] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  374.692387] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  374.692492] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  374.692604] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  374.692700] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  374.692914] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  374.693021] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  374.693132] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  374.693240] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  374.693348] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  374.693450] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  374.693473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  374.693572] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  374.693590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  374.693693] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  374.693856] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  374.693964] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  374.694069] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  374.694169] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  374.694276] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  374.694375] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  374.694481] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  374.694584] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  374.694688] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  374.694855] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  374.694960] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  374.695076] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  374.695198] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  374.695307] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  374.695630] [drm:intel_power_well_enable [i915]] enabling always-on
>[  374.695796] [drm:intel_power_well_enable [i915]] enabling DC off
>[  374.696135] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  374.696267] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  374.696363] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  374.696503] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  374.698293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  374.698329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  374.698367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  374.698402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  374.698437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  374.698472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  374.698509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  374.698544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  374.698579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  374.698614] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  374.698651] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  374.698733] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  374.698802] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  374.698837] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  374.699052] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  374.699088] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  375.140892] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  375.203350] [drm:wait_panel_status [i915]] Wait complete
>[  375.203449] [drm:edp_panel_on [i915]] Wait for panel power on
>[  375.203553] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  375.311964] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  375.312073] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  375.312172] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  375.312359] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  375.403680] [drm:wait_panel_status [i915]] Wait complete
>[  375.403905] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  375.404025] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  375.405862] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  375.405964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.406068] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  375.407418] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  375.407518] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  375.409184] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  375.409601] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  375.412288] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  375.412439] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  375.412535] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  375.412644] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  375.412880] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  375.412980] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  375.429433] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  375.429542] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  375.430146] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  375.431324] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  375.431406] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  375.431491] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  375.431581] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  375.431657] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  375.432216] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  375.432298] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  375.432379] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  375.432461] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  375.432541] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  375.432617] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  375.432634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  375.433317] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  375.433327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  375.433406] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  375.433484] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  375.433562] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  375.433640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.434232] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  375.434319] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  375.434430] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  375.434517] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  375.434597] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  375.434678] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  375.435297] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  375.435377] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  375.435462] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  375.435551] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  375.435631] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  375.446127] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  375.652927] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  375.653081] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  375.663973] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  375.664085] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  375.664203] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  375.716028] [drm:wait_panel_status [i915]] Wait complete
>[  375.716158] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  375.716360] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  375.716468] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  375.716568] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  375.716668] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  375.716884] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  375.717714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  375.717868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  375.717970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  375.718062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  375.718150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  375.718239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  375.718331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  375.718421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  375.718510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  375.718602] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  375.718699] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  375.718875] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  375.719010] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  375.719135] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  375.719227] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  375.719334] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  375.719432] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  375.719532] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  375.719633] [drm:intel_power_well_disable [i915]] disabling DC off
>[  375.719993] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  375.720075] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  375.720674] [drm:intel_power_well_disable [i915]] disabling always-on
>[  375.722102] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  375.722283] [drm:intel_power_well_enable [i915]] enabling always-on
>[  375.722357] [drm:intel_power_well_enable [i915]] enabling DC off
>[  375.722689] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  375.723350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  375.723449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  375.723544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  375.723634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  375.723822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  375.723912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  375.724011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  375.724107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  375.724200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  375.724292] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  375.724389] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  375.724492] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  375.724590] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  375.724792] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  375.724887] [drm:intel_power_well_disable [i915]] disabling DC off
>[  375.724980] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  375.725061] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  375.725668] [drm:intel_power_well_disable [i915]] disabling always-on
>[  375.726822] [drm:drm_mode_addfb2] [FB:89]
>[  375.726879] [drm:drm_mode_addfb2] [FB:91]
>[  375.781589] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  375.782140] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  375.782790] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  375.783311] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  375.783333] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  375.783437] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  375.783471] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  375.783510] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  375.783548] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  375.783581] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  375.783616] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  375.783650] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  375.783730] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  375.783765] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  375.783801] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  375.783836] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  375.783846] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  375.783878] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  375.783885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  375.783922] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  375.783957] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  375.783994] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  375.784030] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.784067] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  375.784104] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  375.784140] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  375.784175] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  375.784212] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  375.784247] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  375.784285] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  375.784330] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  375.784367] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  375.784796] [drm:intel_power_well_enable [i915]] enabling always-on
>[  375.784828] [drm:intel_power_well_enable [i915]] enabling DC off
>[  375.785112] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  375.785160] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  375.785194] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  375.785246] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  375.785388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  375.785423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  375.785461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  375.785496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  375.785531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  375.785566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  375.785602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  375.785637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  375.785721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  375.785759] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  375.785800] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  375.785839] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  375.785909] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  375.785946] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  375.786150] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  375.786188] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  376.172856] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  376.301534] [drm:wait_panel_status [i915]] Wait complete
>[  376.301618] [drm:edp_panel_on [i915]] Wait for panel power on
>[  376.301841] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  376.410154] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  376.410262] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  376.410360] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  376.410557] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  376.502946] [drm:wait_panel_status [i915]] Wait complete
>[  376.503090] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  376.503210] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  376.504936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  376.505038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  376.505142] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  376.506255] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  376.506357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  376.507956] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  376.508371] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  376.511024] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  376.511190] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  376.511288] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  376.511398] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  376.511530] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  376.511627] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  376.528183] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  376.528301] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  376.528611] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  376.562179] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  376.562285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  376.562391] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  376.562505] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  376.562601] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  376.562702] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  376.562908] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  376.563013] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  376.563122] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  376.563225] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  376.563335] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  376.563359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  376.563461] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  376.563479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  376.563586] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  376.563691] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  376.563847] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  376.563960] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  376.564060] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  376.564175] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  376.564275] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  376.564387] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  376.564494] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  376.564599] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  376.564701] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  376.565028] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  376.565143] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  376.565250] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  376.578290] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  376.780936] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  376.781088] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  376.796181] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  376.796294] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  376.796411] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  376.848225] [drm:wait_panel_status [i915]] Wait complete
>[  376.848351] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  376.848551] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  376.848659] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  376.848760] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  376.848859] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  376.849064] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  376.849211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  376.849316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  376.849431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  376.849535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  376.849640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  376.849828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  376.849939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  376.850042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  376.850147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  376.850252] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  376.850366] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  376.850476] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  376.850627] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  376.850828] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  376.850935] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  376.851054] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  376.851164] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  376.851278] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  376.851388] [drm:intel_power_well_disable [i915]] disabling DC off
>[  376.851491] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  376.851584] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  376.852249] [drm:intel_power_well_disable [i915]] disabling always-on
>[  376.853975] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  376.854078] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  376.854184] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  376.854295] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  376.854391] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  376.854492] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  376.854592] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  376.854693] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  376.854896] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  376.854970] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  376.855017] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  376.855026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  376.855070] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  376.855077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  376.855122] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  376.855164] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  376.855212] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  376.855257] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  376.855300] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  376.855347] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  376.855392] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  376.855439] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  376.855485] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  376.855529] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  376.855573] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  376.855622] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  376.855700] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  376.855743] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  376.855929] [drm:intel_power_well_enable [i915]] enabling always-on
>[  376.855967] [drm:intel_power_well_enable [i915]] enabling DC off
>[  376.856260] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  376.856322] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  376.856365] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  376.856430] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  376.856603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  376.856647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  376.856745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  376.856790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  376.856836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  376.856881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  376.856929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  376.856975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  376.857020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  376.857065] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  376.857114] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  376.857161] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  376.857240] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  376.857283] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  376.857505] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  376.857551] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  377.300839] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  377.402293] [drm:wait_panel_status [i915]] Wait complete
>[  377.402382] [drm:edp_panel_on [i915]] Wait for panel power on
>[  377.402477] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  377.510840] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  377.510934] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  377.511023] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  377.511262] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  377.603720] [drm:wait_panel_status [i915]] Wait complete
>[  377.603945] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  377.604066] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  377.606228] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  377.606327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  377.606431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  377.608166] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  377.608269] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  377.609842] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  377.610263] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  377.612388] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  377.612447] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  377.612481] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  377.612521] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  377.612573] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  377.612606] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  377.629445] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  377.629531] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  377.629963] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  377.630908] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  377.630972] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  377.631040] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  377.631109] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  377.631168] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  377.631231] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  377.631293] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  377.631357] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  377.631418] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  377.631477] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  377.631536] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  377.631547] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  377.631606] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  377.631612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  377.631673] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  377.631807] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  377.631870] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  377.631937] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  377.631999] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  377.632070] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  377.632131] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  377.632201] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  377.632264] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  377.632331] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  377.632394] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  377.632467] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  377.632541] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  377.632604] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  377.646199] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  377.852880] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  377.853023] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  377.863960] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  377.864060] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  377.864165] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  377.914248] [drm:wait_panel_status [i915]] Wait complete
>[  377.914365] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  377.914550] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  377.915329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  377.915423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  377.915520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  377.915610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  377.915700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  377.916441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  377.916533] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  377.916623] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  377.916711] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  377.916874] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  377.917401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  377.917493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  377.917585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  377.917674] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  377.917836] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  377.917939] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  377.918073] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  377.918616] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  377.918801] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  377.919205] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  377.919306] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  377.919401] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  377.919501] [drm:intel_power_well_disable [i915]] disabling DC off
>[  377.919591] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  377.919670] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  377.920378] [drm:intel_power_well_disable [i915]] disabling always-on
>[  377.922258] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  377.922361] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  377.922467] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  377.922579] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  377.922674] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  377.922884] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  377.922988] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  377.923096] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  377.923198] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  377.923301] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  377.923400] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  377.923425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  377.923523] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  377.923539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  377.923640] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  377.923796] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  377.923898] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  377.924003] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  377.924100] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  377.924210] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  377.924309] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  377.924418] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  377.924519] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  377.924623] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  377.924746] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  377.924857] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  377.924974] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  377.925076] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  377.925445] [drm:intel_power_well_enable [i915]] enabling always-on
>[  377.925532] [drm:intel_power_well_enable [i915]] enabling DC off
>[  377.925893] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  377.926453] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  377.926496] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  377.926563] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  377.926747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  377.926795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  377.926842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  377.926887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  377.926933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  377.926980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  377.927030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  377.927077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  377.927123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  377.927170] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  377.927221] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  377.927271] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  377.927356] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  377.927403] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  377.927648] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  377.927722] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  378.372859] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  378.501616] [drm:wait_panel_status [i915]] Wait complete
>[  378.501859] [drm:edp_panel_on [i915]] Wait for panel power on
>[  378.501982] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  378.610352] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  378.610458] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  378.610558] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  378.610788] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  378.702446] [drm:wait_panel_status [i915]] Wait complete
>[  378.702590] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  378.702711] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  378.704527] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  378.704627] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  378.704843] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  378.706043] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  378.706144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  378.707557] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  378.707934] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  378.709911] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  378.710026] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  378.710096] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  378.710175] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  378.710273] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  378.710344] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  378.727072] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  378.727189] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  378.727494] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  378.729064] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  378.729156] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  378.729251] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  378.729350] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  378.729436] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  378.729526] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  378.729615] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  378.729701] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  378.729878] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  378.729969] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  378.730066] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  378.730088] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  378.730181] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  378.730200] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  378.730295] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  378.730390] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  378.730487] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  378.730579] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  378.730676] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  378.730818] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  378.730907] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  378.731005] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  378.731868] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  378.731960] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  378.732055] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  378.732150] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  378.732257] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  378.732349] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  378.743903] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  378.948868] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  378.949005] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  378.961995] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  378.962097] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  378.962201] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  379.013167] [drm:wait_panel_status [i915]] Wait complete
>[  379.013299] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  379.013500] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  379.013708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  379.013949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  379.014061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  379.014165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  379.014271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  379.014374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  379.014464] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  379.014563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  379.014665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  379.014773] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  379.014873] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  379.014976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  379.015088] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  379.015203] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  379.015322] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  379.015472] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  379.015614] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  379.015808] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  379.015926] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  379.016038] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  379.016153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  379.016267] [drm:intel_power_well_disable [i915]] disabling DC off
>[  379.016373] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  379.016469] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  379.017097] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  379.017183] [drm:intel_power_well_disable [i915]] disabling always-on
>[  379.018439] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  379.018498] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  379.018561] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  379.018626] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  379.018749] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  379.018811] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  379.018875] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  379.018938] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  379.019001] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  379.019059] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  379.019122] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  379.019135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  379.019192] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  379.019203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  379.019261] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  379.019323] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  379.019384] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  379.019446] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  379.019504] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  379.019566] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  379.019623] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  379.019709] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  379.019766] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  379.019827] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  379.019883] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  379.019947] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  379.020019] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  379.020077] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  379.020321] [drm:intel_power_well_enable [i915]] enabling always-on
>[  379.020372] [drm:intel_power_well_enable [i915]] enabling DC off
>[  379.020740] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  379.021310] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  379.021364] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  379.021449] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  379.021600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  379.021659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  379.021809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  379.021868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  379.021929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  379.021988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  379.022052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  379.022113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  379.022175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  379.022233] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  379.022300] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  379.022364] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  379.022464] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  379.022523] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  379.022811] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  379.022873] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  379.468907] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  379.602457] [drm:wait_panel_status [i915]] Wait complete
>[  379.602570] [drm:edp_panel_on [i915]] Wait for panel power on
>[  379.602687] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  379.711060] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  379.711169] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  379.711269] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  379.711501] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  379.804625] [drm:wait_panel_status [i915]] Wait complete
>[  379.804806] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  379.804927] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  379.806669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  379.806859] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  379.806965] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  379.808221] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  379.808321] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  379.809922] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  379.810337] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  379.812984] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  379.813151] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  379.813247] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  379.813354] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  379.813485] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  379.813581] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  379.830109] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  379.830206] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  379.830470] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  379.831553] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  379.831628] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  379.831787] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  379.831874] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  379.831948] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  379.832028] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  379.832100] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  379.832177] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  379.832252] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  379.832327] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  379.832399] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  379.832415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  379.832485] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  379.832496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  379.832571] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  379.832644] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  379.832780] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  379.832855] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  379.832934] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  379.833015] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  379.833094] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  379.833178] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  379.833256] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  379.833334] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  379.833411] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  379.833497] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  379.833585] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  379.833660] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  379.846968] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  380.052883] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  380.053036] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  380.063937] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  380.064050] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  380.064166] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  380.115991] [drm:wait_panel_status [i915]] Wait complete
>[  380.116121] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  380.116322] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  380.116449] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  380.116549] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  380.116650] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  380.116830] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  380.117206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.117311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.117426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.117529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.117635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.117817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.117934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.118042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.118154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.118258] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.118377] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.118491] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.118638] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  380.118862] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  380.118969] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  380.119096] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  380.119212] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  380.119323] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.119439] [drm:intel_power_well_disable [i915]] disabling DC off
>[  380.119541] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  380.119632] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  380.120337] [drm:intel_power_well_disable [i915]] disabling always-on
>[  380.121896] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  380.122103] [drm:intel_power_well_enable [i915]] enabling always-on
>[  380.122186] [drm:intel_power_well_enable [i915]] enabling DC off
>[  380.122528] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  380.122675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.122887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.122996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.123106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.123214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.123325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.123437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.123544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.123656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.123816] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  380.123922] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.124039] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.124155] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.124305] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  380.124406] [drm:intel_power_well_disable [i915]] disabling DC off
>[  380.124514] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  380.124607] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  380.125301] [drm:intel_power_well_disable [i915]] disabling always-on
>[  380.127966] [drm:drm_mode_addfb2] [FB:89]
>[  380.128128] [drm:drm_mode_addfb2] [FB:91]
>[  380.182911] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  380.183373] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  380.184235] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  380.184744] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  380.184767] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  380.184873] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.184907] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.184946] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.184979] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.185016] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.185050] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.185085] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.185118] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.185152] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.185157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.185189] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.185196] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.185229] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.185262] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.185297] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.185329] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.185363] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.185401] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.185434] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.185470] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  380.185505] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.185539] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.185573] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.185621] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  380.185730] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.185766] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.186124] [drm:intel_power_well_enable [i915]] enabling always-on
>[  380.186153] [drm:intel_power_well_enable [i915]] enabling DC off
>[  380.186434] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  380.186485] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  380.186519] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  380.186572] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  380.187529] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  380.190724] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.190762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.190802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.190843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.190878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.190913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.190946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.190979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.191014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.191049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.191084] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.191120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.191156] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.191221] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  380.191256] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  380.191509] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  380.192528] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  380.193102] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  380.193138] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  380.193191] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  380.193225] [drm:hsw_audio_config_update [i915]] using automatic N
>[  380.193620] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  380.193656] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  380.210184] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.210231] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.210396] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.243741] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.243777] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.243815] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.243847] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.243882] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.243917] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.243951] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.243983] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.244015] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.244023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.244055] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.244058] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.244091] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.244124] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.244157] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.244189] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.244221] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.244259] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.244291] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.244326] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.244359] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.244394] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.244428] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.244462] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.244510] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  380.244554] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.244588] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.260210] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  380.260282] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  380.260403] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  380.277074] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  380.277160] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  380.277310] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  380.277470] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  380.281784] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.281867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.281954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.282044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.282125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.282206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.282286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.282367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.282448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.282529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.282608] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.282694] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.282878] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.283001] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  380.283085] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  380.283197] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  380.283293] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.283381] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.283487] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.283581] [drm:intel_power_well_disable [i915]] disabling DC off
>[  380.283664] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  380.283976] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  380.284568] [drm:intel_power_well_disable [i915]] disabling always-on
>[  380.286278] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.286362] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.286447] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.286524] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.286604] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.286684] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.286862] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.286941] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.287025] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.287042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.287123] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.287136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.287221] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.287301] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.287386] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.287468] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.287550] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.287634] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.287763] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.287850] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.287934] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.288014] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.288097] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.288178] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.288296] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  380.288397] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.288480] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.288829] [drm:intel_power_well_enable [i915]] enabling always-on
>[  380.288885] [drm:intel_power_well_enable [i915]] enabling DC off
>[  380.289193] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  380.289281] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  380.289343] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  380.289429] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  380.289927] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  380.294081] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.294118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.294156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.294193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.294229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.294264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.294299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.294332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.294366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.294399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.294435] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.294471] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.294507] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.294573] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  380.294607] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  380.294954] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  380.295964] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  380.296499] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  380.296533] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  380.296584] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  380.296617] [drm:hsw_audio_config_update [i915]] using automatic N
>[  380.296752] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  380.296788] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  380.313597] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.313647] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.313962] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.314610] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.314666] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.314784] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.314836] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.314895] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.314951] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.315007] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.315060] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.315113] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.315126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.315177] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.315187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.315242] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.315294] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.315348] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.315403] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.315458] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.315517] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.315572] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.315630] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.315716] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.315771] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.315825] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.315880] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.315961] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  380.316029] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.316084] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.330264] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  380.330336] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  380.330446] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  380.346971] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  380.347054] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  380.347203] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  380.347360] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  380.351600] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.351671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.351837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.351915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.351984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.352054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.352124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.352193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.352264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.352332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.352402] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.352479] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.352552] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.352652] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  380.352819] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  380.352925] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  380.353015] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.353095] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.353192] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.353274] [drm:intel_power_well_disable [i915]] disabling DC off
>[  380.353348] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  380.353415] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  380.354605] [drm:intel_power_well_disable [i915]] disabling always-on
>[  380.356041] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.356115] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.356193] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.356263] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.356336] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.356408] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.356480] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.356549] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.356618] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.356629] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.356779] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.356790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.356866] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.356939] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.357014] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.357090] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.357168] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.357247] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.357321] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.357401] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.357479] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.357551] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.357630] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.357745] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.357852] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  380.357943] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.358019] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.358274] [drm:intel_power_well_enable [i915]] enabling always-on
>[  380.358341] [drm:intel_power_well_enable [i915]] enabling DC off
>[  380.358656] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  380.359303] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  380.359361] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  380.359451] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  380.359822] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  380.364058] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.364123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.364191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.364260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.364323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.364385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.364448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.364509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.364573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.364634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.364801] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.364849] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.364897] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.364976] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  380.365019] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  380.365309] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  380.366509] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  380.367116] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  380.367160] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  380.367224] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  380.367266] [drm:hsw_audio_config_update [i915]] using automatic N
>[  380.367374] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  380.367418] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  380.384185] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.384268] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.384496] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.385378] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.385443] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.385509] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.385568] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.385630] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.385775] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.385839] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.385903] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.385963] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.385978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.386038] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.386047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.386114] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.386176] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.386241] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.386307] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.386370] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.386437] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.386499] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.386565] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.386630] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.386728] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.386794] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.386857] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.386949] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  380.387024] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.387088] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.400945] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  380.401026] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  380.401150] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  380.417698] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  380.417846] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  380.417989] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  380.418135] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  380.422369] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.422453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.422540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.422630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.422814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.422900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.422982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.423064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.423149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.423231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.423315] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.423405] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.423495] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.423611] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  380.423745] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  380.423857] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  380.423949] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.424038] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.424144] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.424239] [drm:intel_power_well_disable [i915]] disabling DC off
>[  380.424324] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  380.424398] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  380.425048] [drm:intel_power_well_disable [i915]] disabling always-on
>[  380.426559] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.426641] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.426811] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.426890] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.426981] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.427064] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.427149] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.427226] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.427309] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.427324] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.427403] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.427415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.427498] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.427579] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.427662] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.427807] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.427888] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.427981] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.428065] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.428158] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.428244] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.428333] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.428417] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.428501] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.428619] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  380.428766] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.428850] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.429132] [drm:intel_power_well_enable [i915]] enabling always-on
>[  380.429203] [drm:intel_power_well_enable [i915]] enabling DC off
>[  380.429529] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  380.429641] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  380.429801] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  380.429876] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  380.430181] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  380.434414] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.434482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.434522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.434563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.434599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.434636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.434720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.434758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.434795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.434834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.434872] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.434913] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.435159] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.435229] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  380.435265] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  380.435526] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  380.436758] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  380.437311] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  380.437347] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  380.437400] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  380.437434] [drm:hsw_audio_config_update [i915]] using automatic N
>[  380.437524] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  380.437559] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  380.454394] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.454467] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.454678] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.455656] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.455785] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.455844] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.455898] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.455953] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.456011] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.456063] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.456118] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.456171] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.456184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.456235] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.456243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.456296] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.456351] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.456406] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.456463] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.456517] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.456578] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.456632] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.456723] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.456776] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.456831] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.456886] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.456941] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.457023] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  380.457094] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.457150] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.471080] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  380.471153] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  380.471264] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  380.487944] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  380.488036] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  380.488194] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  380.488365] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  380.492615] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.492691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.493027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.493109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.493181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.493254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.493328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.493402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.493476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.493549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.493622] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.493787] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.493866] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.493982] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  380.494060] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  380.494162] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  380.494252] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.494331] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.494427] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.494513] [drm:intel_power_well_disable [i915]] disabling DC off
>[  380.494589] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  380.494656] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  380.495312] [drm:intel_power_well_disable [i915]] disabling always-on
>[  380.496893] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.496975] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.497059] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.497135] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.497215] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.497294] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.497374] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.497450] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.497528] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.497541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.497617] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.497626] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.497789] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.497870] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.497951] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.498034] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.498114] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.498203] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.498283] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.498372] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.498453] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.498629] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.498769] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.498842] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.498953] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  380.499047] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.499122] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.499378] [drm:intel_power_well_enable [i915]] enabling always-on
>[  380.499442] [drm:intel_power_well_enable [i915]] enabling DC off
>[  380.499802] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  380.500395] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  380.500470] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  380.500571] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  380.501334] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  380.505586] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.505658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.505755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.505800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.505841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.505881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.505920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.505960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.506000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.506039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.506080] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.506123] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.506166] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.506240] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  380.506280] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  380.506661] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  380.507846] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  380.508404] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  380.508443] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  380.508501] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  380.508538] [drm:hsw_audio_config_update [i915]] using automatic N
>[  380.508636] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  380.508723] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  380.525496] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.525573] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.525877] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.526623] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.526682] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.526815] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.526873] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.526935] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.526994] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.527054] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.527111] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.527170] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.527183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.527239] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.527248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.527305] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.527364] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.527422] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.527482] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.527539] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.527606] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.527663] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.527759] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.527819] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.527880] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.527938] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.527998] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.528082] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  380.528157] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.528217] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.542179] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  380.542257] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  380.542373] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  380.559135] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  380.559235] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  380.559403] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  380.559586] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  380.563852] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.563934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.564022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.564112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.564193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.564273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.564353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.564434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.564515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.564594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.564674] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.564875] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.564966] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.565083] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  380.565170] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  380.565282] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  380.565377] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.565465] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.565571] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.565666] [drm:intel_power_well_disable [i915]] disabling DC off
>[  380.565816] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  380.565888] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  380.566478] [drm:intel_power_well_disable [i915]] disabling always-on
>[  380.568046] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.568128] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.568214] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.568290] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.568370] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.568449] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.568528] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.568605] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.568681] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.568773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.568860] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.568871] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.568952] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.569039] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.569126] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.569215] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.569300] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.569393] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.569475] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.569570] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.569654] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.569789] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.569864] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.569940] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.570050] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  380.570140] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.570215] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.570469] [drm:intel_power_well_enable [i915]] enabling always-on
>[  380.570533] [drm:intel_power_well_enable [i915]] enabling DC off
>[  380.570896] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  380.571484] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  380.571558] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  380.571657] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  380.572380] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  380.576664] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.576752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.576799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.576845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.576887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.576929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.576971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.577013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.577054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.577096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.577137] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.577180] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.577223] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.577297] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  380.577336] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  380.577607] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  380.579089] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  380.579633] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  380.579715] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  380.579778] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  380.580035] [drm:hsw_audio_config_update [i915]] using automatic N
>[  380.580139] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  380.580179] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  380.596794] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.596877] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.597105] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.598242] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.598306] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.598374] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.598433] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.598494] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.598556] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.598618] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.598677] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.598805] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.598817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.598881] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.598894] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.598959] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.599020] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.599087] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.599151] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.599217] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.599285] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.599350] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.599421] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.599490] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.599556] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.599623] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.599702] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.599797] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  380.600384] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.600450] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.613427] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  380.613509] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  380.613634] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  380.630630] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  380.630806] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  380.630974] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  380.631164] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  380.635429] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.635519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.635608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.635698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.635883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.636273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.636355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.636438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.636520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.636603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.636684] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.636861] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.636953] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.637074] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  380.637576] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  380.637692] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  380.637875] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.637965] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.638376] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.638471] [drm:intel_power_well_disable [i915]] disabling DC off
>[  380.638551] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  380.638624] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  380.639897] [drm:intel_power_well_disable [i915]] disabling always-on
>[  380.641674] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.641811] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.641898] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.641974] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.642056] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.642136] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.642216] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.642293] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.642369] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.642383] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.642459] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.642468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.642547] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.642624] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.642701] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.642892] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.642985] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.643086] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.643178] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.643282] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.643377] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.643476] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.643569] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.643668] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.643892] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  380.644027] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.644133] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.645535] [drm:intel_power_well_enable [i915]] enabling always-on
>[  380.645626] [drm:intel_power_well_enable [i915]] enabling DC off
>[  380.646412] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  380.646899] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  380.647277] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  380.647330] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  380.647565] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  380.651801] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.651871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.651910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.651950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.651985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.652020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.652054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.652089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.652124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.652159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.652194] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.652230] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.652266] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.652332] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  380.652366] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  380.652652] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  380.653897] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  380.654430] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  380.654464] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  380.654516] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  380.654548] [drm:hsw_audio_config_update [i915]] using automatic N
>[  380.654636] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  380.654713] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  380.671455] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.671529] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.672050] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.673042] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.673099] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.673157] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.673208] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.673262] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.673316] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.673369] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.673420] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.673471] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.673480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.673531] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.673537] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.673590] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.673641] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.673759] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.673817] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.673872] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.673936] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.673991] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.674056] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.674113] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.674172] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.674228] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.674286] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.674368] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  380.674438] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.674494] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.688192] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  380.688266] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  380.688375] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  380.705096] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  380.705188] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  380.705347] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  380.705519] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  380.709766] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.709842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.709922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.710003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.710077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.710150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.710223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.710297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.710371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.710444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.710517] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.710595] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.710672] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.710884] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  380.710960] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  380.711063] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  380.711151] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.711231] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.711327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.711414] [drm:intel_power_well_disable [i915]] disabling DC off
>[  380.711489] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  380.711558] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  380.712200] [drm:intel_power_well_disable [i915]] disabling always-on
>[  380.713583] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.713657] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.713818] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.713889] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.713967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.714041] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.714117] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.714190] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.714264] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.714278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.714349] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.714360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.714432] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.714507] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.714581] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.714658] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.714778] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.714858] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.714935] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.715013] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.715092] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.715170] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.715251] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.715327] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.715439] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  380.715535] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.715612] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.715918] [drm:intel_power_well_enable [i915]] enabling always-on
>[  380.715980] [drm:intel_power_well_enable [i915]] enabling DC off
>[  380.716302] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  380.716401] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  380.716475] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  380.716577] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  380.717006] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  380.721264] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.721348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.721435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.721525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.721606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.721685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.721869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.721921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.721977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.722032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.722087] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.722143] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.722197] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.722283] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  380.722333] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  380.722665] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  380.723907] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  380.724471] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  380.724514] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  380.724577] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  380.724618] [drm:hsw_audio_config_update [i915]] using automatic N
>[  380.725131] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  380.725175] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  380.741546] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.741619] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.741967] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.742659] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.742780] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.742841] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.742894] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.742950] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.743005] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.743060] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.743114] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.743169] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.743181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.743233] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.743241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.743294] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.743350] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.743405] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.743464] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.743518] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.743579] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.743632] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.743765] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.743835] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.743898] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.743964] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.744032] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.744129] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  380.744211] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.744278] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.758248] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  380.758329] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  380.758462] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  380.774913] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  380.775015] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  380.775183] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  380.775369] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  380.779601] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.779684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.779880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.779973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.780058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.780140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.780224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.780307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.780391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.780473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.780557] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.780646] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.780796] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.780922] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  380.781007] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  380.781119] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  380.781214] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.781302] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.781408] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.781501] [drm:intel_power_well_disable [i915]] disabling DC off
>[  380.781584] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  380.781658] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  380.782312] [drm:intel_power_well_disable [i915]] disabling always-on
>[  380.783928] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.784010] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.784094] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.784171] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.784251] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.784331] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.784411] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.784487] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.784563] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.784577] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.784653] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.784749] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.784833] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.784921] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.785005] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.785094] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.785176] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.785268] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.785350] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.785444] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.785531] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.785620] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.785723] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.785809] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.785929] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  380.786032] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.786114] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.786393] [drm:intel_power_well_enable [i915]] enabling always-on
>[  380.786463] [drm:intel_power_well_enable [i915]] enabling DC off
>[  380.786858] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  380.787404] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  380.787465] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  380.787553] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  380.787920] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  380.792112] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.792179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.792223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.792269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.792312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.792353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.792395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.792434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.792478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.792519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.792560] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.792604] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.792646] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.792776] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  380.792817] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  380.793093] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  380.794286] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  380.794872] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  380.794915] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  380.794977] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  380.795017] [drm:hsw_audio_config_update [i915]] using automatic N
>[  380.795130] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  380.795171] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  380.811953] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.812030] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.812249] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.813051] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.813110] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.813171] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.813228] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.813288] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.813346] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.813404] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.813460] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.813517] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.813528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.813583] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.813591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.813648] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.813797] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.813858] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.813923] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.813985] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.814057] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.814118] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.814185] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.814249] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.814315] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.814378] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.814441] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.814529] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  380.814606] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.814670] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.828637] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  380.828769] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  380.828898] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  380.845579] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  380.845681] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  380.845998] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  380.846201] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  380.850458] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.850551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.850648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.850852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.850941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.851032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.851121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.851213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.851305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.851400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.851491] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.851592] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.851690] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.851890] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  380.851985] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  380.852105] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  380.852208] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.852303] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.852417] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.852522] [drm:intel_power_well_disable [i915]] disabling DC off
>[  380.852613] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  380.852695] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  380.853360] [drm:intel_power_well_disable [i915]] disabling always-on
>[  380.855012] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.855103] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.855196] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.855281] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.855369] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.855457] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.855544] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.855629] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.855799] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.855817] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.855910] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.855931] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.856027] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.856119] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.856216] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.856309] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.856405] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.856503] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.856599] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.856697] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.856823] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.856882] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.856938] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.856993] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.857072] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  380.857140] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.857198] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.857395] [drm:intel_power_well_enable [i915]] enabling always-on
>[  380.857442] [drm:intel_power_well_enable [i915]] enabling DC off
>[  380.857796] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  380.858378] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  380.858431] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  380.858506] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  380.859085] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  380.863339] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.863383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.863428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.863474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.863516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.863556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.863597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.863639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.863734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.863776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.863819] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.863871] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.863916] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.864245] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  380.864287] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  380.864572] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  380.865909] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  380.866453] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  380.866494] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  380.866555] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  380.866593] [drm:hsw_audio_config_update [i915]] using automatic N
>[  380.866739] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  380.866780] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  380.883564] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.883646] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.883975] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.884839] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.884904] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.884969] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.885028] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.885093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.885156] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.885218] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.885279] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.885340] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.885353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.885412] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.885420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.885482] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.885544] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.885607] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.885669] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.885792] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.885863] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.885928] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.885996] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.886064] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.886128] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.886197] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.886259] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.886353] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  380.886434] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.886501] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.900207] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  380.900291] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  380.900423] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  380.917005] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  380.917105] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  380.917274] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  380.917459] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  380.921813] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.921909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.922007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.922106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.922196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.922286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.922376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.922466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.922555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.922644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.922819] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.922927] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.923030] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.923164] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  380.923256] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  380.923383] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  380.923490] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.923588] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.923706] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.923888] [drm:intel_power_well_disable [i915]] disabling DC off
>[  380.923986] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  380.924069] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  380.924678] [drm:intel_power_well_disable [i915]] disabling always-on
>[  380.926338] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.926431] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.926524] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.926609] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.926698] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.926877] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.926969] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.927065] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.927156] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.927180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.927266] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.927282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.927378] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.927470] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.927568] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.927662] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.927802] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.927885] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.927959] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.928039] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.928116] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.928198] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.928276] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.928348] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.928454] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  380.928549] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.928625] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.928907] [drm:intel_power_well_enable [i915]] enabling always-on
>[  380.928961] [drm:intel_power_well_enable [i915]] enabling DC off
>[  380.929271] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  380.929354] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  380.929412] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  380.929496] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  380.929825] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  380.934079] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.934124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.934173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.934222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.934266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.934309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.934353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.934394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.934438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.934480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.934525] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.934570] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.934615] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.934751] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  380.934983] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  380.935269] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  380.936628] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  380.937219] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  380.937262] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  380.937326] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  380.937366] [drm:hsw_audio_config_update [i915]] using automatic N
>[  380.937480] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  380.937522] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  380.954253] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.954331] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.954552] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.955314] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.955373] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.955434] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.955489] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.955546] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.955604] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.955661] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.955826] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.955895] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.955913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.955981] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.955995] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.956063] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.956137] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.956206] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.956279] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.956350] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.956426] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.956497] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.956576] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.956647] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.956753] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.956824] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.956893] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.956993] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  380.957078] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.957148] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.971021] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  380.971107] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  380.971249] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  380.987950] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  380.988051] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  380.988221] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  380.988408] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  380.992648] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  380.992801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  380.992890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  380.992978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  380.993060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  380.993141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  380.993222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  380.993303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  380.993384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  380.993465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  380.993545] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  380.993630] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  380.993794] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.993922] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  380.994007] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  380.994151] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  380.994257] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  380.994356] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  380.994473] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  380.994579] [drm:intel_power_well_disable [i915]] disabling DC off
>[  380.994671] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  380.994820] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  380.995424] [drm:intel_power_well_disable [i915]] disabling always-on
>[  380.997106] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  380.997197] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  380.997291] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  380.997376] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  380.997465] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.997553] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  380.997641] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  380.997822] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  380.997914] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.997937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.998027] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.998043] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  380.998139] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  380.998233] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  380.998328] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  380.998423] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.998518] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.998617] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  380.998735] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.998832] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  380.998926] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  380.999019] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  380.999111] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  380.999205] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  380.999343] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  380.999457] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  380.999550] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  380.999882] [drm:intel_power_well_enable [i915]] enabling always-on
>[  380.999929] [drm:intel_power_well_enable [i915]] enabling DC off
>[  381.000231] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  381.000302] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  381.000354] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  381.000427] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  381.000791] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  381.004939] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.004975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.005016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.005056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.005089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.005124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.005157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.005191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.005224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.005257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.005290] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.005327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.005362] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.005429] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  381.005461] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  381.005823] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  381.006802] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.007341] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  381.007374] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  381.007425] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  381.007457] [drm:hsw_audio_config_update [i915]] using automatic N
>[  381.007882] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.007918] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.024343] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.024415] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.024618] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.025349] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.025401] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.025455] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.025503] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.025553] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.025604] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.025654] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.025766] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.025816] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.025832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.025882] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.025892] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.025947] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.026000] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.026054] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.026108] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.026163] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.026221] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.026275] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.026326] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.026381] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.026431] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.026484] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.026533] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.026606] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  381.026668] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.026775] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.041107] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  381.041190] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  381.041324] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  381.058008] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  381.058099] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  381.058258] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  381.058429] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  381.062674] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.062814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.062896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.062979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.063053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.063127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.063201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.063275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.063349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.063423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.063496] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.063574] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.063651] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.063841] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  381.063918] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  381.064019] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  381.064105] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.064184] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.064277] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.064359] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.064433] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  381.064500] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  381.065168] [drm:intel_power_well_disable [i915]] disabling always-on
>[  381.066610] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.066693] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.066862] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.066942] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.067023] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.067106] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.067189] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.067271] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.067350] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.067368] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.067444] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.067456] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.067539] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.067619] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.067703] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.067838] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.067922] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.068013] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.068095] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.068190] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.068274] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.068364] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.068448] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.068538] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.068658] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  381.068818] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.068870] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.069060] [drm:intel_power_well_enable [i915]] enabling always-on
>[  381.069104] [drm:intel_power_well_enable [i915]] enabling DC off
>[  381.069397] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  381.069466] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  381.069516] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  381.069586] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  381.069892] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  381.074129] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.074174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.074222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.074270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.074314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.074356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.074398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.074440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.074485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.074527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.074572] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.074617] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.074662] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.074795] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  381.074837] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  381.075124] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  381.076332] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.076940] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  381.076985] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  381.077049] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  381.077092] [drm:hsw_audio_config_update [i915]] using automatic N
>[  381.077206] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.077250] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.093993] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.094062] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.094265] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.095087] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.095150] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.095216] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.095278] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.095340] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.095403] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.095465] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.095526] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.095586] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.095599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.095658] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.095725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.095795] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.095856] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.095922] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.095987] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.096052] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.096122] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.096188] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.096255] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.096325] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.096389] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.096455] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.096517] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.096613] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  381.096720] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.096788] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.110771] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  381.110853] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  381.110985] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  381.127675] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  381.127841] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  381.128009] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  381.128195] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  381.132448] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.132532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.132619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.132804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.132888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.132976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.133057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.133140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.133219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.133303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.133385] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.133476] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.133564] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.133685] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  381.133861] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  381.133990] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  381.134099] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.134194] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.134308] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.134409] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.134500] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  381.134581] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  381.135240] [drm:intel_power_well_disable [i915]] disabling always-on
>[  381.136869] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.136960] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.137054] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.137139] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.137227] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.137314] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.137402] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.137487] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.137572] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.137587] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.137672] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.137767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.137866] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.137954] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.138050] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.138145] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.138239] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.138338] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.138430] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.138527] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.138623] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.138734] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.138827] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.138920] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.139058] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  381.139173] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.139262] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.139566] [drm:intel_power_well_enable [i915]] enabling always-on
>[  381.139641] [drm:intel_power_well_enable [i915]] enabling DC off
>[  381.140035] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  381.140156] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  381.140245] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  381.140365] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  381.140816] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  381.145072] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.145116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.145161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.145207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.145247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.145288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.145328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.145368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.145410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.145449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.145492] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.145535] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.145578] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.145652] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  381.145743] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  381.146015] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  381.147185] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.147766] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  381.147809] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  381.147870] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  381.147910] [drm:hsw_audio_config_update [i915]] using automatic N
>[  381.148021] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.148062] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.164853] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.164918] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.165115] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.165855] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.165915] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.165978] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.166036] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.166097] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.166155] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.166216] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.166273] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.166331] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.166343] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.166400] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.166408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.166465] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.166524] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.166583] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.166643] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.166746] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.166812] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.166873] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.166941] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.167001] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.167066] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.167127] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.167190] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.167276] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  381.167353] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.167416] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.181562] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  381.181643] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  381.181974] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  381.198963] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  381.199068] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  381.199237] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  381.199424] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  381.203717] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.203894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.203993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.204093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.204183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.204273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.204362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.204452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.204542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.204632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.204802] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.204905] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.205011] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.205142] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  381.205625] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  381.205781] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  381.205892] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.206321] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.206441] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.206549] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.206641] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  381.206790] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  381.208180] [drm:intel_power_well_disable [i915]] disabling always-on
>[  381.210103] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.210197] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.210292] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.210377] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.210466] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.210554] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.210642] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.210819] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.210908] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.210932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.211020] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.211037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.211134] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.211231] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.211327] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.211422] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.211521] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.211619] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.211734] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.211833] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.211927] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.212024] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.212867] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.212959] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.213105] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  381.213223] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.213316] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.213581] [drm:intel_power_well_enable [i915]] enabling always-on
>[  381.213661] [drm:intel_power_well_enable [i915]] enabling DC off
>[  381.214076] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  381.214128] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  381.214164] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  381.214217] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  381.214507] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  381.218796] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.218871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.218910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.218949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.218984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.219019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.219054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.219089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.219124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.219158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.219193] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.219229] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.219265] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.219333] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  381.219368] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  381.219652] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  381.220666] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.221245] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  381.221280] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  381.221332] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  381.221364] [drm:hsw_audio_config_update [i915]] using automatic N
>[  381.221450] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.221483] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.238344] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.238392] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.238559] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.239105] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.239140] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.239177] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.239209] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.239243] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.239278] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.239312] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.239344] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.239376] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.239384] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.239416] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.239420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.239452] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.239485] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.239518] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.239550] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.239582] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.239619] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.239650] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.239731] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.239769] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.239804] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.239841] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.239876] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.239928] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  381.239974] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.240011] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.255026] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  381.255097] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  381.255216] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  381.271853] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  381.271921] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  381.272053] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  381.272185] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  381.276410] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.276468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.276528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.276589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.276644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.276771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.276828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.276888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.276945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.277003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.277057] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.277119] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.277178] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.277262] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  381.277319] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  381.277396] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  381.277462] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.277521] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.277593] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.277657] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.277806] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  381.277879] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  381.278467] [drm:intel_power_well_disable [i915]] disabling always-on
>[  381.279448] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.279522] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.279599] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.279669] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.279818] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.279904] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.279982] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.280059] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.280135] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.280156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.280227] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.280237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.280314] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.280388] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.280463] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.280537] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.280611] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.280690] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.280809] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.280896] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.280975] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.281053] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.281129] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.281206] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.281316] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  381.281411] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.281486] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.281790] [drm:intel_power_well_enable [i915]] enabling always-on
>[  381.281860] [drm:intel_power_well_enable [i915]] enabling DC off
>[  381.282180] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  381.282282] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  381.282355] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  381.282456] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  381.282842] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  381.286764] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.286819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.286875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.286932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.286984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.287035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.287086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.287136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.287189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.287238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.287291] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.287345] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.287398] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.287484] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  381.287533] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  381.287877] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  381.289252] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.289858] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  381.289905] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  381.289971] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  381.290012] [drm:hsw_audio_config_update [i915]] using automatic N
>[  381.290126] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.290169] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.306970] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.307054] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.307282] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.308148] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.308213] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.308280] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.308341] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.308405] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.308468] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.308530] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.308591] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.308652] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.308732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.308798] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.308811] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.308876] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.308941] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.309008] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.309075] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.309143] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.309214] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.309281] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.309350] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.309417] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.309478] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.309543] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.309605] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.309741] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  381.309817] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.309879] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.323667] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  381.323806] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  381.323937] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  381.340602] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  381.340703] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  381.340982] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  381.341168] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  381.345422] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.345506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.345593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.345683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.345863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.345947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.346034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.346120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.346207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.346287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.346369] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.346456] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.346546] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.346665] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  381.346841] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  381.346971] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  381.347075] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.347171] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.347285] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.347390] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.347482] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  381.347565] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  381.348222] [drm:intel_power_well_disable [i915]] disabling always-on
>[  381.349829] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.349919] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.350013] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.350098] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.350187] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.350275] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.350363] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.350448] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.350533] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.350547] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.350632] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.350728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.350827] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.351039] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.351127] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.351217] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.351303] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.351399] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.351485] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.351583] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.351639] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.351733] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.351790] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.351849] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.351933] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  381.352004] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.352058] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.352249] [drm:intel_power_well_enable [i915]] enabling always-on
>[  381.352295] [drm:intel_power_well_enable [i915]] enabling DC off
>[  381.352599] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  381.352716] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  381.352773] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  381.352850] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  381.353163] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  381.357403] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.357448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.357495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.357543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.357587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.357629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.357726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.357769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.357816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.357860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.357907] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.357959] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.358007] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.358084] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  381.358126] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  381.358409] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  381.359614] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.360220] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  381.360263] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  381.360326] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  381.360367] [drm:hsw_audio_config_update [i915]] using automatic N
>[  381.360477] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.360519] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.377269] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.377342] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.377552] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.378391] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.378450] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.378511] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.378566] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.378624] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.378681] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.378802] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.378864] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.378923] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.378939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.378996] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.379006] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.379067] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.379128] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.379191] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.379251] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.379311] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.379376] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.379439] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.379503] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.379561] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.379621] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.379682] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.379806] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.379896] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  381.379972] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.380033] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.394035] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  381.394121] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  381.394261] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  381.410966] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  381.411068] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  381.411237] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  381.411422] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  381.415698] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.415864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.415961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.416060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.416150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.416240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.416329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.416419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.416508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.416597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.416686] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.416866] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.416970] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.417104] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  381.417196] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  381.417316] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  381.417419] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.417514] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.417628] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.417795] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.417892] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  381.417977] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  381.418576] [drm:intel_power_well_disable [i915]] disabling always-on
>[  381.420261] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.420353] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.420448] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.420536] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.420625] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.420749] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.420842] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.420939] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.421034] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.421056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.421142] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.421158] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.421251] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.421346] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.421443] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.421538] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.421635] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.421781] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.421875] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.421969] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.422065] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.422156] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.422247] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.422337] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.422466] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  381.422575] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.422664] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.422977] [drm:intel_power_well_enable [i915]] enabling always-on
>[  381.423030] [drm:intel_power_well_enable [i915]] enabling DC off
>[  381.423336] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  381.423421] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  381.423485] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  381.423576] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  381.423891] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  381.428132] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.428175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.428220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.428266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.428308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.428348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.428388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.428428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.428471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.428511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.428554] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.428597] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.428639] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.428767] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  381.428807] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  381.429082] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  381.430225] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.430807] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  381.430849] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  381.430908] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  381.430947] [drm:hsw_audio_config_update [i915]] using automatic N
>[  381.431058] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.431100] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.447879] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.447936] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.448123] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.448786] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.448854] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.448922] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.448982] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.449042] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.449099] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.449156] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.449211] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.449270] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.449282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.449339] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.449347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.449404] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.449463] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.449521] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.449582] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.449639] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.449743] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.449804] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.449866] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.449929] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.449990] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.450052] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.450111] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.450202] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  381.450277] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.450339] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.464602] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  381.464683] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  381.464983] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  381.481645] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  381.481799] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  381.481957] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  381.482126] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  381.486369] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.486453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.486542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.486633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.486815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.486899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.486986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.487072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.487154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.487235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.487317] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.487405] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.487494] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.487617] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  381.487789] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  381.487917] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  381.488022] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.488117] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.488231] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.488336] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.488428] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  381.488510] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  381.489166] [drm:intel_power_well_disable [i915]] disabling always-on
>[  381.490777] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.490868] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.490961] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.491046] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.491135] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.491223] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.491311] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.491396] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.491480] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.491493] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.491578] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.491588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.491676] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.491843] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.491938] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.492032] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.492128] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.492229] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.492327] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.492428] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.492524] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.492619] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.492733] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.492823] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.492957] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  381.493070] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.493161] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.493472] [drm:intel_power_well_enable [i915]] enabling always-on
>[  381.493547] [drm:intel_power_well_enable [i915]] enabling DC off
>[  381.493937] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  381.494520] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  381.494607] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  381.494785] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  381.495204] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  381.499447] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.499524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.499562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.499601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.499636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.499718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.499752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.499789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.499824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.499859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.499895] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.499934] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.499972] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.500039] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  381.500073] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  381.500361] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  381.501380] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.501950] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  381.501984] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  381.502037] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  381.502071] [drm:hsw_audio_config_update [i915]] using automatic N
>[  381.502170] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.502205] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.519024] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.519072] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.519238] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.520181] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.520236] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.520295] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.520346] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.520401] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.520454] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.520508] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.520559] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.520610] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.520620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.520671] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.521246] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.521308] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.521360] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.521414] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.521468] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.521519] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.521580] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.521633] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.522101] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.522154] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.522208] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.522261] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.522315] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.522395] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  381.522464] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.522518] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.535776] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  381.535848] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  381.535964] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  381.552615] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  381.552972] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  381.553143] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  381.553331] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  381.557591] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.557674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.558072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.558164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.558246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.558328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.558409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.558490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.558570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.558651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.559334] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.559426] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.559514] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.559631] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  381.560085] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  381.560197] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  381.560292] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.560379] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.560479] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.560570] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.560653] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  381.561301] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  381.562503] [drm:intel_power_well_disable [i915]] disabling always-on
>[  381.564223] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.564307] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.564391] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.564468] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.564548] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.564627] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.565253] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.565333] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.565412] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.565428] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.565505] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.565516] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.565596] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.565676] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.566359] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.566439] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.566516] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.566600] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.566677] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.567212] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.567294] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.567374] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.567454] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.567534] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.567656] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  381.568246] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.568327] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.568600] [drm:intel_power_well_enable [i915]] enabling always-on
>[  381.568667] [drm:intel_power_well_enable [i915]] enabling DC off
>[  381.569362] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  381.569411] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  381.569444] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  381.569494] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  381.569906] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  381.574129] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.574207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.574245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.574284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.574320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.574353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.574387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.574420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.574457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.574490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.574527] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.574563] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.574598] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.575080] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  381.575114] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  381.575368] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  381.576471] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.577095] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  381.577128] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  381.577179] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  381.577212] [drm:hsw_audio_config_update [i915]] using automatic N
>[  381.577304] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.577338] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.594161] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.594235] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.594444] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.595424] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.595479] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.595537] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.595588] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.595641] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.596019] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.596074] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.596127] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.596178] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.596189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.596239] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.596247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.596300] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.596354] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.596406] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.596459] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.596513] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.596571] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.596624] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.597364] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.597419] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.597473] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.597526] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.597580] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.597664] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  381.598089] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.598144] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.610911] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  381.610984] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  381.611099] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  381.627801] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  381.627893] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  381.628051] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  381.628222] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  381.632487] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.632571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.632659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.633134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.633216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.633296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.633379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.633460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.633541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.633622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.633702] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.634393] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.634481] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.634603] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  381.634686] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  381.635166] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  381.635262] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.635349] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.635452] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.635542] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.635623] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  381.636207] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  381.637411] [drm:intel_power_well_disable [i915]] disabling always-on
>[  381.639109] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.639191] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.639276] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.639352] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.639433] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.639512] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.639591] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.639667] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.640407] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.640423] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.640499] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.640511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.640590] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.640671] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.641235] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.641316] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.641393] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.641477] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.641553] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.641637] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.642228] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.642312] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.642390] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.642471] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.642596] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  381.642697] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.643121] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.643256] [drm:intel_power_well_enable [i915]] enabling always-on
>[  381.643285] [drm:intel_power_well_enable [i915]] enabling DC off
>[  381.643570] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  381.643619] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  381.643651] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  381.643995] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  381.644223] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  381.648449] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.648525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.648563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.648602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.648637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.648879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.648914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.648948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.648983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.649017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.649052] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.649091] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.649128] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.649195] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  381.649227] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  381.649479] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  381.650822] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.651354] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  381.651389] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  381.651440] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  381.651472] [drm:hsw_audio_config_update [i915]] using automatic N
>[  381.651566] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.651599] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.668431] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.668478] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.668644] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.669610] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.669661] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.669922] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.669971] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.670023] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.670074] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.670123] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.670172] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.670219] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.670228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.670276] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.670283] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.670333] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.670381] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.670430] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.670480] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.670528] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.670582] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.670630] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.671455] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.671507] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.671557] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.671608] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.671657] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.672015] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  381.672081] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.672133] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.685127] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  381.685193] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  381.685305] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  381.701984] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  381.702071] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  381.702221] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  381.702381] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  381.706648] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.706800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.706889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.706978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.707059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.707140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.707221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.707302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.707383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.707464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.707544] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.707630] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.708601] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.708915] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  381.708999] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  381.709110] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  381.709207] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.709295] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.709399] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.709493] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.709575] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  381.709645] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  381.711538] [drm:intel_power_well_disable [i915]] disabling always-on
>[  381.713179] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.713261] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.713346] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.713422] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.713502] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.713581] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.713661] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.714352] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.714431] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.714446] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.714522] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.714534] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.714613] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.714693] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.715334] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.715415] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.715492] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.715577] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.715653] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.716198] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.716280] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.716360] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.716441] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.716521] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.716643] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  381.717251] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.717351] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.717487] [drm:intel_power_well_enable [i915]] enabling always-on
>[  381.717515] [drm:intel_power_well_enable [i915]] enabling DC off
>[  381.717976] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  381.718421] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  381.718454] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  381.718505] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  381.718911] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  381.723138] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.723212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.723251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.723290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.723325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.723358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.723395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.723427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.723464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.723497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.723533] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.723570] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.723605] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.724101] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  381.724136] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  381.724393] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  381.725498] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.726121] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  381.726155] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  381.726206] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  381.726238] [drm:hsw_audio_config_update [i915]] using automatic N
>[  381.726331] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.726365] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.743193] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.743240] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.743404] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.744328] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.744384] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.744442] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.744493] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.744546] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.744602] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.744655] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.745108] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.745161] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.745172] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.745223] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.745231] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.745283] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.745337] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.745389] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.745443] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.745497] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.745558] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.745610] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.745667] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.746370] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.746423] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.746476] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.746530] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.746613] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  381.747002] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.747058] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.759902] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  381.759973] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  381.760091] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  381.776712] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  381.777062] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  381.777221] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  381.777392] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  381.781662] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.781814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.781903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.781991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.782073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.782154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.782235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.782316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.782397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.782478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.782558] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.782644] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.783616] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.783928] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  381.784012] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  381.784123] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  381.784219] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.784308] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.784411] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.784505] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.784587] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  381.784660] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  381.786565] [drm:intel_power_well_disable [i915]] disabling always-on
>[  381.788343] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.788425] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.788511] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.788587] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.788667] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.789350] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.789441] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.789529] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.789617] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.789633] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.790207] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.790219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.790307] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.790393] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.790480] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.790568] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.790654] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.791365] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.791454] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.791550] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.791637] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.792035] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.792069] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.792103] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.792160] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  381.792209] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.792243] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.792380] [drm:intel_power_well_enable [i915]] enabling always-on
>[  381.792408] [drm:intel_power_well_enable [i915]] enabling DC off
>[  381.792976] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  381.793316] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  381.793348] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  381.793399] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  381.793654] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  381.798008] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.798044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.798083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.798122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.798157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.798191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.798226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.798259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.798293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.798328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.798363] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.798399] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.798435] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.798501] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  381.798535] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  381.799233] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  381.800281] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.800906] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  381.800940] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  381.800991] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  381.801023] [drm:hsw_audio_config_update [i915]] using automatic N
>[  381.801117] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.801151] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.817962] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.818019] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.818199] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.819128] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.819183] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.819240] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.819291] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.819345] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.819400] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.819453] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.819504] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.819555] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.819565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.819616] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.819622] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.819675] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.820396] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.820450] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.820505] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.820559] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.820619] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.820672] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.821065] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.821118] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.821170] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.821223] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.821276] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.821359] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  381.821430] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.821483] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.834682] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  381.834807] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  381.834924] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  381.851563] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  381.851655] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  381.852130] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  381.852301] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  381.856562] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.856645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.857016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.857105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.857186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.857267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.857347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.857429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.857509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.857590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.857670] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.858460] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.858548] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.858670] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  381.859075] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  381.859188] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  381.859283] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.859369] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.859470] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.859561] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.859643] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  381.860303] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  381.861506] [drm:intel_power_well_disable [i915]] disabling always-on
>[  381.863172] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.863256] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.863340] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.863417] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.863497] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.863576] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.863656] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.864345] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.864426] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.864441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.864517] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.864529] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.864608] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.864688] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.865328] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.865406] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.865483] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.865569] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.865645] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.866193] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.866275] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.866354] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.866435] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.866515] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.866636] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  381.867235] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.867315] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.867586] [drm:intel_power_well_enable [i915]] enabling always-on
>[  381.867653] [drm:intel_power_well_enable [i915]] enabling DC off
>[  381.868356] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  381.868405] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  381.868439] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  381.868489] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  381.868914] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  381.873139] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.873216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.873254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.873294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.873329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.873362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.873398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.873431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.873468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.873501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.873537] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.873574] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.873609] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.874106] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  381.874140] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  381.874398] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  381.875506] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.876132] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  381.876165] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  381.876217] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  381.876249] [drm:hsw_audio_config_update [i915]] using automatic N
>[  381.876342] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.876375] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.893204] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.893253] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.893419] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.894362] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.894414] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.894468] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.894516] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.894566] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.894617] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.894667] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.895106] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.895156] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.895166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.895214] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.895221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.895271] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.895321] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.895370] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.895421] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.895472] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.895525] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.895575] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.895630] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.896285] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.896336] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.896387] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.896437] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.896513] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  381.896576] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.896627] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.909896] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  381.909962] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  381.910073] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  381.926552] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  381.926617] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  381.926968] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  381.927097] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  381.931327] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.931380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.931438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.931496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.931547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.931599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.931650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.932129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.932182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.932234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.932285] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.932343] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.932398] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.932478] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  381.932530] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  381.932604] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  381.932666] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.933408] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.933496] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.933577] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.933644] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  381.934039] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  381.934619] [drm:intel_power_well_disable [i915]] disabling always-on
>[  381.936097] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.936166] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.936238] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.936302] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.936369] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.936436] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.936503] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.936567] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.936630] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.937260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.937337] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.937348] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.937417] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.937484] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.937549] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.937617] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.937684] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.938297] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.938362] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.938431] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.938497] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.938564] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.938630] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.939164] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.939271] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  381.939358] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.939427] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.939672] [drm:intel_power_well_enable [i915]] enabling always-on
>[  381.940125] [drm:intel_power_well_enable [i915]] enabling DC off
>[  381.940439] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  381.940532] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  381.940597] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  381.941053] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  381.941347] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  381.945583] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  381.945656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  381.945840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  381.945878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  381.945913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  381.945948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  381.945983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  381.946018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  381.946053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  381.946086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  381.946122] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  381.946158] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  381.946194] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.946261] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  381.946294] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  381.946547] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  381.948005] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  381.948540] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  381.948575] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  381.948626] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  381.948858] [drm:hsw_audio_config_update [i915]] using automatic N
>[  381.948958] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  381.948992] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  381.965620] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  381.965909] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  381.966123] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  381.967049] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  381.967104] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  381.967162] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  381.967213] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  381.967266] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  381.967321] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  381.967373] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  381.967424] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  381.967475] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  381.967485] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.967536] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  381.967542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  381.967595] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  381.967646] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  381.968434] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  381.968491] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.968544] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  381.968601] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  381.968655] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  381.969030] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  381.969083] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  381.969136] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  381.969189] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  381.969243] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  381.969325] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  381.969395] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  381.969449] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  381.982336] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  381.982408] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  381.982526] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  381.999106] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  381.999199] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  381.999358] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  381.999531] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  382.003799] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.003894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.003992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.004092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.004182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.004272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.004361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.004451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.004540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.004630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.004831] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.004928] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.005029] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.005163] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  382.005254] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.005377] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.005484] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.005582] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.005699] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.005851] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.005940] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  382.006023] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  382.006626] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.008265] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.008356] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.008449] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.008535] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.008624] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.008801] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.008892] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.008982] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.009072] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.009089] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.009177] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.009190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.009278] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.009370] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.009460] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.009553] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.009642] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.009784] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.009873] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.009968] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.010059] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.010153] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.010244] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.010336] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.010465] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  382.010581] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.010673] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.010958] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.011009] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.011315] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  382.011396] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.011454] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.011535] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  382.011885] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  382.016136] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.016214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.016251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.016290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.016325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.016359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.016395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.016428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.016464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.016497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.016534] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.016570] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.016605] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.016713] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  382.016749] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  382.017037] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  382.018031] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.018564] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  382.018599] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  382.018650] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  382.018720] [drm:hsw_audio_config_update [i915]] using automatic N
>[  382.018819] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.018853] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.035627] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.035706] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.035869] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.036485] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.036541] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.036598] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.036649] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.036765] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.036827] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.036884] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.036943] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.036999] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.037015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.037068] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.037079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.037136] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.037191] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.037251] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.037309] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.037366] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.037425] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.037478] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.037537] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.037594] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.037646] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.037735] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.037792] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.037874] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  382.037942] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.037998] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.052343] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.052415] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.052524] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.069123] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.069212] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  382.069370] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  382.069536] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  382.073785] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.073863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.073943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.074025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.074097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.074172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.074246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.074318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.074393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.074467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.074539] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.074617] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.074694] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.074890] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  382.074970] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.075070] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.075154] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.075231] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.075325] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.075407] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.075484] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  382.075553] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  382.076228] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.077827] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.077920] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.078015] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.078103] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.078195] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.078284] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.078373] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.078461] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.078549] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.078565] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.078650] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.078748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.078839] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.078934] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.079026] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.079123] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.079216] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.079321] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.079414] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.079517] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.079607] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.079705] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.079844] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.079936] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.080072] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  382.080181] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.080274] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.080577] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.080652] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.081044] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  382.081161] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.081245] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.081366] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  382.081809] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  382.086092] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.086167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.086206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.086245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.086280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.086315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.086348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.086383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.086418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.086450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.086487] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.086523] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.086559] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.086624] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  382.086657] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  382.086954] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  382.087968] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.088500] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  382.088535] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  382.088587] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  382.088619] [drm:hsw_audio_config_update [i915]] using automatic N
>[  382.088744] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.088777] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.105559] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.105630] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.105913] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.106568] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.106622] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.106739] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.106794] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.106852] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.106911] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.106968] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.107022] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.107077] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.107092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.107144] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.107155] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.107213] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.107269] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.107326] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.107378] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.107437] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.107495] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.107550] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.107604] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.107659] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.107745] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.107803] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.107859] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.107941] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  382.108006] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.108060] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.122279] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.122353] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.122459] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.139038] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.139127] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  382.139284] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  382.139457] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  382.143774] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.143859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.143946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.144036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.144117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.144197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.144278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.144359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.144439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.144520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.144599] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.144685] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.144845] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.144964] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  382.145051] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.145161] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.145253] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.145337] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.145440] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.145530] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.145613] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  382.145687] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  382.146329] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.147899] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.147983] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.148068] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.148148] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.148230] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.148311] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.148391] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.148470] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.148548] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.148776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.148859] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.148871] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.148956] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.149034] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.149114] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.149194] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.149273] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.149357] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.149436] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.149520] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.149601] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.149680] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.149819] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.149908] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.150031] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  382.150135] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.150215] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.150495] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.150562] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.150946] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  382.151517] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.151590] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.151742] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  382.152109] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  382.155425] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.155503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.155583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.155664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.155832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.155908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.155944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.155981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.156018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.156055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.156092] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.156136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.156178] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.156249] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  382.156287] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  382.156553] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  382.157616] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.158191] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  382.158229] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  382.158285] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  382.158320] [drm:hsw_audio_config_update [i915]] using automatic N
>[  382.158413] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.158449] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.175256] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.175308] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.175482] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.176090] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.176130] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.176172] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.176209] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.176248] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.176287] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.176326] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.176362] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.176398] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.176407] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.176443] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.176448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.176485] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.176522] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.176560] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.176599] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.176635] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.176727] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.176767] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.176810] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.176852] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.176895] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.176938] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.176978] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.177037] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  382.177089] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.177131] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.191945] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.192020] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.192137] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.208625] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.208723] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  382.208859] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  382.208995] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  382.213218] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.213278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.213341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.213406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.213465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.213523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.213581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.213639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.213775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.213835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.213897] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.213962] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.214030] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.214120] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  382.214179] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.214259] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.214326] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.214388] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.214462] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.214531] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.214591] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  382.214643] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  382.215307] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.216863] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.216944] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.217028] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.217105] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.217185] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.217265] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.217345] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.217421] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.217498] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.217511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.217587] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.217596] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.217675] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.217829] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.217914] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.218002] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.218089] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.218178] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.218264] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.218350] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.218437] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.218522] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.218607] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.218691] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.218850] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  382.218959] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.219046] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.219322] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.219391] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.219772] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  382.220351] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.220431] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.220544] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  382.220981] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  382.225250] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.225320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.225363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.225407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.225447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.225487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.225524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.225562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.225603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.225641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.225732] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.225778] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.225823] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.225897] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  382.225935] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  382.226212] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  382.227342] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.227937] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  382.227978] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  382.228036] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  382.228075] [drm:hsw_audio_config_update [i915]] using automatic N
>[  382.228172] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.228212] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.244980] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.245032] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.245205] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.245874] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.245934] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.245995] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.246049] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.246112] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.246171] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.246231] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.246288] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.246347] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.246359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.246416] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.246424] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.246483] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.246541] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.246600] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.246659] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.246761] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.246827] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.246887] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.246954] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.247018] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.247080] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.247146] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.247206] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.247297] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  382.247372] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.247434] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.261762] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.261836] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.261950] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.278583] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.278672] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  382.278967] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  382.279150] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  382.283411] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.283494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.283582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.283671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.283852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.283936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.284022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.284107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.284188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.284267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.284349] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.284440] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.284528] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.284648] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  382.284792] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.284904] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.284998] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.285082] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.285185] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.285280] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.285360] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  382.285435] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  382.286074] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.287554] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.287638] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.287806] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.287889] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.287975] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.288061] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.288145] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.288232] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.288313] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.288334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.288411] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.288424] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.288510] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.288591] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.288674] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.288798] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.288876] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.288961] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.289038] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.289127] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.289206] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.289290] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.289372] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.289455] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.289574] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  382.289677] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.289805] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.289988] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.290028] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.290323] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  382.290389] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.290437] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.290504] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  382.290787] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  382.295025] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.295071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.295119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.295167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.295211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.295255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.295297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.295340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.295384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.295428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.295471] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.295516] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.295561] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.295638] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  382.295739] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  382.296026] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  382.297233] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.297835] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  382.297882] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  382.297947] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  382.297988] [drm:hsw_audio_config_update [i915]] using automatic N
>[  382.298095] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.298140] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.314876] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.314933] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.315118] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.315902] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.315961] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.316024] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.316081] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.316143] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.316201] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.316261] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.316319] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.316377] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.316389] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.316446] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.316455] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.316513] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.316571] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.316630] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.316755] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.316820] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.316892] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.316956] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.317026] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.317092] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.317162] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.317227] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.317295] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.317387] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  382.317464] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.317526] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.331628] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.331764] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.331886] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.348558] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.348655] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  382.348934] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  382.349118] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  382.353402] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.353494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.353591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.353690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.353995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.354083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.354173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.354263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.354358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.354449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.354541] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.354643] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.354798] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.354930] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  382.355025] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.355145] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.355248] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.355342] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.355456] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.355558] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.355651] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  382.355795] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  382.356400] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.358007] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.358098] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.358191] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.358276] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.358365] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.358452] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.358540] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.358625] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.358746] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.358768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.358863] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.358876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.358975] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.359068] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.359162] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.359256] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.359353] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.359454] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.359550] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.359647] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.359802] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.359850] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.359903] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.359952] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.360025] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  382.360086] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.360133] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.360311] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.360351] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.360644] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  382.360746] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.360796] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.360868] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  382.361161] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  382.365403] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.365446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.365491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.365537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.365579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.365618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.365659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.365752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.365795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.365838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.365883] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.365932] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.365978] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.366052] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  382.366092] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  382.366367] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  382.367514] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.368096] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  382.368139] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  382.368200] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  382.368240] [drm:hsw_audio_config_update [i915]] using automatic N
>[  382.368343] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.368385] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.385134] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.385189] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.385366] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.386144] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.386209] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.386275] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.386336] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.386400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.386462] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.386524] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.386585] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.386645] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.386717] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.386785] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.386798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.386865] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.386928] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.386995] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.387065] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.387132] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.387202] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.387268] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.387337] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.387405] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.387469] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.387536] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.387601] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.387726] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  382.387806] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.387867] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.401946] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.402029] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.402152] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.418566] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.418665] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  382.418952] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  382.419169] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  382.423456] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.423549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.423646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.423853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.423942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.424032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.424120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.424215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.424306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.424400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.424492] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.424593] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.424687] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.424882] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  382.424979] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.425106] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.425209] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.425304] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.425418] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.425519] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.425610] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  382.425692] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  382.426350] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.428039] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.428130] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.428224] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.428309] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.428397] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.428486] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.428574] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.428660] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.428831] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.428853] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.428941] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.428960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.429055] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.429148] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.429245] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.429339] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.429436] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.429535] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.429631] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.429788] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.429842] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.429896] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.429950] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.430006] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.430083] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  382.430148] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.430197] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.430385] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.430429] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.430766] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  382.430840] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.430888] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.430960] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  382.431260] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  382.435505] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.435580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.435620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.435659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.435738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.435773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.435810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.435844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.435878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.435911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.435946] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.435985] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.436022] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.436091] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  382.436125] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  382.436378] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  382.437369] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.437938] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  382.437974] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  382.438025] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  382.438059] [drm:hsw_audio_config_update [i915]] using automatic N
>[  382.438149] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.438184] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.454974] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.455046] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.455255] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.456048] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.456104] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.456161] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.456214] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.456270] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.456324] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.456378] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.456431] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.456483] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.456494] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.456545] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.456552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.456605] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.456659] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.456754] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.456811] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.456866] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.456927] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.456982] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.457038] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.457095] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.457150] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.457203] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.457255] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.457335] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  382.457402] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.457458] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.471768] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.471840] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.471948] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.488572] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.488663] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  382.488959] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  382.489144] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  382.493395] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.493479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.493568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.493657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.493830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.493914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.493995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.494076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.494156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.494237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.494320] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.494412] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.494500] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.494620] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  382.494735] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.494851] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.494950] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.495044] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.495145] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.495236] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.495318] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  382.495389] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  382.496035] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.497497] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.497578] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.497663] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.497820] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.497905] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.497993] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.498077] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.498159] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.498240] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.498263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.498340] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.498353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.498439] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.498519] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.498601] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.498685] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.498849] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.498921] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.498987] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.499062] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.499130] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.499209] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.499260] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.499311] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.499383] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  382.499447] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.499499] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.499719] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.499769] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.500064] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  382.500135] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.500186] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.500258] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  382.500552] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  382.504340] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.504393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.504449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.504506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.504556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.504607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.504658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.504778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.504833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.504888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.504943] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.505004] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.505058] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.505147] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  382.505208] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  382.505494] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  382.506721] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.507284] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  382.507327] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  382.507390] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  382.507431] [drm:hsw_audio_config_update [i915]] using automatic N
>[  382.507531] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.507572] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.524355] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.524414] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.524599] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.525830] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.525896] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.525962] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.526021] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.526084] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.526144] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.526205] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.526264] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.526323] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.526335] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.526393] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.526400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.526461] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.526520] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.526580] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.526639] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.526775] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.526842] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.526906] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.526971] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.527034] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.527098] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.527161] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.527224] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.527316] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  382.527394] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.527458] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.541074] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.541159] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.541280] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.557948] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.558048] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  382.558215] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  382.558401] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  382.562692] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.562863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.562962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.563061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.563151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.563240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.563329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.563419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.563509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.563598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.563687] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.563879] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.563986] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.564120] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  382.564213] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.564334] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.564441] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.564539] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.564656] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.564822] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.564919] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  382.565005] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  382.565610] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.567225] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.567315] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.567409] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.567494] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.567583] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.567670] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.567845] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.567936] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.568035] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.568056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.568147] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.568163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.568259] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.568351] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.568450] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.568543] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.568638] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.568781] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.568873] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.568975] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.569074] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.569168] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.569258] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.569356] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.569500] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  382.569595] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.569670] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.569951] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.570001] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.570305] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  382.570385] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.570442] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.570523] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  382.570877] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  382.575133] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.575176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.575222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.575268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.575310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.575351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.575391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.575431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.575474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.575513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.575556] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.575600] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.575642] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.575768] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  382.575810] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  382.576084] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  382.577253] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.577833] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  382.577876] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  382.577937] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  382.577977] [drm:hsw_audio_config_update [i915]] using automatic N
>[  382.578081] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.578122] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.594887] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.594944] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.595124] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.595892] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.595956] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.596025] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.596086] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.596153] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.596216] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.596280] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.596342] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.596404] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.596417] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.596478] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.596487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.596550] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.596613] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.596678] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.596784] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.596853] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.596926] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.596996] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.597065] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.597131] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.597196] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.597263] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.597330] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.597421] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  382.597500] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.597566] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.611631] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.611771] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.611895] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.628556] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.628655] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  382.628972] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  382.629178] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  382.633458] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.633550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.633646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.633850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.633939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.634033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.634124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.634217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.634308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.634401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.634491] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.634593] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.634690] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.634879] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  382.634976] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.635101] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.635207] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.635305] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.635422] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.635525] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.635616] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  382.635697] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  382.636353] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.638022] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.638112] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.638205] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.638290] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.638379] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.638466] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.638554] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.638639] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.638811] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.638832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.638920] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.638940] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.639036] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.639131] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.639229] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.639324] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.639419] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.639514] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.639608] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.639704] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.639830] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.639899] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.639965] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.640032] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.640127] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  382.640207] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.640271] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.640492] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.640545] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.640894] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  382.641487] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.641547] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.641634] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  382.642287] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  382.646549] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.646625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.646711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.646901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.646936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.646969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.647003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.647039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.647073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.647108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.647143] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.647180] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.647215] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.647281] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  382.647314] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  382.647572] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  382.648852] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.649387] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  382.649421] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  382.649473] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  382.649505] [drm:hsw_audio_config_update [i915]] using automatic N
>[  382.649592] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.649625] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.666448] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.666517] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.667070] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.668108] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.668168] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.668228] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.668283] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.668340] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.668398] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.668456] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.668510] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.668565] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.668576] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.668630] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.668712] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.668771] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.668828] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.668889] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.668949] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.669009] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.669072] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.669131] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.669196] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.669256] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.669318] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.669379] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.669438] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.669524] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  382.670209] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.670270] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.683186] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.683266] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.683380] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.700140] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.700241] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  382.700410] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  382.700596] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  382.704907] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.704994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.705085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.705176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.705256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.705337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.705418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.705499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.705580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.705661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.705875] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.705964] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.706527] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.706647] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  382.706851] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.706976] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.707405] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.707507] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.707624] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.707818] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.708220] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  382.708301] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  382.709530] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.711243] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.711336] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.711431] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.711516] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.711606] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.711694] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.711878] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.711967] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.712065] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.712084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.712177] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.712195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.712285] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.712382] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.712476] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.712575] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.712667] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.712819] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.712911] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.713011] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.713105] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.713199] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.713293] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.713390] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.713522] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  382.713636] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.713804] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.714112] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.714191] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.714526] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  382.714650] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.714830] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.714955] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  382.715347] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  382.719638] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.719752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.719791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.719830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.719865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.719900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.719935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.719970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.720005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.720038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.720074] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.720110] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.720146] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.720212] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  382.720246] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  382.720534] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  382.721865] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.722399] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  382.722434] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  382.722485] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  382.722518] [drm:hsw_audio_config_update [i915]] using automatic N
>[  382.722604] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.722637] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.739471] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.739519] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.739839] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.740453] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.740507] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.740566] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.740617] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.740672] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.741157] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.741212] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.741265] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.741317] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.741328] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.741379] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.741389] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.741442] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.741496] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.741548] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.741602] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.741656] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.742334] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.742387] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.742442] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.742495] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.742549] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.742602] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.742656] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.743142] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  382.743214] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.743269] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.756131] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.756206] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.756316] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.773047] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.773142] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  382.773300] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  382.773472] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  382.777789] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.777869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.777950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.778031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.778105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.778179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.778252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.778326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.778399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.778473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.778546] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.778624] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.779818] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.779945] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  382.780027] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.780139] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.780237] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.780326] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.780431] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.780526] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.780608] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  382.780681] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  382.782623] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.784058] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.784133] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.784210] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.784280] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.784353] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.784425] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.784498] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.784568] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.784637] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.784766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.784838] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.784852] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.784926] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.785004] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.785077] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.785157] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.785233] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.785314] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.785390] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.785472] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.785549] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.785626] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.785725] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.785799] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.785910] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  382.786005] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.786081] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.786348] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.786413] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.786792] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  382.787374] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.787449] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.787552] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  382.788228] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  382.792460] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.792533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.792578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.792623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.792663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.792770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.792983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.793023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.793063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.793102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.793141] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.793185] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.793228] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.793302] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  382.793341] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  382.793614] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  382.794993] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.795553] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  382.795592] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  382.795650] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  382.795727] [drm:hsw_audio_config_update [i915]] using automatic N
>[  382.796052] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.796090] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.812608] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.812662] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.813055] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.813808] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.813879] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.813942] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.814001] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.814062] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.814123] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.814181] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.814240] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.814299] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.814313] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.814368] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.814377] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.814435] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.814493] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.814553] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.814609] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.814669] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.814776] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.814836] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.814904] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.814966] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.815030] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.815090] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.815154] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.815237] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  382.815314] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.815377] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.829340] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.829415] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.829531] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.846205] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.846296] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  382.846454] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  382.846626] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  382.850992] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.851080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.851169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.851262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.851344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.851425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.851506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.851588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.851669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.851857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.851941] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.852032] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.852120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.852243] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  382.852328] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.852442] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.852540] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.852628] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.852783] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.852877] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.852960] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  382.853034] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  382.853624] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.855154] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.855239] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.855324] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.855400] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.855483] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.855563] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.855642] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.855803] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.855881] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.855901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.855978] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.855990] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.856069] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.856152] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.856234] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.856317] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.856398] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.856486] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.856565] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.856652] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.856782] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.856866] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.856946] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.857029] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.857143] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  382.857248] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.857331] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.857612] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.857682] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.858059] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  382.858133] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.858184] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.858257] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  382.858842] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  382.863089] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.863135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.863183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.863232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.863276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.863320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.863363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.863407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.863450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.863492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.863536] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.863582] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.863626] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.863882] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  382.863926] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  382.864453] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  382.865973] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.866539] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  382.866583] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  382.866646] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  382.866736] [drm:hsw_audio_config_update [i915]] using automatic N
>[  382.866841] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.866884] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.883586] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.883645] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.883987] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.884845] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.884911] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.884980] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.885041] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.885107] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.885171] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.885235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.885297] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.885360] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.885374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.885435] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.885445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.885506] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.885570] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.885630] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.885733] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.885796] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.885862] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.885924] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.885990] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.886054] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.886119] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.886183] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.886246] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.886336] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  382.886414] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.886478] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.900319] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.900402] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.900524] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.917093] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.917198] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  382.917366] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  382.917553] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  382.921887] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.921974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.922063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.922154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.922236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.922317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.922398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.922479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.922560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.922641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.923391] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.923484] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.923575] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.923711] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  382.924318] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.924443] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.924550] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.924648] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.925288] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.925393] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.925481] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  382.925562] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  382.927103] [drm:intel_power_well_disable [i915]] disabling always-on
>[  382.929152] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.929244] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.929337] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.929423] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.929512] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.929600] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.929688] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.930369] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.930457] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.930473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.930558] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.930572] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.930661] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.931292] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.931384] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.931474] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.931563] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.931657] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.932259] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.932351] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.932407] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.932442] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.932476] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.932510] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.932565] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  382.932613] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.932647] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.932835] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.932864] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.933148] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  382.933198] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.933233] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.933286] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  382.933545] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  382.937781] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.937851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.937890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.937929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.937965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.938000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.938035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.938070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.938104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.938137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.938173] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.938210] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.938245] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.938311] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  382.938345] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  382.938632] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  382.939649] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.940234] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  382.940270] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  382.940322] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  382.940354] [drm:hsw_audio_config_update [i915]] using automatic N
>[  382.940442] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.940475] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.957166] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.957214] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.957380] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.958237] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  382.958293] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.958351] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  382.958404] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  382.958459] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.958514] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  382.958570] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.958623] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  382.958826] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.958836] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.958890] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.958896] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  382.958949] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  382.959004] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  382.959056] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.959113] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.959167] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.959228] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  382.959282] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.959339] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  382.959392] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  382.959447] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.959502] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  382.959558] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  382.959640] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  382.959934] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  382.959988] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  382.974014] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  382.974087] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  382.974195] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  382.990953] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  382.991043] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  382.991201] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  382.991373] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  382.995645] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  382.995796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  382.995886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  382.995977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  382.996058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  382.996139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  382.996221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  382.996302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  382.996383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  382.996464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  382.996544] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  382.996630] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  382.997004] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.997122] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  382.997203] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  382.997316] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  382.997411] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  382.997501] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  382.997607] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  382.997940] [drm:intel_power_well_disable [i915]] disabling DC off
>[  382.998024] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  382.998095] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  382.998683] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.000169] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.000238] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.000309] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.000372] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.000439] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.000507] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  383.000574] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.000638] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.000933] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.000945] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.001011] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.001019] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.001085] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.001152] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.001218] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.001289] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.001356] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.001430] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.001497] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.001569] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.001637] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.001944] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  383.002009] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  383.002077] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  383.002178] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  383.002264] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  383.002331] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  383.002570] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.002629] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.003159] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  383.003247] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.003308] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  383.003396] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  383.003943] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  383.008206] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.008277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.008317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.008356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.008391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.008425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.008461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.008494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.008529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.008562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.008597] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.008633] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.008729] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.008796] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  383.008830] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  383.009612] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  383.010626] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  383.011182] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  383.011217] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  383.011268] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  383.011300] [drm:hsw_audio_config_update [i915]] using automatic N
>[  383.011388] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  383.011421] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  383.028253] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.028301] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  383.028466] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.029424] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.029480] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.029536] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.029587] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.029642] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.029762] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  383.029819] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.029877] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.029932] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.029947] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.030000] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.030011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.030068] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.030124] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.030184] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.030242] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.030299] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.030863] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.030917] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.030976] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.031033] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.031090] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  383.031144] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  383.031200] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  383.031287] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  383.031358] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  383.031413] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  383.044965] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  383.045038] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  383.045146] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  383.061826] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  383.061916] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  383.062074] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  383.062247] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  383.066508] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.066592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.066679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.066870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.066966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.067048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.067133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.067217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.067303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.067385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.067468] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.067560] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.067649] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.067832] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  383.067917] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.068029] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  383.068126] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.068214] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  383.068321] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.068415] [drm:intel_power_well_disable [i915]] disabling DC off
>[  383.068498] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  383.068573] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  383.069237] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.070720] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.070851] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.070936] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.071012] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.071094] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.071174] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  383.071254] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.071330] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.071406] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.071420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.071496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.071505] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.071584] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.071662] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.071813] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.071897] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.071985] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.072075] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.072161] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.072251] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.072337] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.072422] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  383.072509] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  383.072592] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  383.072756] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  383.072860] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  383.072943] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  383.073222] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.073293] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.073618] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  383.073804] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.073868] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  383.073955] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  383.074302] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  383.078568] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.078612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.078658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.078761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.078810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.078852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.078894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.078936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.078978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.079020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.079063] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.079109] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.079155] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.079232] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  383.079275] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  383.079549] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  383.080737] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  383.081281] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  383.081322] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  383.081382] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  383.081421] [drm:hsw_audio_config_update [i915]] using automatic N
>[  383.081520] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  383.081559] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  383.098339] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.098395] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  383.098576] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.099634] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.099750] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.099817] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.099876] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.099940] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.100002] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  383.100064] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.100123] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.100182] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.100192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.100250] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.100257] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.100318] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.100377] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.100437] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.100497] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.100556] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.100621] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.100679] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.101898] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.101964] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.102026] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  383.102088] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  383.102150] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  383.102248] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  383.102329] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  383.102393] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  383.115092] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  383.115178] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  383.115303] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  383.132045] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  383.132140] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  383.132299] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  383.132472] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  383.136790] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.136867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.136949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.137031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.137105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.137179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.137253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.137327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.137401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.137474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.137547] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.137625] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.138774] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.138898] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  383.138980] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.139092] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  383.139189] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.139277] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  383.139381] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.139476] [drm:intel_power_well_disable [i915]] disabling DC off
>[  383.139557] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  383.139630] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  383.141618] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.143048] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.143125] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.143202] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.143271] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.143344] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.143417] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  383.143490] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.143559] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.143629] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.143721] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.143797] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.143806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.143878] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.143954] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.144026] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.144104] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.144177] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.144258] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.144331] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.144412] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.144487] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.144565] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  383.144639] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  383.144753] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  383.144861] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  383.144956] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  383.145032] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  383.145291] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.145355] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.145673] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  383.146312] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.146383] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  383.146487] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  383.147314] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  383.151582] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.151649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.151752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.151797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.151838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.151879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.151919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.151960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.152000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.152041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.152080] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.152125] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.152168] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.152243] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  383.152283] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  383.152558] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  383.153746] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  383.154306] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  383.154345] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  383.154403] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  383.154440] [drm:hsw_audio_config_update [i915]] using automatic N
>[  383.154540] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  383.154578] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  383.171368] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.171421] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  383.171598] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.172690] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.172795] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.172857] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.172912] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.172971] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.173029] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  383.173086] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.173141] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.173196] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.173205] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.173260] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.173266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.173323] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.173378] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.173434] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.173489] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.173544] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.173607] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.173661] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.173778] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.173838] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.173901] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  383.173961] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  383.174024] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  383.174112] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  383.174186] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  383.174246] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  383.188106] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  383.188186] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  383.188332] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  383.205004] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  383.205099] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  383.205258] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  383.205430] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  383.209721] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.209897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.209997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.210097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.210187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.210276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.210366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.210456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.210545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.210635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.210806] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.210913] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.211017] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.211152] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  383.211837] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.212272] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  383.212384] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.212484] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  383.212600] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.212794] [drm:intel_power_well_disable [i915]] disabling DC off
>[  383.212893] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  383.212975] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  383.214275] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.216271] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.216362] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.216456] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.216541] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.216629] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.216806] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  383.216903] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.216994] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.217088] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.217111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.217205] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.217221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.217317] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.217410] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.217504] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.217599] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.218454] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.218550] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.218641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.218802] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.218894] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.218990] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  383.219087] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  383.219181] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  383.219318] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  383.220044] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  383.220078] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  383.220219] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.220249] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.220533] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  383.220581] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.220616] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  383.220714] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  383.221126] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  383.225357] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.225431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.225469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.225509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.225544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.225579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.225614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.225649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.225732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.225768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.225804] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.225846] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.225885] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.226192] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  383.226226] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  383.226491] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  383.227654] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  383.228209] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  383.228244] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  383.228295] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  383.228328] [drm:hsw_audio_config_update [i915]] using automatic N
>[  383.228415] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  383.228448] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  383.245284] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.245331] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  383.245498] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.246514] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.246569] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.246627] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.246751] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.246809] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.246869] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  383.246925] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.246984] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.247039] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.247306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.247364] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.247371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.247426] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.247479] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.247533] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.247586] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.247638] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.247742] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.247799] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.247860] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.247917] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.247976] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  383.248034] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  383.248093] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  383.248179] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  383.248270] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  383.248325] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  383.261990] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  383.262061] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  383.262170] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  383.278858] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  383.278948] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  383.279105] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  383.279276] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  383.283516] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.283592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.283671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.283838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.283914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.283991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.284065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.284142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.284217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.284294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.284368] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.284451] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.284535] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.284642] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  383.284805] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.284922] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  383.285020] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.285107] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  383.285213] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.285306] [drm:intel_power_well_disable [i915]] disabling DC off
>[  383.285389] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  383.285463] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  383.286110] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.287589] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.287670] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.287835] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.287917] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.288005] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.288091] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  383.288170] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.288249] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.288327] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.288341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.288420] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.288434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.288516] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.288596] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.288680] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.288807] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.288896] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.288983] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.289072] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.289163] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.289252] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.289336] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  383.289422] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  383.289507] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  383.289628] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  383.289773] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  383.289857] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  383.290135] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.290203] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.290528] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  383.290637] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.290785] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  383.290860] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  383.291170] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  383.295414] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.295459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.295507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.295556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.295600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.295641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.295739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.295783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.295830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.295877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.295924] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.295974] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.296020] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.296097] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  383.296140] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  383.296423] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  383.297628] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  383.298214] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  383.298257] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  383.298320] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  383.298361] [drm:hsw_audio_config_update [i915]] using automatic N
>[  383.298467] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  383.298508] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  383.315253] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.315311] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  383.315493] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.316152] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.316196] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.316243] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.316283] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.316326] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.316370] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  383.316413] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.316453] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.316493] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.316502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.316542] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.316547] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.316589] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.316629] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.316776] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.316842] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.316908] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.316980] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.317045] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.317115] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.317180] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.317250] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  383.317314] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  383.317382] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  383.317476] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  383.317555] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  383.317619] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  383.332009] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  383.332090] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  383.332210] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  383.348941] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  383.349038] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  383.349206] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  383.349389] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  383.353641] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.353788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.353875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.353963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.354045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.354125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.354206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.354287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.354368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.354448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.354528] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.354614] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.354699] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.354890] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  383.354978] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.355094] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  383.355189] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.355276] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  383.355382] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.355475] [drm:intel_power_well_disable [i915]] disabling DC off
>[  383.355558] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  383.355631] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  383.356282] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.357820] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.357903] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.357988] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.358064] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.358144] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.358224] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  383.358303] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.358380] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.358455] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.358469] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.358545] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.358556] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.358635] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.358795] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.358876] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.358969] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.359053] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.359146] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.359230] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.359319] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.359403] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.359490] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  383.359575] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  383.359660] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  383.359820] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  383.359922] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  383.360007] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  383.360290] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.360360] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.360684] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  383.361304] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.361364] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  383.361453] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  383.361833] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  383.366092] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.366135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.366180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.366226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.366268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.366308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.366348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.366389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.366433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.366472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.366515] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.366559] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.366601] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.366725] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  383.366768] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  383.367044] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  383.368189] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  383.368770] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  383.368813] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  383.368873] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  383.368914] [drm:hsw_audio_config_update [i915]] using automatic N
>[  383.369018] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  383.369060] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  383.385846] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.385900] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  383.386077] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.386823] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.386886] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.386952] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.387011] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.387078] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.387140] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  383.387205] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.387266] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.387329] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.387342] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.387402] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.387412] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.387473] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.387537] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.387601] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.387666] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.387769] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.387838] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.387905] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.387973] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.388042] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.388107] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  383.388176] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  383.388240] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  383.388335] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  383.388414] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  383.388480] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  383.402569] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  383.402651] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  383.402872] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  383.419527] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  383.419624] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  383.419836] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  383.420021] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  383.424277] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.424360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.424447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.424537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.424618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.424698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.424872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.424957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.425045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.425129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.425215] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.425305] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.425399] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.425513] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  383.425594] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.425764] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  383.425863] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.425951] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  383.426054] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.426145] [drm:intel_power_well_disable [i915]] disabling DC off
>[  383.426224] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  383.426299] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  383.426936] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.428429] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.428511] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.428596] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.428672] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.428837] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.428921] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  383.429005] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.429092] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.429174] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.429194] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.429272] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.429287] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.429374] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.429457] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.429543] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.429629] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.429772] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.429826] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.429880] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.429935] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.429986] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.430035] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  383.430090] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  383.430141] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  383.430216] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  383.430281] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  383.430333] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  383.430520] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.430564] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.430895] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  383.430971] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.431018] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  383.431090] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  383.431393] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  383.435612] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.435665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.435800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.435850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.435896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.435940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.435987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.436033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.436080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.436126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.436173] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.436224] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.436274] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.436356] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  383.436403] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  383.436743] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  383.438007] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  383.438556] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  383.438602] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  383.438668] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  383.438758] [drm:hsw_audio_config_update [i915]] using automatic N
>[  383.438873] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  383.438917] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  383.455594] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.455654] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  383.455980] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.456828] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.456892] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.456961] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.457020] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.457084] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.457145] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  383.457206] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.457266] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.457327] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.457340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.457401] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.457408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.457469] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.457530] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.457591] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.457653] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.457797] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.457877] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.457943] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.458018] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.458085] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.458158] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  383.458228] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  383.458299] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  383.458401] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  383.458485] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  383.458556] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  383.472375] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  383.472462] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  383.472592] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  383.489268] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  383.489366] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  383.489534] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  383.489860] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  383.494130] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.494229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.494327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.494427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.494517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.494607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.494697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.495532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.495623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.495713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.496187] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.496287] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.496382] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.496515] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  383.496605] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.497233] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  383.497343] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.497441] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  383.497556] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.497661] [drm:intel_power_well_disable [i915]] disabling DC off
>[  383.498243] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  383.498325] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  383.499533] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.501218] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.501299] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.501386] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.501462] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.501542] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.501624] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  383.501703] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.502375] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.502454] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.502469] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.502545] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.502557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.502636] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.503255] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.503333] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.503415] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.503492] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.503577] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.503653] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.504260] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.504342] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.504408] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  383.504443] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  383.504478] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  383.504532] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  383.504579] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  383.504614] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  383.505054] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.505082] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.505368] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  383.505417] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.505450] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  383.505502] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  383.505951] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  383.510179] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.510255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.510294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.510333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.510368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.510403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.510438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.510471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.510508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.510540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.510577] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.510613] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.510649] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.511161] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  383.511195] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  383.511448] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  383.512562] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  383.513189] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  383.513222] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  383.513274] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  383.513306] [drm:hsw_audio_config_update [i915]] using automatic N
>[  383.513394] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  383.513427] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  383.530253] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.530300] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  383.530463] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.531381] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.531438] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.531496] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.531547] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.531600] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.531654] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  383.532109] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  383.532163] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.532215] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.532227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.532278] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.532286] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.532339] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.532392] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.532446] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.532498] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.532553] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.532613] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.532666] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.533383] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.533437] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.533489] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  383.533542] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  383.533596] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  383.533680] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  383.534116] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  383.534171] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  383.546972] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  383.547041] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  383.547151] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  383.563783] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  383.563872] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  383.564029] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  383.564199] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  383.568467] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.568550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.568638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.569088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.569170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.569251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.569332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.569413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.569494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.569573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.569653] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.570418] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.570506] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.570625] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  383.570979] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.571088] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  383.571184] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.571270] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  383.571371] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.571463] [drm:intel_power_well_disable [i915]] disabling DC off
>[  383.571544] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  383.571619] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  383.572588] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.574173] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  383.574371] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.574438] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.574874] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  383.575451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.575549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.575643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.575839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.575932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.576026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.576122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.576216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.576307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.576399] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.576494] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.576596] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.576697] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.576887] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  383.577008] [drm:intel_power_well_disable [i915]] disabling DC off
>[  383.577103] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  383.577181] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  383.577845] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.578992] [drm:drm_mode_addfb2] [FB:89]
>[  383.579050] [drm:drm_mode_addfb2] [FB:91]
>[  383.631765] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  383.632227] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  383.632876] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  383.633435] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  383.633458] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  383.633563] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.633598] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.633635] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.633716] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.633754] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.633790] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  383.633826] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  383.633862] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.633899] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.633908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.633942] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.633949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.633984] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.634018] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.634055] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.634091] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.634128] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.634166] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.634201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.634236] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  383.634270] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  383.634305] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  383.634339] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  383.634393] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  383.634441] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  383.634477] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  383.634878] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.634908] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.635194] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  383.635241] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.635274] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  383.635327] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  383.635587] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  383.639857] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.639899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.639943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.639987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.640027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.640067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.640107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.640146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.640186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.640226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.640265] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.640306] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.640347] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.640419] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  383.640458] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  383.641115] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  383.642381] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  383.642982] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  383.643029] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  383.643089] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  383.643128] [drm:hsw_audio_config_update [i915]] using automatic N
>[  383.660047] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.660120] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  383.660333] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.693627] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.693739] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.693797] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.693848] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.693904] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.693958] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  383.694012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  383.694063] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.694114] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.694124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.694175] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.694181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.694234] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.694285] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.694337] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.694389] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.694440] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.694499] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.694550] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.694608] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.694661] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.694768] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  383.694824] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  383.694881] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  383.694963] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  383.695035] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  383.695092] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  383.710139] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  383.710230] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  383.710374] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  383.727135] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  383.727306] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  383.727492] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  383.731789] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.731882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.731980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.732080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.732170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.732259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.732349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.732438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.732528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.732616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.732704] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.732930] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.733032] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.733168] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  383.733260] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.733385] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  383.733492] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.733590] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  383.733693] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.733873] [drm:intel_power_well_disable [i915]] disabling DC off
>[  383.733966] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  383.734047] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  383.734653] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.736314] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.736408] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.736501] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.736586] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.736675] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.736860] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  383.736955] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  383.737046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.737145] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.737167] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.737258] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.737272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.737368] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.737461] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.737557] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.737648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.737811] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.737904] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.737997] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.738090] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.738188] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.738283] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  383.738379] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  383.738474] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  383.738608] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  383.738797] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  383.738862] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  383.739089] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.739145] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.739460] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  383.739546] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.739609] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  383.739837] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  383.740188] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  383.744451] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.744529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.744568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.744607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.744642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.744727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.744904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.744938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.744973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.745007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.745042] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.745080] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.745117] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.745185] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  383.745219] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  383.745471] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  383.746766] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  383.747299] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  383.747334] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  383.747386] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  383.747418] [drm:hsw_audio_config_update [i915]] using automatic N
>[  383.764387] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.764462] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  383.764676] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.765857] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.765913] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.765971] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.766022] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.766078] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.766131] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  383.766184] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  383.766236] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.766287] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.766297] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.766348] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.766354] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.766407] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.766458] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.766511] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.766564] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.766615] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.766673] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.766782] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.766841] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.766900] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.766957] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  383.767017] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  383.767075] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  383.767158] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  383.767226] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  383.767284] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  383.781087] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  383.781162] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  383.781282] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  383.797958] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  383.798123] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  383.798295] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  383.802547] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.802631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.802875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.802989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.803082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.803177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.803269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.803363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.803455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.803550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.803640] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.803820] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.803917] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.804059] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  383.804154] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.804278] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  383.804385] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.804483] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  383.804585] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.804686] [drm:intel_power_well_disable [i915]] disabling DC off
>[  383.804844] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  383.804935] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  383.805540] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.807227] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.807322] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.807415] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.807500] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.807589] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.807677] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  383.807851] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  383.807944] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.808040] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.808057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.808149] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.808162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.808259] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.808351] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.808451] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.808546] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.808643] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.808786] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.808883] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.808977] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.809074] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.809169] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  383.809266] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  383.809360] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  383.809509] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  383.809597] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  383.809666] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  383.809964] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.810019] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.810330] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  383.810408] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.810468] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  383.810555] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  383.811262] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  383.815525] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.815598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.815637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.815724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.815766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.815801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.815836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.815871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.815907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.815941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.815977] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.816015] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.816052] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.816120] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  383.816154] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  383.816405] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  383.817415] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  383.817987] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  383.818022] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  383.818077] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  383.818112] [drm:hsw_audio_config_update [i915]] using automatic N
>[  383.835059] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.835134] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  383.835345] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.836385] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.836440] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.836498] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.836549] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.836603] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.836656] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  383.836784] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  383.836839] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.836895] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.836911] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.836963] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.836973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.837031] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.837087] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.837572] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.837628] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.837737] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.837797] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.837853] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.837915] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.838230] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.838282] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  383.838336] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  383.838389] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  383.838474] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  383.838544] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  383.838598] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  383.851851] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  383.851933] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  383.852068] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  383.868789] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  383.868954] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  383.869125] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  383.873377] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.873454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.873536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.873618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.873692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.873862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.874199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.874275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.874353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.874429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.874504] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.874587] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.874669] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.874896] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  383.875414] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.875539] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  383.875644] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.875838] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  383.875940] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.876363] [drm:intel_power_well_disable [i915]] disabling DC off
>[  383.876454] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  383.876533] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  383.877792] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.879402] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.879495] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.879589] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.879674] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.879859] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.879952] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  383.880050] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  383.880141] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.880237] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.880257] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.880348] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.880364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.880459] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.880549] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.880642] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.880800] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.880890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.880993] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.881089] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.881189] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.881290] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.881384] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  383.881476] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  383.881566] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  383.881696] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  383.881880] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  383.881976] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  383.882286] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.882365] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.882699] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  383.883345] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.883429] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  383.883657] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  383.883992] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  383.888222] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.888294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.888333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.888372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.888408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.888443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.888477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.888511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.888547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.888580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.888618] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.888654] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.888734] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.888802] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  383.888983] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  383.889239] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  383.890365] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  383.890936] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  383.890976] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  383.891028] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  383.891061] [drm:hsw_audio_config_update [i915]] using automatic N
>[  383.908034] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.908116] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  383.908335] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.909373] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.909428] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.909486] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.909537] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.909591] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.909644] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  383.909767] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  383.909823] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.909880] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.909896] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.909948] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.909958] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.910012] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.910071] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.910127] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.910188] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.910243] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.910307] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.910363] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.910965] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.911022] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.911078] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  383.911133] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  383.911190] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  383.911276] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  383.911346] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  383.911402] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  383.924777] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  383.924851] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  383.924972] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  383.941508] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  383.941670] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  383.942324] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  383.945848] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.945934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.946024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.946115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.946196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.946277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.946358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.946439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.946520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.946600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.946678] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.946852] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.946944] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.947067] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  383.947596] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.947785] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  383.947888] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.948262] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  383.948354] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.948450] [drm:intel_power_well_disable [i915]] disabling DC off
>[  383.948534] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  383.948609] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  383.949289] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.950803] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.950886] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.950970] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.951047] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.951127] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.951206] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  383.951286] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  383.951363] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.951439] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.951452] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.951528] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.951537] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.951616] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.951693] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.951890] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.951982] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.952076] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.952177] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.952273] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.952372] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.952470] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.952563] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  383.952661] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  383.952798] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  383.952929] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  383.953047] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  383.953140] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  383.953449] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.953527] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.953987] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  383.954502] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.954591] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  383.954892] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  383.955282] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  383.959412] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  383.959448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  383.959487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  383.959525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  383.959561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  383.959596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  383.959631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  383.959715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  383.959752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  383.959790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  383.959827] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  383.960073] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  383.960110] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.960177] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  383.960212] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  383.960465] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  383.961609] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  383.962182] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  383.962221] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  383.962274] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  383.962307] [drm:hsw_audio_config_update [i915]] using automatic N
>[  383.979290] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  383.979377] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  383.979606] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  383.980629] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  383.980731] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.980791] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  383.980842] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  383.980898] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.980952] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  383.981006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  383.981057] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  383.981108] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.981117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.981168] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.981174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  383.981227] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  383.981278] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  383.981330] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.981382] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.981433] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.981492] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  383.981542] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.981600] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  383.981653] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  383.981760] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  383.981817] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  383.981876] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  383.981957] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  383.982028] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  383.982085] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  383.995941] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  383.996014] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  383.996138] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  384.014316] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  384.014479] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  384.014651] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  384.019008] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.019085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.019168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.019250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.019325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.019399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.019472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.019547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.019620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.019694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.019863] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.019947] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.020029] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.020438] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  384.020515] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  384.020620] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  384.020781] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.020866] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.020948] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.021036] [drm:intel_power_well_disable [i915]] disabling DC off
>[  384.021490] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  384.021558] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  384.022225] [drm:intel_power_well_disable [i915]] disabling always-on
>[  384.023992] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.024069] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.024147] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.024216] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.024290] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.024363] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.024436] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.024505] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.024574] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.024587] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.024657] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.024739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.024814] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.024887] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.024965] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.025041] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.025123] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.025203] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.025281] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.025362] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.025443] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.025519] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.025602] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.025680] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.025869] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  384.025983] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.026872] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.027141] [drm:intel_power_well_enable [i915]] enabling always-on
>[  384.027219] [drm:intel_power_well_enable [i915]] enabling DC off
>[  384.027555] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  384.027674] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  384.027841] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  384.027974] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  384.028398] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  384.032685] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.032853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.032951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.033051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.033142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.033232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.033322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.033410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.033500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.033587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.033678] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.033858] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.033929] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.034033] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  384.034096] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  384.034468] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  384.036194] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  384.036850] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  384.036918] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  384.036984] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  384.037027] [drm:hsw_audio_config_update [i915]] using automatic N
>[  384.053900] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.053969] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.054165] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.054860] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.054910] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.054964] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.055012] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.055063] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.055112] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.055161] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.055209] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.055258] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.055268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.055315] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.055322] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.055369] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.055418] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.055466] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.055516] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.055563] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.055615] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.055661] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.055758] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.055810] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.055862] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.055913] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.055964] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.056034] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  384.056099] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.056151] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.070650] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  384.070800] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.070944] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  384.087580] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  384.087862] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  384.088053] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  384.092339] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.092434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.092531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.092630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.092811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.092904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.093000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.093098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.093192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.093286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.093384] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.093488] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.093587] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.093792] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  384.093886] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  384.094008] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  384.094111] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.094217] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.094319] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.094428] [drm:intel_power_well_disable [i915]] disabling DC off
>[  384.094520] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  384.094602] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  384.095279] [drm:intel_power_well_disable [i915]] disabling always-on
>[  384.096923] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.097014] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.097108] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.097193] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.097282] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.097370] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.097458] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.097543] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.097628] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.097726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.097826] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.097844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.097918] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.097993] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.098073] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.098146] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.098223] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.098304] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.098380] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.098459] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.098537] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.098616] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.098695] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.098808] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.098915] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  384.099007] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.099084] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.099339] [drm:intel_power_well_enable [i915]] enabling always-on
>[  384.099403] [drm:intel_power_well_enable [i915]] enabling DC off
>[  384.099784] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  384.100362] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  384.100436] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  384.100542] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  384.101188] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  384.105468] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.105539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.105579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.105618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.105654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.105726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.105762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.105799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.105835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.105872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.105908] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.105950] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.105989] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.106284] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  384.106317] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  384.106569] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  384.107786] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  384.108320] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  384.108354] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  384.108406] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  384.108438] [drm:hsw_audio_config_update [i915]] using automatic N
>[  384.125416] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.125493] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.125790] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.126512] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.126567] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.126624] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.126675] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.126794] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.126852] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.126911] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.126968] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.127026] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.127040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.127096] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.127107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.127163] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.127222] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.127280] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.127334] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.127394] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.127454] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.127510] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.127565] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.127622] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.127674] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.127775] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.127828] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.127917] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  384.127986] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.128042] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.142111] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  384.142184] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.142305] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  384.159006] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  384.159168] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  384.159340] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  384.163610] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.163694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.163880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.163985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.164067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.164151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.164235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.164319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.164402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.164487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.164569] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.164660] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.164817] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.164940] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  384.165028] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  384.165143] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  384.165239] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.165329] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.165420] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.165512] [drm:intel_power_well_disable [i915]] disabling DC off
>[  384.165595] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  384.165669] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  384.166327] [drm:intel_power_well_disable [i915]] disabling always-on
>[  384.167878] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.167962] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.168049] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.168125] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.168205] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.168284] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.168364] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.168440] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.168518] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.168531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.168609] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.168618] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.168697] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.168853] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.168935] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.169021] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.169100] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.169194] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.169276] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.169366] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.169450] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.169538] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.169621] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.169721] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.169838] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  384.169945] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.170029] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.170310] [drm:intel_power_well_enable [i915]] enabling always-on
>[  384.170380] [drm:intel_power_well_enable [i915]] enabling DC off
>[  384.170789] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  384.171327] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  384.171389] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  384.171478] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  384.171860] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  384.176125] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.176199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.176239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.176278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.176313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.176348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.176383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.176417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.176451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.176484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.176522] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.176559] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.176594] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.176661] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  384.176743] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  384.177303] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  384.178425] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  384.178996] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  384.179032] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  384.179086] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  384.179125] [drm:hsw_audio_config_update [i915]] using automatic N
>[  384.196071] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.196147] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.196360] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.197377] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.197433] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.197491] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.197542] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.197597] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.197651] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.197813] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.197882] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.197952] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.197970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.198035] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.198047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.198119] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.198190] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.198264] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.198336] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.198407] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.198481] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.198551] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.198625] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.198713] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.198783] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.198852] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.198926] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.199026] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  384.199789] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.199859] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.212888] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  384.212978] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.213122] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  384.229878] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  384.230051] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  384.230237] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  384.234524] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.234616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.234713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.234920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.235026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.235118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.235208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.235301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.235397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.235488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.235581] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.235680] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.235852] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.235985] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  384.236078] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  384.236205] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  384.236312] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.236411] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.236513] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.236615] [drm:intel_power_well_disable [i915]] disabling DC off
>[  384.236784] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  384.236876] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  384.237487] [drm:intel_power_well_disable [i915]] disabling always-on
>[  384.239184] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.239278] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.239370] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.239455] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.239545] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.239634] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.239806] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.239897] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.239995] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.240015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.240105] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.240121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.240214] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.240306] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.240401] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.240496] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.240590] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.240687] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.240828] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.240897] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.240962] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.241032] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.241098] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.241165] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.241253] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  384.241337] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.241402] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.241627] [drm:intel_power_well_enable [i915]] enabling always-on
>[  384.241739] [drm:intel_power_well_enable [i915]] enabling DC off
>[  384.242049] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  384.242138] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  384.242200] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  384.242290] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  384.242608] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  384.246878] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.246948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.246988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.247027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.247062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.247097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.247132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.247165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.247200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.247233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.247269] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.247306] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.247342] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.247408] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  384.247442] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  384.247997] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  384.249102] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  384.249635] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  384.249708] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  384.249891] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  384.249924] [drm:hsw_audio_config_update [i915]] using automatic N
>[  384.266835] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.266927] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.267168] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.268432] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.268495] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.268562] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.268621] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.268682] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.268815] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.268880] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.268948] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.269012] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.269031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.269091] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.269104] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.269170] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.269236] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.269303] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.269367] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.269433] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.269503] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.270121] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.270191] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.270254] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.270317] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.270383] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.270446] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.270543] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  384.270625] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.270712] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.283440] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  384.283523] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.283657] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  384.300448] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  384.300623] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  384.301281] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  384.305579] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.305674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.305882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.305998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.306091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.306181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.306273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.306367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.306460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.306550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.306641] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.306814] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.306913] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.307055] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  384.307149] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  384.307273] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  384.307381] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.307480] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.307583] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.307685] [drm:intel_power_well_disable [i915]] disabling DC off
>[  384.307844] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  384.307934] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  384.308543] [drm:intel_power_well_disable [i915]] disabling always-on
>[  384.310207] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.310299] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.310393] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.310478] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.310567] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.310655] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.310839] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.310922] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.311011] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.311028] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.311111] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.311126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.311212] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.311297] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.311385] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.311474] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.311559] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.311647] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.311769] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.311858] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.311941] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.312026] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.312113] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.312201] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.312320] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  384.312425] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.312509] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.312854] [drm:intel_power_well_enable [i915]] enabling always-on
>[  384.312903] [drm:intel_power_well_enable [i915]] enabling DC off
>[  384.313212] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  384.313287] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  384.313342] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  384.313423] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  384.313816] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  384.318073] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.318149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.318187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.318226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.318261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.318296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.318331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.318364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.318401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.318434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.318470] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.318506] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.318542] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.318608] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  384.318643] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  384.319213] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  384.320333] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  384.320904] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  384.320938] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  384.321125] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  384.321158] [drm:hsw_audio_config_update [i915]] using automatic N
>[  384.337975] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.338050] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.338261] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.339329] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.339385] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.339443] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.339494] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.339548] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.339601] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.339655] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.339782] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.339836] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.339849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.339905] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.339916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.339970] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.340027] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.340084] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.340143] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.340200] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.340261] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.340317] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.340377] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.340945] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.341001] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.341055] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.341113] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.341197] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  384.341268] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.341324] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.354688] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  384.354812] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.354933] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  384.371614] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  384.372177] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  384.372368] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  384.376638] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.376787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.376878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.376969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.377051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.377132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.377213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.377293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.377375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.377454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.377534] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.377620] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.377781] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.377901] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  384.377988] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  384.378568] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  384.378665] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.378820] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.378914] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.379011] [drm:intel_power_well_disable [i915]] disabling DC off
>[  384.379104] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  384.379177] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  384.379847] [drm:intel_power_well_disable [i915]] disabling always-on
>[  384.381333] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.381417] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.381502] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.381579] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.381659] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.381852] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.381943] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.382042] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.382135] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.382159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.382246] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.382262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.382358] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.382452] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.382546] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.382639] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.382786] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.382874] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.382961] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.383050] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.383132] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.383214] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.383294] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.383376] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.383494] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  384.383598] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.383682] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.384019] [drm:intel_power_well_enable [i915]] enabling always-on
>[  384.384090] [drm:intel_power_well_enable [i915]] enabling DC off
>[  384.384416] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  384.384523] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  384.384603] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  384.384791] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  384.385158] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  384.389442] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.389517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.389556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.389594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.389629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.389708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.389744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.389782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.389819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.390050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.390100] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.390140] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.390178] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.390247] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  384.390280] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  384.390532] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  384.391716] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  384.392248] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  384.392283] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  384.392334] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  384.392366] [drm:hsw_audio_config_update [i915]] using automatic N
>[  384.409330] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.409405] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.409616] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.410592] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.410648] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.410785] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.410840] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.410896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.410952] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.411009] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.411063] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.411118] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.411130] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.411182] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.411190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.411243] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.411299] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.411354] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.411409] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.411463] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.411524] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.411578] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.411634] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.411726] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.411785] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.411843] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.411902] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.411988] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  384.412062] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.412121] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.426037] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  384.426109] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.426229] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  384.442970] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  384.443131] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  384.443304] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  384.447550] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.447626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.447791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.447873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.447950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.448025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.448103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.448178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.448256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.448330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.448408] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.448489] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.448568] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.448679] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  384.448809] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  384.448922] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  384.449013] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.449094] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.449176] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.449260] [drm:intel_power_well_disable [i915]] disabling DC off
>[  384.449336] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  384.449404] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  384.450038] [drm:intel_power_well_disable [i915]] disabling always-on
>[  384.451442] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.451516] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.451593] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.451663] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.451813] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.451892] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.451968] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.452047] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.452122] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.452141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.452213] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.452228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.452305] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.452376] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.452449] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.452520] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.452592] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.452668] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.452787] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.452870] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.452950] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.453028] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.453104] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.453182] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.453295] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  384.453389] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.453462] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.453762] [drm:intel_power_well_enable [i915]] enabling always-on
>[  384.453830] [drm:intel_power_well_enable [i915]] enabling DC off
>[  384.454153] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  384.454248] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  384.454318] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  384.454422] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  384.454777] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  384.459026] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.459070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.459113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.459159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.459201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.459241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.459284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.459324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.459366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.459406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.459449] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.459492] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.459535] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.459609] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  384.459650] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  384.459986] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  384.461127] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  384.461708] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  384.461751] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  384.461812] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  384.461852] [drm:hsw_audio_config_update [i915]] using automatic N
>[  384.478798] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.478867] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.479070] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.479820] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.479875] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.479932] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.479984] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.480043] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.480097] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.480154] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.480208] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.480263] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.480275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.480328] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.480336] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.480389] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.480444] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.480498] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.480554] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.480608] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.480693] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.480823] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.480897] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.480962] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.481028] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.481094] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.481159] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.481254] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  384.481335] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.481401] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.495475] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  384.495556] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.495802] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  384.512430] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  384.512606] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  384.512934] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  384.517229] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.517322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.517420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.517520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.517610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.517700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.517905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.517998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.518097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.518191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.518287] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.518388] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.518486] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.518624] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  384.518744] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  384.518866] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  384.518981] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.519087] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.519188] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.519291] [drm:intel_power_well_disable [i915]] disabling DC off
>[  384.519383] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  384.519462] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  384.520117] [drm:intel_power_well_disable [i915]] disabling always-on
>[  384.521723] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.521865] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.521959] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.522044] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.522133] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.522223] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.522311] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.522396] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.522481] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.522494] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.522578] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.522588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.522676] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.522864] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.522950] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.523033] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.523118] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.523208] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.523294] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.523389] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.523473] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.523562] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.523647] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.523770] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.523890] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  384.523992] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.524080] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.524359] [drm:intel_power_well_enable [i915]] enabling always-on
>[  384.524430] [drm:intel_power_well_enable [i915]] enabling DC off
>[  384.524806] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  384.525390] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  384.525470] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  384.525583] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  384.526013] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  384.530284] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.530364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.530402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.530441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.530476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.530511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.530544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.530578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.530614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.530647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.530727] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.530769] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.530809] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.530878] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  384.530912] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  384.531199] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  384.532192] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  384.532756] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  384.532792] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  384.532844] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  384.532878] [drm:hsw_audio_config_update [i915]] using automatic N
>[  384.549865] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.549940] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.550153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.550873] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.550931] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.550989] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.551044] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.551101] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.551155] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.551210] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.551265] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.551320] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.551333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.551384] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.551392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.551445] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.551501] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.551555] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.551611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.551665] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.551769] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.551825] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.551888] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.551945] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.552006] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.552063] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.552128] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.552208] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  384.552279] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.552336] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.566544] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  384.566615] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.567279] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  384.583144] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  384.583288] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  384.583435] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  384.587666] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.587780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.587849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.587917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.587981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.588043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.588106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.588169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.588232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.588294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.588356] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.588422] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.588487] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.588581] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  384.588645] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  384.588790] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  384.588870] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.588940] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.589014] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.589088] [drm:intel_power_well_disable [i915]] disabling DC off
>[  384.589152] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  384.589208] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  384.589866] [drm:intel_power_well_disable [i915]] disabling always-on
>[  384.591323] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.591406] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.591491] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.591567] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.591647] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.591799] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.591884] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.591969] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.592047] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.592065] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.592143] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.592157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.592243] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.592323] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.592405] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.592488] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.592573] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.592662] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.592786] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.592874] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.592958] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.593041] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.593127] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.593209] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.593325] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  384.593428] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.593510] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.593832] [drm:intel_power_well_enable [i915]] enabling always-on
>[  384.593900] [drm:intel_power_well_enable [i915]] enabling DC off
>[  384.594226] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  384.594304] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  384.594359] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  384.594443] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  384.594813] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  384.599070] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.599113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.599159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.599206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.599248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.599288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.599330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.599372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.599413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.599455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.599497] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.599540] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.599583] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.599656] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  384.599749] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  384.600027] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  384.601185] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  384.601766] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  384.601809] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  384.601874] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  384.601914] [drm:hsw_audio_config_update [i915]] using automatic N
>[  384.618882] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.618961] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.619181] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.619986] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.620046] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.620111] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.620169] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.620231] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.620290] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.620350] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.620408] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.620466] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.620478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.620535] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.620544] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.620601] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.620660] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.620801] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.620875] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.620947] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.621023] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.621096] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.621173] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.621247] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.621320] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.621395] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.621464] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.621565] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  384.621649] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.621758] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.635585] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  384.635671] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.636510] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  384.652214] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  384.652384] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  384.652569] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  384.656875] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.656959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.657046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.657136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.657218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.657299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.657380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.657459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.657542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.657623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.657703] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.657923] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.658021] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.658156] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  384.658250] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  384.658374] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  384.658480] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.658578] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.658678] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.658840] [drm:intel_power_well_disable [i915]] disabling DC off
>[  384.658934] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  384.659021] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  384.659630] [drm:intel_power_well_disable [i915]] disabling always-on
>[  384.661261] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.661352] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.661445] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.661531] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.661620] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.661709] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.661885] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.661974] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.662074] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.662093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.662184] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.662202] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.662296] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.662391] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.662489] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.662582] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.662677] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.662821] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.662914] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.663014] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.663105] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.663195] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.663284] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.663377] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.663505] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  384.663591] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.663661] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.663945] [drm:intel_power_well_enable [i915]] enabling always-on
>[  384.664002] [drm:intel_power_well_enable [i915]] enabling DC off
>[  384.664309] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  384.664394] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  384.664456] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  384.664546] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  384.664906] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  384.669159] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.669238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.669275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.669314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.669349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.669382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.669417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.669450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.669486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.669519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.669555] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.669592] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.669627] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.669737] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  384.669771] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  384.670059] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  384.671051] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  384.671583] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  384.671618] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  384.671702] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  384.671737] [drm:hsw_audio_config_update [i915]] using automatic N
>[  384.688650] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.688772] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.688982] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.689657] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.689769] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.689828] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.689887] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.689945] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.690003] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.690060] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.690117] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.690173] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.690189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.690242] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.690252] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.690305] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.690365] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.690420] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.690478] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.690535] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.690594] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.690648] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.690789] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.690859] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.690926] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.690994] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.691069] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.691171] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  384.691254] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.691323] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.705398] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  384.705488] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.705635] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  384.722441] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  384.722616] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  384.722954] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  384.727243] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.727336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.727433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.727532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.727622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.727712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.727905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.728000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.728098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.728197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.728291] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.728397] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.728494] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.728625] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  384.728743] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  384.728867] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  384.728972] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.729069] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.729167] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.729267] [drm:intel_power_well_disable [i915]] disabling DC off
>[  384.729360] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  384.729442] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  384.730104] [drm:intel_power_well_disable [i915]] disabling always-on
>[  384.731670] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.731814] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.731908] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.731993] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.732084] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.732172] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.732260] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.732346] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.732431] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.732444] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.732529] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.732539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.732627] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.732796] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.732888] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.732986] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.733080] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.733186] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.733280] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.733379] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.733475] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.733574] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.733669] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.733818] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.733898] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  384.733968] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.734023] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.734213] [drm:intel_power_well_enable [i915]] enabling always-on
>[  384.734259] [drm:intel_power_well_enable [i915]] enabling DC off
>[  384.734557] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  384.734632] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  384.734725] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  384.734805] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  384.735117] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  384.739366] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.739445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.739483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.739522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.739557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.739590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.739625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.739658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.739738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.739775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.739812] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.739852] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.739891] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.739956] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  384.739989] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  384.740245] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  384.741240] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  384.741804] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  384.741839] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  384.741894] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  384.741928] [drm:hsw_audio_config_update [i915]] using automatic N
>[  384.758884] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.758960] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.759170] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.759961] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.760015] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.760072] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.760123] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.760177] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.760231] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.760285] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.760336] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.760387] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.760397] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.760448] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.760454] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.760507] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.760559] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.760611] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.760663] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.760773] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.760834] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.760893] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.760955] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.761013] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.761069] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.761126] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.761183] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.761268] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  384.761345] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.761403] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.775610] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  384.775795] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.776453] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  384.792202] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  384.792363] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  384.792534] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  384.796791] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.796885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.796982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.797081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.797172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.797262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.797352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.797440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.797530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.797618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.797708] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.797918] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.798023] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.798157] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  384.798249] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  384.798371] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  384.798477] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.798575] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.798675] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.798831] [drm:intel_power_well_disable [i915]] disabling DC off
>[  384.798926] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  384.799020] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  384.799624] [drm:intel_power_well_disable [i915]] disabling always-on
>[  384.801196] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.801287] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.801380] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.801465] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.801554] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.801643] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.801814] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.801906] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.802003] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.802026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.802119] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.802136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.802232] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.802324] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.802420] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.802516] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.802613] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.802731] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.802836] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.802907] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.802975] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.803043] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.803119] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.803190] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.803293] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  384.803380] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.803449] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.803683] [drm:intel_power_well_enable [i915]] enabling always-on
>[  384.803803] [drm:intel_power_well_enable [i915]] enabling DC off
>[  384.804116] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  384.804199] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  384.804259] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  384.804351] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  384.804771] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  384.808999] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.809076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.809116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.809156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.809193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.809229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.809265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.809300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.809337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.809374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.809410] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.809448] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.809485] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.809552] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  384.809588] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  384.810093] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  384.811172] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  384.811760] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  384.811799] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  384.811856] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  384.811890] [drm:hsw_audio_config_update [i915]] using automatic N
>[  384.828901] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.828988] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.829217] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.830122] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.830190] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.830264] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.830330] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.830401] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.830471] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.830540] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.830605] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.830671] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.830735] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.830801] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.830823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.830891] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.830961] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.831035] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.831107] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.831176] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.831249] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.831322] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.831396] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.831471] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.831543] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.831614] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.831684] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.831820] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  384.831906] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.831975] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.845587] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  384.845677] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.846368] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  384.862097] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  384.862283] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  384.862493] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  384.866856] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.866955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.867053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.867153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.867243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.867332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.867421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.867511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.867600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.867687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.867871] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.867977] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.868077] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.868215] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  384.869142] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  384.869271] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  384.869382] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.869481] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.869582] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.869685] [drm:intel_power_well_disable [i915]] disabling DC off
>[  384.869835] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  384.869926] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  384.871201] [drm:intel_power_well_disable [i915]] disabling always-on
>[  384.873199] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.873292] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.873386] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.873471] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.873561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.873648] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.873825] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.873916] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.874017] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.874039] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.874130] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.874146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.874239] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.874334] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.874429] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.874525] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.874622] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.875415] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.875506] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.875603] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.875694] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.875843] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.875940] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.876036] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.876174] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  384.876809] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.876903] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.877215] [drm:intel_power_well_enable [i915]] enabling always-on
>[  384.877291] [drm:intel_power_well_enable [i915]] enabling DC off
>[  384.877622] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  384.877837] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  384.877936] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  384.877991] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  384.878229] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  384.882455] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.882531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.882569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.882608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.882643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.882724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.882760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.882798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.882835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.882869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.882903] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.882942] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.882978] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.883045] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  384.883080] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  384.883339] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  384.884341] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  384.884908] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  384.884943] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  384.884998] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  384.885031] [drm:hsw_audio_config_update [i915]] using automatic N
>[  384.901992] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.902066] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.902276] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.903298] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.903354] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.903412] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.903463] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.903517] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.903570] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.903624] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.903675] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.903799] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.903813] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.903869] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.903880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.903937] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.903994] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.904053] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.904111] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.904168] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.904226] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.904284] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.904342] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.904402] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.905008] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.905063] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.905120] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.905202] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  384.905274] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.905330] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.918754] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  384.918827] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.918951] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  384.935619] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  384.936174] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  384.936363] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  384.940634] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.940787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.940876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.940968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.941050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.941131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.941212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.941293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.941374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.941455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.941535] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.941621] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.941780] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.941904] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  384.941993] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  384.942440] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  384.942539] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.942627] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.942777] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.942872] [drm:intel_power_well_disable [i915]] disabling DC off
>[  384.942981] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  384.943055] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  384.943644] [drm:intel_power_well_disable [i915]] disabling always-on
>[  384.945190] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.945271] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.945356] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.945432] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.945513] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.945593] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.945672] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.945860] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.945950] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.945974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.946061] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.946078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.946172] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.946267] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.946362] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.946454] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.946551] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.946651] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.946801] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.946893] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.946977] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.947061] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.947148] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.947234] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.947351] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  384.947454] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.947536] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.947864] [drm:intel_power_well_enable [i915]] enabling always-on
>[  384.947932] [drm:intel_power_well_enable [i915]] enabling DC off
>[  384.948256] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  384.948360] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  384.948439] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  384.948556] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  384.948972] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  384.953244] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  384.953321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  384.953359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  384.953398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  384.953433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  384.953468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  384.953501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  384.953536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  384.953572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  384.953605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  384.953642] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  384.953726] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  384.953765] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.953835] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  384.953868] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  384.954118] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  384.955108] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  384.955639] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  384.955707] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  384.955761] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  384.955794] [drm:hsw_audio_config_update [i915]] using automatic N
>[  384.972653] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  384.972757] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  384.972949] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  384.973551] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  384.973596] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  384.973644] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  384.973746] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  384.973795] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  384.973844] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  384.973891] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  384.973940] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  384.973986] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  384.974001] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.974045] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  384.974057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  384.974104] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  384.974151] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  384.974201] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  384.974246] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  384.974291] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  384.974341] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  384.974389] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  384.974437] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  384.974485] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  384.974530] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  384.974574] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  384.974617] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  384.974717] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  384.974775] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  384.974824] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  384.989417] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  384.989480] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  384.989581] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  385.006142] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  385.006288] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  385.006436] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  385.010690] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.010824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.010904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.010986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.011060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.011134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.011207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.011279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.011351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.011423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.011496] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.011574] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.011651] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.011832] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  385.011908] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.012015] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.012102] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.012181] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.012261] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.012343] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.012418] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  385.012485] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  385.013116] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.014540] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.014614] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.014692] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.014840] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.014919] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.014996] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.015075] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.015150] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.015222] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.015240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.015312] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.015326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.015399] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.015478] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.015554] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.015629] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.015743] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.015822] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.015897] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.015980] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.016058] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.016133] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.016204] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.016277] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.016379] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  385.016474] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.016549] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.016856] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.016918] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.017234] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  385.017333] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.017406] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.017510] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  385.017910] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  385.022166] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.022233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.022277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.022323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.022365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.022404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.022444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.022483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.022528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.022567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.022609] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.022653] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.022751] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.022828] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  385.022869] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  385.023144] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  385.024308] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  385.024889] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  385.024930] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  385.024993] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  385.025033] [drm:hsw_audio_config_update [i915]] using automatic N
>[  385.041949] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.042028] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.042246] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.043055] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.043120] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.043186] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.043247] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.043310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.043374] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.043437] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.043498] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.043559] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.043570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.043629] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.043699] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.043764] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.043827] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.043896] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.043961] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.044030] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.044099] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.044166] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.044234] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.044302] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.044367] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.044437] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.044501] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.044595] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  385.044672] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.044782] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.058682] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  385.058811] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  385.058935] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  385.075622] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  385.075891] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  385.076078] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  385.080340] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.080423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.080510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.080600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.080681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.080854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.080940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.081022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.081108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.081192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.081281] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.081374] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.081470] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.081588] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  385.081671] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.081878] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.081984] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.082082] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.082194] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.082301] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.082393] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  385.082478] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  385.083143] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.084699] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.084842] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.084936] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.085021] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.085112] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.085200] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.085289] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.085374] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.085459] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.085473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.085558] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.085567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.085655] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.085836] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.085919] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.086007] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.086091] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.086185] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.086270] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.086361] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.086448] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.086534] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.086617] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.086721] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.086840] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  385.086946] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.087028] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.087301] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.087372] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.087754] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  385.088332] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.088414] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.088526] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  385.088940] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  385.093221] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.093298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.093336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.093375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.093411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.093446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.093481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.093514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.093550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.093583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.093619] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.093655] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.093743] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.093809] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  385.093844] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  385.094130] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  385.095127] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  385.095659] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  385.095731] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  385.095782] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  385.095816] [drm:hsw_audio_config_update [i915]] using automatic N
>[  385.112676] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.112802] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.113014] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.113785] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.113842] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.113900] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.113951] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.114010] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.114067] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.114123] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.114176] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.114231] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.114243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.114295] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.114303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.114357] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.114412] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.114466] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.114522] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.114576] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.114635] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.114742] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.114803] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.114857] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.114915] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.114969] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.115027] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.115105] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  385.115176] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.115231] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.129452] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  385.129525] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  385.129648] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  385.146521] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  385.146683] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  385.146954] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  385.151214] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.151293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.151374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.151456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.151530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.151604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.151677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.151841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.151920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.151999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.152077] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.152180] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.152271] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.152395] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  385.152482] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.152594] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.152690] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.152988] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.153080] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.153175] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.153258] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  385.153331] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  385.153989] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.155499] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.155581] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.155665] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.155827] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.155910] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.156002] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.156086] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.156169] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.156248] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.156263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.156339] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.156351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.156430] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.156508] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.156588] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.156671] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.156811] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.156899] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.156985] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.157074] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.157163] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.157249] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.157336] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.157421] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.157545] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  385.157659] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.157762] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.157966] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.158016] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.158316] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  385.158396] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.158454] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.158539] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  385.158893] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  385.163073] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.163144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.163189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.163235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.163277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.163318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.163360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.163399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.163443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.163482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.163524] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.163568] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.163612] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.163735] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  385.163778] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  385.164056] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  385.165216] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  385.165797] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  385.165839] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  385.165901] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  385.165941] [drm:hsw_audio_config_update [i915]] using automatic N
>[  385.182867] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.182946] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.183164] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.184003] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.184069] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.184137] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.184199] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.184263] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.184329] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.184392] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.184455] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.184518] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.184533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.184592] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.184602] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.184663] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.184820] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.184889] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.184966] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.185037] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.185114] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.185183] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.185263] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.185335] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.185407] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.185475] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.185549] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.185650] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  385.185772] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.185846] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.199672] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  385.199828] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  385.199993] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  385.216635] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  385.216893] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  385.217081] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  385.221373] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.221466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.221564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.221664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.221870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.221968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.222060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.222155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.222246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.222340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.222428] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.222531] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.222632] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.222836] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  385.222933] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.223057] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.223164] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.223263] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.223365] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.223467] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.223560] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  385.223642] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  385.224328] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.226026] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.226119] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.226213] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.226298] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.226386] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.226474] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.226562] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.226647] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.226819] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.226838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.226929] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.226944] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.227040] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.227135] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.227229] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.227322] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.227418] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.227520] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.227616] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.227763] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.227861] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.227959] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.228055] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.228147] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.228284] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  385.228399] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.228491] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.228940] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.228992] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.229298] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  385.229379] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.229437] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.229524] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  385.229828] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  385.234073] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.234138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.234202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.234267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.234326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.234385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.234443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.234500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.234560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.234617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.234678] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.234824] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.234892] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.234990] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  385.235050] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  385.235405] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  385.237018] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  385.237625] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  385.237706] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  385.237794] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  385.237853] [drm:hsw_audio_config_update [i915]] using automatic N
>[  385.254678] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.254810] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.255022] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.255803] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.255861] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.255922] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.255976] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.256034] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.256087] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.256144] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.256197] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.256252] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.256264] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.256317] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.256325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.256380] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.256434] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.256491] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.256547] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.256602] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.256661] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.256775] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.256836] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.256894] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.256952] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.257009] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.257065] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.257149] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  385.257222] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.257280] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.271449] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  385.271543] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  385.271798] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  385.288459] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  385.288618] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  385.288954] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  385.293241] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.293334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.293431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.293531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.293621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.293710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.293916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.294012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.294103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.294193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.294283] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.294383] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.294484] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.294618] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  385.294785] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.294915] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.295021] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.295119] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.295216] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.295316] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.295412] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  385.295496] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  385.296162] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.297666] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.297809] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.297903] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.297988] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.298079] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.298168] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.298256] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.298341] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.298426] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.298439] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.298524] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.298534] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.298622] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.298708] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.298898] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.298959] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.299018] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.299082] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.299142] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.299205] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.299268] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.299329] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.299393] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.299453] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.299540] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  385.299619] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.299677] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.299910] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.299959] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.300266] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  385.300344] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.300401] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.300488] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  385.300902] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  385.305153] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.305196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.305241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.305301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.305341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.305382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.305423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.305463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.305505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.305545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.305588] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.305632] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.305741] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.305817] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  385.305858] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  385.306136] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  385.307301] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  385.307882] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  385.307924] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  385.307986] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  385.308025] [drm:hsw_audio_config_update [i915]] using automatic N
>[  385.324952] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.325032] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.325250] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.326065] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.326125] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.326186] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.326243] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.326302] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.326361] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.326418] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.326476] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.326532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.326544] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.326598] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.326607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.326663] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.326839] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.326905] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.326972] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.327038] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.327112] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.327176] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.327250] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.327315] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.327381] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.327448] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.327515] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.327607] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  385.327687] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.327787] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.341687] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  385.341834] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  385.341970] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  385.358639] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  385.358895] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  385.359081] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  385.362479] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.362564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.362653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.362897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.362990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.363085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.363177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.363271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.363363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.363456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.363548] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.363651] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.363826] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.363966] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  385.364061] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.364185] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.364291] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.364391] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.364494] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.364595] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.364687] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  385.364838] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  385.365449] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.367155] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.367248] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.367344] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.367429] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.367519] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.367608] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.367696] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.367870] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.367961] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.367988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.368076] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.368092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.368188] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.368282] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.368378] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.368471] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.368567] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.368664] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.368800] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.368902] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.368997] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.369093] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.369189] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.369281] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.369420] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  385.369537] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.369630] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.370010] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.370088] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.370426] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  385.370546] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.370635] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.370833] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  385.371396] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  385.375644] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.375756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.375796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.375835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.375870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.375905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.375940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.375975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.376010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.376043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.376079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.376116] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.376151] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.376217] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  385.376252] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  385.376537] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  385.377537] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  385.378108] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  385.378145] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  385.378200] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  385.378235] [drm:hsw_audio_config_update [i915]] using automatic N
>[  385.395175] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.395242] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.395438] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.396270] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.396329] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.396390] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.396445] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.396502] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.396560] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.396617] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.396672] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.396803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.396815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.396876] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.396886] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.396944] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.397004] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.397066] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.397129] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.397190] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.397254] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.397314] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.397378] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.397443] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.397503] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.397568] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.397629] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.397744] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  385.397817] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.397877] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.411916] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  385.411993] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  385.412126] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  385.428788] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  385.428951] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  385.429124] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  385.433385] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.433469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.433557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.433646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.433837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.433917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.434002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.434085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.434172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.434254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.434339] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.434432] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.434522] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.434644] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  385.434797] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.434914] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.435012] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.435103] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.435195] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.435288] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.435372] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  385.435446] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  385.436107] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.437548] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.437634] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.437819] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.437872] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.437930] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.437985] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.438041] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.438094] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.438148] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.438161] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.438212] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.438220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.438273] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.438329] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.438384] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.438439] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.438493] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.438552] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.438606] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.438664] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.438761] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.438821] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.438876] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.438932] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.439018] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  385.439095] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.439154] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.439354] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.439401] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.439759] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  385.440336] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.440387] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.440465] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  385.440822] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  385.445050] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.445107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.445166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.445227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.445282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.445337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.445391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.445444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.445498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.445551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.445607] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.445665] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.445796] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.445888] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  385.445944] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  385.446284] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  385.447810] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  385.448391] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  385.448446] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  385.448524] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  385.448575] [drm:hsw_audio_config_update [i915]] using automatic N
>[  385.465467] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.465549] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.465896] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.466681] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.466815] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.466885] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.466950] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.467015] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.467081] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.467147] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.467214] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.467278] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.467295] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.467355] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.467367] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.467432] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.467495] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.467564] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.467631] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.467814] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.467881] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.467943] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.468009] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.468073] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.468136] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.468200] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.468263] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.468362] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  385.468441] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.468506] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.482241] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  385.482338] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  385.482494] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  385.500515] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  385.500692] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  385.501039] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  385.505333] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.505426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.505524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.505624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.505836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.505929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.506029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.506125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.506226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.506322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.506416] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.506518] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.506619] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.506829] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  385.506924] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.507054] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.507162] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.507262] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.507365] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.507465] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.507559] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  385.507642] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  385.508332] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.510036] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.510128] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.510222] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.510307] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.510396] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.510484] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.510572] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.510658] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.510840] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.510857] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.510950] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.510966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.511063] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.511158] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.511253] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.511347] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.511444] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.511545] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.511642] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.511784] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.511884] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.511972] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.512073] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.512160] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.512294] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  385.512408] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.512501] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.512953] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.513009] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.513319] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  385.513403] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.513465] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.513558] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  385.514238] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  385.518498] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.518575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.518613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.518652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.518734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.518901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.518936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.518970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.519005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.519039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.519074] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.519113] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.519150] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.519218] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  385.519254] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  385.519507] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  385.520734] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  385.521268] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  385.521303] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  385.521354] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  385.521386] [drm:hsw_audio_config_update [i915]] using automatic N
>[  385.538363] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.538438] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.538649] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.539629] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.539752] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.539811] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.540074] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.540129] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.540184] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.540237] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.540288] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.540339] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.540350] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.540401] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.540407] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.540459] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.540511] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.540563] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.540615] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.540666] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.540788] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.540841] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.540905] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.540963] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.541023] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.541079] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.541138] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.541221] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  385.541294] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.541947] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.555056] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  385.555130] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  385.555250] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  385.573499] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  385.573662] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  385.573974] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  385.578246] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.578332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.578421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.578511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.578592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.578674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.578861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.578941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.579027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.579111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.579196] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.579290] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.579379] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.579504] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  385.579590] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.579781] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.579889] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.579978] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.580074] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.580166] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.580250] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  385.580324] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  385.580985] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.582465] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.582547] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.582631] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.582797] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.582883] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.582969] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.583055] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.583138] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.583224] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.583242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.583325] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.583337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.583423] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.583508] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.583596] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.583678] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.583825] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.583913] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.583996] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.584094] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.584178] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.584268] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.584353] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.584436] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.584572] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  385.584661] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.584805] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.585034] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.585089] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.585401] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  385.585486] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.585546] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.585639] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  385.586283] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  385.590433] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.590470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.590508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.590547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.590583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.590617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.590650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.590731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.590767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.590803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.590838] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.590878] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.590916] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.590985] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  385.591020] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  385.591576] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  385.592735] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  385.593269] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  385.593303] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  385.593355] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  385.593387] [drm:hsw_audio_config_update [i915]] using automatic N
>[  385.610381] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.610467] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.610791] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.611595] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.611658] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.611795] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.611857] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.611926] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.611994] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.612060] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.612126] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.612189] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.612205] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.612266] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.612278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.612343] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.612409] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.612475] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.612542] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.612603] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.612696] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.612816] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.612888] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.612957] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.613025] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.613099] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.613170] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.613275] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  385.613363] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.613432] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.627103] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  385.627192] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  385.627338] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  385.644055] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  385.644228] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  385.644417] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  385.648684] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.648834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.648922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.649012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.649093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.649174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.649255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.649336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.649417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.649497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.649577] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.649663] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.649828] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.649947] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  385.650032] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.650146] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.650243] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.650332] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.650425] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.650536] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.650630] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  385.650793] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  385.651400] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.653095] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.653189] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.653283] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.653368] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.653457] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.653544] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.653633] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.653805] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.653894] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.653922] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.654009] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.654027] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.654123] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.654215] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.654314] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.654407] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.654502] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.654600] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.654699] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.654842] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.654937] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.655033] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.655126] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.655221] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.655357] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  385.655470] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.655563] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.655912] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.655967] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.656283] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  385.656368] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.656431] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.656523] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  385.656847] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  385.661110] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.661186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.661225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.661265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.661300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.661335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.661370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.661403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.661438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.661471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.661507] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.661544] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.661579] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.661645] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  385.661728] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  385.662300] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  385.663426] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  385.663997] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  385.664032] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  385.664086] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  385.664126] [drm:hsw_audio_config_update [i915]] using automatic N
>[  385.681078] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.681153] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.681367] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.682096] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.682151] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.682210] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.682261] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.682315] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.682368] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.682422] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.682474] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.682525] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.682534] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.682585] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.682591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.682643] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.682759] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.682812] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.682870] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.682924] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.682983] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.683037] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.683096] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.683151] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.683208] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.683263] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.683318] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.683396] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  385.683465] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.683521] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.697801] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  385.697872] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  385.697985] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  385.714608] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  385.714871] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  385.715044] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  385.719283] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.719360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.719439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.719521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.719596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.719669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.719832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.719915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.719994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.720075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.720153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.720240] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.720320] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.720425] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  385.720500] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.720602] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.720706] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.720849] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.720942] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.721037] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.721124] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  385.721197] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  385.721839] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.723322] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.723403] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.723488] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.723564] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.723644] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.723808] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.723891] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.723981] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.724065] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.724085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.724163] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.724180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.724265] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.724345] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.724425] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.724504] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.724583] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.724668] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.724828] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.724932] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.725022] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.725118] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.725210] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.725310] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.725442] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  385.725554] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.725649] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.726006] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.726088] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.726424] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  385.726543] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.726629] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.726807] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  385.727112] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  385.731349] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.731394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.731441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.731489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.731533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.731575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.731617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.731659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.731756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.731801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.731847] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.731898] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.731946] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.732024] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  385.732067] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  385.732348] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  385.733599] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  385.734204] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  385.734248] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  385.734313] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  385.734355] [drm:hsw_audio_config_update [i915]] using automatic N
>[  385.751241] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.751299] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.751483] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.752128] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.752171] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.752217] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.752258] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.752301] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.752344] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.752387] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.752428] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.752468] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.752477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.752517] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.752522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.752564] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.752604] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.752645] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.752782] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.752837] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.752900] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.752956] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.753018] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.753074] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.753131] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.753188] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.753246] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.753326] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  385.753393] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.753449] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.767998] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  385.768079] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  385.768209] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  385.784967] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  385.785129] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  385.785302] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  385.789555] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.789638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.789821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.789916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.790001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.790084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.790168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.790250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.790335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.790417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.790500] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.790589] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.790679] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.790855] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  385.790938] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.791051] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.791152] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.791247] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.791342] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.791436] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.791524] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  385.791598] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  385.792273] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.793715] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.793848] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.793933] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.794009] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.794091] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.794171] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.794250] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.794327] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.794403] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.794416] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.794493] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.794501] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.794580] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.794658] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.794809] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.794891] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.794981] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.795071] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.795155] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.795245] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.795331] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.795414] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.795502] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.795585] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.795752] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  385.795857] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.795940] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.796221] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.796291] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.796635] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  385.797226] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.797282] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.797368] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  385.797671] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  385.802016] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.802059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.802103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.802149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.802191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.802233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.802273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.802313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.802356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.802396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.802439] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.802482] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.802525] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.802599] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  385.802638] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  385.802964] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  385.804103] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  385.804646] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  385.804728] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  385.804789] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  385.804830] [drm:hsw_audio_config_update [i915]] using automatic N
>[  385.821737] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.821794] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.821975] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.822667] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.822807] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.822880] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.822941] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.823008] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.823074] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.823135] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.823199] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.823259] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.823273] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.823332] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.823342] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.823403] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.823467] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.823529] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.823594] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.823655] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.823770] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.823838] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.823910] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.823977] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.824044] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.824108] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.824178] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.824274] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  385.824353] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.824417] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.838446] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  385.838528] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  385.838659] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  385.855399] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  385.855575] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  385.855869] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  385.860119] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.860202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.860290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.860380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.860461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.860542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.860623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.860704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.860885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.860968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.861053] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.861149] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.861241] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.861363] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  385.861446] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.861557] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.861652] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.861800] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.861896] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.861991] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.862074] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  385.862147] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  385.862786] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.864274] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.864357] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.864442] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.864519] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.864599] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.864679] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.864840] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.864924] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.865010] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.865032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.865111] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.865127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.865211] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.865294] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.865380] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.865464] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.865549] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.865640] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.865767] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.865852] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.865936] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.866023] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.866112] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.866214] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.866322] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  385.866415] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.866490] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.866801] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.866853] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.867157] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  385.867235] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.867293] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.867377] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  385.867758] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  385.872006] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.872050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.872098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.872146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.872190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.872232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.872275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.872318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.872363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.872405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.872450] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.872495] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.872540] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.872616] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  385.872658] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  385.872995] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  385.874202] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  385.874805] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  385.874849] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  385.874914] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  385.874957] [drm:hsw_audio_config_update [i915]] using automatic N
>[  385.891885] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.891945] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.892130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.892859] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.892924] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.892993] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.893055] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.893121] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.893186] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.893250] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.893311] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.893374] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.893387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.893448] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.893457] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.893518] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.893582] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.893645] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.893760] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.893825] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.893897] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.893961] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.894031] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.894096] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.894164] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.894230] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.894296] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.894391] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  385.894476] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.894544] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.908565] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  385.908646] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  385.909298] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  385.925221] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  385.925391] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  385.925577] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  385.929864] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.929948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.930035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.930125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.930207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.930288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.930369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.930450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.930531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.930611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.930691] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.930884] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.930975] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.931100] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  385.931183] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.931294] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.931389] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.931477] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.931567] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.931658] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.931843] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  385.931930] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  385.932532] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.934156] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.934247] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.934340] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.934425] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.934514] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.934603] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.934691] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.934870] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.934961] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.934982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.935075] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.935092] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.935182] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.935276] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.935369] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.935467] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.935558] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.935658] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.935801] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.935907] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.935998] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.936096] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.936193] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.936287] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.936420] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  385.936531] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.936620] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.936992] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.937070] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.937393] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  385.937468] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.937525] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.937610] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  385.937950] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  385.942194] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  385.942239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  385.942286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  385.942335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  385.942379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  385.942422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  385.942466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  385.942508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  385.942552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  385.942594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  385.942639] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  385.942742] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  385.942794] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.942873] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  385.942915] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  385.943202] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  385.944411] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  385.945017] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  385.945060] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  385.945122] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  385.945163] [drm:hsw_audio_config_update [i915]] using automatic N
>[  385.962106] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  385.962185] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  385.962405] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  385.963288] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  385.963351] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.963417] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  385.963475] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  385.963537] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.963599] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  385.963660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  385.963795] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  385.963859] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.963875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.963940] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.963953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  385.964017] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  385.964082] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  385.964147] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  385.964212] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.964278] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.964346] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  385.964411] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.964479] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  385.964547] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  385.964613] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  385.964674] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  385.964774] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  385.964865] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  385.964941] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  385.965003] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  385.978945] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  385.979054] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  385.979221] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  385.995974] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  385.996145] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  385.996327] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  386.000556] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.000639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.000826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.000916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.000998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.001077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.001159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.001240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.001325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.001407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.001491] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.001580] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.001670] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.001875] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  386.001972] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.002099] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.002201] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.002296] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.002393] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.002491] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.002581] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  386.002663] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  386.003324] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.005011] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.005102] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.005195] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.005280] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.005369] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.005458] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.005545] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.005630] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.005801] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.005824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.005912] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.005930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.006024] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.006116] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.006214] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.006309] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.006404] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.006505] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.006601] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.006700] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.006839] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.006937] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.007031] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.007123] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.007258] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  386.007369] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.007458] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.007815] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.007892] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.008228] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  386.008341] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.008427] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.008552] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  386.009001] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  386.013280] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.013349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.013387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.013426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.013461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.013494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.013530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.013563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.013600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.013633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.013716] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.013755] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.013794] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.013862] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  386.013895] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  386.014151] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  386.015147] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  386.015713] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  386.015749] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  386.015800] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  386.015834] [drm:hsw_audio_config_update [i915]] using automatic N
>[  386.032820] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.032870] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.033034] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.033670] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.033787] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.033851] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.033908] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.033970] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.034027] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.034084] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.034140] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.034196] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.034207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.034260] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.034268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.034322] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.034377] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.034430] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.034486] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.034541] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.034601] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.034655] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.034749] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.034809] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.034868] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.034926] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.034983] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.035067] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  386.035135] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.035190] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.049488] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  386.049560] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.049676] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  386.066413] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  386.066575] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  386.066844] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  386.071108] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.071192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.071279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.071370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.071452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.071533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.071614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.071695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.071875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.071959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.072047] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.072142] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.072233] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.072351] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  386.072432] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.072540] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.072637] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.072779] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.072874] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.072972] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.073053] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  386.073123] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  386.073767] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.075252] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.075335] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.075420] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.075497] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.075577] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.075657] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.075815] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.075902] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.075983] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.076003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.076082] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.076098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.076184] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.076269] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.076357] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.076442] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.076526] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.076614] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.076693] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.076822] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.076905] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.076990] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.077069] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.077152] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.077268] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  386.077371] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.077451] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.077781] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.077824] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.078128] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  386.078196] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.078244] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.078321] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  386.078624] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  386.082891] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.082934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.082979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.083026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.083067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.083107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.083151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.083191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.083235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.083274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.083317] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.083360] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.083404] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.083479] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  386.083518] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  386.083827] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  386.084961] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  386.085504] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  386.085545] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  386.085605] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  386.085644] [drm:hsw_audio_config_update [i915]] using automatic N
>[  386.102557] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.102615] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.102935] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.103783] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.103849] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.103913] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.103974] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.104038] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.104100] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.104163] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.104223] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.104283] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.104294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.104354] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.104361] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.104422] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.104483] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.104544] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.104608] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.104668] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.104781] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.104848] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.104917] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.104984] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.105051] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.105117] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.105186] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.105279] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  386.105365] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.105432] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.119290] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  386.119371] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.119501] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  386.136200] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  386.136377] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  386.136565] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  386.140920] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.141013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.141110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.141208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.141298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.141387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.141476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.141566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.141656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.141857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.141952] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.142059] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.142159] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.142295] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  386.142385] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.142506] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.142608] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.142703] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.142858] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.142963] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.143057] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  386.143138] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  386.143798] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.145383] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.145473] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.145566] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.145651] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.145832] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.145927] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.146023] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.146120] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.146212] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.146236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.146321] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.146335] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.146431] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.146520] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.146612] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.146706] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.146877] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.146989] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.147087] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.147193] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.147294] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.147393] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.147493] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.147595] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.147811] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  386.147944] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.148050] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.148393] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.148478] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.148886] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  386.149463] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.149561] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.149703] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  386.150216] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  386.154456] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.154536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.154573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.154612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.154647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.154727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.154761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.154798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.154834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.154872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.154908] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.154948] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.154984] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.155049] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  386.155082] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  386.155369] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  386.156362] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  386.156926] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  386.156964] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  386.157017] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  386.157050] [drm:hsw_audio_config_update [i915]] using automatic N
>[  386.173980] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.174039] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.174221] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.174863] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.174911] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.174962] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.175009] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.175060] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.175109] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.175158] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.175206] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.175254] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.175265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.175312] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.175319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.175368] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.175415] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.175463] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.175514] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.175561] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.175614] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.175662] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.175840] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.175902] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.175966] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.176028] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.176090] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.176177] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  386.176250] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.176311] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.190782] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  386.190869] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.191008] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  386.207649] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  386.207875] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  386.208047] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  386.212308] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.212386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.212467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.212550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.212624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.212698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.212876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.212953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.213033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.213415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.213490] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.213575] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.213656] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.213868] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  386.213988] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.214112] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.214220] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.214318] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.214419] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.214520] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.214613] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  386.214695] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  386.215355] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.217030] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.217122] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.217215] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.217300] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.217389] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.217478] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.217566] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.217651] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.217826] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.217847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.217941] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.217957] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.218047] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.218148] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.218240] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.218339] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.218434] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.218538] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.218629] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.218771] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.218864] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.218963] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.219053] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.219149] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.219282] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  386.219395] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.219487] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.219838] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.219891] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.220203] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  386.220286] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.220347] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.220439] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  386.220823] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  386.225078] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.225157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.225195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.225234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.225269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.225304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.225337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.225370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.225405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.225438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.225474] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.225511] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.225546] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.225613] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  386.225645] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  386.225943] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  386.226940] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  386.227472] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  386.227507] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  386.227558] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  386.227591] [drm:hsw_audio_config_update [i915]] using automatic N
>[  386.244534] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.244607] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.244880] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.245574] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.245629] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.245736] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.245788] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.245847] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.245902] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.245958] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.246012] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.246069] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.246080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.246133] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.246142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.246197] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.246251] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.246307] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.246362] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.246418] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.246477] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.246532] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.246589] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.246646] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.246734] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.246791] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.246845] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.246925] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  386.246993] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.247049] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.261273] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  386.261362] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.261501] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  386.278035] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  386.278196] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  386.278366] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  386.282638] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.282798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.282895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.282994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.283082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.283172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.283261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.283351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.283441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.283529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.283617] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.283801] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.283904] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.284043] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  386.284138] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.284260] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.284363] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.284459] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.284556] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.284655] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.284822] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  386.284910] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  386.285518] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.287202] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.287292] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.287386] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.287471] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.287560] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.287648] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.287822] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.287912] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.288011] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.288033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.288126] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.288144] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.288239] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.288332] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.288429] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.288521] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.288615] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.288715] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.288849] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.288946] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.289039] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.289135] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.289231] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.289319] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.289450] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  386.289564] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.289656] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.289952] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.289996] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.290298] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  386.290366] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.290416] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.290489] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  386.290788] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  386.295033] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.295079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.295127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.295176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.295220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.295263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.295307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.295351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.295394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.295436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.295480] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.295526] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.295570] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.295647] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  386.295752] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  386.296042] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  386.297259] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  386.297865] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  386.297911] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  386.297976] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  386.298019] [drm:hsw_audio_config_update [i915]] using automatic N
>[  386.314914] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.314982] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.315180] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.315932] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.315994] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.316058] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.316115] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.316179] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.316237] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.316297] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.316354] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.316413] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.316426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.316482] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.316491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.316548] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.316608] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.316666] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.316814] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.316882] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.316955] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.317019] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.317088] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.317154] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.317222] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.317287] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.317352] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.317446] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  386.317528] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.317590] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.331659] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  386.331804] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.331937] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  386.348638] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  386.348881] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  386.349067] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  386.353334] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.353419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.353507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.353597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.353678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.353866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.353966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.354049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.354134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.354216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.354300] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.354391] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.354481] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.354603] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  386.354686] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.354906] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.355016] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.355116] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.355221] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.355323] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.355416] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  386.355498] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  386.356180] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.357786] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.357879] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.357973] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.358058] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.358146] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.358235] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.358323] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.358408] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.358493] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.358508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.358593] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.358603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.358691] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.358860] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.358953] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.359050] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.359145] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.359250] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.359344] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.359443] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.359536] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.359636] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.359772] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.359869] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.359999] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  386.360118] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.360212] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.360519] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.360598] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.360982] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  386.361545] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.361607] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.361772] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  386.362100] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  386.366288] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.366357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.366402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.366448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.366490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.366531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.366573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.366612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.366656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.366751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.366794] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.366842] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.366891] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.367217] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  386.367259] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  386.367545] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  386.368861] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  386.369404] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  386.369445] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  386.369505] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  386.369544] [drm:hsw_audio_config_update [i915]] using automatic N
>[  386.386467] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.386548] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.387066] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.388079] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.388138] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.388199] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.388254] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.388311] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.388368] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.388426] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.388480] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.388535] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.388545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.388602] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.388608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.388664] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.388782] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.388841] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.388905] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.388962] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.389029] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.389090] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.389157] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.389217] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.389282] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.389342] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.389406] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.389491] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  386.390159] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.390226] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.403218] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  386.403308] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.403448] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  386.420143] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  386.420315] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  386.420502] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  386.424793] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.424887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.424984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.425083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.425173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.425263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.425353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.425443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.425533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.425621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.425709] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.425922] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.426020] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.426160] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  386.426254] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.426379] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.426486] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.426584] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.426685] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.426855] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.426949] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  386.427036] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  386.427644] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.429234] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.429327] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.429421] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.429507] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.429596] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.429683] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.429860] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.429948] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.430047] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.430071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.430163] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.430182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.430278] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.430372] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.430465] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.430563] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.430659] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.430824] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.430914] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.431009] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.431100] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.431191] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.431288] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.431383] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.431515] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  386.431630] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.431789] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.432013] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.432067] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.432377] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  386.432465] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.432525] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.432616] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  386.432980] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  386.437246] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.437320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.437358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.437397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.437432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.437467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.437502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.437535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.437572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.437607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.437641] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.437726] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.437766] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.438059] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  386.438094] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  386.438349] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  386.439484] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  386.440055] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  386.440096] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  386.440149] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  386.440183] [drm:hsw_audio_config_update [i915]] using automatic N
>[  386.457112] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.457186] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.457391] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.458400] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.458455] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.458513] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.458564] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.458619] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.458672] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.458798] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.458854] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.458910] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.458927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.458979] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.458989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.459043] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.459102] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.459160] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.459219] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.459750] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.459808] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.459864] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.459921] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.459979] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.460033] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.460089] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.460145] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.460230] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  386.460300] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.460356] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.473885] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  386.473959] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.474075] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  386.490787] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  386.490951] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  386.491123] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  386.495385] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.495468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.495555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.495646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.495826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.495926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.496009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.496094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.496177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.496263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.496345] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.496440] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.496527] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.496651] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  386.496809] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.496921] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.497021] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.497110] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.497201] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.497293] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.497376] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  386.497450] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  386.498111] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.499589] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.499671] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.499838] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.499917] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.500006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.500089] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.500173] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.500250] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.500333] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.500349] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.500428] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.500442] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.500524] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.500604] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.500688] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.500828] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.500913] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.501008] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.501093] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.501182] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.501264] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.501349] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.501434] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.501518] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.501637] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  386.501785] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.501872] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.502150] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.502221] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.502547] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  386.502657] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.502804] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.502884] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  386.503184] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  386.507448] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.507489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.507532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.507577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.507617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.507657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.507748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.507789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.507830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.507873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.508077] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.508123] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.508165] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.508240] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  386.508279] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  386.508557] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  386.509874] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  386.510433] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  386.510472] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  386.510530] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  386.510567] [drm:hsw_audio_config_update [i915]] using automatic N
>[  386.527489] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.527559] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.528089] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.529111] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.529173] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.529234] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.529289] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.529346] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.529403] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.529461] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.529515] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.529570] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.529579] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.529634] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.529712] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.529771] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.529833] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.529893] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.529958] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.530017] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.530081] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.530140] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.530208] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.530270] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.530332] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.530394] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.530457] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.530543] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  386.531201] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.531261] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.544217] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  386.544292] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.544416] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  386.561104] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  386.561267] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  386.561438] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  386.565700] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.565857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.565945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.566035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.566116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.566198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.566279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.566360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.566441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.566520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.566600] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.566686] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.566862] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.566983] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  386.567069] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.567184] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.567282] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.567371] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.567462] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.567573] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.567666] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  386.567831] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  386.568435] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.570073] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.570165] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.570259] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.570344] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.570434] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.570522] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.570610] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.570695] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.570880] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.570898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.570993] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.571009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.571105] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.571197] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.571296] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.571391] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.571488] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.571586] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.571680] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.571832] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.571925] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.572023] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.572115] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.572213] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.572343] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  386.572460] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.572553] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.572907] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.572962] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.573273] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  386.573357] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.573419] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.573513] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  386.574129] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  386.578391] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.578467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.578505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.578544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.578580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.578615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.578649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.578730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.578766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.578802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.578839] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.578879] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.578919] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.579203] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  386.579239] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  386.579494] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  386.580703] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  386.581237] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  386.581271] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  386.581323] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  386.581355] [drm:hsw_audio_config_update [i915]] using automatic N
>[  386.598314] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.598362] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.598527] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.599426] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.599481] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.599539] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.599590] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.599644] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.599762] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.599819] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.599878] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.599934] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.599951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.600003] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.600015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.600071] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.600128] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.600186] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.600243] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.600300] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.600362] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.600963] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.601024] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.601079] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.601136] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.601191] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.601247] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.601331] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  386.601402] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.601456] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.615019] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  386.615090] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.615207] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  386.631969] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  386.632132] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  386.632302] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  386.636563] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.636648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.636836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.636939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.637022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.637108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.637190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.637274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.637357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.637442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.637523] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.637615] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.637777] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.637902] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  386.637988] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.638103] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.638199] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.638288] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.638380] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.638472] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.638556] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  386.638629] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  386.639295] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.640895] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.640979] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.641064] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.641140] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.641220] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.641299] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.641378] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.641454] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.641530] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.641544] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.641620] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.641629] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.641787] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.641871] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.641959] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.642045] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.642131] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.642222] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.642308] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.642397] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.642485] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.642568] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.642654] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.642811] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.642945] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  386.643059] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.643155] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.643464] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.643543] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.643937] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  386.644494] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.644556] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.644647] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  386.645225] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  386.649496] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.649538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.649581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.649627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.649717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.649759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.649800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.649842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.650105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.650143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.650183] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.650226] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.650267] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.650340] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  386.650379] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  386.650649] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  386.652112] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  386.652708] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  386.652755] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  386.652815] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  386.652853] [drm:hsw_audio_config_update [i915]] using automatic N
>[  386.669814] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.669889] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.670101] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.670844] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.670911] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.670971] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.671026] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.671081] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.671137] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.671192] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.671247] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.671301] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.671314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.671365] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.671373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.671428] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.671482] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.671536] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.671591] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.671648] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.671799] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.671861] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.671934] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.671999] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.672068] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.672132] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.672198] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.672294] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  386.672376] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.672443] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.686510] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  386.686593] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.686998] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  386.703677] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  386.703925] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  386.704111] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  386.708373] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.708457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.708544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.708633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.708812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.708899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.708984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.709074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.709181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.709269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.709356] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.709457] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.709557] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.709688] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  386.709845] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.709972] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.710079] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.710176] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.710273] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.710374] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.710465] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  386.710549] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  386.711212] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.712684] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.712815] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.712900] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.712977] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.713059] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.713139] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.713219] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.713296] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.713372] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.713386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.713462] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.713471] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.713550] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.713627] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.713778] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.713860] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.713950] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.714038] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.714124] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.714217] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.714304] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.714389] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.714476] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.714559] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.714683] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  386.714833] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.714893] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.715080] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.715127] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.715424] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  386.715497] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.715551] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.715632] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  386.715941] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  386.720192] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.720235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.720279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.720325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.720365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.720405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.720444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.720484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.720525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.720565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.720607] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.720650] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.720746] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.720822] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  386.720862] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  386.721137] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  386.722299] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  386.722878] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  386.722920] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  386.722982] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  386.723021] [drm:hsw_audio_config_update [i915]] using automatic N
>[  386.739934] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.740008] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.740220] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.741041] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.741104] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.741170] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.741231] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.741295] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.741358] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.741420] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.741481] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.741541] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.741553] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.741612] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.741621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.741682] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.741811] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.741879] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.741945] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.742010] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.742082] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.742147] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.742216] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.742281] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.742347] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.742412] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.742481] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.742571] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  386.742652] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.742752] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.756655] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  386.756869] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.757030] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  386.773702] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  386.773940] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  386.774125] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  386.778397] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.778490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.778586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.778685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.778879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.778975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.779068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.779166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.779255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.779345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.779436] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.779535] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.779634] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.779832] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  386.779921] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.780045] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.780148] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.780246] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.780346] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.780448] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.780540] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  386.780622] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  386.781258] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.782933] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.783025] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.783118] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.783203] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.783292] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.783381] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.783469] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.783554] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.783639] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.783737] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.783826] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.783843] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.783939] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.784031] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.784128] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.784220] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.784318] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.784417] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.784515] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.784613] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.784712] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.784849] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.784939] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.785034] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.785160] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  386.785271] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.785363] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.785653] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.785809] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.786105] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  386.786172] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.786219] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.786292] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  386.786578] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  386.790768] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.790813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.790860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.790908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.790951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.790992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.791036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.791077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.791121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.791162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.791207] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.791252] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.791297] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.791374] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  386.791415] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  386.791744] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  386.792942] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  386.793506] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  386.793549] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  386.793612] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  386.793652] [drm:hsw_audio_config_update [i915]] using automatic N
>[  386.810488] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.810558] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.810869] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.811590] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.811653] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.811785] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.811846] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.811917] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.811982] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.812048] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.812111] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.812178] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.812192] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.812255] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.812266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.812333] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.812398] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.812465] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.812527] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.812593] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.812659] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.812792] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.812866] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.812932] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.812999] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.813066] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.813131] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.813229] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  386.813314] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.813384] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.827297] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  386.827385] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.827524] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  386.844181] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  386.844356] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  386.844544] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  386.848896] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.848989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.849087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.849187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.849275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.849366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.849455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.849542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.849634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.849831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.849929] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.850035] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.850138] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.850271] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  386.850362] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.850484] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.850590] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.850687] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.850851] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.850952] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.851049] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  386.851130] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  386.851806] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.853338] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.853429] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.853522] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.853607] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.853696] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.853873] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.853964] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.854061] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.854155] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.854173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.854259] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.854277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.854373] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.854467] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.854563] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.854657] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.854798] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.854896] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.854983] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.855081] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.855172] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.855258] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.855347] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.855462] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.855533] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  386.855598] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.855651] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.855865] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.855909] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.856203] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  386.856270] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.856319] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.856395] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  386.856747] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  386.860986] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.861065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.861103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.861142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.861177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.861210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.861243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.861276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.861312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.861345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.861383] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.861419] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.861454] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.861520] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  386.861554] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  386.861846] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  386.862840] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  386.863372] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  386.863407] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  386.863458] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  386.863490] [drm:hsw_audio_config_update [i915]] using automatic N
>[  386.880443] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.880491] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.880655] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.881194] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.881228] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.881264] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.881296] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.881332] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.881367] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.881401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.881433] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.881465] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.881473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.881505] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.881509] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.881542] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.881574] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.881607] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.881639] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.881756] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.881813] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.881865] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.881924] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.881977] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.882032] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.882086] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.882140] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.882216] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  386.882280] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.882335] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.897123] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  386.897188] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.897297] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  386.913984] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  386.914135] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  386.914292] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  386.918535] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.918612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.918691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.918859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.918932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.919006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.919078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.919153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.919227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.919304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.919379] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.919462] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.919542] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.919652] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  386.919786] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.919888] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.919979] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.920057] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.920137] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.920217] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.920291] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  386.920360] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  386.920999] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.922378] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.922453] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.922531] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.922600] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.922673] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.922820] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.922895] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.922973] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.923048] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.923068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.923139] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.923152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.923230] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.923308] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.923388] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.923465] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.923543] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.923619] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.923694] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.923810] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.923885] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.923959] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.924032] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.924103] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.924206] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  386.924301] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.924374] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.924623] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.924710] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.925032] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  386.925128] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.925198] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.925303] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  386.925575] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  386.929822] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.929879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.929938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.929998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.930051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.930104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.930158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.930211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.930266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.930319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.930374] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.930432] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.930488] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.930578] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  386.930631] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  386.931034] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  386.932373] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  386.932977] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  386.933021] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  386.933086] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  386.933128] [drm:hsw_audio_config_update [i915]] using automatic N
>[  386.950019] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.950090] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.950295] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.951125] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.951188] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.951258] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.951317] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.951383] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.951446] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.951510] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.951570] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.951630] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.951700] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.951767] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.951776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.951845] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.951909] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.951974] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.952039] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.952104] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.952172] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.952237] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.952306] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.952375] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.952440] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.952509] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.952577] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.952668] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  386.952818] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.952887] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.966812] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  386.966899] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  386.967038] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  386.983720] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  386.983957] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  386.984144] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  386.988412] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  386.988504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  386.988601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  386.988700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  386.988894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  386.988990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  386.989085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  386.989179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  386.989270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  386.989360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  386.989449] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  386.989550] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  386.989647] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.989846] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  386.989939] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  386.990061] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  386.990165] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  386.990262] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  386.990360] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  386.990460] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.990550] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  386.990631] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  386.991308] [drm:intel_power_well_disable [i915]] disabling always-on
>[  386.992985] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  386.993075] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  386.993169] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  386.993254] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  386.993343] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  386.993430] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  386.993518] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  386.993603] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  386.993688] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  386.993799] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.993893] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  386.993906] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  386.994008] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  386.994100] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  386.994198] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  386.994293] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.994388] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  386.994484] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  386.994580] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  386.994682] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  386.994825] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  386.994889] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  386.994955] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  386.995019] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  386.995115] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  386.995196] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  386.995259] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  386.995483] [drm:intel_power_well_enable [i915]] enabling always-on
>[  386.995537] [drm:intel_power_well_enable [i915]] enabling DC off
>[  386.995900] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  386.996467] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  386.996519] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  386.996598] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  386.996907] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  387.001154] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.001196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.001241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.001287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.001329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.001371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.001410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.001452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.001493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.001533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.001575] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.001618] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.001661] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.001790] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  387.001831] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  387.002108] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  387.003262] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  387.003842] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  387.003886] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  387.003949] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  387.003987] [drm:hsw_audio_config_update [i915]] using automatic N
>[  387.020904] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.020977] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  387.021188] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.022045] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.022110] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.022176] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.022237] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.022301] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.022363] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  387.022426] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  387.022487] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.022548] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.022560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.022618] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.022627] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.022759] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.022827] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.022892] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  387.022961] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.023027] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.023099] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.023164] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.023235] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.023300] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.023366] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  387.023435] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  387.023501] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  387.023594] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  387.023670] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  387.023808] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  387.037659] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  387.037803] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.037947] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  387.054635] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  387.054879] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  387.055066] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  387.059355] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.059447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.059544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.059644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.059846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.059939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.060035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.060129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.060227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.060316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.060407] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.060505] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.060602] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.060802] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  387.060899] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  387.061026] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  387.061130] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.061225] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  387.061323] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.061427] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.061518] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  387.061602] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  387.062264] [drm:intel_power_well_disable [i915]] disabling always-on
>[  387.063642] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  387.063922] [drm:intel_power_well_enable [i915]] enabling always-on
>[  387.063997] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.064326] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  387.064459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.064555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.064648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.064835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.064929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.065023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.065127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.065223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.065322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.065417] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.065515] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.065621] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.065749] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.065870] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  387.065925] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.065978] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  387.066022] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  387.066580] [drm:intel_power_well_disable [i915]] disabling always-on
>[  387.067223] [drm:drm_mode_addfb2] [FB:89]
>[  387.067306] [drm:drm_mode_addfb2] [FB:91]
>[  387.123733] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  387.124183] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  387.124840] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  387.125394] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  387.125417] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  387.125522] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.125558] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.125595] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.125627] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.125710] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.125745] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.125779] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.125813] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.125848] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.125854] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.125886] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.125891] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.125924] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.125959] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.125993] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.126028] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.126062] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.126099] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.126132] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.126165] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  387.126200] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.126234] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.126288] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  387.126336] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.126371] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.126757] [drm:intel_power_well_enable [i915]] enabling always-on
>[  387.126787] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.127069] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  387.127117] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  387.127151] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  387.127203] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  387.127460] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  387.131684] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.131796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.131834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.131874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.131909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.131944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.131979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.132014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.132049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.132083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.132118] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.132155] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.132190] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.132257] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  387.132289] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  387.132576] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  387.133559] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  387.134105] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  387.134143] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  387.134196] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  387.134230] [drm:hsw_audio_config_update [i915]] using automatic N
>[  387.151146] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.151213] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.151409] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.184890] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.184953] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.185015] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.185069] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.185128] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.185186] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.185243] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.185298] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.185352] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.185362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.185417] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.185423] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.185480] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.185535] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.185590] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.185648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.185764] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.185827] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.185889] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.185954] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.186018] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.186078] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.186141] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.186237] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  387.186316] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.186378] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.201283] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  387.201382] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.201527] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  387.218165] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  387.218339] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  387.218505] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  387.222798] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.222892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.222990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.223090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.223180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.223269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.223358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.223448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.223538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.223627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.223845] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.223946] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.224046] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.224183] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  387.224275] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  387.224398] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  387.224507] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.224605] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.224706] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.224852] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.224947] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  387.225029] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  387.225631] [drm:intel_power_well_disable [i915]] disabling always-on
>[  387.228088] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.228181] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.228275] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.228360] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.228450] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.228539] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.228627] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.228812] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.228901] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.228918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.229004] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.229020] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.229108] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.229198] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.229290] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.229380] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.229472] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.229568] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.229659] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.229802] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.229897] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.229986] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.230078] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.230210] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  387.230327] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.230418] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.230779] [drm:intel_power_well_enable [i915]] enabling always-on
>[  387.230862] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.231193] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  387.231311] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  387.231401] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  387.231528] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  387.231974] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  387.237164] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.237235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.237275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.237314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.237350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.237385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.237419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.237454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.237489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.237522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.237558] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.237594] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.237630] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.237747] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  387.237963] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  387.238228] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  387.239415] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  387.239968] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  387.240004] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  387.240208] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  387.240240] [drm:hsw_audio_config_update [i915]] using automatic N
>[  387.257019] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.257091] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.257297] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.258310] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.258366] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.258424] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.258475] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.258530] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.258584] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.258638] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.258759] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.258814] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.258827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.258880] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.258891] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.258950] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.259007] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.259066] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.259123] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.259180] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.259243] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.259299] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.259921] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.259976] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.260034] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.260089] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.260175] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  387.260247] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.260300] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.273806] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  387.273879] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.273997] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  387.290670] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  387.290896] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  387.291049] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  387.295301] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.295380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.295461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.295544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.295618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.295692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.295865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.295943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.296424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.296499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.296572] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.296655] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.296816] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.297211] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  387.297288] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  387.297388] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  387.297474] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.297556] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.297634] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.297795] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.297872] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  387.297964] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  387.298547] [drm:intel_power_well_disable [i915]] disabling always-on
>[  387.299517] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.299591] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.299668] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.299814] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.299897] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.299974] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.300054] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.300131] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.300209] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.300223] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.300295] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.300306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.300380] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.300454] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.300530] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.300605] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.300700] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.300847] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.300941] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.301047] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.301141] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.301239] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.301335] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.301476] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  387.301589] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.301682] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.302048] [drm:intel_power_well_enable [i915]] enabling always-on
>[  387.302123] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.302449] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  387.302555] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  387.302632] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  387.302811] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  387.303097] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  387.307343] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.307388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.307436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.307485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.307529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.307572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.307616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.307659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.307758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.307802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.307848] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.307899] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.307949] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.308028] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  387.308073] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  387.308357] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  387.309559] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  387.310145] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  387.310191] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  387.310256] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  387.310297] [drm:hsw_audio_config_update [i915]] using automatic N
>[  387.327189] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.327266] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.327480] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.328370] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.328435] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.328500] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.328559] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.328620] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.328683] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.328854] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.328926] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.328994] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.329011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.329077] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.329091] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.329162] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.329234] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.329307] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.329373] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.329446] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.329520] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.329588] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.329657] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.329767] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.329835] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.329906] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.330009] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  387.330092] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.330159] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.343957] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  387.344043] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.344185] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  387.360938] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  387.361112] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  387.361279] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  387.365546] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.365630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.365816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.365906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.365988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.366067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.366151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.366235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.366319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.366401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.366486] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.366575] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.366665] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.366886] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  387.366983] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  387.367108] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  387.367213] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.367308] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.367406] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.367505] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.367597] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  387.367679] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  387.368346] [drm:intel_power_well_disable [i915]] disabling always-on
>[  387.370024] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.370115] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.370209] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.370294] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.370383] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.370469] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.370557] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.370642] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.370819] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.370840] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.370927] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.370949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.371045] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.371137] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.371235] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.371330] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.371424] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.371524] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.371618] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.371766] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.371864] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.371961] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.372056] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.372191] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  387.372304] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.372397] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.372772] [drm:intel_power_well_enable [i915]] enabling always-on
>[  387.372832] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.373126] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  387.373189] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  387.373235] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  387.373304] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  387.373593] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  387.377837] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.377916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.377954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.377993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.378028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.378061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.378096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.378129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.378167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.378200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.378235] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.378272] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.378308] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.378374] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  387.378407] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  387.378736] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  387.379716] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  387.380230] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  387.380265] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  387.380317] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  387.380349] [drm:hsw_audio_config_update [i915]] using automatic N
>[  387.397299] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.397349] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.397515] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.398278] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.398334] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.398391] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.398442] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.398497] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.398551] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.398603] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.398654] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.398771] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.398785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.398838] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.398849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.398907] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.398963] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.399022] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.399079] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.399136] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.399197] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.399255] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.399317] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.399375] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.399432] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.399490] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.399569] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  387.399638] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.399731] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.413999] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  387.414069] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.414185] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  387.430863] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  387.431026] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  387.431177] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  387.435430] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.435514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.435601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.435691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.435872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.435955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.436041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.436127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.436214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.436296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.436380] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.436471] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.436559] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.436682] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  387.436823] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  387.436942] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  387.437038] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.437126] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.437216] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.437305] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.437388] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  387.437463] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  387.438110] [drm:intel_power_well_disable [i915]] disabling always-on
>[  387.439614] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.439696] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.439863] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.439946] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.440030] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.440114] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.440195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.440277] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.440357] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.440375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.440452] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.440465] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.440547] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.440628] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.440760] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.440844] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.440931] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.441023] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.441109] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.441195] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.441288] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.441373] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.441462] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.441582] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  387.441684] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.441818] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.442108] [drm:intel_power_well_enable [i915]] enabling always-on
>[  387.442173] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.442495] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  387.442592] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  387.442662] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  387.442819] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  387.443107] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  387.447347] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.447390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.447435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.447481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.447523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.447565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.447604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.447644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.447739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.447782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.447829] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.447877] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.447923] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.447999] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  387.448040] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  387.448312] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  387.449440] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  387.450000] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  387.450043] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  387.450105] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  387.450146] [drm:hsw_audio_config_update [i915]] using automatic N
>[  387.467038] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.467104] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.467303] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.468070] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.468133] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.468197] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.468256] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.468318] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.468379] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.468441] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.468500] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.468559] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.468569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.468628] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.468705] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.468774] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.468836] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.468906] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.468970] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.469036] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.469106] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.469174] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.469243] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.469314] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.469381] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.469448] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.469540] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  387.469619] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.469683] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.483832] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  387.483912] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.484044] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  387.500717] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  387.500957] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  387.501122] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  387.505349] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.505433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.505520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.505610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.505692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.505869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.505952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.506042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.506127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.506215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.506298] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.506395] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.506483] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.506608] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  387.506781] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  387.506905] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  387.507011] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.507112] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.507218] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.507316] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.507408] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  387.507489] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  387.508147] [drm:intel_power_well_disable [i915]] disabling always-on
>[  387.509708] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.509851] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.509945] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.510031] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.510122] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.510210] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.510298] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.510383] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.510467] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.510480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.510565] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.510574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.510663] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.510830] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.510927] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.511017] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.511110] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.511208] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.511305] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.511401] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.511497] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.511593] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.511691] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.511869] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  387.511963] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.512043] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.512303] [drm:intel_power_well_enable [i915]] enabling always-on
>[  387.512365] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.512681] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  387.513301] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  387.513360] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  387.513444] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  387.513822] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  387.518071] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.518114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.518159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.518204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.518244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.518284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.518325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.518365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.518407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.518446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.518489] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.518532] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.518576] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.518650] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  387.518746] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  387.519023] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  387.520159] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  387.520720] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  387.520763] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  387.520826] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  387.520864] [drm:hsw_audio_config_update [i915]] using automatic N
>[  387.537813] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.537894] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.538114] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.538954] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.539017] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.539087] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.539149] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.539215] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.539279] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.539343] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.539406] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.539469] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.539482] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.539542] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.539553] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.539613] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.539677] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.539819] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.539891] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.539963] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.540040] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.540112] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.540187] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.540261] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.540332] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.540404] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.540505] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  387.540595] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.540662] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.554532] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  387.554619] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.555457] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  387.571177] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  387.571350] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  387.571514] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  387.575794] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.575887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.575984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.576081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.576172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.576261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.576350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.576440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.576529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.576617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.576705] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.576912] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.577016] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.577151] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  387.577241] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  387.577360] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  387.577464] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.577560] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.577660] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.577822] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.577918] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  387.578003] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  387.578608] [drm:intel_power_well_disable [i915]] disabling always-on
>[  387.580240] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.580332] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.580427] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.580515] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.580607] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.580711] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.580857] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.580934] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.581013] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.581032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.581105] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.581120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.581198] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.581274] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.581351] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.581431] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.581509] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.581585] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.581662] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.581779] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.581855] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.581930] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.582005] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.582112] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  387.582203] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.582276] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.582535] [drm:intel_power_well_enable [i915]] enabling always-on
>[  387.582598] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.582974] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  387.583557] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  387.583628] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  387.583781] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  387.584138] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  387.588413] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.588458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.588506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.588554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.588598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.588639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.588741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.588785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.588834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.588879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.588925] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.588976] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.589022] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.589100] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  387.589142] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  387.589424] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  387.590620] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  387.591205] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  387.591249] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  387.591312] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  387.591352] [drm:hsw_audio_config_update [i915]] using automatic N
>[  387.608243] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.608304] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.608491] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.609313] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.609378] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.609444] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.609503] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.609564] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.609626] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.609755] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.609822] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.609885] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.609903] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.609964] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.609976] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.610041] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.610105] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.610173] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.610240] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.610308] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.610378] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.610443] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.610510] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.610577] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.610643] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.610740] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.610834] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  387.610913] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.610977] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.625007] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  387.625089] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.625222] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  387.641951] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  387.642124] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  387.642289] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  387.646549] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.646633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.646817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.646910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.646993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.647077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.647159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.647243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.647328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.647414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.647496] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.647587] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.647674] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.647887] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  387.647983] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  387.648108] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  387.648215] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.648312] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.648412] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.648511] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.648602] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  387.648683] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  387.649347] [drm:intel_power_well_disable [i915]] disabling always-on
>[  387.651025] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.651118] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.651212] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.651297] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.651386] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.651473] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.651561] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.651646] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.651819] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.651843] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.651931] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.651951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.652047] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.652139] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.652234] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.652330] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.652426] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.652526] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.652620] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.652737] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.652832] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.652930] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.653027] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.653160] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  387.653275] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.653367] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.653683] [drm:intel_power_well_enable [i915]] enabling always-on
>[  387.653809] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.654123] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  387.654205] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  387.654269] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  387.654358] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  387.654677] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  387.658996] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.659073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.659110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.659149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.659185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.659220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.659253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.659286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.659321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.659354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.659392] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.659428] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.659463] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.659529] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  387.659563] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  387.659857] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  387.660845] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  387.661358] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  387.661393] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  387.661444] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  387.661476] [drm:hsw_audio_config_update [i915]] using automatic N
>[  387.678410] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.678486] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.678771] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.679480] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.679535] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.679593] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.679644] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.679767] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.679825] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.679882] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.679939] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.679994] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.680008] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.680060] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.680072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.680130] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.680186] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.680245] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.680300] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.680357] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.680419] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.680476] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.680534] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.680590] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.680643] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.680734] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.680813] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  387.680887] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.680946] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.695134] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  387.695205] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.695320] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  387.713616] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  387.713925] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  387.714094] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  387.718350] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.718434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.718524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.718613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.718695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.718881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.718968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.719057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.719144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.719230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.719313] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.719408] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.719496] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.719624] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  387.719735] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  387.719846] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  387.719942] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.720035] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.720126] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.720220] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.720303] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  387.720376] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  387.721022] [drm:intel_power_well_disable [i915]] disabling always-on
>[  387.722475] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.722556] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.722640] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.722805] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.722892] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.722979] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.723064] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.723146] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.723231] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.723247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.723326] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.723338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.723417] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.723500] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.723581] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.723664] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.723808] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.723887] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.723931] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.723980] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.724026] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.724074] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.724120] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.724187] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  387.724246] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.724290] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.724458] [drm:intel_power_well_enable [i915]] enabling always-on
>[  387.724495] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.724820] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  387.724881] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  387.724921] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  387.724985] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  387.725272] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  387.729505] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.729550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.729597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.729646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.729747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.729792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.729837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.729881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.729926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.729969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.730014] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.730062] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.730109] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.730190] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  387.730233] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  387.730516] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  387.731740] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  387.732284] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  387.732327] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  387.732390] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  387.732431] [drm:hsw_audio_config_update [i915]] using automatic N
>[  387.749365] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.749447] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.749667] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.750554] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.750616] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.750682] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.750810] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.750881] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.750947] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.751016] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.751080] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.751146] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.751158] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.751219] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.751228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.751291] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.751353] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.751418] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.751483] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.751548] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.751615] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.751678] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.751780] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.751847] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.751915] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.751981] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.752079] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  387.752160] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.752224] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.766060] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  387.766140] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.766271] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  387.782979] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  387.783149] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  387.783314] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  387.787572] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.787655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.787838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.787932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.788015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.788100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.788182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.788267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.788350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.788436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.788517] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.788609] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.788697] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.788918] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  387.789010] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  387.789139] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  387.789245] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.789343] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.789443] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.789541] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.789633] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  387.789777] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  387.790380] [drm:intel_power_well_disable [i915]] disabling always-on
>[  387.792075] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.792168] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.792262] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.792347] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.792436] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.792524] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.792612] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.792697] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.792874] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.792893] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.792981] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.792999] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.793089] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.793181] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.793275] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.793370] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.793461] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.793559] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.793653] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.793801] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.793869] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.793932] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.793996] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.794085] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  387.794166] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.794234] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.794449] [drm:intel_power_well_enable [i915]] enabling always-on
>[  387.794503] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.794862] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  387.795440] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  387.795502] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  387.795592] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  387.795923] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  387.800178] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.800221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.800266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.800312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.800354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.800396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.800435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.800477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.800519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.800558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.800600] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.800644] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.800741] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.800817] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  387.800859] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  387.801132] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  387.802258] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  387.802819] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  387.802862] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  387.802924] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  387.802964] [drm:hsw_audio_config_update [i915]] using automatic N
>[  387.819868] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.819950] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.820171] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.820983] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.821043] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.821104] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.821161] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.821221] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.821281] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.821340] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.821396] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.821453] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.821463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.821518] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.821528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.821585] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.821642] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.821790] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.821861] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.821934] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.822008] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.822078] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.822152] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.822226] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.822298] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.822369] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.822470] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  387.822557] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.822626] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.836601] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  387.836690] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.837513] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  387.853209] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  387.853380] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  387.853548] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  387.857872] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.857964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.858061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.858160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.858250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.858340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.858430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.858520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.858609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.858699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.858894] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.859003] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.859105] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.859246] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  387.859340] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  387.859463] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  387.859569] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.859666] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.859825] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.859930] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.860021] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  387.860102] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  387.860765] [drm:intel_power_well_disable [i915]] disabling always-on
>[  387.862278] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.862368] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.862462] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.862547] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.862636] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.862814] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.862905] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.863001] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.863095] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.863115] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.863202] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.863221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.863311] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.863404] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.863500] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.863596] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.863690] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.863837] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.863914] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.863992] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.864074] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.864153] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.864227] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.864331] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  387.864425] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.864501] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.864810] [drm:intel_power_well_enable [i915]] enabling always-on
>[  387.864865] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.865176] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  387.865258] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  387.865318] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  387.865410] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  387.865809] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  387.869948] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.869984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.870022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.870061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.870096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.870129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.870162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.870195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.870229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.870264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.870300] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.870337] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.870372] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.870437] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  387.870470] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  387.870795] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  387.871772] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  387.872284] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  387.872318] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  387.872370] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  387.872402] [drm:hsw_audio_config_update [i915]] using automatic N
>[  387.889363] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.889440] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.889651] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.890415] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.890472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.890529] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.890580] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.890635] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.890750] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.890806] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.890864] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.890921] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.890935] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.890988] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.891000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.891058] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.891115] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.891175] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.891229] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.891284] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.891342] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.891395] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.891452] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.891509] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.891563] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.891618] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.891734] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  387.891805] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.891862] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.905985] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  387.906057] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.906169] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  387.922860] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  387.923021] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  387.923173] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  387.927421] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.927498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.927578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.927659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.927821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.927905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.927982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.928062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.928137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.928218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.928296] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.928380] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.928460] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.928573] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  387.928650] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  387.928854] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  387.928967] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.929071] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.929173] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.929274] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.929366] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  387.929447] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  387.930102] [drm:intel_power_well_disable [i915]] disabling always-on
>[  387.931689] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.931833] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.931927] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.932012] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.932103] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.932191] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.932279] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.932364] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.932448] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.932463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.932547] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.932557] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.932645] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.932812] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.932904] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.933002] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.933096] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.933199] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.933293] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.933394] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.933490] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.933588] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.933681] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.933862] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  387.933959] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.934036] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.934289] [drm:intel_power_well_enable [i915]] enabling always-on
>[  387.934353] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.934670] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  387.935305] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  387.935378] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  387.935480] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  387.935853] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  387.940000] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.940037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.940075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.940114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.940149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.940182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.940217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.940250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.940286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.940321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.940356] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.940393] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.940428] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.940493] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  387.940526] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  387.940806] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  387.941777] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  387.942290] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  387.942324] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  387.942376] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  387.942408] [drm:hsw_audio_config_update [i915]] using automatic N
>[  387.959367] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.959443] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.959654] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.960413] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  387.960467] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.960525] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  387.960576] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  387.960631] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.960747] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  387.960804] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  387.960862] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  387.960919] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.960936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.960988] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.960999] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  387.961055] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  387.961111] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  387.961171] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  387.961229] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.961286] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.961347] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  387.961404] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.961461] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  387.961520] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  387.961574] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  387.961630] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  387.961745] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  387.961811] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  387.961866] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  387.976040] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  387.976114] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  387.976233] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  387.992879] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  387.993042] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  387.993196] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  387.997441] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  387.997518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  387.997598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  387.997682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  387.997852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  387.997933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  387.998011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  387.998088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  387.998163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  387.998240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  387.998314] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  387.998399] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  387.998480] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.998595] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  387.998693] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  387.998859] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  387.998958] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  387.999052] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  387.999141] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  387.999231] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.999314] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  387.999387] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  388.000040] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.001518] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.001601] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.001686] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.001844] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.001932] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.002021] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.002107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.002194] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.002276] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.002296] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.002375] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.002389] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.002470] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.002556] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.002637] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.002772] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.002850] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.002938] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.003015] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.003101] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.003190] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.003273] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.003359] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.003482] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  388.003585] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.003668] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.003951] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.003995] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.004293] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  388.004364] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.004415] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.004490] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  388.004803] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  388.009040] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.009085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.009132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.009180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.009224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.009265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.009307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.009350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.009395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.009437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.009482] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.009527] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.009572] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.009648] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  388.009748] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  388.010031] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  388.011227] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  388.011809] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  388.011857] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  388.011924] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  388.011966] [drm:hsw_audio_config_update [i915]] using automatic N
>[  388.028870] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.028957] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.029186] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.030045] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.030112] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.030179] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.030240] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.030305] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.030371] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.030434] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.030498] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.030561] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.030576] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.030634] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.030699] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.030761] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.030823] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.030886] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.030953] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.031015] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.031084] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.031146] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.031214] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.031277] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.031342] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.031405] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.031496] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  388.031575] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.031639] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.045591] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  388.045674] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.046490] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  388.062219] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  388.062389] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  388.062553] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  388.066874] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.066966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.067063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.067162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.067252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.067342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.067431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.067519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.067611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.067700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.067894] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.067997] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.068103] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.068237] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  388.068328] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  388.068450] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  388.068555] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.068651] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.068821] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.068924] [drm:intel_power_well_disable [i915]] disabling DC off
>[  388.069015] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  388.069096] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  388.069692] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.071327] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.071417] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.071511] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.071596] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.071685] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.071864] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.071956] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.072052] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.072146] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.072169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.072256] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.072275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.072370] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.072459] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.072549] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.072639] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.072791] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.072890] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.072978] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.073076] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.073169] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.073268] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.073361] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.073493] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  388.073606] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.073700] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.073879] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.073923] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.074219] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  388.074291] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.074343] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.074418] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  388.074769] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  388.079011] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.079057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.079104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.079152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.079194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.079236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.079281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.079322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.079366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.079408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.079454] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.079499] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.079544] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.079621] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  388.079664] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  388.079996] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  388.081192] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  388.081775] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  388.081819] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  388.081881] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  388.081924] [drm:hsw_audio_config_update [i915]] using automatic N
>[  388.098846] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.098918] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.099122] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.099830] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.099894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.099960] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.100021] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.100083] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.100146] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.100211] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.100273] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.100336] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.100350] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.100411] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.100421] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.100482] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.100546] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.100609] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.100674] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.100815] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.100892] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.100965] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.101046] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.101116] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.101187] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.101259] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.101359] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  388.101447] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.101518] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.115578] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  388.115666] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.115955] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  388.132638] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  388.132879] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  388.133045] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  388.137323] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.137416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.137513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.137611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.137701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.137895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.137989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.138086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.138182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.138277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.138370] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.138469] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.138566] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.138698] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  388.138855] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  388.138981] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  388.139087] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.139184] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.139282] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.139378] [drm:intel_power_well_disable [i915]] disabling DC off
>[  388.139471] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  388.139553] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  388.140216] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.141828] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.141918] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.142012] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.142097] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.142186] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.142275] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.142363] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.142449] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.142533] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.142546] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.142631] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.142730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.142822] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.142916] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.143009] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.143108] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.143202] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.143303] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.143393] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.143495] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.143588] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.143685] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.143824] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.143958] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  388.144070] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.144167] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.144469] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.144548] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.144921] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  388.145484] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.145534] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.145610] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  388.145893] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  388.150114] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.150195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.150233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.150272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.150307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.150342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.150377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.150412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.150447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.150480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.150515] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.150552] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.150587] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.150653] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  388.150729] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  388.151017] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  388.152004] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  388.152517] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  388.152552] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  388.152603] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  388.152635] [drm:hsw_audio_config_update [i915]] using automatic N
>[  388.169564] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.169636] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.169982] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.170781] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.170841] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.170901] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.170956] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.171015] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.171073] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.171131] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.171188] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.171245] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.171256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.171311] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.171317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.171374] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.171431] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.171489] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.171545] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.171603] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.171665] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.171776] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.171843] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.171907] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.171968] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.172031] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.172119] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  388.172196] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.172257] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.186286] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  388.186361] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.186482] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  388.203038] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  388.203198] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  388.203350] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  388.207589] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.207672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.207857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.207949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.208031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.208113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.208194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.208277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.208362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.208444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.208529] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.208618] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.208773] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.208894] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  388.208977] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  388.209088] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  388.209182] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.209269] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.209362] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.209451] [drm:intel_power_well_disable [i915]] disabling DC off
>[  388.209534] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  388.209608] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  388.210296] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.211842] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.211932] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.212026] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.212111] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.212200] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.212289] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.212377] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.212464] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.212549] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.212562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.212647] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.212938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.213035] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.213125] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.213211] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.213303] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.213395] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.213491] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.213581] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.213677] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.213836] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.213931] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.214029] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.214168] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  388.214285] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.214383] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.214552] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.214594] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.214928] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  388.214995] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.215042] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.215112] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  388.215389] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  388.219631] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.219706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.219751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.219797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.219839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.219879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.219919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.219960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.220002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.220041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.220084] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.220127] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.220170] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.220243] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  388.220282] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  388.220555] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  388.221703] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  388.222226] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  388.222267] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  388.222327] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  388.222365] [drm:hsw_audio_config_update [i915]] using automatic N
>[  388.239266] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.239325] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.239504] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.240113] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.240155] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.240198] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.240237] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.240279] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.240320] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.240361] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.240399] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.240438] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.240446] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.240485] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.240489] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.240528] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.240567] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.240607] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.240645] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.240788] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.240858] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.240922] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.240993] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.241059] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.241129] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.241194] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.241287] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  388.241366] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.241433] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.256000] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  388.256081] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.256210] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  388.272924] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  388.273094] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  388.273260] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  388.277516] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.277599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.277686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.277875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.277955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.278037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.278118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.278205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.278287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.278371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.278454] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.278547] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.278634] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.278812] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  388.278900] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  388.279011] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  388.279105] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.279190] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.279277] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.279366] [drm:intel_power_well_disable [i915]] disabling DC off
>[  388.279448] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  388.279523] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  388.280181] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.281640] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.281771] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.281857] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.281934] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.282017] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.282097] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.282176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.282253] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.282329] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.282341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.282418] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.282426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.282505] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.282583] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.282661] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.282811] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.282893] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.282986] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.283070] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.283159] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.283243] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.283330] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.283415] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.283536] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  388.283641] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.283769] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.284040] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.284108] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.284430] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  388.284504] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.284559] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.284637] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  388.284948] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  388.289169] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.289225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.289284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.289344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.289400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.289453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.289505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.289558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.289613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.289666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.289788] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.289851] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.289911] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.290006] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  388.290060] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  388.290388] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  388.291697] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  388.292241] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  388.292284] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  388.292347] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  388.292387] [drm:hsw_audio_config_update [i915]] using automatic N
>[  388.309281] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.309344] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.309529] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.310384] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.310449] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.310516] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.310575] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.310638] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.310768] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.310832] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.310898] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.310962] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.310979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.311039] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.311051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.311117] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.311181] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.311248] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.311316] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.311383] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.311452] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.311519] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.311584] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.311650] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.311746] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.311811] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.311899] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  388.311976] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.312038] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.326020] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  388.326100] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.326230] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  388.342930] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  388.343101] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  388.343265] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  388.347543] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.347636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.347837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.347943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.348034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.348125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.348217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.348310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.348406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.348497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.348591] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.348692] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.348854] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.348987] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  388.349080] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  388.349206] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  388.349311] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.349408] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.349506] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.349602] [drm:intel_power_well_disable [i915]] disabling DC off
>[  388.349693] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  388.349838] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  388.350446] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.352039] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.352129] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.352223] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.352308] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.352397] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.352486] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.352574] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.352659] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.352833] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.352852] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.352946] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.352965] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.353060] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.353152] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.353252] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.353345] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.353441] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.353541] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.353636] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.353776] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.353870] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.353967] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.354060] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.354190] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  388.354303] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.354395] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.354688] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.354829] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.355125] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  388.355186] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.355228] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.355293] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  388.355562] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  388.359810] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.359885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.359923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.359963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.359998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.360033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.360068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.360101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.360137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.360170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.360208] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.360244] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.360280] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.360346] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  388.360378] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  388.360711] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  388.361654] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  388.362208] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  388.362243] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  388.362295] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  388.362327] [drm:hsw_audio_config_update [i915]] using automatic N
>[  388.379256] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.379318] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.379504] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.380235] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.380294] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.380352] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.380403] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.380456] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.380510] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.380562] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.380614] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.380664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.380775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.380831] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.380838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.380899] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.380957] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.381017] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.381075] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.381134] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.381196] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.381255] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.381315] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.381375] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.381435] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.381495] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.381583] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  388.381656] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.381746] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.396010] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  388.396091] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.396224] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  388.412939] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  388.413101] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  388.413252] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  388.417545] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.417629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.417825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.417918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.418002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.418086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.418168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.418254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.418336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.418420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.418502] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.418590] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.418681] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.418852] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  388.418935] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  388.419047] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  388.419144] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.419233] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.419324] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.419412] [drm:intel_power_well_disable [i915]] disabling DC off
>[  388.419495] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  388.419570] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  388.420253] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.421704] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.421839] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.421924] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.422001] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.422083] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.422163] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.422242] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.422319] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.422395] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.422409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.422485] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.422494] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.422573] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.422651] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.422804] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.422887] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.422973] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.423061] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.423147] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.423242] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.423328] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.423413] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.423497] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.423623] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  388.423751] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.423839] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.424124] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.424194] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.424518] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  388.424625] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.424745] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.424832] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  388.425170] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  388.429426] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.429472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.429519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.429568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.429612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.429654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.429758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.429804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.429851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.429895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.429939] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.429988] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.430036] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.430116] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  388.430160] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  388.430446] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  388.431645] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  388.432214] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  388.432257] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  388.432320] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  388.432361] [drm:hsw_audio_config_update [i915]] using automatic N
>[  388.449257] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.449319] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.449505] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.450305] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.450370] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.450436] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.450495] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.450557] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.450618] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.450680] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.450809] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.450874] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.450891] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.450956] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.450969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.451035] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.451100] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.451166] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.451232] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.451297] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.451367] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.451432] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.451503] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.451570] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.451634] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.451733] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.451829] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  388.451909] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.451972] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.465998] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  388.466081] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.466211] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  388.482935] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  388.483108] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  388.483274] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  388.487525] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.487609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.487697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.487886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.487969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.488053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.488136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.488220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.488302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.488386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.488468] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.488560] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.488649] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.488861] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  388.488958] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  388.489083] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  388.489189] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.489286] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.489387] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.489485] [drm:intel_power_well_disable [i915]] disabling DC off
>[  388.489576] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  388.489658] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  388.490327] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.491993] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.492083] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.492176] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.492261] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.492350] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.492438] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.492526] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.492611] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.492696] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.492795] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.492892] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.492905] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.493005] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.493099] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.493197] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.493291] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.493387] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.493488] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.493583] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.493681] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.493830] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.493917] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.494001] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.494118] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  388.494222] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.494305] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.494581] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.494651] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.495040] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  388.495123] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.495187] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.495276] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  388.495625] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  388.499894] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.499942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.499991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.500042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.500089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.500133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.500179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.500223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.500270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.500314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.500362] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.500410] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.500457] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.500537] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  388.500580] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  388.500928] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  388.502195] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  388.502770] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  388.502817] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  388.502887] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  388.502930] [drm:hsw_audio_config_update [i915]] using automatic N
>[  388.519871] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.519960] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.520190] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.521029] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.521096] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.521163] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.521225] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.521290] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.521355] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.521417] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.521481] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.521540] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.521552] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.521613] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.521623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.521686] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.521835] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.521913] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.521983] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.522059] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.522135] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.522207] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.522282] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.522358] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.522430] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.522504] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.522603] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  388.522687] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.522798] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.536579] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  388.536667] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.536973] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  388.553661] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  388.553907] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  388.554077] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  388.558341] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.558425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.558513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.558601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.558683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.558861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.558948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.559036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.559121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.559209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.559293] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.559386] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.559472] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.559596] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  388.559696] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  388.559878] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  388.559982] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.560078] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.560175] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.560275] [drm:intel_power_well_disable [i915]] disabling DC off
>[  388.560365] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  388.560449] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  388.561108] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.562711] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.562859] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.562953] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.563038] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.563130] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.563219] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.563307] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.563393] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.563477] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.563491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.563576] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.563586] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.563674] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.563845] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.563942] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.564039] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.564136] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.564235] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.564331] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.564431] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.564533] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.564627] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.564768] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.564899] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  388.565018] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.565107] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.565419] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.565494] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.565891] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  388.566467] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.566557] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.566683] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  388.567178] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  388.571388] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.571425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.571463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.571502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.571538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.571573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.571608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.571642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.571725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.571759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.571796] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.571836] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.571876] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.571944] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  388.571978] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  388.572230] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  388.573214] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  388.573762] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  388.573798] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  388.573851] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  388.573884] [drm:hsw_audio_config_update [i915]] using automatic N
>[  388.590791] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.590868] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.591080] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.591793] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.591848] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.591906] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.591957] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.592016] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.592072] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.592127] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.592181] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.592237] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.592249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.592301] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.592309] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.592362] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.592417] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.592472] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.592528] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.592581] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.592641] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.592732] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.592793] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.592851] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.592908] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.592967] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.593050] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  388.593122] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.593179] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.607501] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  388.607577] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.607828] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  388.624448] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  388.624612] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  388.624915] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  388.629202] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.629295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.629393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.629492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.629582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.629672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.629871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.629964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.630061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.630157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.630254] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.630352] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.630450] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.630590] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  388.630680] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  388.630870] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  388.630974] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.631070] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.631171] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.631269] [drm:intel_power_well_disable [i915]] disabling DC off
>[  388.631362] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  388.631445] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  388.632105] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.633697] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.633843] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.633938] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.634023] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.634114] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.634202] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.634291] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.634375] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.634461] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.634475] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.634560] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.634570] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.634658] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.634831] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.634893] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.634953] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.635015] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.635081] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.635145] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.635208] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.635272] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.635333] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.635398] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.635486] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  388.635562] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.635619] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.635872] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.635921] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.636228] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  388.636306] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.636364] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.636449] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  388.636815] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  388.641067] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.641113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.641160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.641208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.641252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.641295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.641337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.641379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.641423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.641465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.641509] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.641554] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.641601] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.641734] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  388.641778] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  388.642071] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  388.643269] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  388.643854] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  388.643899] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  388.643963] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  388.644006] [drm:hsw_audio_config_update [i915]] using automatic N
>[  388.660903] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.660985] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.661204] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.662081] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.662146] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.662215] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.662277] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.662343] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.662408] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.662472] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.662534] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.662597] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.662610] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.662670] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.662759] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.662835] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.662912] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.662992] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.663072] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.663148] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.663232] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.663312] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.663390] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.663469] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.663545] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.663627] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.663776] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  388.663867] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.663943] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.677684] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  388.677853] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.678007] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  388.694836] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  388.695025] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  388.695207] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  388.699497] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.699601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.699710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.699944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.700046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.700148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.700249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.700355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.700459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.700564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.700666] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.700848] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.700962] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.701121] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  388.701226] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  388.701360] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  388.701478] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.701590] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.701703] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.701877] [drm:intel_power_well_disable [i915]] disabling DC off
>[  388.701990] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  388.702085] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  388.702702] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.704499] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.704601] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.704706] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.704904] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.705016] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.705124] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.705231] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.705331] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.705430] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.705449] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.705547] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.705563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.705665] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.705834] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.705944] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.706047] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.706156] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.706266] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.706375] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.706484] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.706593] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.706697] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.706824] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.706903] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  388.706971] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.707023] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.707212] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.707257] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.707553] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  388.707622] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.707712] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.707790] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  388.708095] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  388.712344] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.712421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.712459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.712498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.712533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.712568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.712603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.712636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.712719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.712754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.712790] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.712831] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.712869] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.712935] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  388.712968] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  388.713256] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  388.714245] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  388.714793] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  388.714831] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  388.714884] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  388.714916] [drm:hsw_audio_config_update [i915]] using automatic N
>[  388.731869] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.731942] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.732146] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.732882] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.732937] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.732996] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.733050] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.733107] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.733163] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.733220] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.733273] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.733328] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.733340] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.733392] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.733400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.733455] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.733509] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.733565] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.733619] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.733672] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.733811] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.733877] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.733948] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.734015] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.734084] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.734148] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.734245] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  388.734328] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.734394] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.748600] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  388.748681] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.749036] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  388.765791] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  388.765963] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  388.766128] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  388.770390] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.770473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.770561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.770651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.770823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.770911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.770994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.771080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.771164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.771250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.771333] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.771425] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.771511] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.771632] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  388.771807] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  388.771932] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  388.772044] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.772143] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.772247] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.772346] [drm:intel_power_well_disable [i915]] disabling DC off
>[  388.772438] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  388.772517] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  388.773185] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.774793] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.774885] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.774979] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.775064] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.775153] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.775241] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.775329] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.775415] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.775500] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.775515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.775599] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.775611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.775699] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.775872] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.775965] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.776061] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.776155] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.776260] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.776353] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.776454] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.776551] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.776646] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.776794] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.776891] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  388.776974] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.777042] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.777262] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.777316] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.777622] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  388.777754] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.777820] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.777909] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  388.778209] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  388.782471] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.782548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.782586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.782626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.782705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.782743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.782781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.782818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.782855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.782890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.782924] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.782963] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.782999] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.783067] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  388.783101] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  388.783353] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  388.784335] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  388.784884] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  388.784920] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  388.784972] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  388.785006] [drm:hsw_audio_config_update [i915]] using automatic N
>[  388.801925] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.801996] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.802198] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.802928] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.802982] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.803038] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.803088] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.803143] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.803195] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.803247] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.803298] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.803349] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.803360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.803410] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.803418] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.803469] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.803520] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.803573] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.803627] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.803733] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.803797] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.803855] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.803917] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.803977] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.804035] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.804093] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.804176] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  388.804248] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.804302] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.818661] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  388.818789] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.818907] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  388.835579] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  388.835832] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  388.835986] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  388.840228] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.840305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.840385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.840466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.840541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.840615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.840688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.840850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.840931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.841009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.841088] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.841176] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.841261] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.841371] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  388.841446] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  388.841547] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  388.841632] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.841767] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.841850] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.841934] [drm:intel_power_well_disable [i915]] disabling DC off
>[  388.842008] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  388.842074] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  388.842654] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.844191] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.844275] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.844360] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.844436] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.844516] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.844596] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.844676] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.844832] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.844912] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.844935] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.845013] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.845027] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.845114] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.845199] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.845285] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.845371] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.845460] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.845550] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.845635] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.845762] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.845848] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.845933] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.846016] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.846132] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  388.846235] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.846317] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.846586] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.846657] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.847020] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  388.847090] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.847141] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.847217] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  388.847517] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  388.851785] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.851839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.851894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.851952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.852004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.852055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.852104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.852154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.852207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.852256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.852309] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.852363] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.852418] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.852504] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  388.852553] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  388.852923] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  388.854120] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  388.854663] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  388.854748] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  388.854812] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  388.854854] [drm:hsw_audio_config_update [i915]] using automatic N
>[  388.871607] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x18001a18, pins 0x00000040
>[  388.871662] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - long
>[  388.871713] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 6 - cnt: 0
>[  388.871765] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.871834] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.871917] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - long
>[  388.872153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.872449] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[  388.872516] [drm:i915_hotplug_work_func [i915]] Connector DP-2 (pin 6) received hotplug event.
>[  388.872579] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  388.872654] [drm:i915_hotplug_work_func [i915]] Connector HDMI-A-1 (pin 6) received hotplug event.
>[  388.872780] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.953038] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  388.957212] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  388.957306] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  388.957317] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  388.958359] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.958443] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.958532] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.958609] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.958692] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.958882] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.958967] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.959049] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.959128] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.959146] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.959222] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.959234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.959314] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.959397] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.959478] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.959561] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.959642] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.959766] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.959850] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.959942] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.960029] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.960119] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.960202] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.960326] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  388.960430] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.960513] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.960877] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  388.960988] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  388.961164] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  388.971534] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  388.971668] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  388.971836] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  388.976059] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.976116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.976175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.976235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.976290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.976344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.976399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.976454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.976509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.976563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.976617] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.976675] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.976800] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.976885] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  388.976942] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  388.977019] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  388.977083] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  388.977142] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  388.977203] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.977263] [drm:intel_power_well_disable [i915]] disabling DC off
>[  388.977320] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  388.977370] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  388.978023] [drm:intel_power_well_disable [i915]] disabling always-on
>[  388.979411] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  388.979485] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  388.979563] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  388.979633] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  388.979806] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  388.979871] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  388.979938] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  388.979999] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  388.980062] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  388.980075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.980135] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  388.980145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  388.980206] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  388.980269] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  388.980332] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  388.980398] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  388.980461] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  388.980531] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  388.980593] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  388.980658] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  388.980760] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  388.980828] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  388.980895] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  388.980990] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  388.981077] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  388.981144] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  388.981366] [drm:intel_power_well_enable [i915]] enabling always-on
>[  388.981420] [drm:intel_power_well_enable [i915]] enabling DC off
>[  388.981769] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  388.982359] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.982416] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  388.982504] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  388.982838] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  388.987067] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  388.987132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  388.987199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  388.987269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  388.987332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  388.987395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  388.987456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  388.987517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  388.987580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  388.987641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  388.987782] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  388.987857] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  388.987929] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  388.988032] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  388.988095] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  388.988441] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  388.990112] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  388.990767] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  388.990835] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  388.990898] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  388.990941] [drm:hsw_audio_config_update [i915]] using automatic N
>[  389.007817] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.007878] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.008062] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.008883] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.008955] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.009027] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.009096] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.009167] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.009237] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.009305] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.009374] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.009441] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.009456] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.009519] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.009530] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.009596] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.009666] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.009779] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.009851] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.009923] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.010000] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.010072] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.010143] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.010216] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.010287] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.010360] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.010464] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  389.010551] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.010620] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.024533] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  389.024622] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  389.025375] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  389.041198] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  389.041369] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  389.041533] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  389.045811] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.045904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.046002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.046100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.046190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.046279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.046368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.046458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.046548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.046637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.046834] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.046934] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.047042] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.047185] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  389.047275] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  389.047398] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  389.047504] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.047601] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.047699] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.047864] [drm:intel_power_well_disable [i915]] disabling DC off
>[  389.047962] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  389.048048] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  389.048647] [drm:intel_power_well_disable [i915]] disabling always-on
>[  389.050235] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.050326] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.050419] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.050504] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.050593] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.050681] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.050831] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.050927] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.051015] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.051037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.051124] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.051141] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.051232] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.051323] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.051415] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.051512] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.051605] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.051699] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.051841] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.051921] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.051998] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.052072] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.052149] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.052255] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  389.052349] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.052424] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.052674] [drm:intel_power_well_enable [i915]] enabling always-on
>[  389.052795] [drm:intel_power_well_enable [i915]] enabling DC off
>[  389.053098] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  389.053176] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  389.053232] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  389.053316] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  389.053617] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  389.055819] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.055879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.055942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.056005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.056064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.056120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.056177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.056235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.056294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.056350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.056408] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.056469] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.056530] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.056626] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  389.056706] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  389.057054] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  389.058597] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  389.059206] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  389.059241] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  389.059293] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  389.059326] [drm:hsw_audio_config_update [i915]] using automatic N
>[  389.069009] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x18001a18, pins 0x00000040
>[  389.069045] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - long
>[  389.069079] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 6 - cnt: 1
>[  389.069150] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - long
>[  389.076184] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.076255] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.076460] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.076799] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[  389.076853] [drm:i915_hotplug_work_func [i915]] Connector DP-2 (pin 6) received hotplug event.
>[  389.076902] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  389.085690] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.094666] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.103501] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.112292] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.121085] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.129881] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.138659] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.147482] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.156285] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.165070] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.173871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.182685] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.191526] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.200314] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.209093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.217950] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.226738] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.235523] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.244384] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.253272] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.262127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.270986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.279841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.288769] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.297620] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.306676] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.315601] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.324806] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.333706] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.342705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.351845] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.360842] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  389.360896] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  389.361006] [drm:i915_hotplug_work_func [i915]] Connector HDMI-A-1 (pin 6) received hotplug event.
>[  389.361104] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.442246] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  389.446422] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  389.446538] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  389.446551] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  389.447229] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.447336] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.447447] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.447546] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.447653] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.447828] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.447928] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.448031] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.448131] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.448150] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.448245] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.448260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.448362] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.448463] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.448567] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.448665] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.448817] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.448923] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.449025] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.449132] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.449234] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.449335] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.449439] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.449582] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  389.449710] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.449865] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.450236] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  389.450366] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  389.451085] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  389.460900] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  389.461033] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  389.461149] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  389.465368] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.465425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.465486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.465546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.465601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.465656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.465789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.465847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.465907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.465964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.466022] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.466084] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.466143] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.466224] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  389.466280] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  389.466357] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  389.466425] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.466484] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.466543] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.466602] [drm:intel_power_well_disable [i915]] disabling DC off
>[  389.466658] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  389.466805] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  389.467390] [drm:intel_power_well_disable [i915]] disabling always-on
>[  389.468361] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.468435] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.468514] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.468584] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.468660] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.468808] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.468884] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.468963] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.469040] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.469060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.469132] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.469147] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.469224] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.469301] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.469377] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.469450] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.469523] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.469601] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.469670] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.469820] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.469880] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.469945] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.470009] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.470096] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  389.470171] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.470229] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.470432] [drm:intel_power_well_enable [i915]] enabling always-on
>[  389.470482] [drm:intel_power_well_enable [i915]] enabling DC off
>[  389.470829] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  389.471417] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  389.471473] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  389.471556] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  389.471899] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  389.476135] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.476180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.476228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.476277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.476321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.476363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.476405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.476447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.476490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.476532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.476578] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.476624] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.476727] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.476806] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  389.476849] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  389.477136] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  389.478336] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  389.478922] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  389.478964] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  389.479030] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  389.479073] [drm:hsw_audio_config_update [i915]] using automatic N
>[  389.495981] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.496043] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.496231] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.496894] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.496943] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.496995] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.497042] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.497093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.497141] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.497188] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.497235] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.497282] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.497292] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.497337] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.497347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.497394] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.497441] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.497488] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.497535] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.497581] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.497633] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.497776] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.497842] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.497907] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.497969] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.498034] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.498127] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  389.498206] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.498270] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.512677] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  389.512816] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  389.512947] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  389.530204] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  389.530368] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  389.530520] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  389.534772] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.534848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.534929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.535011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.535085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.535159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.535232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.535306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.535380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.535454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.535526] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.535604] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.535681] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.535901] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  389.535979] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  389.536083] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  389.536171] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.536251] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.536333] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.536414] [drm:intel_power_well_disable [i915]] disabling DC off
>[  389.536490] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  389.536558] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  389.537219] [drm:intel_power_well_disable [i915]] disabling always-on
>[  389.538649] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.538805] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.538862] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.538913] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.538968] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.539023] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.539077] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.539128] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.539178] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.539189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.539240] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.539245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.539298] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.539350] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.539401] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.539453] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.539504] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.539563] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.539614] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.539672] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.539788] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.539844] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.539906] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.539988] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  389.540064] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.540122] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.540315] [drm:intel_power_well_enable [i915]] enabling always-on
>[  389.540363] [drm:intel_power_well_enable [i915]] enabling DC off
>[  389.540661] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  389.540776] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  389.540830] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  389.540907] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  389.541221] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  389.545450] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.545507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.545566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.545626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.545712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.545767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.545824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.545880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.545938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.545992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.546049] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.546110] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.546171] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.546263] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  389.546319] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  389.546640] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  389.548146] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  389.548812] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  389.548858] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  389.548921] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  389.548964] [drm:hsw_audio_config_update [i915]] using automatic N
>[  389.565859] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.565920] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.566105] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.566889] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.566953] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.567022] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.567083] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.567149] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.567213] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.567277] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.567339] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.567402] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.567414] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.567473] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.567483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.567544] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.567606] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.567667] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.567796] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.567861] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.567933] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.567993] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.568066] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.568128] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.568193] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.568257] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.568350] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  389.568431] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.568495] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.582567] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  389.582648] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  389.583354] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  389.599197] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  389.599368] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  389.599532] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  389.603797] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.603881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.603969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.604059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.604140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.604221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.604301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.604382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.604462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.604541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.604621] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.604807] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.604902] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.605041] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  389.605134] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  389.605254] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  389.605360] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.605457] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.605558] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.605655] [drm:intel_power_well_disable [i915]] disabling DC off
>[  389.605873] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  389.605952] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  389.606556] [drm:intel_power_well_disable [i915]] disabling always-on
>[  389.608270] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.608364] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.608458] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.608543] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.608632] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.608823] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.608915] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.609007] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.609094] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.609115] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.609202] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.609216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.609307] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.609400] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.609490] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.609584] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.609673] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.609824] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.609897] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.609983] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.610056] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.610137] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.610213] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.610321] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  389.610416] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.610492] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.610841] [drm:intel_power_well_enable [i915]] enabling always-on
>[  389.610910] [drm:intel_power_well_enable [i915]] enabling DC off
>[  389.611230] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  389.611329] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  389.611404] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  389.611508] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  389.611928] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  389.616191] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.616255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.616300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.616347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.616389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.616430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.616472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.616513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.616553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.616593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.616633] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.616740] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.616786] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.616866] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  389.617162] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  389.617451] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  389.618766] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  389.619292] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  389.619333] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  389.619393] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  389.619432] [drm:hsw_audio_config_update [i915]] using automatic N
>[  389.636337] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.636395] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.636578] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.637576] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.637636] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.637767] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.637824] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.637890] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.637950] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.638012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.638071] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.638132] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.638573] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.638637] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.638704] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.638765] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.638824] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.638884] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.638947] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.639008] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.639075] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.639347] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.639410] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.639471] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.639529] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.639589] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.639677] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  389.639798] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.639861] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.653065] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  389.653140] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  389.653264] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  389.669943] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  389.670104] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  389.670256] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  389.674496] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.674582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.674670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.674865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.674962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.675045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.675130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.675213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.675299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.675382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.675465] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.675556] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.675644] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.675834] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  389.675920] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  389.676033] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  389.676129] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.676217] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.676309] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.676398] [drm:intel_power_well_disable [i915]] disabling DC off
>[  389.676481] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  389.676556] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  389.677221] [drm:intel_power_well_disable [i915]] disabling always-on
>[  389.678677] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.678808] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.678893] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.678970] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.679052] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.679132] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.679212] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.679289] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.679365] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.679378] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.679455] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.679463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.679542] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.679620] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.679698] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.679849] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.679931] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.680023] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.680105] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.680199] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.680284] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.680373] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.680456] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.680573] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  389.680678] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.680804] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.681079] [drm:intel_power_well_enable [i915]] enabling always-on
>[  389.681150] [drm:intel_power_well_enable [i915]] enabling DC off
>[  389.681475] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  389.681582] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  389.681660] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  389.681839] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  389.682194] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  389.686465] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.686507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.686551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.686595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.686635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.686726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.686767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.686808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.686851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.686892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.686935] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.686981] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.687192] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.687269] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  389.687308] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  389.687582] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  389.688883] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  389.689420] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  389.689460] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  389.689517] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  389.689554] [drm:hsw_audio_config_update [i915]] using automatic N
>[  389.706477] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.706561] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.706980] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.707814] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.707875] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.707940] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.707995] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.708056] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.708117] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.708175] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.708235] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.708292] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.708308] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.708362] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.708371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.708428] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.708488] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.708544] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.708606] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.708664] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.708771] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.708832] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.708899] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.708958] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.709019] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.709082] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.709171] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  389.709250] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.709312] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.723256] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  389.723343] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  389.723493] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  389.740063] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  389.740236] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  389.740401] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  389.744691] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.744858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.744957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.745056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.745147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.745237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.745327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.745417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.745507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.745596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.745685] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.745866] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.745967] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.746108] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  389.746203] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  389.746327] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  389.746432] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.746530] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.746630] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.746788] [drm:intel_power_well_disable [i915]] disabling DC off
>[  389.746888] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  389.746977] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  389.747584] [drm:intel_power_well_disable [i915]] disabling always-on
>[  389.749228] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.749321] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.749417] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.749502] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.749591] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.749680] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.749854] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.749945] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.750042] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.750063] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.750156] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.750172] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.750268] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.750360] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.750458] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.750553] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.750644] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.750788] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.750884] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.750981] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.751078] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.751168] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.751257] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.751399] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  389.751492] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.751567] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.751865] [drm:intel_power_well_enable [i915]] enabling always-on
>[  389.751929] [drm:intel_power_well_enable [i915]] enabling DC off
>[  389.752247] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  389.752346] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  389.752418] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  389.752524] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  389.752930] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  389.757195] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.757274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.757312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.757351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.757386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.757421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.757454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.757487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.757524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.757557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.757593] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.757630] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.757711] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.757779] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  389.757814] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  389.758099] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  389.759082] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  389.759594] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  389.759629] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  389.759712] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  389.759746] [drm:hsw_audio_config_update [i915]] using automatic N
>[  389.776653] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.776859] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.777071] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.777807] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.777863] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.777921] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.777974] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.778030] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.778085] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.778141] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.778195] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.778250] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.778262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.778315] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.778323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.778376] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.778432] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.778488] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.778546] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.778600] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.778660] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.778748] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.778809] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.778870] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.778924] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.778984] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.779061] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  389.779132] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.779191] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.793460] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  389.793553] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  389.793794] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  389.810326] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  389.810490] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  389.810645] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  389.815084] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.815178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.815276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.815376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.815466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.815556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.815646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.815849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.815947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.816043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.816137] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.816240] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.816338] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.816477] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  389.816569] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  389.816691] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  389.816857] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.816958] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.817064] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.817165] [drm:intel_power_well_disable [i915]] disabling DC off
>[  389.817257] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  389.817338] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  389.818007] [drm:intel_power_well_disable [i915]] disabling always-on
>[  389.819581] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.819672] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.819856] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.819948] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.820044] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.820141] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.820231] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.820323] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.820411] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.820431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.820516] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.820528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.820620] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.820710] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.820853] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.820953] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.821047] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.821149] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.821243] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.821347] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.821441] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.821542] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.821637] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.821807] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  389.821881] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.821941] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.822149] [drm:intel_power_well_enable [i915]] enabling always-on
>[  389.822199] [drm:intel_power_well_enable [i915]] enabling DC off
>[  389.822503] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  389.822583] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  389.822639] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  389.822838] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  389.823117] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  389.827390] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.827431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.827474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.827518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.827558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.827597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.827637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.827732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.827773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.827815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.827858] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.827905] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.827950] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.828024] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  389.828063] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  389.828329] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  389.829457] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  389.830032] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  389.830071] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  389.830131] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  389.830170] [drm:hsw_audio_config_update [i915]] using automatic N
>[  389.847084] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.847164] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.847382] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.848202] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.848262] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.848323] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.848378] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.848435] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.848493] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.848550] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.848605] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.848659] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.848738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.848798] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.848812] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.848870] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.848934] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.848995] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.849058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.849120] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.849185] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.849246] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.849308] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.849372] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.849434] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.849498] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.849582] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  389.849654] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.849796] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.863844] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  389.863935] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  389.864083] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  389.880799] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  389.880970] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  389.881140] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  389.885420] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.885514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.885614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.885714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.885920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.886015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.886114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.886208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.886306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.886398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.886491] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.886591] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.886691] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.886880] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  389.886970] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  389.887093] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  389.887199] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.887296] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.887397] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.887494] [drm:intel_power_well_disable [i915]] disabling DC off
>[  389.887585] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  389.887666] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  389.888321] [drm:intel_power_well_disable [i915]] disabling always-on
>[  389.889935] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.890027] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.890121] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.890206] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.890295] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.890383] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.890471] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.890556] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.890641] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.890740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.890830] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.890849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.890944] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.891038] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.891134] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.891231] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.891330] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.891429] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.891525] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.891624] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.891741] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.891831] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.891922] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.892055] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  389.892168] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.892259] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.892557] [drm:intel_power_well_enable [i915]] enabling always-on
>[  389.892655] [drm:intel_power_well_enable [i915]] enabling DC off
>[  389.893003] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  389.893075] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  389.893129] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  389.893209] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  389.893586] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  389.897840] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.897919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.897957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.897996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.898031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.898064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.898098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.898131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.898168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.898201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.898237] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.898274] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.898309] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.898374] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  389.898407] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  389.898738] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  389.899715] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  389.900228] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  389.900262] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  389.900314] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  389.900346] [drm:hsw_audio_config_update [i915]] using automatic N
>[  389.917302] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.917379] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.917590] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.918363] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.918418] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.918476] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.918527] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.918580] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.918634] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.918754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.918809] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.918870] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.918882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.918939] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.918949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.919007] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.919061] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.919123] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.919179] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.919236] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.919297] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.919354] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.919411] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.919472] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.919529] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.919584] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.919660] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  389.919768] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.919821] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.934061] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  389.934145] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  389.934280] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  389.950959] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  389.951119] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  389.951272] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  389.955530] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.955614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.955701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.955890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.955974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.956058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.956140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.956225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.956307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.956391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.956473] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.956564] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.956652] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.956867] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  389.956962] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  389.957088] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  389.957194] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.957292] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.957392] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.957491] [drm:intel_power_well_disable [i915]] disabling DC off
>[  389.957582] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  389.957661] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  389.958326] [drm:intel_power_well_disable [i915]] disabling always-on
>[  389.960022] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.960113] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.960206] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.960291] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.960380] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.960469] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.960556] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.960641] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.960812] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.960831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.960917] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.960937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.961027] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.961122] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.961223] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.961318] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.961415] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.961513] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.961609] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.961715] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.961853] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.961959] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.962039] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.962155] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  389.962258] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.962342] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  389.962613] [drm:intel_power_well_enable [i915]] enabling always-on
>[  389.962683] [drm:intel_power_well_enable [i915]] enabling DC off
>[  389.963064] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  389.963138] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  389.963192] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  389.963269] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  389.963645] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  389.967953] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  389.968030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  389.968068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  389.968107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  389.968142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  389.968175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  389.968210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  389.968243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  389.968278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  389.968311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  389.968347] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  389.968383] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  389.968421] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.968485] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  389.968518] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  389.968802] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  389.969780] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  389.970293] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  389.970327] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  389.970378] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  389.970410] [drm:hsw_audio_config_update [i915]] using automatic N
>[  389.987370] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  389.987446] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  389.987657] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  389.988444] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  389.988500] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  389.988558] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  389.988609] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  389.988663] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.988781] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  389.988838] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  389.988897] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  389.988952] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.988966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.989019] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.989031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  389.989087] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  389.989144] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  389.989202] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  389.989260] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.989319] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.989379] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  389.989438] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.989496] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  389.989553] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  389.989612] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  389.989670] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  389.989780] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  389.989849] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  389.989904] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  390.004084] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  390.004158] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  390.004276] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  390.020943] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  390.021105] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  390.021257] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  390.025482] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  390.025560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  390.025641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  390.025836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  390.025911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  390.025984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  390.026061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  390.026136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  390.026213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  390.026288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  390.026364] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.026447] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  390.026527] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.026641] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  390.026780] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  390.026888] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  390.026976] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  390.027057] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  390.027140] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.027219] [drm:intel_power_well_disable [i915]] disabling DC off
>[  390.027293] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  390.027360] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  390.027995] [drm:intel_power_well_disable [i915]] disabling always-on
>[  390.029397] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  390.029471] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.029548] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  390.029618] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  390.029691] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.029844] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  390.029919] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  390.029994] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  390.030066] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.030083] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.030154] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.030166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.030240] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  390.030314] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  390.030388] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  390.030466] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.030538] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.030620] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  390.030692] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.030812] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  390.030891] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  390.030967] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  390.031043] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  390.031146] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  390.031242] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  390.031318] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  390.031568] [drm:intel_power_well_enable [i915]] enabling always-on
>[  390.031631] [drm:intel_power_well_enable [i915]] enabling DC off
>[  390.032023] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  390.032167] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  390.032257] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  390.032470] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  390.033001] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  390.037299] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  390.037373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  390.037416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  390.037460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  390.037500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  390.037539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  390.037579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  390.037617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  390.037658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  390.037839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  390.037880] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.037925] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  390.037969] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.038042] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  390.038082] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  390.038350] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  390.039489] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  390.040071] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  390.040111] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  390.040169] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  390.040208] [drm:hsw_audio_config_update [i915]] using automatic N
>[  390.057130] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  390.057193] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  390.057379] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.058036] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  390.058080] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.058126] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  390.058167] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  390.058210] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.058253] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  390.058296] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  390.058336] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  390.058376] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.058385] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.058426] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.058430] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.058472] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  390.058512] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  390.058554] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  390.058594] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.058635] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.058740] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  390.058782] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.058832] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  390.058876] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  390.058920] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  390.058964] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  390.059029] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  390.059085] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  390.059128] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  390.073941] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  390.074025] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  390.074159] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  390.090777] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  390.090923] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  390.091055] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  390.095320] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  390.095404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  390.095492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  390.095582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  390.095664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  390.095992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  390.096077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  390.096159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  390.096244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  390.096325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  390.096409] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.096505] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  390.096593] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.096942] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  390.097027] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  390.097140] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  390.097236] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  390.097325] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  390.097416] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.097506] [drm:intel_power_well_disable [i915]] disabling DC off
>[  390.097589] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  390.097663] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  390.098479] [drm:intel_power_well_disable [i915]] disabling always-on
>[  390.100198] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  390.100279] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.100364] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  390.100440] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  390.100521] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.100601] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  390.100681] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  390.101005] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  390.101086] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.101100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.101177] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.101187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.101266] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  390.101349] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  390.101427] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  390.101511] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.101591] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.101680] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  390.102005] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.102092] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  390.102173] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  390.102254] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  390.102339] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  390.102456] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  390.102559] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  390.102642] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  390.103071] [drm:intel_power_well_enable [i915]] enabling always-on
>[  390.103125] [drm:intel_power_well_enable [i915]] enabling DC off
>[  390.103434] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  390.103518] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  390.103578] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  390.103670] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  390.104240] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  390.108503] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  390.108579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  390.108618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  390.108657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  390.108799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  390.108834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  390.108869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  390.108904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  390.108938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  390.108973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  390.109009] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.109048] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  390.109086] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.109155] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  390.109189] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  390.109479] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  390.110560] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  390.111186] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  390.111221] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  390.111273] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  390.111305] [drm:hsw_audio_config_update [i915]] using automatic N
>[  390.128257] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  390.128334] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  390.128546] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.129390] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  390.129444] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.129502] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  390.129553] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  390.129607] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.129661] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  390.129888] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  390.129942] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  390.129995] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.130007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.130060] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.130068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.130124] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  390.130177] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  390.130233] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  390.130288] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.130343] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.130402] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  390.130457] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.130514] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  390.130570] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  390.130625] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  390.130839] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  390.130920] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  390.130989] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  390.131045] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  390.145023] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  390.145109] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  390.145256] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  390.161939] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  390.162099] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  390.162252] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  390.166503] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  390.166580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  390.166660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  390.166954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  390.167029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  390.167106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  390.167179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  390.167254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  390.167330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  390.167409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  390.167482] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.167566] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  390.167646] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.168025] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  390.168109] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  390.168222] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  390.168317] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  390.168406] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  390.168497] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.168586] [drm:intel_power_well_disable [i915]] disabling DC off
>[  390.168669] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  390.168959] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  390.169549] [drm:intel_power_well_disable [i915]] disabling always-on
>[  390.171254] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  390.171338] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.171423] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  390.171500] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  390.171580] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.171660] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  390.171979] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  390.172060] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  390.172142] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.172157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.172236] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.172248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.172327] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  390.172410] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  390.172491] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  390.172574] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.172654] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.172991] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  390.173072] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.173156] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  390.173238] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  390.173322] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  390.173402] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  390.173525] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  390.173629] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  390.173910] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  390.174128] [drm:intel_power_well_enable [i915]] enabling always-on
>[  390.174182] [drm:intel_power_well_enable [i915]] enabling DC off
>[  390.174490] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  390.174571] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  390.174632] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  390.174955] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  390.175301] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  390.179561] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  390.179637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  390.179775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  390.179815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  390.179849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  390.179884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  390.179918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  390.179952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  390.179987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  390.180021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  390.180057] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.180095] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  390.180131] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.180197] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  390.180231] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  390.180482] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  390.181565] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  390.182165] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  390.182199] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  390.182249] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  390.182281] [drm:hsw_audio_config_update [i915]] using automatic N
>[  390.199227] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  390.199304] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  390.199515] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.200382] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  390.200437] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.200495] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  390.200546] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  390.200600] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.200653] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  390.200889] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  390.200943] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  390.200998] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.201007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.201063] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.201069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.201125] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  390.201180] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  390.201235] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  390.201290] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.201345] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.201403] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  390.201458] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.201515] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  390.201572] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  390.201627] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  390.201958] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  390.202058] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  390.202143] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  390.202210] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  390.216000] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  390.216089] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  390.216233] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  390.232977] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  390.233148] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  390.233315] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  390.237602] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  390.237694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  390.238034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  390.238138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  390.238230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  390.238324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  390.238416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  390.238509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  390.238601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  390.238695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  390.239023] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.239124] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  390.239219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.239355] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  390.239447] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  390.239571] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  390.239673] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  390.239874] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  390.239975] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.240075] [drm:intel_power_well_disable [i915]] disabling DC off
>[  390.240164] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  390.240247] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  390.240925] [drm:intel_power_well_disable [i915]] disabling always-on
>[  390.242508] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  390.242600] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.242693] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  390.242876] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  390.242968] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.243064] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  390.243155] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  390.243248] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  390.243337] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.243356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.243443] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.243455] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.243550] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  390.243637] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  390.243791] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  390.243882] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.243973] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.244068] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  390.244159] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.244254] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  390.244347] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  390.244438] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  390.244531] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  390.244659] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  390.244829] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  390.244883] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  390.245076] [drm:intel_power_well_enable [i915]] enabling always-on
>[  390.245122] [drm:intel_power_well_enable [i915]] enabling DC off
>[  390.245422] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  390.245496] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  390.245547] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  390.245630] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  390.246071] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  390.250325] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  390.250402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  390.250441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  390.250480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  390.250515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  390.250548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  390.250583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  390.250617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  390.250651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  390.250810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  390.250845] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.250883] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  390.250922] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.250989] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  390.251023] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  390.251312] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  390.252376] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  390.252932] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  390.252968] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  390.253019] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  390.253053] [drm:hsw_audio_config_update [i915]] using automatic N
>[  390.270015] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  390.270091] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  390.270301] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.271071] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  390.271127] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.271186] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  390.271239] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  390.271294] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.271350] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  390.271406] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  390.271459] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  390.271512] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.271522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.271573] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.271585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.271638] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  390.271754] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  390.271809] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  390.271868] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.271922] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.271985] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  390.272037] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.272098] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  390.272152] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  390.272211] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  390.272264] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  390.272347] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  390.272415] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  390.272469] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  390.286834] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  390.286922] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  390.287065] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  390.303699] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  390.303934] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  390.304086] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  390.308348] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  390.308432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  390.308520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  390.308609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  390.308691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  390.309018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  390.309101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  390.309186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  390.309269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  390.309353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  390.309435] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.309528] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  390.309617] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.309959] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  390.310043] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  390.310154] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  390.310250] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  390.310339] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  390.310430] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.310518] [drm:intel_power_well_disable [i915]] disabling DC off
>[  390.310602] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  390.310676] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  390.311497] [drm:intel_power_well_disable [i915]] disabling always-on
>[  390.313200] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  390.313282] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.313368] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  390.313444] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  390.313524] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.313604] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  390.313683] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  390.314006] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  390.314089] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.314105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.314185] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.314197] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.314276] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  390.314360] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  390.314440] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  390.314524] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.314604] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.314694] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  390.315028] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.315114] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  390.315196] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  390.315277] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  390.315362] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  390.315481] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  390.315587] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  390.315670] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  390.316149] [drm:intel_power_well_enable [i915]] enabling always-on
>[  390.316204] [drm:intel_power_well_enable [i915]] enabling DC off
>[  390.316514] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  390.316597] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  390.316657] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  390.316982] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  390.317297] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  390.321557] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  390.321633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  390.321768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  390.321808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  390.321842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  390.321878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  390.321913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  390.321949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  390.321984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  390.322019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  390.322055] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.322094] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  390.322131] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.322198] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  390.322233] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  390.322485] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  390.323575] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  390.324131] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  390.324166] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  390.324218] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  390.324252] [drm:hsw_audio_config_update [i915]] using automatic N
>[  390.341211] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  390.341287] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  390.341497] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.342296] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  390.342352] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.342409] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  390.342461] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  390.342514] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.342568] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  390.342622] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  390.342673] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  390.342801] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.342812] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.342868] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.342875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.342931] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  390.342987] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  390.343041] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  390.343099] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.343152] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.343212] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  390.343266] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.343328] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  390.343382] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  390.343439] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  390.343495] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  390.343573] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  390.343639] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  390.343725] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  390.357969] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  390.358058] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  390.358201] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  390.376276] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  390.376436] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  390.376589] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  390.380872] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  390.380966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  390.381063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  390.381163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  390.381253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  390.381343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  390.381433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  390.381523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  390.381613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  390.381700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  390.382103] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.382208] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  390.382310] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.382443] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  390.382534] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  390.382660] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  390.383002] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  390.383101] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  390.383202] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.383301] [drm:intel_power_well_disable [i915]] disabling DC off
>[  390.383392] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  390.383475] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  390.384687] [drm:intel_power_well_disable [i915]] disabling always-on
>[  390.386280] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  390.386372] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.386466] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  390.386551] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  390.386640] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.386842] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  390.386923] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  390.386965] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  390.387005] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.387015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.387054] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.387062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.387105] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  390.387145] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  390.387187] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  390.387228] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.387270] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.387316] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  390.387358] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.387403] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  390.387444] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  390.387485] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  390.387528] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  390.387590] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  390.387646] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  390.387719] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  390.387877] [drm:intel_power_well_enable [i915]] enabling always-on
>[  390.387913] [drm:intel_power_well_enable [i915]] enabling DC off
>[  390.388200] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  390.388257] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  390.388297] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  390.388358] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  390.388653] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  390.392227] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  390.392272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  390.392319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  390.392366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  390.392408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  390.392450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  390.392492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  390.392534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  390.392575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  390.392614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  390.392656] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.392763] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  390.392813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.392889] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  390.392932] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  390.393227] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  390.394365] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  390.394932] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  390.394975] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  390.395039] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  390.395079] [drm:hsw_audio_config_update [i915]] using automatic N
>[  390.412014] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  390.412096] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  390.412315] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.413154] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  390.413215] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.413275] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  390.413330] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  390.413389] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.413446] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  390.413504] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  390.413559] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  390.413613] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.413624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.413679] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.413761] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.413821] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  390.413885] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  390.413946] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  390.414011] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.414070] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.414137] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  390.414198] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.414262] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  390.414321] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  390.414382] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  390.414444] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  390.414531] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  390.414605] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  390.414668] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  390.428789] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  390.428872] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  390.429011] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  390.445677] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  390.445930] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  390.446095] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  390.450382] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  390.450475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  390.450572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  390.450671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  390.450875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  390.450973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  390.451068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  390.451163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  390.451255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  390.451349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  390.451440] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.451544] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  390.451642] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.451848] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  390.451941] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  390.452067] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  390.452174] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  390.452273] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  390.452374] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.452473] [drm:intel_power_well_disable [i915]] disabling DC off
>[  390.452564] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  390.452646] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  390.453330] [drm:intel_power_well_disable [i915]] disabling always-on
>[  390.455026] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  390.455119] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.455212] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  390.455297] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  390.455386] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.455476] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  390.455564] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  390.455649] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  390.455823] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.455841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.455935] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.455954] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.456047] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  390.456139] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  390.456237] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  390.456331] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.456427] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.456530] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  390.456623] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.456743] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:89, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  390.456839] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  390.456934] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  390.457031] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  390.457162] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  390.457277] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  390.457371] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  390.457682] [drm:intel_power_well_enable [i915]] enabling always-on
>[  390.457904] [drm:intel_power_well_enable [i915]] enabling DC off
>[  390.458299] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  390.458381] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  390.458438] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  390.458526] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  390.458859] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  390.463087] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  390.463163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  390.463201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  390.463240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  390.463275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  390.463310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  390.463345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  390.463378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  390.463413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  390.463446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  390.463483] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.463519] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  390.463555] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.463621] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  390.463656] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  390.463995] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  390.464995] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  390.465509] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  390.465544] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  390.465595] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  390.465627] [drm:hsw_audio_config_update [i915]] using automatic N
>[  390.482601] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  390.482684] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  390.483025] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.483889] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  390.483954] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.484020] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  390.484079] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  390.484142] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.484204] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  390.484266] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  390.484325] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  390.484384] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.484395] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.484454] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.484460] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.484521] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  390.484581] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  390.484641] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  390.484770] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.484831] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.484902] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  390.484966] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.485035] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] FB:91, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  390.485102] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  390.485169] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  390.485237] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  390.485330] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  390.485411] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  390.485478] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  390.499318] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  390.499402] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  390.499539] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  390.516130] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  390.516302] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  390.516467] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  390.520801] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  390.520897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  390.520994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  390.521094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  390.521184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  390.521274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  390.521364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  390.521454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  390.521544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  390.521632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  390.521804] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.521908] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  390.522017] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.522154] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  390.522247] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  390.522372] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  390.522479] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  390.522578] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  390.522679] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.522845] [drm:intel_power_well_disable [i915]] disabling DC off
>[  390.522938] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  390.523025] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  390.523632] [drm:intel_power_well_disable [i915]] disabling always-on
>[  390.525020] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  390.525245] [drm:intel_power_well_enable [i915]] enabling always-on
>[  390.525319] [drm:intel_power_well_enable [i915]] enabling DC off
>[  390.525650] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  390.526317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  390.526416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  390.526545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  390.526636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  390.526816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  390.526910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  390.527011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  390.527109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  390.527207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  390.527303] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  390.527401] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.527503] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  390.527605] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.527817] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  390.527887] [drm:intel_power_well_disable [i915]] disabling DC off
>[  390.527956] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  390.528015] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  390.528596] [drm:intel_power_well_disable [i915]] disabling always-on
>[  390.536121] [IGT] kms_flip: exiting, ret=0
>[  390.560621] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  390.560656] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.560725] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  390.560767] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  390.560799] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  390.560836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.560871] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  390.560905] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  390.560938] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  390.560970] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  390.561002] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.561009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  390.561041] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.561044] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  390.561077] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  390.561109] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  390.561144] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  390.561176] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.561208] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.561245] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  390.561277] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.561312] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  390.561346] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  390.561380] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  390.561414] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  390.561456] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  390.561488] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.561527] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  390.561559] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  390.561593] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.561627] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  390.561681] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  390.561713] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  390.561744] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.561748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.561779] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.561783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  390.561815] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  390.561847] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  390.561881] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  390.561913] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.561945] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.561979] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  390.562011] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.562044] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  390.562079] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  390.562112] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  390.562146] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  390.562181] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  390.562226] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  390.562260] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  390.562298] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  390.562331] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  390.562494] [drm:intel_power_well_enable [i915]] enabling always-on
>[  390.562521] [drm:intel_power_well_enable [i915]] enabling DC off
>[  390.562861] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  390.562917] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  390.563050] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  390.563085] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  390.563140] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  390.563309] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  390.566731] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  390.566780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  390.566828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  390.566883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  390.566932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  390.566980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  390.567028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  390.567076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  390.567123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  390.567172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  390.567219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.567271] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  390.567321] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.567407] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  390.567453] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  390.567809] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  390.567860] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  390.567920] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  390.567969] [drm:wait_panel_status [i915]] Wait complete
>[  390.568019] [drm:edp_panel_on [i915]] Wait for panel power on
>[  390.568074] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  390.676483] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  390.676531] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  390.676579] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  390.676659] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  390.768783] [drm:wait_panel_status [i915]] Wait complete
>[  390.768875] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  390.768936] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  390.770390] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  390.770445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  390.770506] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  390.771448] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  390.771503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  390.772754] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  390.773065] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  390.775038] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  390.775139] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  390.775194] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  390.775257] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  390.775339] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  390.775392] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  390.775471] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  390.775529] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  390.775800] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  390.775858] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  390.776213] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  390.778179] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  390.778827] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  390.778885] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  390.778968] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  390.779000] [drm:hsw_audio_config_update [i915]] using automatic N
>[  390.796041] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  390.796114] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  390.796354] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  390.796617] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  390.796722] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  390.796947] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  390.797483] Console: switching to colour frame buffer device 240x67
>[  391.009750] Console: switching to colour dummy device 80x25
>[  391.009997] [IGT] kms_flip: executing
>[  391.034425] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  391.034492] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  391.034553] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  391.034608] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  391.034660] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  391.034807] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  391.035411] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  391.036015] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  391.036034] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  391.036040] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  391.036086] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  391.036150] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  391.036783] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  391.037214] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  391.037260] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  391.037325] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  391.046056] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.054859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.063671] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.072517] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.081338] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.090235] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.099063] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.107886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.116762] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.125668] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.134659] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.143627] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.152602] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.161613] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.170669] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.179715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.188832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.197880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.206875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.215854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.224856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.233849] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.242823] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.251880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.260860] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.269832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.278872] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.287852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.296822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.305870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.314851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.323833] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.323880] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  391.323895] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  391.323967] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  391.324075] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  391.405240] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  391.409457] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  391.409574] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  391.409586] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  391.410390] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  391.410401] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  391.410410] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  391.410416] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  391.410886] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  391.410900] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  391.410910] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  391.410923] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  391.410932] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  391.410942] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  391.410955] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  391.410964] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  391.410973] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  391.410984] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  391.410993] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  391.411006] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  391.411015] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  391.411025] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  391.411034] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  391.411043] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  391.411052] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  391.411066] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  391.411075] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  391.411088] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  391.411097] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  391.411106] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  391.411116] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  391.411125] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  391.412706] [IGT] kms_flip: starting subtest basic-flip-vs-modeset
>[  391.415787] [drm:drm_mode_addfb2] [FB:71]
>[  391.415950] [drm:drm_mode_addfb2] [FB:91]
>[  391.522700] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  391.522810] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  391.523007] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  391.724840] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  391.724932] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  391.727344] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  391.727404] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  391.727469] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  391.777630] [drm:wait_panel_status [i915]] Wait complete
>[  391.777765] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  391.777847] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  391.777997] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  391.778165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  391.778241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  391.778316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  391.778383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  391.778451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  391.778517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  391.778584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  391.778652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  391.778789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  391.778859] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  391.778947] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  391.779025] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  391.779102] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  391.779843] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  391.779921] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  391.779996] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  391.780151] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  391.795792] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  391.795908] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  391.796197] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  391.796394] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  391.796657] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  391.796886] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  391.797691] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  391.814258] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  391.814440] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  391.814644] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  391.819051] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  391.819148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  391.819247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  391.819349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  391.819439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  391.819529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  391.819618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  391.819831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  391.819925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  391.820022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  391.820466] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  391.820575] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  391.820676] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  391.820890] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  391.821038] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  391.821154] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  391.821292] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  391.821436] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  391.821546] [drm:intel_power_well_disable [i915]] disabling DC off
>[  391.821650] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  391.821837] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  391.822462] [drm:intel_power_well_disable [i915]] disabling always-on
>[  391.823347] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  391.824142] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  391.824192] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  391.824463] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  391.824568] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  391.824674] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  391.824888] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  391.824970] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  391.825057] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  391.825141] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  391.825225] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  391.825315] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  391.825399] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  391.825481] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  391.825500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  391.825583] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  391.825595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  391.825678] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  391.825948] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  391.826032] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  391.826113] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  391.826197] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  391.826285] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  391.826367] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  391.826449] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  391.826534] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  391.826613] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  391.826693] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  391.826851] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  391.826951] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  391.827037] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  391.827656] [drm:intel_power_well_enable [i915]] enabling always-on
>[  391.827806] [drm:intel_power_well_enable [i915]] enabling DC off
>[  391.828136] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  391.828247] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  391.828483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  391.828567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  391.828657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  391.828825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  391.828912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  391.829000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  391.829094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  391.829180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  391.829266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  391.829351] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  391.829446] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  391.829535] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  391.829897] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  391.829931] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  391.830129] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  391.830165] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  392.236891] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  392.303144] [drm:wait_panel_status [i915]] Wait complete
>[  392.303256] [drm:edp_panel_on [i915]] Wait for panel power on
>[  392.303373] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  392.411746] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  392.411854] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  392.411954] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  392.412200] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  392.505391] [drm:wait_panel_status [i915]] Wait complete
>[  392.505537] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  392.505657] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  392.507521] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  392.507619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  392.507839] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  392.509037] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  392.509138] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  392.510630] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  392.511128] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  392.513800] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  392.513965] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  392.514061] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  392.514169] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  392.514302] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  392.514400] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  392.514527] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  392.514627] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  392.531008] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  392.531141] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  392.531472] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  392.547481] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  392.547530] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  392.564572] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  392.564922] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  392.580861] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  392.788863] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  392.789017] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  392.798043] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  392.798160] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  392.798278] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  392.850102] [drm:wait_panel_status [i915]] Wait complete
>[  392.850217] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  392.850337] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  392.850539] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  392.850638] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  392.850739] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  392.850838] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  392.851016] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  392.851255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  392.851378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  392.851486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  392.851592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  392.851696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  392.851881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  392.851991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  392.852099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  392.852210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  392.852320] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  392.852442] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  392.852556] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  392.852668] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  392.852888] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  392.853036] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  392.853168] [drm:intel_power_well_disable [i915]] disabling DC off
>[  392.853273] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  392.853365] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  392.854054] [drm:intel_power_well_disable [i915]] disabling always-on
>[  392.855060] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  392.855112] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  392.855387] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  392.855489] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  392.855595] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  392.855706] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  392.855906] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  392.856012] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  392.856124] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  392.856230] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  392.856335] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  392.856439] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  392.856544] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  392.856566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  392.856671] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  392.856738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  392.856841] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  392.856943] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  392.857054] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  392.857158] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  392.857264] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  392.857374] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  392.857484] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  392.857588] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  392.857692] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  392.858004] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  392.858106] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  392.858215] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  392.858330] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  392.858437] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  392.858903] [drm:intel_power_well_enable [i915]] enabling always-on
>[  392.858996] [drm:intel_power_well_enable [i915]] enabling DC off
>[  392.859338] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  392.859477] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  392.859722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  392.859935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  392.860053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  392.860159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  392.860269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  392.860377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  392.860488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  392.860591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  392.860696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  392.861036] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  392.861077] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  392.861114] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  392.861185] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  392.861220] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  392.861416] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  392.861452] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  393.300891] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  393.402267] [drm:wait_panel_status [i915]] Wait complete
>[  393.402380] [drm:edp_panel_on [i915]] Wait for panel power on
>[  393.402497] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  393.510846] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  393.510953] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  393.511053] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  393.511281] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  393.603109] [drm:wait_panel_status [i915]] Wait complete
>[  393.603249] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  393.603370] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  393.605192] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  393.605294] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  393.605399] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  393.606654] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  393.606849] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  393.608429] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  393.609034] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  393.611651] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  393.611871] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  393.611968] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  393.612075] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  393.612210] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  393.612307] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  393.612435] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  393.612534] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  393.628794] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  393.628849] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  393.629038] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  393.629421] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  393.629523] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  393.645365] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  393.852889] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  393.852952] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  393.863819] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  393.863881] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  393.863946] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  393.915692] [drm:wait_panel_status [i915]] Wait complete
>[  393.915803] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  393.915869] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  393.916002] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  393.916133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  393.916195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  393.916252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  393.916306] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  393.916360] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  393.916414] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  393.916494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  393.916549] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  393.916604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  393.916659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  393.916809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  393.916885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  393.916967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  393.917046] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  393.917138] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  393.917225] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  393.917307] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  393.917419] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  393.917528] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  393.917625] [drm:intel_power_well_disable [i915]] disabling DC off
>[  393.917730] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  393.917795] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  393.918384] [drm:intel_power_well_disable [i915]] disabling always-on
>[  393.919331] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  393.919371] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  393.919587] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  393.919660] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  393.919820] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  393.919904] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  393.919985] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  393.920065] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  393.920142] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  393.920214] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  393.920292] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  393.920366] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  393.920441] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  393.920453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  393.920526] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  393.920537] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  393.920612] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  393.920686] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  393.920824] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  393.920902] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  393.920984] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  393.921065] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  393.921140] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  393.921218] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  393.921299] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  393.921375] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  393.921454] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  393.921533] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  393.921625] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  393.921719] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  393.922010] [drm:intel_power_well_enable [i915]] enabling always-on
>[  393.922073] [drm:intel_power_well_enable [i915]] enabling DC off
>[  393.922391] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  393.922496] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  393.922682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  393.922846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  393.922933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  393.923009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  393.923087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  393.923163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  393.923244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  393.923320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  393.923400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  393.923475] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  393.923560] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  393.923642] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  393.923826] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  393.923903] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  393.924243] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  393.924321] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  394.372902] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  394.503199] [drm:wait_panel_status [i915]] Wait complete
>[  394.503314] [drm:edp_panel_on [i915]] Wait for panel power on
>[  394.503429] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  394.611848] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  394.611956] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  394.612056] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  394.612222] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  394.703962] [drm:wait_panel_status [i915]] Wait complete
>[  394.704103] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  394.704224] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  394.705941] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  394.706043] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  394.706146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  394.707251] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  394.707353] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  394.708945] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  394.709360] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  394.712032] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  394.712205] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  394.712301] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  394.712408] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  394.712539] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  394.712635] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  394.712851] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  394.712961] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  394.729161] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  394.729262] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  394.729525] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  394.730220] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  394.730400] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  394.745839] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  394.948965] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  394.949114] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  394.964193] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  394.964304] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  394.964421] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  395.016237] [drm:wait_panel_status [i915]] Wait complete
>[  395.016353] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  395.016471] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  395.016654] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  395.016754] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  395.016854] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  395.017028] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  395.017329] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  395.017568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  395.017689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  395.017863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  395.017978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  395.018082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  395.018190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  395.018299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  395.018405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  395.018505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  395.018613] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  395.018784] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  395.018897] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  395.019007] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  395.019151] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  395.019296] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  395.019430] [drm:intel_power_well_disable [i915]] disabling DC off
>[  395.019532] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  395.019624] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  395.020274] [drm:intel_power_well_disable [i915]] disabling always-on
>[  395.021325] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  395.021375] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  395.021661] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  395.021852] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  395.021970] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  395.022091] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  395.022192] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  395.022297] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  395.022401] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  395.022503] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  395.022607] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  395.022707] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  395.022890] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  395.022914] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  395.022984] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  395.022994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  395.023038] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  395.023083] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  395.023130] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  395.023174] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  395.023220] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  395.023267] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  395.023313] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  395.023359] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  395.023405] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  395.023452] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  395.023497] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  395.023544] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  395.023598] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  395.023644] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  395.023848] [drm:intel_power_well_enable [i915]] enabling always-on
>[  395.023885] [drm:intel_power_well_enable [i915]] enabling DC off
>[  395.024177] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  395.024242] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  395.024408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  395.024453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  395.024501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  395.024546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  395.024592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  395.024637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  395.024750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  395.024796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  395.024842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  395.024888] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  395.024942] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  395.024990] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  395.025070] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  395.025115] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  395.025342] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  395.025386] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  395.468860] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  395.602114] [drm:wait_panel_status [i915]] Wait complete
>[  395.602203] [drm:edp_panel_on [i915]] Wait for panel power on
>[  395.602296] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  395.710745] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  395.710850] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  395.710950] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  395.711123] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  395.804252] [drm:wait_panel_status [i915]] Wait complete
>[  395.804394] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  395.804513] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  395.806480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  395.806581] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  395.806685] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  395.808200] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  395.808301] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  395.809858] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  395.810276] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  395.812956] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  395.813120] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  395.813216] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  395.813324] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  395.813457] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  395.813554] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  395.813682] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  395.813883] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  395.830079] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  395.830178] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  395.830440] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  395.831423] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  395.831604] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  395.846689] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  396.052891] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  396.053047] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  396.063940] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  396.064055] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  396.064173] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  396.115967] [drm:wait_panel_status [i915]] Wait complete
>[  396.116087] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  396.116207] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  396.116407] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  396.116508] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  396.116609] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  396.116709] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  396.116886] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  396.117959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  396.118079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  396.118186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  396.118287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  396.118388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  396.118488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  396.118593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  396.118694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  396.119614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  396.119716] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  396.120163] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  396.120272] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  396.120377] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  396.120522] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  396.120670] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  396.121368] [drm:intel_power_well_disable [i915]] disabling DC off
>[  396.121470] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  396.121561] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  396.122923] [drm:intel_power_well_disable [i915]] disabling always-on
>[  396.124540] [drm:drm_mode_addfb2] [FB:71]
>[  396.124984] [drm:drm_mode_addfb2] [FB:91]
>[  396.180704] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  396.181163] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  396.181819] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  396.182361] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  396.182381] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  396.182485] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  396.182518] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  396.182557] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  396.182597] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  396.182629] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  396.182711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  396.182748] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  396.182785] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  396.182823] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  396.182858] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  396.182895] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  396.182903] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  396.182938] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  396.182944] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  396.182980] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  396.183015] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  396.183053] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  396.183090] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  396.183127] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  396.183166] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  396.183200] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  396.183239] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  396.183276] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  396.183310] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  396.183346] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  396.183381] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  396.183424] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  396.183460] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  396.183845] [drm:intel_power_well_enable [i915]] enabling always-on
>[  396.183876] [drm:intel_power_well_enable [i915]] enabling DC off
>[  396.184162] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  396.184210] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  396.184243] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  396.184297] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  396.184421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  396.184457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  396.184494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  396.184529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  396.184564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  396.184599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  396.184635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  396.184712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  396.184747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  396.184785] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  396.184825] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  396.184865] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  396.184934] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  396.184968] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  396.185177] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  396.185213] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  396.572854] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  396.702412] [drm:wait_panel_status [i915]] Wait complete
>[  396.702513] [drm:edp_panel_on [i915]] Wait for panel power on
>[  396.702618] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  396.811056] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  396.811163] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  396.811262] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  396.811434] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  396.904348] [drm:wait_panel_status [i915]] Wait complete
>[  396.904491] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  396.904612] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  396.906556] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  396.906655] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.906920] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  396.908205] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  396.908307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  396.909919] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  396.910333] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  396.912585] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  396.912809] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  396.912889] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  396.912980] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  396.913089] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  396.913169] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  396.929673] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  396.929850] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  396.930139] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  396.946246] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  396.946295] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  396.963358] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  396.963589] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  396.979636] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  397.188882] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  397.188943] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  397.197629] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  397.197767] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  397.197833] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  397.249783] [drm:wait_panel_status [i915]] Wait complete
>[  397.249857] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  397.249988] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  397.250120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  397.250181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  397.250239] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  397.250292] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  397.250345] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  397.250430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  397.250484] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  397.250540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  397.250595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  397.250649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  397.251400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  397.251456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  397.251511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  397.251565] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  397.251630] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  397.252130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  397.252209] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  397.252318] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  397.252419] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  397.252492] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  397.252599] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  397.252676] [drm:intel_power_well_disable [i915]] disabling DC off
>[  397.253323] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  397.253390] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  397.254581] [drm:intel_power_well_disable [i915]] disabling always-on
>[  397.255047] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  397.255086] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  397.255297] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  397.255370] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  397.255449] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  397.255531] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  397.255601] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  397.255674] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  397.255846] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  397.255928] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  397.256006] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  397.256086] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  397.256160] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  397.256178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  397.256249] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  397.256265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  397.256342] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  397.256419] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  397.256495] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  397.256572] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  397.256650] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  397.256773] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  397.256848] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  397.256923] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  397.256998] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  397.257071] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  397.257146] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  397.257229] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  397.257316] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  397.257393] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  397.257676] [drm:intel_power_well_enable [i915]] enabling always-on
>[  397.257803] [drm:intel_power_well_enable [i915]] enabling DC off
>[  397.258121] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  397.258220] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  397.258295] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  397.258397] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  397.258613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  397.258689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  397.258848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  397.258929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  397.259001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  397.259076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  397.259154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  397.259230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  397.259305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  397.259382] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  397.259464] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  397.259542] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  397.259664] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  397.259811] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  397.260052] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  397.260088] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  397.700900] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  397.803100] [drm:wait_panel_status [i915]] Wait complete
>[  397.803211] [drm:edp_panel_on [i915]] Wait for panel power on
>[  397.803328] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  397.911740] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  397.911847] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  397.911946] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  397.912115] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  398.004788] [drm:wait_panel_status [i915]] Wait complete
>[  398.004937] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  398.005061] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  398.006906] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  398.007009] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  398.007115] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  398.008304] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  398.008405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  398.009931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  398.010346] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  398.013036] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  398.013188] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  398.013284] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  398.013392] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  398.013523] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  398.013621] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  398.030199] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  398.030315] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  398.030623] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  398.031451] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  398.031666] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  398.046877] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  398.252878] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  398.253028] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  398.263921] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  398.264037] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  398.264154] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  398.315968] [drm:wait_panel_status [i915]] Wait complete
>[  398.316099] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  398.316299] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  398.316453] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  398.316553] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  398.316652] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  398.316827] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  398.317581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  398.317704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  398.317877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  398.317979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  398.318086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  398.318188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  398.318299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  398.318401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  398.318507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  398.318609] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  398.318789] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  398.318901] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  398.319013] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  398.319160] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  398.319300] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  398.319405] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  398.319552] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  398.319661] [drm:intel_power_well_disable [i915]] disabling DC off
>[  398.319823] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  398.319917] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  398.321228] [drm:intel_power_well_disable [i915]] disabling always-on
>[  398.322204] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  398.322255] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  398.322537] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  398.322637] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  398.322845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  398.322962] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  398.323065] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  398.323172] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  398.323274] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  398.323379] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  398.323481] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  398.323585] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  398.323682] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  398.323765] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  398.323863] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  398.323875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  398.323974] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  398.324079] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  398.324180] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  398.324286] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  398.324386] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  398.324497] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  398.324596] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  398.324700] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  398.324851] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  398.324952] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  398.325056] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  398.325164] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  398.325284] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  398.325387] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  398.325816] [drm:intel_power_well_enable [i915]] enabling always-on
>[  398.325904] [drm:intel_power_well_enable [i915]] enabling DC off
>[  398.326251] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  398.326380] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  398.326479] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  398.326620] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  398.326917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  398.326967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  398.327019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  398.327068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  398.327118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  398.327165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  398.327215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  398.327264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  398.327313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  398.327361] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  398.327417] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  398.327471] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  398.327555] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  398.328071] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  398.328281] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  398.328316] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  398.772906] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  398.901553] [drm:wait_panel_status [i915]] Wait complete
>[  398.901666] [drm:edp_panel_on [i915]] Wait for panel power on
>[  398.901913] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  399.010151] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  399.010259] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  399.010359] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  399.010526] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  399.102202] [drm:wait_panel_status [i915]] Wait complete
>[  399.102345] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  399.102466] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  399.104826] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  399.104926] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  399.105031] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  399.106929] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  399.107032] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  399.108535] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  399.108944] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  399.110593] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  399.110775] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  399.110837] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  399.110913] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  399.110999] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  399.111061] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  399.127832] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  399.127938] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  399.128226] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  399.129277] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  399.129475] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  399.144308] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  399.348873] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  399.349019] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  399.361968] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  399.362081] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  399.362199] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  399.414019] [drm:wait_panel_status [i915]] Wait complete
>[  399.414148] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  399.414348] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  399.414464] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  399.414564] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  399.414663] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  399.414837] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  399.415027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  399.415147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  399.415256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  399.415363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  399.415462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  399.415568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  399.415677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  399.415841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  399.415951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  399.416057] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  399.416183] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  399.416301] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  399.416415] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  399.416561] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  399.416705] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  399.416889] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  399.417037] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  399.417155] [drm:intel_power_well_disable [i915]] disabling DC off
>[  399.417258] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  399.417349] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  399.418037] [drm:intel_power_well_disable [i915]] disabling always-on
>[  399.419030] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  399.419081] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  399.419362] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  399.419462] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  399.419567] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  399.419679] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  399.419877] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  399.419981] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  399.420089] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  399.420196] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  399.420308] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  399.420413] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  399.420517] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  399.420538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  399.420642] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  399.420711] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  399.420814] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  399.420918] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  399.421024] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  399.421134] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  399.421240] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  399.421348] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  399.421455] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  399.421562] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  399.421668] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  399.421843] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  399.421942] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  399.422054] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  399.422166] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  399.422273] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  399.422661] [drm:intel_power_well_enable [i915]] enabling always-on
>[  399.422787] [drm:intel_power_well_enable [i915]] enabling DC off
>[  399.423076] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  399.423129] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  399.423165] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  399.423221] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  399.423374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  399.423410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  399.423448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  399.423482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  399.423518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  399.423552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  399.423587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  399.423621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  399.423655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  399.423735] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  399.423776] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  399.423816] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  399.423886] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  399.423921] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  399.424157] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  399.424195] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  399.868958] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  400.003373] [drm:wait_panel_status [i915]] Wait complete
>[  400.003485] [drm:edp_panel_on [i915]] Wait for panel power on
>[  400.003602] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  400.111946] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  400.112052] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  400.112152] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  400.112318] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  400.204159] [drm:wait_panel_status [i915]] Wait complete
>[  400.204305] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  400.204424] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  400.206229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  400.206329] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  400.206434] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  400.207683] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  400.207876] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  400.209826] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  400.210248] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  400.212095] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  400.212174] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  400.212219] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  400.212272] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  400.212337] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  400.212382] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  400.229188] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  400.229277] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  400.229527] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  400.230416] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  400.230583] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  400.245806] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  400.452918] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  400.453069] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  400.463958] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  400.464073] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  400.464191] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  400.515923] [drm:wait_panel_status [i915]] Wait complete
>[  400.516047] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  400.516248] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  400.516462] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  400.516563] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  400.516662] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  400.516836] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  400.516942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  400.517057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  400.517177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  400.517286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  400.517394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  400.517500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  400.517612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  400.517717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  400.517875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  400.517978] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  400.518103] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  400.518217] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  400.518330] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  400.518609] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  400.518830] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  400.518936] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  400.519082] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  400.519194] [drm:intel_power_well_disable [i915]] disabling DC off
>[  400.519297] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  400.519389] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  400.520592] [drm:intel_power_well_disable [i915]] disabling always-on
>[  400.521994] [drm:drm_mode_addfb2] [FB:71]
>[  400.522122] [drm:drm_mode_addfb2] [FB:91]
>[  400.579115] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  400.579572] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  400.580213] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  400.580953] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  400.580974] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  400.581078] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  400.581112] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  400.581152] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  400.581192] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  400.581224] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  400.581259] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  400.581295] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  400.581330] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  400.581364] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  400.581396] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  400.581428] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  400.581435] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  400.581467] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  400.581471] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  400.581504] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  400.581536] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  400.581569] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  400.581601] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  400.581635] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  400.581886] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  400.581920] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  400.581953] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  400.581989] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  400.582022] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  400.582061] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  400.582102] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  400.582138] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  400.582501] [drm:intel_power_well_enable [i915]] enabling always-on
>[  400.582531] [drm:intel_power_well_enable [i915]] enabling DC off
>[  400.582952] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  400.583439] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  400.583474] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  400.583526] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  400.583659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  400.583800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  400.583839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  400.583874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  400.583909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  400.583943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  400.583980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  400.584016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  400.584051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  400.584086] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  400.584126] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  400.584163] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  400.584232] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  400.584266] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  400.584466] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  400.584501] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  400.972892] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  401.102802] [drm:wait_panel_status [i915]] Wait complete
>[  401.102893] [drm:edp_panel_on [i915]] Wait for panel power on
>[  401.102988] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  401.211401] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  401.211460] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  401.211514] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  401.211607] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  401.303235] [drm:wait_panel_status [i915]] Wait complete
>[  401.303355] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  401.303453] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  401.305159] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  401.305240] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  401.305324] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  401.306638] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  401.306769] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  401.308520] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  401.309101] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  401.311355] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  401.311477] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  401.311554] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  401.311640] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  401.312213] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  401.312291] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  401.328469] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  401.328577] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  401.328993] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  401.345060] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  401.345108] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  401.362249] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  401.362482] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  401.378416] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  401.580876] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  401.581028] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  401.596131] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  401.596244] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  401.596362] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  401.648169] [drm:wait_panel_status [i915]] Wait complete
>[  401.648299] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  401.648500] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  401.648667] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  401.648769] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  401.648869] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  401.649045] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  401.649176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  401.649297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  401.649405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  401.649509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  401.649615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  401.649718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  401.649883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  401.649985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  401.650091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  401.650193] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  401.650311] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  401.650426] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  401.650538] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  401.650690] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  401.650884] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  401.650991] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  401.651139] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  401.651245] [drm:intel_power_well_disable [i915]] disabling DC off
>[  401.651348] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  401.651441] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  401.652114] [drm:intel_power_well_disable [i915]] disabling always-on
>[  401.653588] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  401.653631] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  401.654324] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  401.654408] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  401.654492] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  401.654582] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  401.654659] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  401.654834] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  401.654913] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  401.654958] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  401.655004] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  401.655052] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  401.655307] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  401.655316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  401.655358] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  401.655364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  401.655407] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  401.655450] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  401.655495] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  401.655536] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  401.655580] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  401.655627] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  401.655704] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  401.655749] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  401.655795] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  401.655842] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  401.655891] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  401.655949] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  401.655996] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  401.656544] [drm:intel_power_well_enable [i915]] enabling always-on
>[  401.656581] [drm:intel_power_well_enable [i915]] enabling DC off
>[  401.656930] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  401.657720] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  401.657763] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  401.657827] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  401.657986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  401.658030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  401.658077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  401.658121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  401.658164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  401.658208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  401.658253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  401.658296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  401.658340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  401.658383] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  401.658429] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  401.658474] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  401.658551] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  401.658593] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  401.659186] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  401.659233] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  402.100915] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  402.202654] [drm:wait_panel_status [i915]] Wait complete
>[  402.202843] [drm:edp_panel_on [i915]] Wait for panel power on
>[  402.202958] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  402.311344] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  402.311450] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  402.311550] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  402.311715] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  402.404986] [drm:wait_panel_status [i915]] Wait complete
>[  402.405127] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  402.405249] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  402.406985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  402.407084] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  402.407188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  402.408875] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  402.408977] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  402.410847] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  402.411267] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  402.414040] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  402.414122] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  402.414158] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  402.414198] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  402.414250] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  402.414285] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  402.431129] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  402.431215] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  402.431450] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  402.432107] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  402.432594] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  402.447829] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  402.652924] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  402.653077] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  402.666010] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  402.666122] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  402.666240] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  402.717990] [drm:wait_panel_status [i915]] Wait complete
>[  402.718120] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  402.718321] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  402.718525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  402.718627] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  402.718728] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  402.718827] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  402.719002] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  402.719895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  402.720006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  402.720114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  402.720216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  402.720321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  402.720429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  402.720534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  402.720637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  402.720801] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  402.720917] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  402.721030] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  402.721142] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  402.721291] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  402.721432] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  402.721537] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  402.721682] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  402.721844] [drm:intel_power_well_disable [i915]] disabling DC off
>[  402.721948] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  402.722038] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  402.722649] [drm:intel_power_well_disable [i915]] disabling always-on
>[  402.724253] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  402.724306] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  402.724591] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  402.724693] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  402.724952] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  402.725071] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  402.725168] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  402.725277] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  402.725379] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  402.725485] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  402.725588] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  402.725692] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  402.725865] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  402.725886] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  402.725982] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  402.725997] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  402.726100] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  402.726200] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  402.726304] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  402.726405] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  402.726504] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  402.726613] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  402.726716] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  402.726844] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  402.726890] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  402.726936] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  402.726986] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  402.727042] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  402.727089] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  402.727285] [drm:intel_power_well_enable [i915]] enabling always-on
>[  402.727324] [drm:intel_power_well_enable [i915]] enabling DC off
>[  402.727620] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  402.727716] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  402.727762] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  402.727830] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  402.728203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  402.728248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  402.728296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  402.728342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  402.728386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  402.728431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  402.728477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  402.728523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  402.728569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  402.728614] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  402.728663] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  402.728786] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  402.728867] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  402.728915] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  402.729148] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  402.729196] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  403.172857] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  403.302927] [drm:wait_panel_status [i915]] Wait complete
>[  403.302979] [drm:edp_panel_on [i915]] Wait for panel power on
>[  403.303034] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  403.411492] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  403.411541] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  403.411585] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  403.411693] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  403.503574] [drm:wait_panel_status [i915]] Wait complete
>[  403.503670] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  403.503878] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  403.505485] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  403.505565] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  403.505649] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  403.507201] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  403.507283] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  403.508635] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  403.509063] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  403.511175] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  403.511297] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  403.511374] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  403.511460] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  403.511567] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  403.511645] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  403.528333] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  403.528450] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  403.528872] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  403.529621] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  403.529953] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  403.544883] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  403.748874] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  403.749022] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  403.761971] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  403.762085] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  403.762202] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  403.814048] [drm:wait_panel_status [i915]] Wait complete
>[  403.814178] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  403.814380] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  403.814481] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  403.814582] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  403.814681] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  403.814857] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  403.815624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  403.815773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  403.815881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  403.815989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  403.816096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  403.816203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  403.816315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  403.817241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  403.817344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  403.817446] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  403.817567] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  403.817675] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  403.818490] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  403.818641] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  403.819061] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  403.819165] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  403.819311] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  403.819420] [drm:intel_power_well_disable [i915]] disabling DC off
>[  403.819524] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  403.819618] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  403.820239] [drm:intel_power_well_disable [i915]] disabling always-on
>[  403.821429] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  403.821480] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  403.822002] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  403.822106] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  403.822214] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  403.822330] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  403.822429] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  403.822535] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  403.822640] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  403.822955] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  403.822989] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  403.823023] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  403.823055] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  403.823063] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  403.823094] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  403.823098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  403.823131] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  403.823165] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  403.823198] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  403.823232] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  403.823264] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  403.823302] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  403.823336] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  403.823371] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  403.823404] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  403.823439] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  403.823475] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  403.823517] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  403.823551] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  403.823739] [drm:intel_power_well_enable [i915]] enabling always-on
>[  403.823769] [drm:intel_power_well_enable [i915]] enabling DC off
>[  403.824056] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  403.824105] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  403.824139] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  403.824192] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  403.824626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  403.824698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  403.824735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  403.824772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  403.824807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  403.824843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  403.824880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  403.824916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  403.824951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  403.824986] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  403.825026] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  403.825064] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  403.825132] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  403.825167] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  403.825745] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  403.825782] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  404.268859] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  404.403299] [drm:wait_panel_status [i915]] Wait complete
>[  404.403381] [drm:edp_panel_on [i915]] Wait for panel power on
>[  404.403467] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  404.511843] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  404.511941] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  404.512032] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  404.512203] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  404.604702] [drm:wait_panel_status [i915]] Wait complete
>[  404.604922] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  404.605043] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  404.606966] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  404.607069] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  404.607173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  404.608452] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  404.608552] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  404.610219] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  404.610635] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  404.612666] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  404.612777] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  404.612820] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  404.612872] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  404.612934] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  404.612977] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  404.629832] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  404.629921] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  404.630168] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  404.630803] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  404.630967] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  404.646415] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  404.852938] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  404.853087] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  404.863964] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  404.864077] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  404.864195] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  404.915931] [drm:wait_panel_status [i915]] Wait complete
>[  404.916062] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  404.916263] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  404.916454] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  404.916555] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  404.916654] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  404.916827] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  404.917613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  404.917845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  404.917956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  404.918058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  404.918160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  404.918262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  404.918368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  404.919308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  404.919411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  404.919514] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  404.919635] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  404.920288] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  404.920398] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  404.920544] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  404.920681] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  404.921359] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  404.921506] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  404.921611] [drm:intel_power_well_disable [i915]] disabling DC off
>[  404.922262] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  404.922356] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  404.923822] [drm:intel_power_well_disable [i915]] disabling always-on
>[  404.926637] [drm:drm_mode_addfb2] [FB:71]
>[  404.926869] [drm:drm_mode_addfb2] [FB:91]
>[  404.981153] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  404.981613] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  404.982217] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  404.982905] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  404.982926] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  404.983031] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  404.983067] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  404.983104] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  404.983138] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  404.983173] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  404.983207] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  404.983241] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  404.983274] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  404.983307] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  404.983314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  404.983346] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  404.983350] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  404.983383] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  404.983415] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  404.983453] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  404.983487] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  404.983520] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  404.983556] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  404.983589] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  404.983623] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  404.983657] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  404.983734] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  404.983773] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  404.983825] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  404.983875] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  404.983913] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  404.984272] [drm:intel_power_well_enable [i915]] enabling always-on
>[  404.984301] [drm:intel_power_well_enable [i915]] enabling DC off
>[  404.984586] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  404.984637] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  404.984709] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  404.984764] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  404.985021] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  404.989251] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  404.989328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  404.989367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  404.989406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  404.989442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  404.989477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  404.989512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  404.989547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  404.989582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  404.989616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  404.989651] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  404.989740] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  404.989779] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  404.989847] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  404.989881] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  404.990661] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  404.991957] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  404.992516] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  404.992555] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  404.992614] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  404.992651] [drm:hsw_audio_config_update [i915]] using automatic N
>[  404.992797] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  404.992836] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  405.009606] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.009678] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.009981] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.026156] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.026183] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  405.043059] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.043208] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  405.059543] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  405.059638] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  405.060036] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.076698] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.076877] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  405.077047] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  405.077232] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  405.081521] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.081614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.081710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.081922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.082015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.082109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.082200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.082306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.082397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.082491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.082581] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.082689] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.082852] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.082950] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.083086] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  405.083180] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.083305] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.083437] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.083555] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.083647] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  405.083807] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  405.084414] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.085438] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.085483] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  405.085829] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  405.085929] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.086024] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  405.086116] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  405.086209] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.086303] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  405.086393] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.086485] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  405.086575] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.086592] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.086677] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.086752] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.086850] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  405.086943] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  405.087036] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.087138] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.087229] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.087326] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  405.087413] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.087513] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.087607] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.087704] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  405.087841] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  405.087972] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  405.088086] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  405.088179] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  405.088490] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.088569] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.088936] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  405.089500] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.089547] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.089614] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  405.090052] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  405.094297] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.094374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.094412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.094451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.094486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.094521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.094556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.094591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.094626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.094659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.094742] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.094783] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.094824] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.094892] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  405.094926] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  405.095183] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  405.096186] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  405.096756] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  405.096792] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  405.096845] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  405.096879] [drm:hsw_audio_config_update [i915]] using automatic N
>[  405.096971] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  405.097006] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  405.113887] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.113937] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.114103] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.114444] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.114539] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  405.130436] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  405.130511] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  405.130629] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.147344] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.147434] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  405.147584] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  405.147871] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  405.152126] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.152210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.152297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.152387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.152469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.152550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.152631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.152829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.152912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.152994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.153076] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.153170] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.153261] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.153349] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.153470] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  405.153554] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.153668] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.153859] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.153967] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.154052] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  405.154125] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  405.154782] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.155625] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.155705] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  405.155939] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  405.156022] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.156108] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  405.156188] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  405.156271] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.156354] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  405.156436] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.156517] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  405.156596] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.156608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.156684] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.156764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.156850] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  405.156933] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  405.157013] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.157098] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.157177] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.157266] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  405.157345] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.157430] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.157511] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.157597] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  405.157679] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  405.157850] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  405.157937] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  405.158005] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  405.158242] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.158301] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.158615] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  405.158769] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.158833] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.158927] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  405.159251] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  405.163522] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.163565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.163611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.163657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.163821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.163863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.163905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.163945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.163989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.164030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.164072] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.164120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.164166] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.164242] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  405.164283] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  405.164558] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  405.165841] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  405.166384] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  405.166425] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  405.166485] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  405.166524] [drm:hsw_audio_config_update [i915]] using automatic N
>[  405.166628] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  405.166813] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  405.183454] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.183509] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.183759] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.184163] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.184283] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  405.200052] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  405.200105] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  405.200195] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.216689] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.216829] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  405.216972] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  405.217119] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  405.221356] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.221422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.221490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.221559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.221622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.221685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.221945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.222017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.222081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.222146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.222208] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.222283] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.222353] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.222421] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.222516] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  405.222582] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.222670] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.222947] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.223032] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.223096] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  405.223152] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  405.224338] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.224741] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.224777] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  405.224958] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  405.225022] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.225088] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  405.225149] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  405.225212] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.225275] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  405.225339] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.225400] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  405.225462] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.225471] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.225530] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.225539] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.225600] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  405.225662] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  405.225780] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.225843] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.225908] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.225975] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  405.226038] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.226102] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.226169] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.226232] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  405.226297] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  405.226388] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  405.226470] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  405.226534] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  405.226788] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.226843] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.227150] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  405.227240] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.227303] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.227390] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  405.227793] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  405.232042] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.232088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.232136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.232184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.232228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.232272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.232315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.232359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.232403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.232446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.232489] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.232535] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.232580] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.232656] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  405.232759] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  405.233046] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  405.234261] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  405.234868] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  405.234912] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  405.234977] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  405.235020] [drm:hsw_audio_config_update [i915]] using automatic N
>[  405.235133] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  405.235176] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  405.251940] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.252025] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.252252] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.252885] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.253059] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  405.268537] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  405.268616] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  405.268833] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.285509] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.285609] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  405.286311] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  405.286504] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  405.290778] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.290862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.290949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.291040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.291121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.291202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.291282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.291372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.291452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.291533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.291613] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.291703] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.291893] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.291987] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.292110] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  405.292193] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.292303] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.292421] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.292528] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.292611] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  405.292685] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  405.293353] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.294294] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.294337] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  405.294566] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  405.294647] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.294819] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  405.294899] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  405.294990] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.295074] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  405.295161] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.295244] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  405.295329] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.295342] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.295426] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.295441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.295525] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  405.295608] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  405.295695] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.295819] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.295900] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.295986] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  405.296066] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.296147] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.296228] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.296314] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  405.296395] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  405.296516] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  405.296621] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  405.296781] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  405.297006] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.297062] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.297371] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  405.297456] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.297516] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.297602] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  405.298162] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  405.302425] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.302469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.302514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.302560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.302602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.302643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.302740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.302783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.302827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.302872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.302914] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.302962] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.303008] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.303087] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  405.303129] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  405.303411] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  405.304567] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  405.305150] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  405.305192] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  405.305254] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  405.305296] [drm:hsw_audio_config_update [i915]] using automatic N
>[  405.305817] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  405.305859] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  405.322260] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.322345] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.322574] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.323197] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.323371] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  405.338830] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  405.338910] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  405.339042] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.355680] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.355856] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  405.356024] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  405.356210] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  405.360475] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.360561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.360649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.360844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.360928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.361013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.361096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.361190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.361273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.361358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.361440] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.361537] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.361628] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.361781] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.361902] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  405.361987] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.362099] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.362217] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.362324] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.362407] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  405.362480] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  405.363145] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.364063] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.364104] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  405.364332] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  405.364413] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.364497] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  405.364574] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  405.364654] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.364821] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  405.364903] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.364990] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  405.365074] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.365093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.365171] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.365185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.365272] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  405.365357] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  405.365445] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.365528] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.365633] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.365776] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  405.365871] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.365962] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.366059] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.366154] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  405.366249] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  405.366379] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  405.366493] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  405.366586] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  405.367100] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.367180] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.367518] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  405.367641] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.367813] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.367887] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  405.368191] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  405.372445] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.372488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.372533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.372579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.372621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.372663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.372761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.372804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.372847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.372892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.372934] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.372981] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.373028] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.373104] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  405.373146] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  405.373424] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  405.374593] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  405.375179] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  405.375223] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  405.375285] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  405.375326] [drm:hsw_audio_config_update [i915]] using automatic N
>[  405.375435] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  405.375477] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  405.392213] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.392281] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.392483] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.393110] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.393283] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  405.408859] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  405.408940] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  405.409070] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.425812] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.425911] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  405.426081] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  405.426269] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  405.430557] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.430650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.430860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.430964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.431057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.431151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.431243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.431346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.431437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.431533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.431623] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.431763] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.431864] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.431973] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.432105] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  405.432197] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.432321] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.432451] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.432571] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.432662] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  405.432814] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  405.433423] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.434444] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.434489] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  405.434829] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  405.434927] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.435029] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  405.435118] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  405.435214] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.435305] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  405.435398] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.435487] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  405.435577] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.435593] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.435681] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.435757] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.435853] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  405.435946] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  405.436041] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.436138] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.436235] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.436335] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  405.436429] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.436524] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.436622] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.436735] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  405.436831] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  405.436967] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  405.437081] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  405.437178] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  405.437493] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.437571] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.438027] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  405.438500] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.438545] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.438613] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  405.438891] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  405.443141] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.443216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.443255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.443293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.443328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.443363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.443398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.443433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.443468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.443501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.443538] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.443574] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.443610] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.443723] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  405.443760] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  405.444058] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  405.445066] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  405.445600] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  405.445635] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  405.445723] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  405.445758] [drm:hsw_audio_config_update [i915]] using automatic N
>[  405.445855] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  405.445890] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  405.462643] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.462772] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.462982] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.463470] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.463620] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  405.479275] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  405.479345] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  405.479458] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.496023] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.496115] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  405.496273] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  405.496444] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  405.500806] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.500899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.500997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.501097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.501187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.501276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.501366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.501464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.501553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.501642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.501822] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.501929] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.502034] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.502137] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.502270] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  405.502362] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.502487] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.502616] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.502812] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.502909] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  405.502995] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  405.503604] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.504519] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.504566] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  405.504908] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  405.505004] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.505097] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  405.505188] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  405.505281] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.505375] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  405.505465] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.505555] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  405.505644] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.505729] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.505821] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.505833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.505932] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  405.506026] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  405.506124] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.506220] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.506316] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.506419] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  405.506515] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.506612] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.506709] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.506846] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  405.506938] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  405.507074] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  405.507188] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  405.507281] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  405.507589] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.507669] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.508045] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  405.508124] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.508177] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.508257] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  405.508569] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  405.512868] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.512943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.512981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.513020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.513055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.513090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.513125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.513160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.513195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.513228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.513264] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.513300] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.513336] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.513402] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  405.513435] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  405.513763] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  405.514754] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  405.515287] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  405.515321] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  405.515373] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  405.515405] [drm:hsw_audio_config_update [i915]] using automatic N
>[  405.515497] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  405.515530] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  405.532381] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.532455] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.532667] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.533237] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.533388] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  405.548961] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  405.549035] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  405.549149] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.565780] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.565865] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  405.566015] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  405.566173] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  405.570415] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.570485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.570559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.570635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.570794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.570863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.570934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.571012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.571083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.571155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.571223] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.571304] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.571382] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.571455] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.571560] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  405.571632] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.571788] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.571892] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.571982] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.572052] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  405.572114] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  405.572761] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.573562] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.573596] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  405.573866] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  405.573937] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.574012] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  405.574079] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  405.574150] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.574219] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  405.574288] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.574355] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  405.574423] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.574433] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.574499] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.574509] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.574576] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  405.574645] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  405.574771] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.574844] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.574913] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.574990] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  405.575058] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.575133] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.575204] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.575277] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  405.575346] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  405.575449] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  405.575539] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  405.575612] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  405.575944] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.576014] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.576339] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  405.576449] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.576529] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.576640] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  405.577080] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  405.581327] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.581373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.581421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.581469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.581513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.581557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.581600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.581644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.581747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.581792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.581839] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.581890] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.581938] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.582017] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  405.582061] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  405.582354] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  405.583571] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  405.584176] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  405.584221] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  405.584286] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  405.584329] [drm:hsw_audio_config_update [i915]] using automatic N
>[  405.584443] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  405.584487] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  405.601286] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.601369] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.601596] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.602220] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.602393] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  405.617852] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  405.617932] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  405.618061] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.634720] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.634897] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  405.635065] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  405.635252] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  405.639541] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.639636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.639847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.639952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.640044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.640138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.640231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.640333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.640425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.640519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.640610] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.640791] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.640896] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.641005] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.641137] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  405.641229] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.641353] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.641482] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.641601] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.641693] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  405.641844] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  405.642454] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.643478] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.643523] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  405.643860] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  405.643954] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.644052] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  405.644141] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  405.644237] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.644327] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  405.644420] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.644509] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  405.644600] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.644614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.644699] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.644782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.644876] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  405.644971] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  405.645068] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.645156] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.645253] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.645352] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  405.645446] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.645538] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.645635] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.645769] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  405.645866] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  405.645998] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  405.646114] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  405.646211] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  405.646522] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.646603] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.647054] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  405.647529] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.647574] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.647643] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  405.648113] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  405.652359] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.652434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.652471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.652508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.652542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.652576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.652611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.652646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.652728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.652764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.652801] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.652842] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.652881] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.653164] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  405.653199] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  405.653453] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  405.654588] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  405.655158] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  405.655194] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  405.655374] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  405.655407] [drm:hsw_audio_config_update [i915]] using automatic N
>[  405.655500] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  405.655533] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  405.672252] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.672325] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.672536] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.673311] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.673463] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  405.688836] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  405.688906] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  405.689020] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.705658] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.705822] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  405.705981] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  405.706152] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  405.710408] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.710486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.710567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.710648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.710818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.710907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.710982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.711068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.711172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.711267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.711357] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.711465] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.711564] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.711664] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.711864] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  405.711960] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.712084] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.712212] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.712330] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.712422] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  405.712504] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  405.713187] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.714135] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.714180] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  405.714433] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  405.714522] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.714615] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  405.714700] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  405.714892] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.714981] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  405.715074] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.715163] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  405.715254] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.715268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.715356] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.715370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.715458] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  405.715551] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  405.715640] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.715782] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.715868] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.715970] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  405.716059] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.716153] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.716243] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.716337] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  405.716428] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  405.716560] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  405.716673] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  405.716810] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  405.717112] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.717189] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.717522] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  405.717644] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.717801] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.717872] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  405.718175] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  405.722438] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.722479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.722522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.722566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.722606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.722645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.722737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.722777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.722816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.722857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.722897] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.722941] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.722984] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.723057] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  405.723096] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  405.723469] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  405.724610] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  405.725207] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  405.725246] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  405.725306] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  405.725345] [drm:hsw_audio_config_update [i915]] using automatic N
>[  405.725451] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  405.725492] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  405.742279] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.742350] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.742551] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.743135] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.743298] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  405.758876] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  405.758953] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  405.759075] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.775529] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.775623] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  405.775994] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  405.776185] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  405.780446] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.780529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.780617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.780802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.780894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.780978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.781064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.781155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.781237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.781318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.781400] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.781496] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.781584] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.781674] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.781838] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  405.781922] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.782036] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.782152] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.782257] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.782339] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  405.782412] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  405.783070] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.783982] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.784024] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  405.784251] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  405.784331] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.784415] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  405.784491] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  405.784571] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.784651] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  405.784809] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.784890] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  405.784976] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.784994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.785077] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.785093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.785179] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  405.785262] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  405.785348] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.785432] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.785520] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.785609] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  405.785711] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.785825] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.785906] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.785983] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  405.786056] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  405.786164] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  405.786257] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  405.786332] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  405.786578] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.786641] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.787008] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  405.787105] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.787177] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.787278] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  405.787613] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  405.789794] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.789839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.789886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.789934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.789978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.790020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.790062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.790104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.790148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.790189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.790231] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.790276] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.790321] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.790397] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  405.790438] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  405.790767] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  405.791753] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  405.792284] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  405.792319] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  405.792370] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  405.792402] [drm:hsw_audio_config_update [i915]] using automatic N
>[  405.792491] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  405.792524] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  405.809379] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.809451] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.809661] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.810218] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.810370] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  405.825951] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  405.826038] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  405.826175] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.842873] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.842965] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  405.843123] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  405.843292] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  405.847534] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.847610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.847690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.847862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.847936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.848009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.848081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.848163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.848241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.848315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.848391] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.848477] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.848557] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.848639] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.848844] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  405.848944] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.849066] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.849192] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.849308] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.849399] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  405.849479] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  405.850148] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.851087] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.851132] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  405.851379] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  405.851468] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.851560] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  405.851646] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  405.851824] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.851918] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  405.852015] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.852108] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  405.852201] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.852220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.852311] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.852330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.852426] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  405.852520] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  405.852615] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.852710] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.852846] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.852947] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  405.853041] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.853136] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.853229] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.853318] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  405.853414] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  405.853541] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  405.853652] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  405.853802] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  405.854102] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.854177] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.854492] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  405.854553] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.854596] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.854659] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  405.854955] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  405.859193] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.859236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.859281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.859327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.859369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.859410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.859450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.859490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.859531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.859570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.859613] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.859656] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.859757] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.859831] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  405.859872] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  405.860152] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  405.861292] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  405.861872] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  405.861916] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  405.861979] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  405.862019] [drm:hsw_audio_config_update [i915]] using automatic N
>[  405.862124] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  405.862165] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  405.878987] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.879070] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.879297] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.879920] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.880093] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  405.895543] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  405.895622] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  405.895832] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.912363] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.912441] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  405.912583] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  405.912810] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  405.917043] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.917108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.917177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.917245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.917309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.917372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.917434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.917503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.917566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.917627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.917721] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.917802] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.917871] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.917946] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.918038] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  405.918102] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.918187] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.918277] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.918359] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.918422] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  405.918477] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  405.919141] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.920056] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.920098] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  405.920321] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  405.920403] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.920487] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  405.920563] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  405.920643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.920803] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  405.920886] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.920974] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  405.921058] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.921078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.921157] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.921173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.921259] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  405.921345] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  405.921433] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.921519] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.921604] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.921695] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  405.921818] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.921906] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.921986] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.922070] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  405.922147] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  405.922261] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  405.922362] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  405.922445] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  405.922766] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.922837] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.923167] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  405.923274] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.923351] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.923447] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  405.923784] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  405.928033] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.928078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.928125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.928174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.928218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.928262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.928303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.928347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.928389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.928434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.928477] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.928523] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.928567] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.928645] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  405.928747] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  405.929036] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  405.930242] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  405.930845] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  405.930889] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  405.930955] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  405.930998] [drm:hsw_audio_config_update [i915]] using automatic N
>[  405.931110] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  405.931153] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  405.947926] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.947999] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.948208] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.948744] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.948897] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  405.964506] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  405.964576] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  405.964756] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.981362] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.981453] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  405.981612] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  405.981925] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  405.986189] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.986272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.986359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.986449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.986530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.986611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.986692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.986876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.986965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.987050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.987136] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  405.987233] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.987321] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.987407] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.987522] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  405.987603] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.987771] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.987889] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  405.987995] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.988077] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  405.988150] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  405.988788] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.989721] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  405.989764] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  405.989990] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  405.990071] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.990157] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  405.990234] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  405.990317] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.990397] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  405.990479] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.990557] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  405.990637] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.990728] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.990805] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.990815] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  405.990894] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  405.990977] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  405.991058] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.991141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.991222] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.991317] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  405.991398] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.991484] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.991569] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.991657] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  405.991780] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  405.991899] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  405.992005] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  405.992093] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  405.992370] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.992439] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.992835] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  405.993358] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.993402] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.993467] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  405.993773] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  405.998015] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  405.998059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  405.998104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  405.998149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  405.998191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  405.998233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  405.998273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  405.998313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  405.998354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  405.998394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  405.998437] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  405.998480] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  405.998523] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  405.998596] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  405.998636] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  405.998965] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  406.000107] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  406.000649] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  406.000730] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  406.000791] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  406.000831] [drm:hsw_audio_config_update [i915]] using automatic N
>[  406.000937] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  406.000977] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  406.017812] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.017894] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  406.018122] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.018715] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  406.018892] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  406.034366] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  406.034462] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  406.034612] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  406.051375] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  406.051478] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  406.051647] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  406.052002] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  406.056284] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  406.056377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  406.056474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  406.056573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  406.056661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  406.056854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  406.056951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  406.057058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  406.057149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  406.057239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  406.057329] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.057430] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  406.057528] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  406.057625] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.057783] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  406.057877] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  406.058004] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  406.058130] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  406.058246] [drm:intel_power_well_disable [i915]] disabling DC off
>[  406.058336] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  406.058417] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  406.059079] [drm:intel_power_well_disable [i915]] disabling always-on
>[  406.060034] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  406.060080] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  406.060327] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  406.060417] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  406.060511] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  406.060597] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  406.060688] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  406.060856] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  406.060952] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  406.061046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  406.061139] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  406.061159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  406.061251] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  406.061270] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  406.061365] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  406.061458] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  406.061553] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  406.061646] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  406.061782] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  406.061883] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  406.061974] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  406.062065] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  406.062162] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  406.062260] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  406.062354] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  406.062488] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  406.062601] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  406.062696] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  406.062972] [drm:intel_power_well_enable [i915]] enabling always-on
>[  406.063022] [drm:intel_power_well_enable [i915]] enabling DC off
>[  406.063331] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  406.063387] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  406.063426] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  406.063486] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  406.063761] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  406.068013] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  406.068055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  406.068098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  406.068142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  406.068182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  406.068222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  406.068259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  406.068297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  406.068337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  406.068374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  406.068417] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  406.068458] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  406.068499] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.068570] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  406.068607] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  406.068922] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  406.070056] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  406.070614] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  406.070653] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  406.070747] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  406.070786] [drm:hsw_audio_config_update [i915]] using automatic N
>[  406.070888] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  406.070926] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  406.087760] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.087838] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  406.088056] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.088559] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  406.088781] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  406.104335] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  406.104431] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  406.104581] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  406.121273] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  406.121378] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  406.121547] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  406.121892] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  406.126173] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  406.126269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  406.126367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  406.126464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  406.126555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  406.126644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  406.126843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  406.126948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  406.127039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  406.127130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  406.127219] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.127325] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  406.127424] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  406.127524] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.127654] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  406.127809] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  406.127938] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  406.128068] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  406.128185] [drm:intel_power_well_disable [i915]] disabling DC off
>[  406.128277] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  406.128361] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  406.129015] [drm:intel_power_well_disable [i915]] disabling always-on
>[  406.129983] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  406.130028] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  406.130280] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  406.130369] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  406.130461] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  406.130546] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  406.130635] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  406.130811] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  406.130904] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  406.130999] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  406.131090] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  406.131112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  406.131199] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  406.131215] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  406.131311] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  406.131403] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  406.131498] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  406.131594] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  406.131693] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  406.131875] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  406.131979] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  406.132088] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  406.132194] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  406.132301] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  406.132401] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  406.132545] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  406.132669] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  406.132830] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  406.133169] [drm:intel_power_well_enable [i915]] enabling always-on
>[  406.133255] [drm:intel_power_well_enable [i915]] enabling DC off
>[  406.133568] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  406.133630] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  406.133704] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  406.133768] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  406.134034] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  406.138271] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  406.138349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  406.138387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  406.138425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  406.138460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  406.138495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  406.138528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  406.138561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  406.138598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  406.138631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  406.138711] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  406.138753] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  406.138794] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.138860] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  406.138893] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  406.139178] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  406.140171] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  406.140735] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  406.140770] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  406.140821] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  406.140855] [drm:hsw_audio_config_update [i915]] using automatic N
>[  406.140951] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  406.140985] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  406.157856] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.157926] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  406.158127] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.158588] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  406.158790] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  406.174405] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  406.174470] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  406.174578] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  406.191145] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  406.191225] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  406.191367] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  406.191515] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  406.195787] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  406.195853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  406.195922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  406.195992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  406.196057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  406.196120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  406.196183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  406.196252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  406.196314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  406.196377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  406.196439] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.196508] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  406.196574] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  406.196639] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.196799] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  406.196866] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  406.196957] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  406.197048] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  406.197131] [drm:intel_power_well_disable [i915]] disabling DC off
>[  406.197195] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  406.197252] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  406.197907] [drm:intel_power_well_disable [i915]] disabling always-on
>[  406.198788] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  406.198826] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  406.199034] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  406.199107] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  406.199184] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  406.199255] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  406.199328] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  406.199399] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  406.199472] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  406.199542] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  406.199612] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  406.199623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  406.199692] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  406.199775] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  406.199855] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  406.199930] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  406.200009] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  406.200086] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  406.200162] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  406.200244] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  406.200320] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  406.200398] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  406.200475] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  406.200551] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  406.200628] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  406.200775] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  406.200870] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  406.200943] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  406.201204] [drm:intel_power_well_enable [i915]] enabling always-on
>[  406.201268] [drm:intel_power_well_enable [i915]] enabling DC off
>[  406.201586] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  406.201683] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  406.201800] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  406.201906] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  406.202309] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  406.206584] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  406.206630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  406.206730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  406.206779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  406.206825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  406.206868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  406.206913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  406.206957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  406.207002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  406.207046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  406.207091] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  406.207140] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  406.207187] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.207265] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  406.207309] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  406.207592] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  406.208822] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  406.209386] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  406.209429] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  406.209492] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  406.209533] [drm:hsw_audio_config_update [i915]] using automatic N
>[  406.209646] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  406.209730] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  406.226491] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.226575] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  406.226890] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.227426] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  406.227595] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  406.237259] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x18001a18, pins 0x00000040
>[  406.237324] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - long
>[  406.237384] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 6 - cnt: 0
>[  406.237519] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - long
>[  406.243070] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  406.243172] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  406.243334] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  406.260107] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  406.260206] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  406.260374] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  406.260559] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  406.264913] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  406.265006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  406.265104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  406.265204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  406.265295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  406.265385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  406.265474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  406.265572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  406.265662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  406.265870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  406.265965] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.266077] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  406.266179] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  406.266278] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.266407] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  406.266499] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  406.266621] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  406.266822] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  406.266944] [drm:intel_power_well_disable [i915]] disabling DC off
>[  406.267036] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  406.267117] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  406.267788] [drm:intel_power_well_disable [i915]] disabling always-on
>[  406.268550] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[  406.268648] [drm:i915_hotplug_work_func [i915]] Connector DP-2 (pin 6) received hotplug event.
>[  406.268854] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  406.268944] [drm:intel_power_well_enable [i915]] enabling always-on
>[  406.269021] [drm:intel_power_well_enable [i915]] enabling DC off
>[  406.269358] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  406.269468] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  406.269552] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  406.270150] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  406.270541] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  406.270581] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  406.270747] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  406.270790] [drm:intel_power_well_disable [i915]] disabling DC off
>[  406.270832] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  406.270867] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  406.271416] [drm:intel_power_well_disable [i915]] disabling always-on
>[  406.271460] [drm:i915_hotplug_work_func [i915]] Connector HDMI-A-1 (pin 6) received hotplug event.
>[  406.271501] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.271537] [drm:intel_power_well_enable [i915]] enabling always-on
>[  406.271570] [drm:intel_power_well_enable [i915]] enabling DC off
>[  406.272066] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  406.272121] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  406.272160] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  406.351839] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  406.355972] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  406.356048] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  406.356056] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  406.356115] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  406.356203] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  406.356262] [drm:intel_power_well_disable [i915]] disabling DC off
>[  406.356324] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  406.356380] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  406.357030] [drm:intel_power_well_disable [i915]] disabling always-on
>[  406.357140] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  406.357177] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  406.357367] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  406.357431] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  406.357500] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  406.357561] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  406.357628] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  406.357768] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  406.357835] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  406.357902] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  406.357967] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  406.357981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  406.358041] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  406.358052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  406.358118] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  406.358182] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  406.358250] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  406.358314] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  406.358379] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  406.358449] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  406.358513] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  406.358579] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  406.358645] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  406.358742] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  406.358811] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  406.358902] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  406.358985] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  406.359051] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  406.359245] [drm:intel_power_well_enable [i915]] enabling always-on
>[  406.359297] [drm:intel_power_well_enable [i915]] enabling DC off
>[  406.359611] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  406.359761] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  406.359826] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  406.359912] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  406.360195] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  406.364415] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  406.364474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  406.364536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  406.364597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  406.364652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  406.364783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  406.364838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  406.364894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  406.364951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  406.365007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  406.365063] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  406.365127] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  406.365186] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.365280] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  406.365335] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  406.365654] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  406.367198] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  406.367830] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  406.367886] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  406.367968] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  406.368022] [drm:hsw_audio_config_update [i915]] using automatic N
>[  406.368155] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  406.368211] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  406.384911] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.385001] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  406.385239] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.386124] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  406.386314] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  406.401509] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  406.401605] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  406.402090] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  406.418784] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  406.418880] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  406.419037] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  406.419210] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  406.423469] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  406.423546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  406.423626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  406.423750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  406.423828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  406.423910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  406.423987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  406.424073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  406.424150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  406.424229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  406.424592] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.424681] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  406.424820] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  406.424902] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.425274] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  406.425351] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  406.425451] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  406.425559] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  406.425654] [drm:intel_power_well_disable [i915]] disabling DC off
>[  406.425807] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  406.425878] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  406.427087] [drm:intel_power_well_disable [i915]] disabling always-on
>[  406.428121] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  406.428163] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  406.428394] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  406.428475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  406.428560] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  406.428636] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  406.428809] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  406.428894] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  406.428981] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  406.429064] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  406.429148] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  406.429162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  406.429240] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  406.429258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  406.429339] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  406.429422] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  406.429512] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  406.429595] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  406.429681] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  406.429811] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  406.429894] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  406.429981] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  406.430066] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  406.430152] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  406.430234] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  406.430354] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  406.430457] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  406.430541] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  406.430881] [drm:intel_power_well_enable [i915]] enabling always-on
>[  406.430938] [drm:intel_power_well_enable [i915]] enabling DC off
>[  406.431244] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  406.431330] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  406.431392] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  406.431482] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  406.431928] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  406.434917] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x18001a18, pins 0x00000040
>[  406.434984] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - long
>[  406.435045] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 6 - cnt: 1
>[  406.435160] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - long
>[  406.436101] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  406.436152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  406.436205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  406.436259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  406.436308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  406.436357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  406.436405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  406.436454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  406.436502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  406.436551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  406.436599] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  406.436650] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  406.436795] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.436875] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  406.436919] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  406.437217] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  406.438439] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  406.439047] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  406.439093] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  406.439157] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  406.439198] [drm:hsw_audio_config_update [i915]] using automatic N
>[  406.439308] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  406.439352] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  406.456034] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.456099] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  406.456295] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.456608] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[  406.456661] [drm:i915_hotplug_work_func [i915]] Connector DP-2 (pin 6) received hotplug event.
>[  406.456755] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  406.465510] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.474278] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.483030] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.491837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.500690] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.509550] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.518367] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.527271] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.536161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.545055] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.553956] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.562856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.571823] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.580840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.589825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.598839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.607834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.616845] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.625839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.634830] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.643822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.652837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.661815] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.670815] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.679822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.688822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.697823] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.706825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.715824] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.724824] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.733834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.742844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.742892] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  406.743000] [drm:i915_hotplug_work_func [i915]] Connector HDMI-A-1 (pin 6) received hotplug event.
>[  406.743098] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.822346] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  406.826519] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  406.826632] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  406.826761] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  406.826938] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  406.827225] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  406.827532] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  406.827658] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  406.828012] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  406.840157] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  406.840283] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  406.840480] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  406.840707] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  406.845113] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  406.845217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  406.845327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  406.845438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  406.845539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  406.845640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  406.845867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  406.845985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  406.846090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  406.846193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  406.846298] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.846414] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  406.846524] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  406.846636] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.846852] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  406.846955] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  406.847089] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  406.847232] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  406.847365] [drm:intel_power_well_disable [i915]] disabling DC off
>[  406.847467] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  406.847559] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  406.848251] [drm:intel_power_well_disable [i915]] disabling always-on
>[  406.849214] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  406.849265] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  406.849543] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  406.849643] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  406.849860] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  406.849967] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  406.850075] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  406.850180] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  406.850281] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  406.850377] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  406.850476] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  406.850491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  406.850586] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  406.850600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  406.850700] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  406.850874] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  406.850950] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  406.850996] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  406.851039] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  406.851086] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  406.851129] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  406.851176] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  406.851221] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  406.851266] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  406.851309] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  406.851373] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  406.851427] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  406.851468] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  406.851592] [drm:intel_power_well_enable [i915]] enabling always-on
>[  406.851627] [drm:intel_power_well_enable [i915]] enabling DC off
>[  406.851948] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  406.852009] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  406.852049] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  406.852111] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  406.852336] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  406.856462] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  406.856505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  406.856550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  406.856596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  406.856637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  406.856736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  406.856781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  406.856825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  406.856870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  406.856911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  406.856952] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  406.856996] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  406.857040] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.857113] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  406.857155] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  406.857434] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  406.858576] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  406.859159] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  406.859199] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  406.859261] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  406.859301] [drm:hsw_audio_config_update [i915]] using automatic N
>[  406.859768] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  406.859809] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  406.876238] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.876310] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  406.876520] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.877093] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  406.877266] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  406.892836] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  406.892917] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  406.893046] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  406.909698] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  406.909874] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  406.910043] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  406.910227] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  406.914487] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  406.914571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  406.914658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  406.914843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  406.914929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  406.915016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  406.915098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  406.915192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  406.915274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  406.915358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  406.915440] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.915535] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  406.915627] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  406.915801] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.915934] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  406.916025] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  406.916148] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  406.916277] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  406.916394] [drm:intel_power_well_disable [i915]] disabling DC off
>[  406.916486] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  406.916569] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  406.917245] [drm:intel_power_well_disable [i915]] disabling always-on
>[  406.918183] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  406.918229] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  406.918479] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  406.918568] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  406.918662] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  406.918837] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  406.918932] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  406.919026] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  406.919120] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  406.919214] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  406.919301] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  406.919314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  406.919407] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  406.919422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  406.919512] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  406.919606] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  406.919700] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  406.919836] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  406.919929] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  406.920024] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  406.920117] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  406.920209] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  406.920298] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  406.920389] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  406.920480] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  406.920607] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  406.920781] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  406.920879] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  406.921159] [drm:intel_power_well_enable [i915]] enabling always-on
>[  406.921202] [drm:intel_power_well_enable [i915]] enabling DC off
>[  406.921500] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  406.921573] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  406.921624] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  406.921733] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  406.922334] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  406.926587] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  406.926661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  406.926747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  406.926913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  406.926947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  406.926983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  406.927018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  406.927053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  406.927088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  406.927121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  406.927156] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  406.927193] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  406.927230] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.927296] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  406.927329] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  406.927581] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  406.928829] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  406.929362] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  406.929397] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  406.929448] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  406.929480] [drm:hsw_audio_config_update [i915]] using automatic N
>[  406.929569] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  406.929602] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  406.946461] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.946535] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  406.946831] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.947321] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  406.947472] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  406.963079] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  406.963159] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  406.963290] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  406.980032] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  406.980125] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  406.980285] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  406.980456] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  406.984816] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  406.984911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  406.985011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  406.985110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  406.985200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  406.985290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  406.985380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  406.985478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  406.985568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  406.985657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  406.985828] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  406.985935] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  406.986038] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  406.986146] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.986277] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  406.986811] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  406.987243] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  406.987379] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  406.987499] [drm:intel_power_well_disable [i915]] disabling DC off
>[  406.987592] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  406.987673] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  406.989080] [drm:intel_power_well_disable [i915]] disabling always-on
>[  406.990392] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  406.990438] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  406.990694] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  406.990885] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  406.990985] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  406.991076] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  406.991174] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  406.991266] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  406.991362] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  406.991458] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  406.991574] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  406.991588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  406.991676] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  406.991760] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  406.991827] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  406.991895] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  406.991963] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  406.992029] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  406.992101] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  406.992176] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  406.992247] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  406.992320] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  406.992394] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  406.992466] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  406.992540] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  406.992642] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  406.992764] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  406.992841] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  406.993078] [drm:intel_power_well_enable [i915]] enabling always-on
>[  406.993137] [drm:intel_power_well_enable [i915]] enabling DC off
>[  406.993450] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  406.993544] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  406.993612] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  406.993755] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  406.994367] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  406.998601] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  406.998676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  406.998760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  406.998930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  406.998966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  406.999001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  406.999036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  406.999071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  406.999106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  406.999139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  406.999174] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  406.999211] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  406.999248] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  406.999315] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  406.999348] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  406.999601] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  407.000834] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  407.001366] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  407.001399] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  407.001450] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  407.001482] [drm:hsw_audio_config_update [i915]] using automatic N
>[  407.001576] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  407.001610] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  407.018462] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.018534] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.018825] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.019319] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.019473] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  407.035041] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  407.035111] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  407.035225] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  407.051839] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  407.051932] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  407.052090] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  407.052258] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  407.056560] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.056651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.056859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.056963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.057060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.057157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.057253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.057361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.057456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.057550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.057640] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.057795] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.057895] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.057992] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.058128] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  407.058219] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  407.058343] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  407.058471] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.058590] [drm:intel_power_well_disable [i915]] disabling DC off
>[  407.058681] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  407.058818] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  407.059422] [drm:intel_power_well_disable [i915]] disabling always-on
>[  407.060400] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.060445] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  407.060694] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  407.060872] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  407.060970] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  407.061067] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  407.061163] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.061258] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  407.061353] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  407.061448] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  407.061537] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.061554] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.061639] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.061708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.061797] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  407.061886] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  407.061976] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  407.062075] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.062167] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.062270] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  407.062363] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.062462] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  407.062552] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  407.062644] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  407.062778] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  407.062910] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  407.063023] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  407.063115] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  407.063418] [drm:intel_power_well_enable [i915]] enabling always-on
>[  407.063498] [drm:intel_power_well_enable [i915]] enabling DC off
>[  407.063859] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  407.064426] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  407.064472] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  407.064539] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  407.064904] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  407.069144] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.069223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.069261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.069299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.069334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.069369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.069402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.069435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.069470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.069505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.069541] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.069577] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.069614] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.069724] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  407.069761] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  407.070045] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  407.071039] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  407.071571] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  407.071606] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  407.071657] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  407.071727] [drm:hsw_audio_config_update [i915]] using automatic N
>[  407.071822] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  407.071856] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  407.088648] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.088763] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.088960] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.089395] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.089532] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  407.105151] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  407.105205] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  407.105292] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  407.123817] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  407.123893] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  407.124030] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  407.124166] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  407.128392] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.128454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.128517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.128582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.128641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.128790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.128850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.128918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.128976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.129037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.129095] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.129164] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.129230] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.129293] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.129382] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  407.129443] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  407.129527] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  407.129615] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.129744] [drm:intel_power_well_disable [i915]] disabling DC off
>[  407.129806] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  407.129859] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  407.130428] [drm:intel_power_well_disable [i915]] disabling always-on
>[  407.130794] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.130825] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  407.130997] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  407.131056] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  407.131116] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  407.131172] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  407.131232] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.131290] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  407.131349] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  407.131406] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  407.131462] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.131473] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.131527] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.131535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.131592] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  407.131649] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  407.131771] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  407.131829] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.131889] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.131953] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  407.132011] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.132072] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  407.132134] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  407.132194] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  407.132256] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  407.132342] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  407.132420] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  407.132479] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  407.132732] [drm:intel_power_well_enable [i915]] enabling always-on
>[  407.132782] [drm:intel_power_well_enable [i915]] enabling DC off
>[  407.133086] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  407.133168] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  407.133223] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  407.133304] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  407.133606] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  407.137836] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.137897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.137960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.138024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.138084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.138142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.138201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.138259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.138318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.138374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.138432] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.138494] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.138555] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.138650] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  407.138936] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  407.139286] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  407.140761] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  407.141310] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  407.141355] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  407.141422] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  407.141465] [drm:hsw_audio_config_update [i915]] using automatic N
>[  407.141579] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  407.141624] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  407.158323] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.158385] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.158576] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.159144] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.159276] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  407.174971] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  407.175030] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  407.175129] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  407.191669] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  407.191815] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  407.191957] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  407.192106] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  407.196347] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.196413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.196482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.196551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.196614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.196678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.196935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.197007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.197070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.197135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.197198] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.197272] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.197341] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.197410] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.197504] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  407.197568] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  407.197658] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  407.197985] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.198075] [drm:intel_power_well_disable [i915]] disabling DC off
>[  407.198145] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  407.198206] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  407.199393] [drm:intel_power_well_disable [i915]] disabling always-on
>[  407.199816] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.199851] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  407.200046] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  407.200116] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  407.200189] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  407.200255] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  407.200324] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.200393] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  407.200462] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  407.200529] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  407.200594] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.200606] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.200670] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.200768] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.200844] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  407.200922] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  407.200995] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  407.201072] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.201144] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.201225] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  407.201297] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.201373] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  407.201448] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  407.201525] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  407.201600] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  407.201753] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  407.201846] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  407.201920] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  407.202175] [drm:intel_power_well_enable [i915]] enabling always-on
>[  407.202238] [drm:intel_power_well_enable [i915]] enabling DC off
>[  407.202556] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  407.202654] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  407.202794] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  407.202896] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  407.203257] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  407.207558] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.207602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.207647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.207812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.207855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.207897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.207939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.207981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.208024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.208065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.208107] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.208153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.208198] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.208276] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  407.208317] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  407.208593] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  407.209867] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  407.210409] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  407.210451] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  407.210511] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  407.210549] [drm:hsw_audio_config_update [i915]] using automatic N
>[  407.210652] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  407.210738] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  407.227484] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.227546] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.227797] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.228227] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.228428] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  407.244081] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  407.244163] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  407.244289] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  407.260996] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  407.261087] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  407.261245] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  407.261414] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  407.265660] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.265825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.265922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.266019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.266110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.266199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.266286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.266385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.266474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.266562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.266651] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.266834] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.266944] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.267048] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.267180] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  407.267271] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  407.267394] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  407.267522] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.267639] [drm:intel_power_well_disable [i915]] disabling DC off
>[  407.267792] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  407.267881] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  407.268486] [drm:intel_power_well_disable [i915]] disabling always-on
>[  407.269483] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.269528] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  407.269863] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  407.269956] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  407.270054] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  407.270142] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  407.270238] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.270328] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  407.270421] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  407.270510] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  407.270600] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.270614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.270703] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.270770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.270860] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  407.270956] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  407.271051] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  407.271148] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.271247] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.271349] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  407.271442] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.271535] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  407.271633] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  407.271771] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  407.271868] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  407.272003] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  407.272115] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  407.272207] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  407.272510] [drm:intel_power_well_enable [i915]] enabling always-on
>[  407.272588] [drm:intel_power_well_enable [i915]] enabling DC off
>[  407.272983] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  407.273521] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  407.273573] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  407.273649] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  407.274217] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  407.278473] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.278548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.278588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.278626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.278709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.278745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.278783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.278820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.279003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.279036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.279072] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.279111] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.279147] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.279213] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  407.279247] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  407.279499] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  407.280751] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  407.281285] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  407.281320] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  407.281371] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  407.281403] [drm:hsw_audio_config_update [i915]] using automatic N
>[  407.281497] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  407.281530] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  407.298379] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.298451] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.298661] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.299207] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.299358] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  407.314986] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  407.315061] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  407.315182] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  407.331789] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  407.331882] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  407.332040] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  407.332209] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  407.336514] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.336607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.336704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.336908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.337003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.337100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.337192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.337295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.337386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.337480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.337570] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.337677] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.337831] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.337933] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.338062] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  407.338152] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  407.338275] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  407.338403] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.338522] [drm:intel_power_well_disable [i915]] disabling DC off
>[  407.338613] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  407.338694] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  407.339352] [drm:intel_power_well_disable [i915]] disabling always-on
>[  407.340360] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.340405] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  407.340648] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  407.340825] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  407.340923] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  407.341020] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  407.341118] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.341214] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  407.341307] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  407.341402] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  407.341489] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.341503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.341588] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.341600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.341709] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  407.341837] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  407.341922] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  407.342004] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.342095] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.342184] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  407.342270] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.342358] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  407.342447] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  407.342533] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  407.342618] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  407.342781] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  407.342882] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  407.342966] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  407.343234] [drm:intel_power_well_enable [i915]] enabling always-on
>[  407.343303] [drm:intel_power_well_enable [i915]] enabling DC off
>[  407.343625] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  407.343768] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  407.343839] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  407.343935] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  407.344248] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  407.348492] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.348535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.348580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.348626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.348668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.348759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.348803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.348845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.348889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.348932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.348977] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.349025] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.349073] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.349149] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  407.349191] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  407.349468] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  407.350608] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  407.351189] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  407.351231] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  407.351293] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  407.351333] [drm:hsw_audio_config_update [i915]] using automatic N
>[  407.351439] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  407.351479] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  407.368241] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.368319] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.368536] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.369115] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.369276] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  407.384857] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  407.384936] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  407.385056] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  407.401681] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  407.401844] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  407.402002] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  407.402171] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  407.406436] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.406520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.406607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.406696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.407007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.407093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.407175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.407270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.407352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.407437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.407518] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.407614] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.407964] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.408066] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.408195] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  407.408287] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  407.408410] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  407.408540] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.408656] [drm:intel_power_well_disable [i915]] disabling DC off
>[  407.408981] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  407.409063] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  407.409671] [drm:intel_power_well_disable [i915]] disabling always-on
>[  407.410607] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.410865] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  407.411122] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  407.411211] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  407.411303] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  407.411388] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  407.411477] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.411565] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  407.411653] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  407.412002] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  407.412091] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.412105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.412193] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.412205] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.412294] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  407.412386] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  407.412475] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  407.412568] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.412657] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.413011] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  407.413102] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.413193] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  407.413282] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  407.413372] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  407.413462] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  407.413595] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  407.413708] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  407.413951] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  407.414154] [drm:intel_power_well_enable [i915]] enabling always-on
>[  407.414204] [drm:intel_power_well_enable [i915]] enabling DC off
>[  407.414509] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  407.414591] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  407.414651] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  407.414880] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  407.415228] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  407.419482] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.419559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.419598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.419636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.419774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.419809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.419844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.419878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.419914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.419950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.419986] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.420024] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.420061] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.420131] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  407.420165] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  407.420417] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  407.421509] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  407.422083] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  407.422117] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  407.422169] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  407.422203] [drm:hsw_audio_config_update [i915]] using automatic N
>[  407.422298] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  407.422332] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  407.439176] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.439250] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.439460] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.440031] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.440184] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  407.455747] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  407.455818] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  407.455932] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  407.472560] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  407.472650] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  407.473025] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  407.473196] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  407.477501] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.477594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.477691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.478038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.478131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.478225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.478317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.478420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.478512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.478606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.478698] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.479029] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.479132] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.479229] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.479361] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  407.479454] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  407.479580] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  407.479710] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.480058] [drm:intel_power_well_disable [i915]] disabling DC off
>[  407.480148] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  407.480228] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  407.481438] [drm:intel_power_well_disable [i915]] disabling always-on
>[  407.482564] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.482610] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  407.483079] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  407.483170] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  407.483264] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  407.483349] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  407.483438] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.483525] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  407.483614] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  407.483699] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  407.484049] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.484065] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.484154] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.484167] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.484255] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  407.484347] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  407.484437] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  407.484529] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.484618] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.484729] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  407.485008] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.485083] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  407.485158] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  407.485229] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  407.485305] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  407.485413] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  407.485507] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  407.485582] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  407.486031] [drm:intel_power_well_enable [i915]] enabling always-on
>[  407.486095] [drm:intel_power_well_enable [i915]] enabling DC off
>[  407.486416] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  407.486518] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  407.486588] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  407.486869] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  407.487263] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  407.491535] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.491609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.491647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.491787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.491823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.491858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.491893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.491929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.491964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.491999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.492034] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.492073] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.492112] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.492179] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  407.492213] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  407.492503] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  407.493596] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  407.494171] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  407.494206] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  407.494258] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  407.494292] [drm:hsw_audio_config_update [i915]] using automatic N
>[  407.494388] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  407.494421] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  407.511262] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.511336] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.511546] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.512174] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.512325] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  407.527852] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  407.527924] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  407.528038] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  407.544666] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  407.544820] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  407.544969] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  407.545125] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  407.549368] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.549439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.549512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.549587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.549655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.549923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.549994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.550072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.550141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.550211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.550279] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.550359] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.550435] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.550511] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.550613] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  407.550941] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  407.551055] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  407.551175] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.551283] [drm:intel_power_well_disable [i915]] disabling DC off
>[  407.551366] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  407.551441] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  407.552641] [drm:intel_power_well_disable [i915]] disabling always-on
>[  407.553546] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.553586] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  407.553903] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  407.553985] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  407.554074] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  407.554153] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  407.554240] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.554322] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  407.554405] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  407.554485] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  407.554566] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.554579] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.554656] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.554747] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.554831] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  407.554912] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  407.554995] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  407.555077] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.555159] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.555245] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  407.555329] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.555410] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  407.555494] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  407.555575] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  407.555659] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  407.555826] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  407.555927] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  407.556008] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  407.556284] [drm:intel_power_well_enable [i915]] enabling always-on
>[  407.556352] [drm:intel_power_well_enable [i915]] enabling DC off
>[  407.556679] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  407.557310] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  407.557361] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  407.557437] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  407.557778] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  407.562036] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.562110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.562149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.562188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.562223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.562258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.562293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.562328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.562363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.562396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.562431] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.562467] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.562503] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.562569] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  407.562601] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  407.562940] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  407.563941] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  407.564473] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  407.564508] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  407.564559] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  407.564591] [drm:hsw_audio_config_update [i915]] using automatic N
>[  407.564723] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  407.564757] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  407.581520] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.581594] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.581891] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.582378] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.582530] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  407.598152] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  407.598226] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  407.598341] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  407.615024] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  407.615114] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  407.615273] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  407.615441] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  407.619696] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.619840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.619920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.620002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.620078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.620151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.620226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.620306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.620380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.620454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.620527] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.620608] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.620687] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.621028] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.621135] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  407.621211] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  407.621314] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  407.621422] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.621520] [drm:intel_power_well_disable [i915]] disabling DC off
>[  407.621596] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  407.621662] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  407.622563] [drm:intel_power_well_disable [i915]] disabling always-on
>[  407.623728] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.623774] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  407.624027] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  407.624116] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  407.624209] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  407.624294] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  407.624383] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.624472] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  407.624560] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  407.624645] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  407.624829] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.624844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.624931] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.624949] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.625039] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  407.625128] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  407.625223] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  407.625313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.625404] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.625500] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  407.625592] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.625682] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  407.625829] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  407.625912] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  407.625996] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  407.626111] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  407.626211] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  407.626295] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  407.626570] [drm:intel_power_well_enable [i915]] enabling always-on
>[  407.626640] [drm:intel_power_well_enable [i915]] enabling DC off
>[  407.627034] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  407.627148] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  407.627225] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  407.627338] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  407.627695] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  407.631997] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.632033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.632072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.632110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.632146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.632181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.632216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.632249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.632286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.632319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.632355] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.632392] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.632427] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.632493] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  407.632525] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  407.632908] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  407.633946] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  407.634479] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  407.634514] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  407.634566] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  407.634598] [drm:hsw_audio_config_update [i915]] using automatic N
>[  407.634794] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  407.634828] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  407.651557] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.651614] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.651861] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.652278] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.652401] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  407.668160] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  407.668217] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  407.668313] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  407.684927] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  407.685012] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  407.685162] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  407.685319] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  407.689558] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.689628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.689777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.689849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.689915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.689979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.690045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.690115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.690182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.690245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.690310] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.690382] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.690452] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.690522] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.690618] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  407.690737] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  407.690829] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  407.690925] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.691008] [drm:intel_power_well_disable [i915]] disabling DC off
>[  407.691073] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  407.691130] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  407.691771] [drm:intel_power_well_disable [i915]] disabling always-on
>[  407.692561] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.692594] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  407.692845] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  407.692909] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  407.692978] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  407.693041] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  407.693108] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.693171] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  407.693235] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  407.693297] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  407.693360] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.693371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.693432] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.693441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.693504] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  407.693567] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  407.693631] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  407.693752] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.693817] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.693887] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  407.693954] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.694021] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  407.694089] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  407.694153] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  407.694217] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  407.694307] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  407.694393] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  407.694460] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  407.694740] [drm:intel_power_well_enable [i915]] enabling always-on
>[  407.694793] [drm:intel_power_well_enable [i915]] enabling DC off
>[  407.695105] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  407.695192] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  407.695252] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  407.695342] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  407.695688] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  407.700037] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.700082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.700129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.700177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.700221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.700265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.700311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.700354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.700397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.700441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.700486] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.700532] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.700577] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.700654] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  407.700755] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  407.701043] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  407.702259] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  407.702867] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  407.702912] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  407.702977] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  407.703020] [drm:hsw_audio_config_update [i915]] using automatic N
>[  407.703132] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  407.703176] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  407.719941] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.720016] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.720226] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.720936] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.721111] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  407.736542] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  407.736622] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  407.736896] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  407.753571] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  407.753675] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  407.754372] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  407.754580] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  407.758844] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.758936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.759033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.759132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.759223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.759313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.759402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.759501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.759590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.759680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.759892] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.760003] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.760107] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.760566] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.760699] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  407.760860] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  407.760989] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  407.761427] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.761551] [drm:intel_power_well_disable [i915]] disabling DC off
>[  407.761643] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  407.761803] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  407.762424] [drm:intel_power_well_disable [i915]] disabling always-on
>[  407.763424] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.763470] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  407.763720] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  407.763911] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  407.763992] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  407.764071] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  407.764148] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.764226] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  407.764297] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  407.764372] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  407.764445] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.764460] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.764530] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.764542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.764616] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  407.764690] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  407.764819] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  407.764901] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.764976] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.765061] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  407.765136] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.765219] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  407.765297] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  407.765375] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  407.765453] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  407.765561] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  407.765655] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  407.765770] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  407.766024] [drm:intel_power_well_enable [i915]] enabling always-on
>[  407.766088] [drm:intel_power_well_enable [i915]] enabling DC off
>[  407.766409] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  407.766510] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  407.766581] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  407.766685] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  407.767100] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  407.771369] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.771446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.771484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.771523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.771558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.771593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.771628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.771713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.771750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.771787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.771822] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.771862] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.771901] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.771968] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  407.772003] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  407.772254] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  407.773258] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  407.773829] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  407.773865] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  407.773916] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  407.773951] [drm:hsw_audio_config_update [i915]] using automatic N
>[  407.774047] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  407.774082] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  407.790854] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.790927] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.791136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.791614] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.791961] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  407.807495] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  407.807567] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  407.807921] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  407.824551] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  407.824642] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  407.824894] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  407.825066] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  407.829313] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.829389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.829469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.829550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.829625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.829699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.829857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.829944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.830021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.830098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.830175] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.830260] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.830338] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.830417] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.830523] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  407.830599] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  407.830815] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  407.830955] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.831072] [drm:intel_power_well_disable [i915]] disabling DC off
>[  407.831163] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  407.831241] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  407.831905] [drm:intel_power_well_disable [i915]] disabling always-on
>[  407.832855] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.832903] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  407.833149] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  407.833240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  407.833335] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  407.833423] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  407.833515] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.833605] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  407.833696] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  407.833866] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  407.833957] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.833980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.834067] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.834083] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.834176] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  407.834268] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  407.834365] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  407.834460] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.834556] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.834658] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  407.834793] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.834885] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  407.834978] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  407.835077] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  407.835172] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  407.835300] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  407.835421] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  407.835463] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  407.835623] [drm:intel_power_well_enable [i915]] enabling always-on
>[  407.835659] [drm:intel_power_well_enable [i915]] enabling DC off
>[  407.835983] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  407.836046] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  407.836090] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  407.836153] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  407.836414] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  407.840653] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.840731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.840775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.840821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.840863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.840903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.840944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.840984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.841025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.841065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.841107] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.841151] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.841193] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.841268] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  407.841307] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  407.841578] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  407.842739] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  407.843281] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  407.843322] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  407.843383] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  407.843422] [drm:hsw_audio_config_update [i915]] using automatic N
>[  407.843525] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  407.843565] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  407.860310] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.860387] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.860604] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.861174] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.861335] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  407.876952] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  407.877031] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  407.877160] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  407.893870] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  407.893970] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  407.894138] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  407.894320] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  407.898581] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.898664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.898852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.898942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.899025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.899104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.899189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.899280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.899364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.899446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.899530] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.899624] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.899743] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.899834] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.899949] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  407.900055] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  407.900176] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  407.900303] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.900418] [drm:intel_power_well_disable [i915]] disabling DC off
>[  407.900506] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  407.900590] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  407.901260] [drm:intel_power_well_disable [i915]] disabling always-on
>[  407.902201] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.902246] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  407.902489] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  407.902577] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  407.902670] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  407.902847] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  407.902939] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.903035] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  407.903128] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  407.903222] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  407.903313] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.903334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.903421] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.903439] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.903529] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  407.903626] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  407.903732] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  407.903827] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.903919] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.904020] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  407.904106] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.904199] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  407.904288] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  407.904379] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  407.904470] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  407.904599] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  407.904707] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  407.904849] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  407.905142] [drm:intel_power_well_enable [i915]] enabling always-on
>[  407.905217] [drm:intel_power_well_enable [i915]] enabling DC off
>[  407.905553] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  407.905673] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  407.905828] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  407.905890] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  407.906149] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  407.910389] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.910431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.910477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.910523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.910564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.910605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.910646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.910739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.910782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.910825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.910868] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.910917] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.910964] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.911039] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  407.911080] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  407.911353] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  407.912488] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  407.913068] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  407.913110] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  407.913173] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  407.913212] [drm:hsw_audio_config_update [i915]] using automatic N
>[  407.913317] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  407.913358] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  407.930136] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.930194] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.930377] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.930939] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.931101] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  407.946798] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  407.946877] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  407.947008] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  407.963606] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  407.963705] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  407.963979] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  407.964167] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  407.967872] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.967955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.968043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.968133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.968212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.968295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.968376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.968463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.968544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.968624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.968704] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  407.968884] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.968976] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.969067] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.969187] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  407.969270] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  407.969380] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  407.969494] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  407.969629] [drm:intel_power_well_disable [i915]] disabling DC off
>[  407.969777] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  407.969866] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  407.970471] [drm:intel_power_well_disable [i915]] disabling always-on
>[  407.971449] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  407.971495] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  407.971824] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  407.971914] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  407.972009] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  407.972097] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  407.972192] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.972283] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  407.972375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  407.972464] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  407.972554] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.972568] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.972657] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.972732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  407.972829] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  407.972921] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  407.973019] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  407.973111] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.973204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.973302] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  407.973398] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.973492] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  407.973588] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  407.973683] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  407.973809] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  407.973937] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  407.974055] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  407.974150] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  407.974450] [drm:intel_power_well_enable [i915]] enabling always-on
>[  407.974525] [drm:intel_power_well_enable [i915]] enabling DC off
>[  407.974934] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  407.975499] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  407.975589] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  407.975765] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  407.976188] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  407.980465] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  407.980539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  407.980576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  407.980615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  407.980650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  407.980727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  407.980761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  407.980798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  407.980834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  407.980871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  407.980907] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  407.980947] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  407.980983] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  407.981049] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  407.981082] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  407.981367] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  407.982360] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  407.982924] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  407.982959] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  407.983012] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  407.983045] [drm:hsw_audio_config_update [i915]] using automatic N
>[  407.983135] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  407.983170] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  408.000008] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.000058] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  408.000225] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.000579] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  408.000797] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  408.016588] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  408.016657] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.016890] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  408.033507] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  408.033597] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  408.033876] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  408.034061] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  408.038321] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.038405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.038491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.038581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.038662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.038838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.038922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.039019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.039099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.039180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.039260] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.039353] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.039445] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.039532] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.039652] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  408.039792] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  408.039909] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  408.040030] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  408.040133] [drm:intel_power_well_disable [i915]] disabling DC off
>[  408.040213] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  408.040285] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  408.040927] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.041856] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  408.041897] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  408.042122] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  408.042205] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.042290] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  408.042370] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  408.042453] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.042534] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  408.042614] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  408.042694] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  408.042851] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.042870] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.042948] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.042966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.043052] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  408.043135] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  408.043221] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  408.043306] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.043393] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  408.043481] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  408.043565] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.043650] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  408.043774] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  408.043857] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  408.043947] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  408.044067] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  408.044168] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  408.044250] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  408.044524] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.044592] [drm:intel_power_well_enable [i915]] enabling DC off
>[  408.044969] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  408.045556] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  408.045636] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  408.045798] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  408.046185] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  408.050429] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.050504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.050542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.050581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.050616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.050651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.050730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.050766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.050804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.050840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.050878] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.050916] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.050952] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.051017] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  408.051052] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  408.051339] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  408.052334] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  408.052899] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  408.052935] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  408.052987] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  408.053021] [drm:hsw_audio_config_update [i915]] using automatic N
>[  408.053111] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  408.053145] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  408.069974] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.070045] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  408.070253] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.070809] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  408.070964] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  408.086574] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  408.086645] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.086896] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  408.103529] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  408.103620] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  408.103871] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  408.104040] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  408.108290] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.108367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.108446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.108528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.108602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.108675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.108842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.108930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.109007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.109086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.109163] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.109254] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.109333] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.109413] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.109518] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  408.109595] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  408.109796] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  408.109934] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  408.110049] [drm:intel_power_well_disable [i915]] disabling DC off
>[  408.110138] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  408.110217] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  408.110877] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.111843] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  408.111890] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  408.112143] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  408.112232] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.112325] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  408.112410] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  408.112499] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.112588] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  408.112676] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  408.112853] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  408.112949] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.112966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.113060] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.113078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.113171] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  408.113266] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  408.113362] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  408.113457] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.113548] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  408.113646] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  408.113785] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.113879] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  408.113974] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  408.114067] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  408.114163] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  408.114297] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  408.114406] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  408.114496] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  408.114859] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.114935] [drm:intel_power_well_enable [i915]] enabling DC off
>[  408.115268] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  408.115388] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  408.115477] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  408.115598] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  408.115916] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  408.120164] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.120208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.120253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.120299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.120340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.120382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.120424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.120465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.120507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.120546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.120588] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.120632] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.120732] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.120812] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  408.120853] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  408.121128] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  408.122271] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  408.122852] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  408.122895] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  408.122956] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  408.122995] [drm:hsw_audio_config_update [i915]] using automatic N
>[  408.123095] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  408.123136] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  408.139914] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.139974] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  408.140164] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.140588] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  408.140839] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  408.156557] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  408.156638] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.156849] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  408.173506] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  408.173597] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  408.173881] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  408.174065] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  408.178328] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.178412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.178499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.178590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.178672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.178852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.178936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.179035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.179115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.179197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.179276] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.179372] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.179464] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.179554] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.179675] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  408.179851] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  408.179978] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  408.180116] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  408.180231] [drm:intel_power_well_disable [i915]] disabling DC off
>[  408.180320] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  408.180400] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  408.181059] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.181984] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  408.182031] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  408.182284] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  408.182373] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.182466] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  408.182550] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  408.182639] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.182823] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  408.182919] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  408.183010] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  408.183104] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.183123] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.183211] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.183227] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.183317] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  408.183414] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  408.183507] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  408.183604] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.183698] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  408.183848] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  408.183937] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.184033] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  408.184125] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  408.184222] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  408.184316] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  408.184454] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  408.184564] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  408.184653] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  408.185016] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.185091] [drm:intel_power_well_enable [i915]] enabling DC off
>[  408.185425] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  408.185547] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  408.185632] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  408.185824] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  408.186109] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  408.190352] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.190395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.190440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.190486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.190528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.190570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.190610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.190650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.190744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.190787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.190829] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.190877] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.190924] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.190998] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  408.191039] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  408.191318] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  408.192463] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  408.193046] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  408.193089] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  408.193150] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  408.193191] [drm:hsw_audio_config_update [i915]] using automatic N
>[  408.193296] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  408.193338] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  408.210102] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.210169] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  408.210372] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.210895] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  408.211043] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  408.226749] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  408.226814] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.226917] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  408.243513] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  408.243596] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  408.243831] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  408.244015] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  408.248269] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.248345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.248424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.248506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.248578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.248652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.248818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.248907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.248984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.249063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.249138] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.249226] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.249309] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.249389] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.249500] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  408.249577] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  408.249681] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  408.249841] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  408.249943] [drm:intel_power_well_disable [i915]] disabling DC off
>[  408.250018] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  408.250085] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  408.250667] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.251555] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  408.251594] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  408.251879] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  408.251956] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.252037] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  408.252110] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  408.252188] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.252262] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  408.252338] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  408.252410] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  408.252485] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.252497] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.252569] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.252580] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.252654] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  408.252775] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  408.252857] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  408.252932] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.253013] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  408.253097] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  408.253175] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.253248] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  408.253328] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  408.253405] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  408.253483] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  408.253595] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  408.253688] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  408.253808] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  408.254066] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.254130] [drm:intel_power_well_enable [i915]] enabling DC off
>[  408.254448] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  408.254547] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  408.254621] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  408.254764] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  408.255083] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  408.259326] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.259372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.259419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.259467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.259511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.259555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.259597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.259639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.259741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.259787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.259832] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.259882] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.259932] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.260010] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  408.260054] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  408.260336] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  408.261547] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  408.262152] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  408.262197] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  408.262261] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  408.262304] [drm:hsw_audio_config_update [i915]] using automatic N
>[  408.262408] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  408.262453] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  408.279216] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.279287] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  408.279495] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.280044] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  408.280198] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  408.295824] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  408.295902] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.296022] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  408.312645] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  408.312788] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  408.312938] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  408.313094] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  408.317336] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.317406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.317482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.317557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.317625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.317692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.317848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.317930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.317999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.318069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.318137] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.318218] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.318292] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.318367] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.318470] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  408.318540] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  408.318634] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  408.318831] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  408.318938] [drm:intel_power_well_disable [i915]] disabling DC off
>[  408.319022] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  408.319098] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  408.319688] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.320604] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  408.320730] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  408.320962] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  408.321047] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.321130] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  408.321206] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  408.321289] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.321370] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  408.321451] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  408.321530] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  408.321609] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.321621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.321697] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.321782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.321870] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  408.321954] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  408.322045] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  408.322129] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.322217] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  408.322305] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  408.322392] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.322477] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  408.322564] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  408.322648] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  408.322773] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  408.322891] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  408.322996] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  408.323079] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  408.323357] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.323427] [drm:intel_power_well_enable [i915]] enabling DC off
>[  408.323815] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  408.324394] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  408.324457] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  408.324550] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  408.324914] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  408.329163] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.329206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.329251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.329297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.329339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.329381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.329422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.329464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.329505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.329547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.329588] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.329632] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.329729] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.329805] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  408.329845] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  408.330126] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  408.331268] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  408.331850] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  408.331893] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  408.331954] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  408.331995] [drm:hsw_audio_config_update [i915]] using automatic N
>[  408.332096] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  408.332137] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  408.348913] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.348980] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  408.349182] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.349746] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  408.349912] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  408.365522] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  408.365601] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.365838] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  408.382519] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  408.382619] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  408.382901] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  408.383088] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  408.387358] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.387440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.387528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.387617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.387699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.387883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.387969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.388058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.388143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.388225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.388309] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.388403] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.388495] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.388582] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.388769] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  408.388857] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  408.388968] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  408.389084] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  408.389191] [drm:intel_power_well_disable [i915]] disabling DC off
>[  408.389271] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  408.389345] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  408.389994] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.391368] [drm:drm_mode_addfb2] [FB:71]
>[  408.391495] [drm:drm_mode_addfb2] [FB:91]
>[  408.449359] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  408.449968] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  408.450406] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  408.451164] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  408.451184] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  408.451288] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  408.451321] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.451358] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  408.451390] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  408.451424] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.451458] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  408.451493] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  408.451525] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  408.451559] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.451564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.451596] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.451599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.451632] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  408.452270] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  408.452303] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  408.452339] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.452371] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  408.452410] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  408.452442] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.452477] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  408.452511] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  408.452545] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  408.452579] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  408.452628] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  408.453192] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  408.453226] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  408.453564] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.453593] [drm:intel_power_well_enable [i915]] enabling DC off
>[  408.454100] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  408.454496] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  408.454529] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  408.454582] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  408.455045] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  408.459278] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.459351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.459389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.459428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.459464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.459499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.459533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.459569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.459604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.459639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.459791] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.459830] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.459867] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.459931] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  408.459966] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  408.460252] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  408.461304] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  408.461951] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  408.461988] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  408.462044] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  408.462081] [drm:hsw_audio_config_update [i915]] using automatic N
>[  408.479005] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.479059] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  408.479233] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.495582] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  408.495610] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  408.512511] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  408.512704] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  408.528976] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  408.529069] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.529210] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  408.545966] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  408.546151] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  408.546355] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  408.550636] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.550801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.550899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.550998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.551089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.551179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.551268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.551366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.551456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.551544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.551633] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.551825] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.551932] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.552033] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.552165] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  408.552255] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  408.552377] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  408.552501] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  408.552595] [drm:intel_power_well_disable [i915]] disabling DC off
>[  408.552683] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  408.552867] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  408.553481] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.554529] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  408.554580] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  408.554950] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  408.555054] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.555158] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  408.555261] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  408.555365] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.555470] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  408.555571] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  408.555674] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  408.555841] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.555866] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.555970] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.555987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.556095] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  408.556199] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  408.556309] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  408.556413] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.556520] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  408.556630] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  408.556785] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.556887] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  408.557001] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  408.557107] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  408.557214] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  408.557353] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  408.557475] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  408.557576] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  408.557906] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.557945] [drm:intel_power_well_enable [i915]] enabling DC off
>[  408.558238] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  408.558300] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  408.558344] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  408.558414] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  408.558738] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  408.562937] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.562973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.563011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.563049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.563085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.563120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.563154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.563187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.563224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.563257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.563293] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.563329] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.563365] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.563431] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  408.563463] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  408.563789] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  408.564775] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  408.565307] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  408.565342] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  408.565393] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  408.565425] [drm:hsw_audio_config_update [i915]] using automatic N
>[  408.582379] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.582441] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  408.582634] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.583311] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  408.583463] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  408.599008] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  408.599084] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.599222] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  408.615957] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  408.616109] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  408.616266] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  408.620509] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.620579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.620652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.620919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.620988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.621059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.621127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.621204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.621274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.621344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.621412] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.621492] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.621567] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.621642] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.622009] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  408.622090] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  408.622201] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  408.622315] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  408.622402] [drm:intel_power_well_disable [i915]] disabling DC off
>[  408.622484] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  408.622556] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  408.623796] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.624865] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  408.624907] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  408.625135] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  408.625215] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.625300] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  408.625377] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  408.625457] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.625535] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  408.625615] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  408.625692] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  408.625861] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.625874] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.625957] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.625968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.626054] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  408.626134] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  408.626220] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  408.626301] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.626385] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  408.626474] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  408.626556] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.626639] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  408.626764] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  408.626847] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  408.626933] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  408.627047] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  408.627147] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  408.627235] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  408.627505] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.627575] [drm:intel_power_well_enable [i915]] enabling DC off
>[  408.627967] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  408.628520] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  408.628588] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  408.628735] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  408.629052] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  408.633253] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.633290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.633329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.633368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.633403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.633438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.633473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.633508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.633543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.633576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.633611] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.633648] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.633739] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.633807] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  408.633843] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  408.634101] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  408.635105] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  408.635638] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  408.635710] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  408.635763] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  408.635797] [drm:hsw_audio_config_update [i915]] using automatic N
>[  408.652772] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.652847] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  408.653058] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.653516] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  408.653664] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  408.669261] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  408.669330] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.669460] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  408.685984] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  408.686149] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  408.686320] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  408.690596] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.690682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.690890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.690983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.691067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.691151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.691233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.691326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.691409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.691494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.691575] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.691671] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.691806] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.691894] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.692017] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  408.692100] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  408.692214] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  408.692333] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  408.692422] [drm:intel_power_well_disable [i915]] disabling DC off
>[  408.692505] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  408.692579] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  408.693244] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.694157] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  408.694198] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  408.694430] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  408.694512] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.694596] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  408.694672] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  408.694848] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.694933] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  408.695019] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  408.695106] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  408.695186] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.695202] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.695284] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.695301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.695385] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  408.695472] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  408.695558] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  408.695640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.695771] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  408.695858] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  408.695937] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.696019] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  408.696102] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  408.696183] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  408.696271] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  408.696393] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  408.696496] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  408.696579] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  408.696886] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.696930] [drm:intel_power_well_enable [i915]] enabling DC off
>[  408.697228] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  408.697298] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  408.697349] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  408.697426] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  408.697800] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  408.702050] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.702093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.702138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.702184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.702226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.702267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.702309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.702350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.702392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.702432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.702474] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.702517] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.702560] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.702634] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  408.702733] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  408.703124] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  408.704283] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  408.704867] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  408.704908] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  408.704969] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  408.705009] [drm:hsw_audio_config_update [i915]] using automatic N
>[  408.721927] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.721996] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  408.722201] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.722721] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  408.722866] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  408.738566] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  408.738646] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.738890] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  408.755533] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  408.755683] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  408.755926] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  408.760185] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.760269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.760356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.760445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.760526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.760607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.760687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.760878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.760964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.761045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.761125] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.761218] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.761304] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.761395] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.761514] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  408.761597] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  408.761766] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  408.761889] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  408.761980] [drm:intel_power_well_disable [i915]] disabling DC off
>[  408.762060] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  408.762130] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  408.762775] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.763624] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  408.763748] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  408.763976] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  408.764056] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.764140] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  408.764217] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  408.764300] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.764382] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  408.764464] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  408.764543] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  408.764622] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.764634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.764782] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.764801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.764882] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  408.764968] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  408.765056] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  408.765139] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.765226] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  408.765313] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  408.765400] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.765487] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  408.765574] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  408.765659] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  408.765782] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  408.765898] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  408.765998] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  408.766082] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  408.766356] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.766423] [drm:intel_power_well_enable [i915]] enabling DC off
>[  408.766769] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  408.766832] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  408.766872] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  408.766936] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  408.767203] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  408.771446] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.771489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.771535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.771581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.771623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.771664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.771757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.771799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.771843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.771886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.771929] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.771977] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.772020] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.772094] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  408.772134] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  408.772410] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  408.773603] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  408.774189] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  408.774232] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  408.774293] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  408.774334] [drm:hsw_audio_config_update [i915]] using automatic N
>[  408.791213] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.791290] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  408.791506] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.792085] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  408.792247] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  408.807884] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  408.807964] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.808081] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  408.824627] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  408.824822] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  408.824967] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  408.829198] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.829262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.829329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.829398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.829461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.829524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.829585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.829654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.829797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.829863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.829931] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.830007] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.830079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.830147] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.830242] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  408.830308] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  408.830395] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  408.830485] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  408.830554] [drm:intel_power_well_disable [i915]] disabling DC off
>[  408.830618] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  408.830695] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  408.831341] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.832320] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  408.832362] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  408.832585] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  408.832665] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.832834] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  408.832918] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  408.833006] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.833094] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  408.833179] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  408.833265] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  408.833347] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.833364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.833443] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.833456] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.833541] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  408.833622] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  408.833727] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  408.833806] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.833886] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  408.833972] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  408.834061] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.834144] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  408.834233] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  408.834318] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  408.834405] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  408.834526] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  408.834627] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  408.834764] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  408.835033] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.835103] [drm:intel_power_well_enable [i915]] enabling DC off
>[  408.835428] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  408.835535] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  408.835615] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  408.835802] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  408.836514] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  408.840793] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.840836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.840882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.840929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.840971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.841013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.841054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.841096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.841137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.841179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.841219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.841265] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.841307] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.841382] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  408.841421] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  408.841749] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  408.843102] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  408.843648] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  408.843732] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  408.843973] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  408.844013] [drm:hsw_audio_config_update [i915]] using automatic N
>[  408.860752] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.860818] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  408.861016] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.861440] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  408.861571] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  408.877360] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  408.877446] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.877568] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  408.894147] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  408.894311] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  408.894481] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  408.898720] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.898883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.898975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.899065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.899146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.899227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.899308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.899395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.899477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.899557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.899635] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.899817] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.899906] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.899997] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.900119] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  408.900202] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  408.900314] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  408.900431] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  408.900519] [drm:intel_power_well_disable [i915]] disabling DC off
>[  408.900602] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  408.900676] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  408.901338] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.902295] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  408.902337] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  408.902567] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  408.902647] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.902818] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  408.902901] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  408.902985] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.903069] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  408.903152] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  408.903236] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  408.903319] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.903334] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.903413] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.903429] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.903510] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  408.903593] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  408.903677] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  408.903797] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.903883] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  408.903973] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  408.904056] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.904112] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  408.904170] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  408.904226] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  408.904284] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  408.904369] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  408.904446] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  408.904507] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  408.904774] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.904828] [drm:intel_power_well_enable [i915]] enabling DC off
>[  408.905140] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  408.905218] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  408.905275] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  408.905362] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  408.905670] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  408.910031] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.910074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.910121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.910167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.910209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.910251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.910292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.910334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.910375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.910417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.910458] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.910502] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.910544] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.910618] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  408.910659] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  408.911398] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  408.912729] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  408.913273] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  408.913314] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  408.913374] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  408.913413] [drm:hsw_audio_config_update [i915]] using automatic N
>[  408.930352] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.930421] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  408.930626] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.931456] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  408.931617] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  408.946952] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  408.947034] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  408.947157] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  408.963919] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  408.964104] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  408.964307] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  408.968604] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.968696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.969153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.969257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.969347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.969437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.969527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.969626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.970252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.970344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.970434] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  408.970540] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.970639] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.971246] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.971378] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  408.971468] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  408.971588] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  408.972152] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  408.972256] [drm:intel_power_well_disable [i915]] disabling DC off
>[  408.972348] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  408.972432] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  408.973807] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.974965] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  408.975014] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  408.975269] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  408.975360] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.975452] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  408.975537] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  408.975626] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.976297] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  408.976389] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  408.976478] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  408.976567] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.976579] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.976667] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.977272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  408.977374] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  408.977460] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  408.977547] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  408.977633] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.978216] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  408.978313] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  408.978401] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.978494] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  408.978581] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  408.978671] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  408.979369] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  408.979496] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  408.979546] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  408.979580] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  408.979923] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.979953] [drm:intel_power_well_enable [i915]] enabling DC off
>[  408.980239] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  408.980286] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  408.980322] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  408.980374] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  408.980606] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  408.984738] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  408.984776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  408.984815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  408.984854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  408.984890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  408.984925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  408.984959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  408.984995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  408.985029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  408.985064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  408.985099] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  408.985135] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  408.985171] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  408.985237] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  408.985272] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  408.985556] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  408.987072] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  408.987606] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  408.987641] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  408.987845] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  408.987878] [drm:hsw_audio_config_update [i915]] using automatic N
>[  409.004753] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.004827] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.005039] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.005522] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.005670] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  409.021278] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  409.021350] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.021458] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  409.037978] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  409.038116] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  409.038255] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  409.042503] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.042563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.042628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.042963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.043023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.043081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.043140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.043205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.043263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.043321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.043379] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.043446] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.043507] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.043568] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.043655] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  409.044382] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  409.044465] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  409.044556] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.044621] [drm:intel_power_well_disable [i915]] disabling DC off
>[  409.045061] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  409.045130] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  409.046328] [drm:intel_power_well_disable [i915]] disabling always-on
>[  409.047389] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.047428] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  409.047640] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  409.048039] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.048119] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  409.048191] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  409.048266] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.048342] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  409.048415] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  409.048487] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  409.048561] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.048574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.048643] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.049380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.049463] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  409.049534] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  409.049605] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  409.049679] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.050163] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  409.050242] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  409.050315] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.050391] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  409.050464] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  409.050538] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  409.050612] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  409.051279] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  409.051376] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  409.051448] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  409.052013] [drm:intel_power_well_enable [i915]] enabling always-on
>[  409.052078] [drm:intel_power_well_enable [i915]] enabling DC off
>[  409.052398] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  409.052492] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  409.052560] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  409.052663] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  409.053282] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  409.057516] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.057589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.057627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.057855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.057890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.057925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.057960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.057995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.058029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.058064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.058100] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.058136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.058172] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.058240] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  409.058275] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  409.058528] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  409.059955] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  409.060490] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  409.060524] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  409.060576] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  409.060608] [drm:hsw_audio_config_update [i915]] using automatic N
>[  409.077579] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.077652] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.078098] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.078584] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.078961] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  409.094181] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  409.094275] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.094430] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  409.111129] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  409.111291] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  409.111462] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  409.115809] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.115895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.115985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.116074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.116156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.116236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.116317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.116406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.116486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.116565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.116646] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.117591] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.117680] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.118045] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.118167] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  409.118249] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  409.118361] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  409.118478] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.118563] [drm:intel_power_well_disable [i915]] disabling DC off
>[  409.118644] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  409.119302] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  409.120505] [drm:intel_power_well_disable [i915]] disabling always-on
>[  409.121487] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.121528] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  409.121845] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  409.121929] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.122019] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  409.122096] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  409.122184] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.122266] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  409.122349] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  409.122429] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  409.122508] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.122519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.122601] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.122613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.122709] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  409.122851] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  409.122930] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  409.123010] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.123088] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  409.123173] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  409.123248] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.123329] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  409.123407] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  409.123484] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  409.123560] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  409.123671] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  409.123809] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  409.123888] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  409.124152] [drm:intel_power_well_enable [i915]] enabling always-on
>[  409.124216] [drm:intel_power_well_enable [i915]] enabling DC off
>[  409.124534] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  409.124632] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  409.124778] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  409.124887] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  409.125226] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  409.129494] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.129570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.129608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.129647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.129731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.129766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.129801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.129837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.129871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.129907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.129942] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.129982] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.130020] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.130087] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  409.130122] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  409.130375] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  409.131375] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  409.131942] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  409.131977] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  409.132031] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  409.132063] [drm:hsw_audio_config_update [i915]] using automatic N
>[  409.149026] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.149099] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.149310] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.149856] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.150008] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  409.165604] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  409.165672] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.165911] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  409.182547] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  409.182833] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  409.183015] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  409.187273] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.187356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.187443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.187533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.187614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.187695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.187874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.187972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.188054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.188135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.188217] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.188314] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.188403] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.188493] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.188608] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  409.188692] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  409.188861] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  409.188976] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.189064] [drm:intel_power_well_disable [i915]] disabling DC off
>[  409.189146] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  409.189218] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  409.189861] [drm:intel_power_well_disable [i915]] disabling always-on
>[  409.190773] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.190813] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  409.191033] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  409.191113] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.191195] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  409.191272] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  409.191352] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.191431] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  409.191511] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  409.191588] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  409.191664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.191762] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.191843] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.191859] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.191939] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  409.192022] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  409.192110] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  409.192195] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.192282] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  409.192370] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  409.192457] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.192540] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  409.192625] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  409.192727] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  409.192811] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  409.192931] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  409.193033] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  409.193118] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  409.193393] [drm:intel_power_well_enable [i915]] enabling always-on
>[  409.193464] [drm:intel_power_well_enable [i915]] enabling DC off
>[  409.193858] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  409.194396] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  409.194446] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  409.194524] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  409.195065] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  409.199324] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.199366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.199410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.199454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.199494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.199534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.199574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.199614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.199653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.199744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.199785] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.199831] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.199876] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.200196] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  409.200235] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  409.200510] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  409.201821] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  409.202380] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  409.202419] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  409.202477] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  409.202513] [drm:hsw_audio_config_update [i915]] using automatic N
>[  409.219478] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.219556] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.219865] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.220567] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.220805] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  409.236011] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  409.236086] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.236201] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  409.252769] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  409.252911] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  409.253049] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  409.257287] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.257349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.257413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.257478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.257537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.257595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.257654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.257806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.257866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.257926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.257985] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.258055] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.258120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.258184] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.258273] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  409.258335] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  409.258419] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  409.258508] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.258572] [drm:intel_power_well_disable [i915]] disabling DC off
>[  409.258632] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  409.258752] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  409.259342] [drm:intel_power_well_disable [i915]] disabling always-on
>[  409.260326] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.260369] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  409.260597] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  409.260677] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.260845] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  409.260923] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  409.261011] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.261092] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  409.261176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  409.261256] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  409.261337] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.261350] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.261427] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.261440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.261520] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  409.261600] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  409.261683] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  409.261808] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.261888] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  409.261975] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  409.262055] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.262138] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  409.262218] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  409.262303] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  409.262385] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  409.262499] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  409.262606] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  409.262689] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  409.263006] [drm:intel_power_well_enable [i915]] enabling always-on
>[  409.263078] [drm:intel_power_well_enable [i915]] enabling DC off
>[  409.263410] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  409.263513] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  409.263590] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  409.263764] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  409.264165] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  409.268421] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.268486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.268531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.268577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.268619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.268661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.268752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.268793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.268841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.268885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.268930] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.268976] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.269022] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.269098] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  409.269140] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  409.269411] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  409.270550] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  409.271131] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  409.271173] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  409.271235] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  409.271275] [drm:hsw_audio_config_update [i915]] using automatic N
>[  409.288232] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.288314] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.288545] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.289153] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.289326] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  409.304802] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  409.304883] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.305000] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  409.321515] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  409.321657] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  409.321886] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  409.326119] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.326183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.326251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.326320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.326382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.326446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.326507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.326574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.326635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.326775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.326840] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.326919] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.326990] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.327057] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.327145] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  409.327207] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  409.327294] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  409.327385] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.327453] [drm:intel_power_well_disable [i915]] disabling DC off
>[  409.327517] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  409.327576] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  409.328239] [drm:intel_power_well_disable [i915]] disabling always-on
>[  409.329079] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.329122] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  409.329344] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  409.329424] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.329511] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  409.329588] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  409.329670] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.329829] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  409.329917] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  409.330000] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  409.330084] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.330101] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.330184] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.330198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.330283] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  409.330366] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  409.330451] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  409.330537] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.330626] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  409.330732] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  409.330815] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.330898] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  409.330985] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  409.331069] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  409.331152] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  409.331266] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  409.331367] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  409.331449] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  409.331769] [drm:intel_power_well_enable [i915]] enabling always-on
>[  409.331840] [drm:intel_power_well_enable [i915]] enabling DC off
>[  409.332173] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  409.332277] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  409.332355] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  409.332470] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  409.332869] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  409.337076] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.337121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.337169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.337217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.337261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.337304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.337346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.337388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.337431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.337475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.337519] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.337565] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.337611] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.337741] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  409.337785] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  409.338075] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  409.339281] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  409.339883] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  409.339929] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  409.339996] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  409.340038] [drm:hsw_audio_config_update [i915]] using automatic N
>[  409.356955] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.357027] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.357236] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.357770] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.357923] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  409.373536] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  409.373604] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.373778] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  409.390382] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  409.390544] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  409.391061] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  409.395332] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.395416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.395504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.395594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.395675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.395867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.395953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.396044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.396129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.396211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.396294] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.396389] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.396478] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.396568] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.396687] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  409.396840] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  409.396952] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  409.397070] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.397157] [drm:intel_power_well_disable [i915]] disabling DC off
>[  409.397240] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  409.397311] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  409.398517] [drm:intel_power_well_disable [i915]] disabling always-on
>[  409.399596] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.399820] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  409.400055] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  409.400135] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.400219] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  409.400296] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  409.400376] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.400455] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  409.400534] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  409.400611] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  409.400687] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.400945] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.401027] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.401036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.401121] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  409.401219] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  409.401309] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  409.401399] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.401490] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  409.401586] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  409.401677] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.402022] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  409.402112] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  409.402204] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  409.402291] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  409.402423] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  409.402539] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  409.402631] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  409.403153] [drm:intel_power_well_enable [i915]] enabling always-on
>[  409.403233] [drm:intel_power_well_enable [i915]] enabling DC off
>[  409.403564] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  409.403681] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  409.403977] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  409.404101] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  409.404496] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  409.408781] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.408860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.408898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.408937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.408972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.409007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.409042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.409075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.409110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.409143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.409179] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.409216] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.409251] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.409317] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  409.409350] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  409.409636] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  409.410641] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  409.411213] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  409.411247] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  409.411299] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  409.411331] [drm:hsw_audio_config_update [i915]] using automatic N
>[  409.428309] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.428387] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.428606] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.429270] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.429424] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  409.444885] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  409.444958] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.445100] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  409.461815] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  409.461976] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  409.462144] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  409.466427] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.466520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.466615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.466714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.467055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.467146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.467240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.467344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.467440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.467531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.467623] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.467907] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.468008] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.468107] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.468236] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  409.468328] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  409.468453] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  409.468581] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.468679] [drm:intel_power_well_disable [i915]] disabling DC off
>[  409.469006] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  409.469087] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  409.469686] [drm:intel_power_well_disable [i915]] disabling always-on
>[  409.470624] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.470771] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  409.471024] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  409.471117] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.471211] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  409.471296] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  409.471387] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.471477] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  409.471565] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  409.471653] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  409.471845] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.471860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.471953] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.471966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.472059] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  409.472148] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  409.472239] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  409.472333] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.472423] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  409.472521] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  409.472613] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.472702] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  409.472851] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  409.472915] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  409.472981] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  409.473072] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  409.473151] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  409.473219] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  409.473442] [drm:intel_power_well_enable [i915]] enabling always-on
>[  409.473496] [drm:intel_power_well_enable [i915]] enabling DC off
>[  409.473860] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  409.474444] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  409.474504] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  409.474594] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  409.474929] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  409.479158] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.479215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.479275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.479335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.479391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.479446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.479500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.479555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.479610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.479663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.479788] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.479852] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.479913] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.480009] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  409.480066] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  409.480404] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  409.481662] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  409.482229] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  409.482270] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  409.482331] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  409.482369] [drm:hsw_audio_config_update [i915]] using automatic N
>[  409.499282] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.499338] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.499521] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.500150] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.500308] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  409.515900] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  409.515969] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.516076] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  409.532588] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  409.532806] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  409.532938] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  409.537136] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.537207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.537281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.537356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.537425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.537493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.537561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.537635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.537797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.537867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.537939] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.538022] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.538096] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.538172] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.538274] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  409.538344] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  409.538443] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  409.538543] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.538616] [drm:intel_power_well_disable [i915]] disabling DC off
>[  409.538749] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  409.538815] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  409.539397] [drm:intel_power_well_disable [i915]] disabling always-on
>[  409.539798] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.539833] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  409.540029] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  409.540097] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.540167] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  409.540231] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  409.540298] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.540365] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  409.540431] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  409.540495] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  409.540559] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.540567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.540631] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.540718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.540786] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  409.540855] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  409.540925] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  409.540998] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.541068] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  409.541146] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  409.541215] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.541290] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  409.541359] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  409.541433] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  409.541502] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  409.541604] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  409.541690] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  409.541798] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  409.542038] [drm:intel_power_well_enable [i915]] enabling always-on
>[  409.542096] [drm:intel_power_well_enable [i915]] enabling DC off
>[  409.542410] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  409.542501] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  409.542568] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  409.542665] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  409.543048] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  409.547305] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.547351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.547398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.547447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.547491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.547534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.547578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.547620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.547665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.547764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.547808] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.547861] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.547908] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.547988] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  409.548032] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  409.548324] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  409.549540] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  409.550147] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  409.550192] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  409.550260] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  409.550302] [drm:hsw_audio_config_update [i915]] using automatic N
>[  409.567253] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.567339] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.567567] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.568182] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.568355] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  409.583857] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  409.583942] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.584069] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  409.600721] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  409.600973] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  409.601160] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  409.605424] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.605508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.605594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.605684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.605874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.605956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.606041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.606133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.606220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.606301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.606386] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.606479] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.606571] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.606658] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.606841] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  409.606949] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  409.607073] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  409.607201] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.607299] [drm:intel_power_well_disable [i915]] disabling DC off
>[  409.607391] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  409.607472] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  409.608152] [drm:intel_power_well_disable [i915]] disabling always-on
>[  409.609092] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.609137] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  409.609386] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  409.609476] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.609569] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  409.609654] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  409.609835] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.609926] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  409.610022] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  409.610116] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  409.610211] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.610230] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.610320] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.610337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.610427] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  409.610524] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  409.610619] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  409.610735] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.610823] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  409.610922] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  409.611018] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.611112] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  409.611207] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  409.611301] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  409.611394] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  409.611521] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  409.611633] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  409.611792] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  409.612090] [drm:intel_power_well_enable [i915]] enabling always-on
>[  409.612164] [drm:intel_power_well_enable [i915]] enabling DC off
>[  409.612484] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  409.612554] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  409.612604] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  409.612729] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  409.613038] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  409.617288] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.617331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.617375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.617421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.617463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.617504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.617545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.617585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.617626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.617717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.617760] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.617808] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.617856] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.617931] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  409.617973] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  409.618259] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  409.619414] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  409.619997] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  409.620040] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  409.620102] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  409.620143] [drm:hsw_audio_config_update [i915]] using automatic N
>[  409.637058] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.637143] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.637371] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.637990] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.638165] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  409.653674] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  409.653815] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.653970] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  409.670645] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  409.670896] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  409.671083] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  409.675346] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.675441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.675537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.675636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.675880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.675987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.676089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.676210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.676314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.676420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.676523] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.676643] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.677010] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.677123] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.677271] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  409.677374] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  409.677513] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  409.677658] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.677852] [drm:intel_power_well_disable [i915]] disabling DC off
>[  409.677963] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  409.678059] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  409.678677] [drm:intel_power_well_disable [i915]] disabling always-on
>[  409.679752] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.679804] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  409.680081] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  409.680181] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.680285] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  409.680381] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  409.680480] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.680579] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  409.680678] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  409.680875] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  409.680973] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.680995] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.681093] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.681114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.681219] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  409.681326] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  409.681436] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  409.681541] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.681649] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  409.681810] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  409.681922] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.682023] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  409.682132] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  409.682237] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  409.682346] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  409.682491] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  409.682618] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  409.682722] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  409.682999] [drm:intel_power_well_enable [i915]] enabling always-on
>[  409.683047] [drm:intel_power_well_enable [i915]] enabling DC off
>[  409.683350] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  409.683425] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  409.683478] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  409.683559] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  409.683896] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  409.688094] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.688131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.688169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.688208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.688244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.688278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.688313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.688348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.688383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.688418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.688453] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.688489] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.688525] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.688591] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  409.688625] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  409.688971] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  409.689976] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  409.690510] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  409.690545] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  409.690596] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  409.690628] [drm:hsw_audio_config_update [i915]] using automatic N
>[  409.707600] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.707672] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.707962] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.708442] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.708593] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  409.724185] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  409.724256] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.724362] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  409.740990] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  409.741133] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  409.741281] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  409.745520] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.745585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.745652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.745803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.745868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.745933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.745998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.746070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.746134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.746199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.746264] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.746340] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.746408] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.746476] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.746570] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  409.746636] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  409.746777] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  409.746870] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.746940] [drm:intel_power_well_disable [i915]] disabling DC off
>[  409.747005] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  409.747061] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  409.747635] [drm:intel_power_well_disable [i915]] disabling always-on
>[  409.748499] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.748532] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  409.748779] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  409.748847] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.748914] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  409.748978] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  409.749043] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.749109] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  409.749172] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  409.749235] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  409.749298] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.749311] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.749369] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.749380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.749443] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  409.749506] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  409.749571] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  409.749633] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.749752] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  409.749821] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  409.749888] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.749955] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  409.750025] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  409.750089] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  409.750158] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  409.750250] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  409.750333] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  409.750399] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  409.750665] [drm:intel_power_well_enable [i915]] enabling always-on
>[  409.750881] [drm:intel_power_well_enable [i915]] enabling DC off
>[  409.751201] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  409.751299] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  409.751369] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  409.751474] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  409.751882] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  409.756114] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.756173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.756232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.756293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.756349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.756404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.756458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.756513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.756567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.756620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.756674] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.756803] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.756863] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.756958] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  409.757013] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  409.757337] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  409.758748] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  409.759320] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  409.759368] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  409.759437] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  409.759483] [drm:hsw_audio_config_update [i915]] using automatic N
>[  409.776367] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.776433] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.776628] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.777245] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.777383] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  409.792985] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  409.793079] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.793219] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  409.809960] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  409.810113] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  409.810271] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  409.814519] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.814596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.814675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.814854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.814930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.815007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.815082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.815167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.815243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.815322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.815397] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.815485] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.815566] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.815648] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.815817] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  409.815895] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  409.816001] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  409.816109] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.816190] [drm:intel_power_well_disable [i915]] disabling DC off
>[  409.816267] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  409.816334] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  409.817542] [drm:intel_power_well_disable [i915]] disabling always-on
>[  409.818561] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.818608] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  409.818948] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  409.819041] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.819140] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  409.819228] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  409.819325] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.819416] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  409.819509] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  409.819598] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  409.819689] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.819769] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.819865] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.819884] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.819979] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  409.820074] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  409.820174] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  409.820271] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.820367] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  409.820467] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  409.820563] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.820653] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  409.820798] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  409.820856] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  409.820919] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  409.821008] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  409.821085] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  409.821145] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  409.821356] [drm:intel_power_well_enable [i915]] enabling always-on
>[  409.821407] [drm:intel_power_well_enable [i915]] enabling DC off
>[  409.821794] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  409.822341] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  409.822393] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  409.822470] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  409.822820] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  409.827071] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.827146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.827184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.827223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.827258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.827293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.827328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.827361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.827397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.827430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.827467] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.827503] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.827539] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.827605] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  409.827639] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  409.827979] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  409.828987] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  409.829520] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  409.829554] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  409.829606] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  409.829638] [drm:hsw_audio_config_update [i915]] using automatic N
>[  409.846597] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.846673] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.846956] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.847433] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.847584] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  409.863194] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  409.863263] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.863400] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  409.880021] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  409.880181] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  409.880352] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  409.884602] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.884680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.884852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.884947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.885022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.885100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.885175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.885261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.885336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.885413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.885488] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.885575] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.885658] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.885793] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.885902] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  409.886003] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  409.886127] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  409.886255] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.886353] [drm:intel_power_well_disable [i915]] disabling DC off
>[  409.886445] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  409.886527] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  409.887219] [drm:intel_power_well_disable [i915]] disabling always-on
>[  409.888152] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.888197] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  409.888450] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  409.888538] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.888631] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  409.888806] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  409.888900] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.889000] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  409.889095] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  409.889191] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  409.889282] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.889303] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.889390] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.889407] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.889504] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  409.889597] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  409.889686] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  409.889825] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.889918] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  409.890019] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  409.890111] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.890207] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  409.890301] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  409.890391] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  409.890481] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  409.890613] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  409.890799] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  409.890893] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  409.891211] [drm:intel_power_well_enable [i915]] enabling always-on
>[  409.891289] [drm:intel_power_well_enable [i915]] enabling DC off
>[  409.891625] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  409.892238] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  409.892288] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  409.892363] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  409.892664] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  409.896965] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.897040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.897079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.897118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.897153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.897189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.897224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.897259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.897294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.897327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.897363] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.897399] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.897434] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.897501] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  409.897533] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  409.897809] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  409.898802] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  409.899334] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  409.899369] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  409.899420] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  409.899452] [drm:hsw_audio_config_update [i915]] using automatic N
>[  409.916421] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.916496] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.916790] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.917268] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.917420] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  409.933048] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  409.933129] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  409.933261] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  409.949870] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  409.950032] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  409.950202] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  409.954501] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.954595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.954691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.954905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.954998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.955092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.955184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.955288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.955380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.955473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.955565] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.955671] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.955845] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.955957] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.956091] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  409.956184] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  409.956308] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  409.956440] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.956539] [drm:intel_power_well_disable [i915]] disabling DC off
>[  409.956630] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  409.956788] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  409.957394] [drm:intel_power_well_disable [i915]] disabling always-on
>[  409.958420] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.958467] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  409.958717] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  409.958905] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  409.959002] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  409.959098] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  409.959196] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  409.959289] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  409.959379] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  409.959471] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  409.959560] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  409.959578] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.959664] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  409.959745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  409.959837] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  409.959934] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  409.960027] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  409.960128] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  409.960223] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  409.960325] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  409.960417] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  409.960512] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  409.960603] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  409.960700] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  409.960844] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  409.960974] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  409.961088] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  409.961182] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  409.961488] [drm:intel_power_well_enable [i915]] enabling always-on
>[  409.961566] [drm:intel_power_well_enable [i915]] enabling DC off
>[  409.961927] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  409.962496] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  409.962545] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  409.962618] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  409.962881] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  409.967156] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  409.967192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  409.967229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  409.967268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  409.967303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  409.967337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  409.967372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  409.967405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  409.967440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  409.967473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  409.967509] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  409.967545] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  409.967580] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.967646] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  409.967728] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  409.968018] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  409.969025] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  409.969557] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  409.969592] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  409.969643] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  409.969714] [drm:hsw_audio_config_update [i915]] using automatic N
>[  409.986642] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  409.986763] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  409.986966] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  409.987406] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  409.987546] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  410.003237] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.003310] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.003426] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.020111] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  410.020276] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  410.020446] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  410.024707] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.024854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.024936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.025018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.025092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.025166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.025239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.025320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.025393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.025467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.025541] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.025623] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.025783] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.025862] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.025977] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  410.026055] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  410.026158] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  410.026269] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.026349] [drm:intel_power_well_disable [i915]] disabling DC off
>[  410.026424] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  410.026492] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  410.027160] [drm:intel_power_well_disable [i915]] disabling always-on
>[  410.028081] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.028128] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  410.028382] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  410.028488] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.028580] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  410.028665] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  410.028871] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.028962] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  410.029052] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  410.029143] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  410.029231] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.029248] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.029333] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.029347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.029438] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  410.029527] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  410.029620] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  410.029710] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.029850] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  410.029949] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  410.030040] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.030132] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  410.030226] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  410.030314] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  410.030406] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  410.030539] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  410.030652] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  410.030804] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  410.031085] [drm:intel_power_well_enable [i915]] enabling always-on
>[  410.031154] [drm:intel_power_well_enable [i915]] enabling DC off
>[  410.031481] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  410.031588] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  410.031666] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  410.031829] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  410.032190] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  410.036489] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.036533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.036578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.036623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.036666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.036761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.036804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.036848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.036892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.036937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.036980] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.037026] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.037069] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.037143] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  410.037184] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  410.037463] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  410.038603] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  410.039184] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  410.039226] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  410.039288] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  410.039328] [drm:hsw_audio_config_update [i915]] using automatic N
>[  410.056255] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.056320] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.056518] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.057025] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.057162] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  410.072776] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.072841] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.072943] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.089493] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  410.089645] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  410.089939] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  410.094186] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.094262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.094342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.094424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.094499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.094573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.094647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.094818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.094896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.094977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.095053] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.095143] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.095221] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.095302] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.095413] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  410.095486] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  410.095589] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  410.095693] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.095822] [drm:intel_power_well_disable [i915]] disabling DC off
>[  410.095901] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  410.095972] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  410.096560] [drm:intel_power_well_disable [i915]] disabling always-on
>[  410.096989] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.097028] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  410.097234] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  410.097310] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.097387] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  410.097459] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  410.097534] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.097608] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  410.097681] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  410.097824] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  410.097904] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.097918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.097994] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.098007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.098085] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  410.098160] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  410.098238] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  410.098315] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.098392] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  410.098474] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  410.098551] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.098628] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  410.098741] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  410.098817] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  410.098899] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  410.099010] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  410.099103] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  410.099178] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  410.099433] [drm:intel_power_well_enable [i915]] enabling always-on
>[  410.099494] [drm:intel_power_well_enable [i915]] enabling DC off
>[  410.099866] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  410.100437] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  410.100481] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  410.100550] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  410.100877] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  410.105117] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.105162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.105210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.105258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.105302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.105346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.105387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.105431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.105475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.105518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.105561] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.105607] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.105652] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.105786] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  410.105828] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  410.106114] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  410.107322] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  410.107926] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  410.107970] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  410.108035] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  410.108078] [drm:hsw_audio_config_update [i915]] using automatic N
>[  410.124993] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.125055] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.125246] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.125782] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.125957] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  410.141594] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.141676] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.142438] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.158215] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  410.158375] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  410.158547] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  410.162795] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.162874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.162954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.163035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.163110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.163183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.163257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.163338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.163411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.163485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.163558] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.163639] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.163813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.163897] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.164007] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  410.164083] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  410.164183] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  410.164287] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.164365] [drm:intel_power_well_disable [i915]] disabling DC off
>[  410.164439] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  410.164507] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  410.165188] [drm:intel_power_well_disable [i915]] disabling always-on
>[  410.166110] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.166156] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  410.166406] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  410.166495] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.166590] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  410.166677] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  410.166865] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.166962] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  410.167056] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  410.167153] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  410.167243] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.167264] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.167351] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.167371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.167467] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  410.167560] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  410.167649] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  410.167794] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.167886] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  410.167981] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  410.168074] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.168170] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  410.168264] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  410.168357] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  410.168445] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  410.168570] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  410.168680] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  410.168830] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  410.169136] [drm:intel_power_well_enable [i915]] enabling always-on
>[  410.169211] [drm:intel_power_well_enable [i915]] enabling DC off
>[  410.169531] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  410.169600] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  410.169650] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  410.169762] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  410.170069] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  410.174319] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.174362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.174406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.174452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.174494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.174536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.174575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.174617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.174659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.174756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.174800] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.174849] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.174896] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.174969] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  410.175011] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  410.175290] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  410.176443] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  410.177027] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  410.177070] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  410.177133] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  410.177172] [drm:hsw_audio_config_update [i915]] using automatic N
>[  410.194133] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.194219] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.194449] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.195073] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.195247] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  410.210826] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.210920] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.211071] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.227784] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  410.227943] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  410.228110] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  410.232388] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.232480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.232576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.232674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.232870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.232963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.233062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.233167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.233258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.233348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.233436] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.233542] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.233640] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.233798] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.233931] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  410.234022] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  410.234142] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  410.234266] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.234365] [drm:intel_power_well_disable [i915]] disabling DC off
>[  410.234456] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  410.234539] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  410.235199] [drm:intel_power_well_disable [i915]] disabling always-on
>[  410.236143] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.236189] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  410.236436] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  410.236525] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.236618] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  410.236703] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  410.236889] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.236983] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  410.237076] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  410.237174] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  410.237267] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.237283] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.237370] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.237386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.237482] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  410.237576] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  410.237675] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  410.237813] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.237910] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  410.238003] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  410.238092] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.238189] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  410.238279] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  410.238371] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  410.238458] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  410.238587] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  410.238697] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  410.238843] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  410.239142] [drm:intel_power_well_enable [i915]] enabling always-on
>[  410.239219] [drm:intel_power_well_enable [i915]] enabling DC off
>[  410.239557] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  410.239671] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  410.239826] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  410.239895] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  410.240164] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  410.244404] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.244447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.244492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.244538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.244580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.244621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.244661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.244755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.244798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.244843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.244886] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.244935] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.244982] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.245055] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  410.245095] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  410.245373] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  410.246511] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  410.247094] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  410.247137] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  410.247199] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  410.247239] [drm:hsw_audio_config_update [i915]] using automatic N
>[  410.264166] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.264236] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.264439] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.264969] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.265114] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  410.280779] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.280858] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.280991] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.297499] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  410.297646] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  410.297879] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  410.302109] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.302174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.302243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.302312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.302375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.302438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.302500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.302569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.302632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.302772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.302837] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.302914] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.302985] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.303050] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.303143] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  410.303208] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  410.303293] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  410.303388] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.303456] [drm:intel_power_well_disable [i915]] disabling DC off
>[  410.303520] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  410.303578] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  410.304241] [drm:intel_power_well_disable [i915]] disabling always-on
>[  410.305122] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.305166] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  410.305392] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  410.305474] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.305559] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  410.305638] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  410.305805] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.305892] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  410.305975] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  410.306062] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  410.306145] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.306162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.306240] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.306258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.306345] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  410.306431] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  410.306517] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  410.306598] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.306683] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  410.306812] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  410.306896] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.306974] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  410.307054] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  410.307133] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  410.307213] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  410.307329] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  410.307434] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  410.307516] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  410.307848] [drm:intel_power_well_enable [i915]] enabling always-on
>[  410.307916] [drm:intel_power_well_enable [i915]] enabling DC off
>[  410.308242] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  410.308345] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  410.308425] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  410.308540] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  410.308955] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  410.313201] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.313245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.313290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.313336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.313378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.313419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.313459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.313498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.313542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.313581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.313624] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.313718] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.313764] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.313841] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  410.313881] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  410.314158] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  410.315300] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  410.315881] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  410.315924] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  410.315987] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  410.316026] [drm:hsw_audio_config_update [i915]] using automatic N
>[  410.332969] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.333041] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.333254] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.333820] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.333972] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  410.349552] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.349632] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.350277] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.366134] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  410.366278] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  410.366426] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  410.370653] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.370773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.370841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.370911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.370974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.371037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.371099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.371168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.371231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.371293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.371355] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.371425] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.371491] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.371556] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.371646] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  410.371775] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  410.371866] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  410.371960] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.372026] [drm:intel_power_well_disable [i915]] disabling DC off
>[  410.372091] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  410.372145] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  410.372825] [drm:intel_power_well_disable [i915]] disabling always-on
>[  410.373722] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.373766] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  410.373989] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  410.374071] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.374156] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  410.374236] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  410.374318] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.374399] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  410.374480] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  410.374560] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  410.374638] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.374727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.374806] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.374826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.374907] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  410.374992] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  410.375080] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  410.375163] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.375247] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  410.375337] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  410.375421] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.375509] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  410.375599] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  410.375686] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  410.375814] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  410.375930] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  410.376029] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  410.376113] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  410.376383] [drm:intel_power_well_enable [i915]] enabling always-on
>[  410.376451] [drm:intel_power_well_enable [i915]] enabling DC off
>[  410.376839] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  410.377395] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  410.377442] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  410.377512] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  410.377788] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  410.382030] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.382073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.382117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.382163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.382203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.382244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.382284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.382324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.382365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.382405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.382447] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.382491] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.382533] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.382607] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  410.382648] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  410.382980] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  410.384134] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  410.384718] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  410.384759] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  410.384820] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  410.384859] [drm:hsw_audio_config_update [i915]] using automatic N
>[  410.401876] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.401960] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.402189] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.402771] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.402939] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  410.418383] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.418462] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.418592] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.435266] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  410.435437] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  410.435622] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  410.439988] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.440081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.440178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.440277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.440367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.440457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.440547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.440643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.440841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.440935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.441028] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.441139] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.441241] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.441336] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.441466] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  410.441558] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  410.441681] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  410.441880] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.441976] [drm:intel_power_well_disable [i915]] disabling DC off
>[  410.442066] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  410.442146] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  410.442811] [drm:intel_power_well_disable [i915]] disabling always-on
>[  410.443724] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.443771] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  410.444015] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  410.444106] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.444200] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  410.444288] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  410.444380] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.444470] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  410.444560] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  410.444648] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  410.444814] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.444832] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.444925] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.444945] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.445039] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  410.445131] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  410.445226] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  410.445322] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.445419] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  410.445521] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  410.445617] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.445710] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  410.445847] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  410.445934] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  410.446024] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  410.446149] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  410.446260] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  410.446349] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  410.446630] [drm:intel_power_well_enable [i915]] enabling always-on
>[  410.446707] [drm:intel_power_well_enable [i915]] enabling DC off
>[  410.447001] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  410.447065] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  410.447108] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  410.447179] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  410.447451] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  410.451695] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.451771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.451816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.451861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.451903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.451943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.451986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.452026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.452067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.452106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.452148] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.452192] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.452236] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.452310] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  410.452349] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  410.452621] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  410.453776] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  410.454317] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  410.454358] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  410.454418] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  410.454456] [drm:hsw_audio_config_update [i915]] using automatic N
>[  410.471377] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.471439] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.471627] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.472214] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.472374] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  410.488012] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.488092] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.488221] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.504952] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  410.505114] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  410.505284] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  410.509524] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.509600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.509679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.509848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.509921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.509996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.510070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.510155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.510230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.510307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.510384] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.510471] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.510552] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.510633] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.510797] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  410.510875] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  410.510976] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  410.511079] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.511157] [drm:intel_power_well_disable [i915]] disabling DC off
>[  410.511231] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  410.511300] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  410.511982] [drm:intel_power_well_disable [i915]] disabling always-on
>[  410.512912] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.512957] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  410.513202] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  410.513291] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.513384] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  410.513469] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  410.513558] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.513646] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  410.513826] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  410.513914] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  410.514011] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.514030] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.514122] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.514142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.514238] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  410.514333] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  410.514431] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  410.514525] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.514613] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  410.514706] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  410.514858] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.514949] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  410.515041] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  410.515135] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  410.515230] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  410.515359] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  410.515470] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  410.515559] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  410.515919] [drm:intel_power_well_enable [i915]] enabling always-on
>[  410.515994] [drm:intel_power_well_enable [i915]] enabling DC off
>[  410.516326] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  410.516446] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  410.516531] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  410.516655] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  410.517048] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  410.521291] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.521334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.521378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.521424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.521466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.521505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.521546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.521586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.521629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.521719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.521763] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.521809] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.521855] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.521931] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  410.521972] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  410.522242] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  410.523380] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  410.523961] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  410.524004] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  410.524065] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  410.524104] [drm:hsw_audio_config_update [i915]] using automatic N
>[  410.541024] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.541086] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.541277] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.541824] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.541996] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  410.557624] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.557777] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.557908] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.574522] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  410.574693] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  410.574974] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  410.579230] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.579314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.579402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.579492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.579574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.579655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.579833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.579928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.580012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.580093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.580173] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.580265] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.580352] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.580442] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.580560] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  410.580644] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  410.580837] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  410.580958] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.581043] [drm:intel_power_well_disable [i915]] disabling DC off
>[  410.581123] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  410.581194] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  410.581839] [drm:intel_power_well_disable [i915]] disabling always-on
>[  410.582761] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.582805] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  410.583028] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  410.583111] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.583196] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  410.583275] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  410.583358] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.583439] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  410.583519] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  410.583598] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  410.583677] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.583762] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.583842] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.583862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.583943] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  410.584028] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  410.584114] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  410.584200] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.584288] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  410.584378] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  410.584464] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.584547] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  410.584637] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  410.584760] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  410.584851] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  410.584964] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  410.585079] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  410.585142] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  410.585348] [drm:intel_power_well_enable [i915]] enabling always-on
>[  410.585400] [drm:intel_power_well_enable [i915]] enabling DC off
>[  410.585769] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  410.586337] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  410.586394] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  410.586477] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  410.586837] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  410.591017] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.591085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.591131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.591177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.591217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.591259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.591300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.591342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.591383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.591423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.591465] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.591508] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.591551] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.591625] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  410.591666] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  410.592003] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  410.593169] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  410.593753] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  410.593796] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  410.593859] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  410.593900] [drm:hsw_audio_config_update [i915]] using automatic N
>[  410.610880] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.610961] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.611181] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.611774] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.611944] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  410.627426] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.627511] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.627642] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.644432] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  410.644604] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  410.644938] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  410.649228] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.649323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.649421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.649521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.649612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.649701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.649898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.650003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.650096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.650190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.650281] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.650392] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.650490] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.650590] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.650798] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  410.650894] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  410.651017] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  410.651149] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.651247] [drm:intel_power_well_disable [i915]] disabling DC off
>[  410.651339] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  410.651421] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  410.652092] [drm:intel_power_well_disable [i915]] disabling always-on
>[  410.653009] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.653054] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  410.653302] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  410.653392] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.653485] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  410.653570] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  410.653659] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.653837] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  410.653929] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  410.654023] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  410.654113] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.654135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.654222] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.654238] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.654333] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  410.654428] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  410.654522] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  410.654615] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.654706] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  410.654848] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  410.654944] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.655037] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  410.655130] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  410.655224] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  410.655318] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  410.655447] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  410.655556] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  410.655649] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  410.655941] [drm:intel_power_well_enable [i915]] enabling always-on
>[  410.655991] [drm:intel_power_well_enable [i915]] enabling DC off
>[  410.656310] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  410.656383] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  410.656435] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  410.656514] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  410.656817] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  410.661068] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.661111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.661156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.661202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.661244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.661285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.661326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.661368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.661409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.661449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.661491] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.661534] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.661576] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.661651] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  410.661742] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  410.662018] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  410.663158] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  410.663738] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  410.663780] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  410.663842] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  410.663881] [drm:hsw_audio_config_update [i915]] using automatic N
>[  410.680861] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.680940] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.681159] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.681737] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.681909] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  410.697419] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.697504] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.697643] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.714455] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  410.714625] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  410.714954] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  410.719237] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.719330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.719427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.719526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.719617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.719707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.719900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.720005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.720097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.720188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.720276] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.720379] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.720475] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.720571] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.720777] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  410.720876] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  410.720999] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  410.721126] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.721220] [drm:intel_power_well_disable [i915]] disabling DC off
>[  410.721309] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  410.721392] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  410.722054] [drm:intel_power_well_disable [i915]] disabling always-on
>[  410.722998] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.723046] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  410.723294] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  410.723385] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.723479] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  410.723567] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  410.723659] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.723831] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  410.723923] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  410.724020] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  410.724111] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.724133] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.724219] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.724236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.724326] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  410.724423] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  410.724516] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  410.724611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.724704] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  410.724851] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  410.724922] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.724991] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  410.725061] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  410.725132] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  410.725203] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  410.725300] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  410.725398] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  410.725442] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  410.725601] [drm:intel_power_well_enable [i915]] enabling always-on
>[  410.725637] [drm:intel_power_well_enable [i915]] enabling DC off
>[  410.725963] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  410.726024] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  410.726065] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  410.726131] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  410.726391] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  410.730629] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.730705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.730749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.730795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.730837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.730876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.730916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.730957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.730999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.731038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.731082] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.731125] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.731168] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.731241] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  410.731280] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  410.731551] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  410.732730] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  410.733273] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  410.733315] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  410.733375] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  410.733413] [drm:hsw_audio_config_update [i915]] using automatic N
>[  410.750337] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.750396] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.750582] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.751167] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.751328] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  410.766970] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.767049] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.767178] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.783944] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  410.784105] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  410.784272] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  410.788521] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.788598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.788677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.788847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.788920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.788995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.789069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.789151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.789226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.789303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.789403] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.789510] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.789611] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.789709] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.789899] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  410.789995] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  410.790123] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  410.790248] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.790343] [drm:intel_power_well_disable [i915]] disabling DC off
>[  410.790430] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  410.790508] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  410.791173] [drm:intel_power_well_disable [i915]] disabling always-on
>[  410.792112] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.792157] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  410.792399] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  410.792488] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.792581] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  410.792666] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  410.792846] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.792938] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  410.793037] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  410.793131] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  410.793224] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.793244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.793334] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.793353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.793449] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  410.793535] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  410.793625] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  410.793738] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.793831] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  410.793927] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  410.794023] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.794114] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  410.794213] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  410.794305] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  410.794402] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  410.794533] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  410.794644] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  410.794809] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  410.795106] [drm:intel_power_well_enable [i915]] enabling always-on
>[  410.795184] [drm:intel_power_well_enable [i915]] enabling DC off
>[  410.795517] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  410.795634] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  410.795793] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  410.795885] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  410.796155] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  410.800399] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.800442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.800488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.800534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.800576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.800617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.800659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.800756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.800799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.800844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.800888] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.800935] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.800980] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.801059] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  410.801101] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  410.801378] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  410.802525] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  410.803108] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  410.803150] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  410.803212] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  410.803253] [drm:hsw_audio_config_update [i915]] using automatic N
>[  410.820178] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.820239] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.820425] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.820995] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.821160] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  410.836813] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.836896] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.837026] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.853664] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  410.853891] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  410.854062] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  410.858320] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.858404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.858491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.858579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.858661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.858840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.858926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.859022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.859106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.859189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.859273] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.859367] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.859454] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.859544] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.859665] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  410.859818] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  410.859930] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  410.860050] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.860139] [drm:intel_power_well_disable [i915]] disabling DC off
>[  410.860222] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  410.860296] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  410.860950] [drm:intel_power_well_disable [i915]] disabling always-on
>[  410.861888] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.861930] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  410.862158] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  410.862238] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.862322] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  410.862399] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  410.862479] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.862557] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  410.862636] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  410.862797] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  410.862877] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.862896] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.862974] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.862988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.863072] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  410.863155] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  410.863240] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  410.863323] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.863408] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  410.863497] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  410.863583] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.863666] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  410.863790] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  410.863873] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  410.863959] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  410.864077] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  410.864185] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  410.864268] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  410.864546] [drm:intel_power_well_enable [i915]] enabling always-on
>[  410.864616] [drm:intel_power_well_enable [i915]] enabling DC off
>[  410.865021] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  410.865586] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  410.865666] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  410.865828] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  410.866130] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  410.870383] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.870426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.870471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.870517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.870558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.870600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.870641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.870734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.870777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.870820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.870866] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.870915] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.870962] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.871038] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  410.871080] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  410.871360] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  410.872513] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  410.873097] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  410.873139] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  410.873202] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  410.873243] [drm:hsw_audio_config_update [i915]] using automatic N
>[  410.890098] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.890170] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.890374] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.890930] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.891095] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  410.906793] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.906875] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.907008] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.923653] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  410.923876] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  410.924047] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  410.928304] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.928390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.928480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.928570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.928652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.928831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.928919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.929033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.929125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.929219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.929310] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.929417] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.929516] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.929617] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.929822] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  410.929918] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  410.930043] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  410.930174] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.930271] [drm:intel_power_well_disable [i915]] disabling DC off
>[  410.930365] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  410.930446] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  410.931120] [drm:intel_power_well_disable [i915]] disabling always-on
>[  410.932067] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.932112] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  410.932363] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  410.932451] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  410.932543] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  410.932628] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  410.932809] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  410.932900] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  410.932996] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  410.933090] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  410.933186] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  410.933206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.933296] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  410.933313] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  410.933409] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  410.933503] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  410.933599] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  410.933690] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  410.933827] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  410.933925] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  410.934016] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  410.934110] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  410.934208] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  410.934295] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  410.934387] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  410.934516] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  410.934630] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  410.934797] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  410.935109] [drm:intel_power_well_enable [i915]] enabling always-on
>[  410.935187] [drm:intel_power_well_enable [i915]] enabling DC off
>[  410.935521] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  410.935639] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  410.935809] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  410.935885] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  410.936188] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  410.940329] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.940365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.940404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.940443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.940478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.940513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.940547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.940580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.940617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.940650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.940741] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.940780] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.940818] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.940887] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  410.940923] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  410.941179] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  410.942178] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  410.942745] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  410.942783] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  410.942835] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  410.942869] [drm:hsw_audio_config_update [i915]] using automatic N
>[  410.959857] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.959929] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  410.960132] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.960588] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  410.960822] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  410.976426] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  410.976503] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  410.976626] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  410.993275] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  410.993439] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  410.993611] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  410.997885] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  410.997969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  410.998058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  410.998147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  410.998229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  410.998309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  410.998390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  410.998479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  410.998559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  410.998638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  410.998827] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  410.998929] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  410.999022] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  410.999435] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  410.999557] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  410.999641] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  410.999823] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  411.000224] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.000313] [drm:intel_power_well_disable [i915]] disabling DC off
>[  411.000395] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  411.000469] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  411.001146] [drm:intel_power_well_disable [i915]] disabling always-on
>[  411.002057] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.002099] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  411.002329] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  411.002410] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.002494] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  411.002571] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  411.002651] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.002816] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  411.002898] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  411.002985] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  411.003066] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.003085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.003163] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.003175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.003260] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  411.003343] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  411.003428] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  411.003512] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.003599] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  411.003686] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  411.003808] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.003892] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  411.003980] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  411.004067] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  411.004152] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  411.004270] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  411.004376] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  411.004460] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  411.004805] [drm:intel_power_well_enable [i915]] enabling always-on
>[  411.004877] [drm:intel_power_well_enable [i915]] enabling DC off
>[  411.005204] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  411.005312] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  411.005392] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  411.005506] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  411.005954] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  411.010233] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.010307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.010345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.010384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.010419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.010454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.010489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.010522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.010557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.010590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.010629] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.010713] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.010752] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.010820] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  411.010856] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  411.011147] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  411.012152] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  411.012721] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  411.012758] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  411.012810] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  411.012844] [drm:hsw_audio_config_update [i915]] using automatic N
>[  411.029842] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.029917] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.030128] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.030609] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.030821] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  411.046396] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  411.046469] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.046584] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  411.063233] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  411.063394] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  411.063566] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  411.067883] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.067959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.068039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.068121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.068195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.068269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.068343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.068424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.068497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.068569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.068642] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.068819] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.068900] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.068986] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.069099] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  411.069175] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  411.069278] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  411.069386] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.069486] [drm:intel_power_well_disable [i915]] disabling DC off
>[  411.069578] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  411.069659] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  411.070341] [drm:intel_power_well_disable [i915]] disabling always-on
>[  411.071355] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.071400] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  411.071654] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  411.071842] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.071941] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  411.072034] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  411.072129] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.072225] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  411.072315] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  411.072407] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  411.072493] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.072510] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.072597] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.072611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.072699] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  411.072859] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  411.072956] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  411.073053] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.073147] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  411.073251] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  411.073340] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.073433] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  411.073526] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  411.073623] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  411.073731] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  411.073868] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  411.073982] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  411.074075] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  411.074384] [drm:intel_power_well_enable [i915]] enabling always-on
>[  411.074463] [drm:intel_power_well_enable [i915]] enabling DC off
>[  411.074861] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  411.075399] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  411.075452] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  411.075531] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  411.075883] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  411.080138] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.080213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.080251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.080291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.080326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.080361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.080396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.080430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.080465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.080498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.080534] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.080572] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.080608] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.080719] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  411.080753] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  411.081046] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  411.082048] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  411.082580] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  411.082615] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  411.082701] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  411.082734] [drm:hsw_audio_config_update [i915]] using automatic N
>[  411.099658] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.099783] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.099994] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.100456] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.100604] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  411.116294] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  411.116373] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.116508] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  411.133136] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  411.133301] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  411.133471] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  411.137830] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.137926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.138026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.138127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.138215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.138304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.138392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.138491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.138581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.138670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.138856] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.138965] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.139066] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.139172] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.139312] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  411.140143] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  411.140272] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  411.140407] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.140507] [drm:intel_power_well_disable [i915]] disabling DC off
>[  411.140599] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  411.140680] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  411.141368] [drm:intel_power_well_disable [i915]] disabling always-on
>[  411.142375] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.142421] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  411.142674] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  411.142858] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.142958] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  411.143054] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  411.143150] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.143249] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  411.143339] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  411.143431] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  411.143519] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.143536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.143622] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.143703] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.143798] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  411.143892] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  411.143985] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  411.144082] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.144176] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  411.144276] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  411.144370] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.144466] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  411.144565] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  411.144658] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  411.144799] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  411.144871] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  411.144937] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  411.144985] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  411.145170] [drm:intel_power_well_enable [i915]] enabling always-on
>[  411.145212] [drm:intel_power_well_enable [i915]] enabling DC off
>[  411.145507] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  411.145575] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  411.145624] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  411.145743] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  411.146268] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  411.150517] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.150593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.150631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.150715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.150756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.150791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.150825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.150861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.150897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.150932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.150968] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.151008] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.151046] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.151113] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  411.151147] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  411.151399] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  411.152403] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  411.152974] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  411.153010] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  411.153063] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  411.153096] [drm:hsw_audio_config_update [i915]] using automatic N
>[  411.170022] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.170097] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.170311] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.170873] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.171025] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  411.186678] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  411.186806] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.186929] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  411.203563] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  411.203852] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  411.204042] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  411.208348] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.208443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.208539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.208639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.208840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.208935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.209023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.209128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.209220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.209314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.209406] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.209513] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.209614] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.209790] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.209929] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  411.210022] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  411.210146] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  411.210276] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.210375] [drm:intel_power_well_disable [i915]] disabling DC off
>[  411.210467] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  411.210549] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  411.211220] [drm:intel_power_well_disable [i915]] disabling always-on
>[  411.212165] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.212212] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  411.212463] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  411.212553] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.212645] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  411.212820] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  411.212916] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.213014] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  411.213107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  411.213200] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  411.213291] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.213310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.213397] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.213413] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.213506] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  411.213598] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  411.213693] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  411.213829] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.213918] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  411.214019] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  411.214110] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.214208] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  411.214306] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  411.214400] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  411.214495] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  411.214629] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  411.214788] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  411.214850] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  411.215058] [drm:intel_power_well_enable [i915]] enabling always-on
>[  411.215108] [drm:intel_power_well_enable [i915]] enabling DC off
>[  411.215413] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  411.215490] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  411.215546] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  411.215632] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  411.215981] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  411.220238] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.220283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.220328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.220374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.220416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.220457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.220499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.220540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.220581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.220621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.220663] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.220762] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.220807] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.220886] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  411.220928] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  411.221210] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  411.222368] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  411.222953] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  411.222996] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  411.223060] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  411.223101] [drm:hsw_audio_config_update [i915]] using automatic N
>[  411.240049] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.240129] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.240350] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.240979] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.241153] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  411.256623] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  411.256785] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.256921] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  411.273578] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  411.273859] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  411.274049] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  411.278307] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.278391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.278481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.278570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.278652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.278831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.278918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.279013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.279097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.279182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.279264] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.279359] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.279448] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.279540] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.279663] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  411.279812] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  411.279927] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  411.280044] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.280134] [drm:intel_power_well_disable [i915]] disabling DC off
>[  411.280218] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  411.280291] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  411.280980] [drm:intel_power_well_disable [i915]] disabling always-on
>[  411.281916] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.281962] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  411.282213] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  411.282302] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.282395] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  411.282480] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  411.282569] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.282656] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  411.282836] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  411.282924] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  411.283021] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.283038] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.283130] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.283149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.283244] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  411.283338] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  411.283435] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  411.283528] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.283626] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  411.283743] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  411.283836] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.283929] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  411.284025] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  411.284117] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  411.284215] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  411.284346] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  411.284460] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  411.284553] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  411.284896] [drm:intel_power_well_enable [i915]] enabling always-on
>[  411.284953] [drm:intel_power_well_enable [i915]] enabling DC off
>[  411.285258] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  411.285336] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  411.285393] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  411.285478] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  411.285815] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  411.290072] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.290115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.290160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.290206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.290248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.290289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.290330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.290370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.290411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.290450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.290493] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.290537] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.290580] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.290654] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  411.290751] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  411.291033] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  411.292186] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  411.292769] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  411.292811] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  411.292872] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  411.292913] [drm:hsw_audio_config_update [i915]] using automatic N
>[  411.309858] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.309933] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.310146] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.310628] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.310907] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  411.326443] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  411.326526] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.326657] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  411.343395] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  411.343567] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  411.344264] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  411.348533] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.348619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.348804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.348909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.348993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.349078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.349160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.349253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.349336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.349420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.349502] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.349598] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.349688] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.349844] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.349965] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  411.350051] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  411.350163] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  411.350282] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.350370] [drm:intel_power_well_disable [i915]] disabling DC off
>[  411.350455] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  411.350529] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  411.351190] [drm:intel_power_well_disable [i915]] disabling always-on
>[  411.352101] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.352142] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  411.352370] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  411.352450] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.352534] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  411.352610] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  411.352690] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.352856] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  411.352938] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  411.353023] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  411.353105] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.353125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.353202] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.353217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.353298] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  411.353383] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  411.353466] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  411.353555] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.353640] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  411.353767] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  411.353852] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.353936] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  411.354022] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  411.354112] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  411.354195] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  411.354315] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  411.354419] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  411.354503] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  411.354842] [drm:intel_power_well_enable [i915]] enabling always-on
>[  411.354893] [drm:intel_power_well_enable [i915]] enabling DC off
>[  411.355199] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  411.355278] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  411.355336] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  411.355419] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  411.355793] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  411.360047] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.360090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.360136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.360182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.360224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.360266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.360307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.360349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.360390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.360430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.360472] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.360516] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.360558] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.360633] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  411.360724] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  411.361003] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  411.362155] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  411.362737] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  411.362781] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  411.362843] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  411.362884] [drm:hsw_audio_config_update [i915]] using automatic N
>[  411.379900] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.379987] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.380217] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.380814] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.380988] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  411.396411] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  411.396495] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.396628] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  411.413451] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  411.413622] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  411.413961] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  411.418247] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.418339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.418436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.418537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.418627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.418758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.418855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.418962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.419058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.419157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.419250] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.419359] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.419457] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.419554] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.419683] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  411.419839] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  411.419966] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  411.420096] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.420192] [drm:intel_power_well_disable [i915]] disabling DC off
>[  411.420283] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  411.420365] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  411.421028] [drm:intel_power_well_disable [i915]] disabling always-on
>[  411.421974] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.422019] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  411.422268] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  411.422357] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.422449] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  411.422534] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  411.422623] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.422711] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  411.422888] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  411.422976] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  411.423074] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.423093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.423188] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.423206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.423298] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  411.423393] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  411.423490] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  411.423586] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.423681] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  411.423822] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  411.423915] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.424004] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  411.424092] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  411.424187] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  411.424279] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  411.424405] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  411.424519] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  411.424612] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  411.424914] [drm:intel_power_well_enable [i915]] enabling always-on
>[  411.424953] [drm:intel_power_well_enable [i915]] enabling DC off
>[  411.425244] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  411.425306] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  411.425349] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  411.425419] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  411.425737] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  411.429981] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.430024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.430069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.430115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.430157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.430196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.430237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.430277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.430318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.430358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.430401] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.430444] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.430487] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.430561] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  411.430600] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  411.430922] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  411.432064] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  411.432606] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  411.432648] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  411.432747] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  411.432787] [drm:hsw_audio_config_update [i915]] using automatic N
>[  411.449674] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.449781] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.449972] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.450384] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.450508] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  411.466275] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  411.466354] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.466484] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  411.483128] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  411.483302] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  411.483487] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  411.487755] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.487839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.487926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.488016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.488097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.488178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.488259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.488346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.488428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.488507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.488588] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.488678] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.488872] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.488962] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.489086] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  411.489168] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  411.489279] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  411.489395] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.489482] [drm:intel_power_well_disable [i915]] disabling DC off
>[  411.489564] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  411.489638] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  411.490296] [drm:intel_power_well_disable [i915]] disabling always-on
>[  411.491263] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.491305] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  411.491531] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  411.491612] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.491697] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  411.491851] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  411.491944] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.492027] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  411.492115] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  411.492197] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  411.492285] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.492302] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.492382] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.492398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.492480] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  411.492566] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  411.492647] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  411.492769] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.492852] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  411.492937] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  411.493018] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.493103] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  411.493188] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  411.493272] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  411.493356] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  411.493469] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  411.493570] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  411.493650] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  411.493984] [drm:intel_power_well_enable [i915]] enabling always-on
>[  411.494054] [drm:intel_power_well_enable [i915]] enabling DC off
>[  411.494369] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  411.494436] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  411.494483] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  411.494556] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  411.494845] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  411.499090] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.499133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.499177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.499224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.499266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.499305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.499348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.499388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.499431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.499470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.499512] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.499555] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.499598] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.499721] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  411.499764] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  411.500039] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  411.501179] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  411.501760] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  411.501802] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  411.501861] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  411.501901] [drm:hsw_audio_config_update [i915]] using automatic N
>[  411.518827] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.518893] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.519089] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.519519] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.519649] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  411.535429] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  411.535511] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.535640] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  411.552407] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  411.552578] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  411.552872] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  411.557136] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.557221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.557309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.557398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.557479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.557560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.557641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.557833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.557913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.557994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.558075] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.558168] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.558261] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.558349] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.558470] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  411.558555] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  411.558668] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  411.558848] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.558939] [drm:intel_power_well_disable [i915]] disabling DC off
>[  411.559025] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  411.559098] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  411.559685] [drm:intel_power_well_disable [i915]] disabling always-on
>[  411.560594] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.560717] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  411.560973] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  411.561065] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.561158] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  411.561247] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  411.561342] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.561433] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  411.561526] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  411.561614] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  411.561705] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.561780] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.561869] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.561888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.561984] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  411.562076] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  411.562173] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  411.562269] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.562365] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  411.562465] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  411.562560] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.562653] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  411.562791] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  411.562882] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  411.562980] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  411.563106] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  411.563217] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  411.563312] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  411.563600] [drm:intel_power_well_enable [i915]] enabling always-on
>[  411.563677] [drm:intel_power_well_enable [i915]] enabling DC off
>[  411.564056] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  411.564115] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  411.564157] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  411.564221] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  411.564507] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  411.568798] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.568842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.568887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.568933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.568975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.569016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.569058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.569097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.569140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.569180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.569223] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.569266] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.569308] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.569381] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  411.569420] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  411.569747] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  411.570894] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  411.571436] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  411.571478] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  411.571538] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  411.571576] [drm:hsw_audio_config_update [i915]] using automatic N
>[  411.588510] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.588569] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.588894] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.589439] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.589613] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  411.605110] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  411.605189] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.605320] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  411.622020] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  411.622194] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  411.622380] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  411.626645] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.626798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.626887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.626976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.627058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.627139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.627219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.627308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.627389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.627470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.627550] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.627640] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.627810] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.627896] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.628020] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  411.628104] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  411.628216] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  411.628337] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.628425] [drm:intel_power_well_disable [i915]] disabling DC off
>[  411.628507] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  411.628581] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  411.629220] [drm:intel_power_well_disable [i915]] disabling always-on
>[  411.630197] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.630243] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  411.630493] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  411.630582] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.630676] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  411.630864] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  411.630959] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.631050] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  411.631142] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  411.631232] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  411.631323] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.631337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.631425] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.631438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.631529] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  411.631619] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  411.631712] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  411.631849] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.631941] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  411.632037] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  411.632128] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.632220] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  411.632314] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  411.632402] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  411.632494] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  411.632624] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  411.632765] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  411.632857] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  411.633169] [drm:intel_power_well_enable [i915]] enabling always-on
>[  411.633246] [drm:intel_power_well_enable [i915]] enabling DC off
>[  411.633583] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  411.633699] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  411.633822] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  411.633902] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  411.634460] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  411.638710] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.638822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.638861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.638899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.638935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.638970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.639005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.639039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.639074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.639109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.639144] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.639180] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.639216] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.639282] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  411.639315] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  411.639601] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  411.640603] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  411.641176] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  411.641211] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  411.641263] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  411.641297] [drm:hsw_audio_config_update [i915]] using automatic N
>[  411.658264] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.658339] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.658551] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.659194] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.659369] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  411.674827] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  411.674916] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.675057] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  411.691810] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  411.691982] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  411.692166] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  411.696455] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.696548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.696646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.697139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.697230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.697319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.697409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.697508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.697598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.697687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.698439] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.698548] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.698647] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.699099] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.699232] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  411.699323] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  411.699442] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  411.699574] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.699668] [drm:intel_power_well_disable [i915]] disabling DC off
>[  411.700334] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  411.700415] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  411.701625] [drm:intel_power_well_disable [i915]] disabling always-on
>[  411.702561] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.702606] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  411.703270] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  411.703362] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.703456] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  411.703541] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  411.703631] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.704228] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  411.704318] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  411.704406] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  411.704494] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.704508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.704594] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.704606] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.704694] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  411.705522] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  411.705609] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  411.705698] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.706141] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  411.706239] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  411.706328] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.706416] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  411.706506] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  411.706595] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  411.706684] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  411.707188] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  411.707235] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  411.707269] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  411.707405] [drm:intel_power_well_enable [i915]] enabling always-on
>[  411.707433] [drm:intel_power_well_enable [i915]] enabling DC off
>[  411.707945] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  411.708338] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  411.708372] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  411.708425] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  411.708879] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  411.713104] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.713181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.713219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.713257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.713293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.713328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.713363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.713398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.713433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.713466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.713503] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.713539] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.713576] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.713644] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  411.714158] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  411.714413] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  411.715503] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  411.716130] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  411.716164] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  411.716215] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  411.716247] [drm:hsw_audio_config_update [i915]] using automatic N
>[  411.733217] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.733291] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.733506] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.734259] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.734414] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  411.749797] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  411.749867] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.749985] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  411.766631] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  411.766868] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  411.767036] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  411.771283] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.771367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.771457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.771547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.771628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.772191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.772273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.772365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.772447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.772529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.772611] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.773212] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.773301] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.773387] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.773508] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  411.773590] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  411.774183] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  411.774307] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.774396] [drm:intel_power_well_disable [i915]] disabling DC off
>[  411.774477] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  411.774550] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  411.775792] [drm:intel_power_well_disable [i915]] disabling always-on
>[  411.776623] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.776744] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  411.776975] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  411.777056] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.777141] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  411.777218] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  411.777306] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.777386] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  411.777469] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  411.777549] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  411.777631] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.777713] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.777792] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.777805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.777886] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  411.777966] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  411.778054] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  411.778140] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.778227] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  411.778315] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  411.778399] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.778486] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  411.778574] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  411.778659] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  411.778793] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  411.778881] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  411.778957] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  411.779018] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  411.779221] [drm:intel_power_well_enable [i915]] enabling always-on
>[  411.779271] [drm:intel_power_well_enable [i915]] enabling DC off
>[  411.779578] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  411.779656] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  411.779757] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  411.779844] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  411.780168] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  411.784401] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.784463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.784528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.784593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.784652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.784778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.784839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.784901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.784965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.785025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.785086] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.785155] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.785219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.785324] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  411.785364] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  411.785636] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  411.786803] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  411.787361] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  411.787400] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  411.787459] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  411.787495] [drm:hsw_audio_config_update [i915]] using automatic N
>[  411.804418] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.804473] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.804648] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.805359] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.805521] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  411.821042] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  411.821119] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.821242] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  411.837976] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  411.838137] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  411.838307] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  411.842551] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.842639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.842837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.843231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.843313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.843394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.843475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.843564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.843646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.843811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.843899] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.844001] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.844097] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.844624] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.844783] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  411.845163] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  411.845276] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  411.845395] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  411.845481] [drm:intel_power_well_disable [i915]] disabling DC off
>[  411.845566] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  411.845638] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  411.847009] [drm:intel_power_well_disable [i915]] disabling always-on
>[  411.848346] [drm:drm_mode_addfb2] [FB:71]
>[  411.848474] [drm:drm_mode_addfb2] [FB:91]
>[  411.905664] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  411.906109] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  411.906911] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  411.907322] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  411.907343] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  411.907446] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  411.907479] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  411.907517] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  411.907549] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  411.907585] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  411.907619] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  411.907654] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  411.907765] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  411.907799] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  411.907805] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.907839] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  411.907845] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  411.907881] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  411.907915] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  411.907950] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  411.907986] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  411.908021] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  411.908057] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  411.908090] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  411.908127] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  411.908162] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  411.908197] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  411.908250] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  411.908297] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  411.908331] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  411.908662] [drm:intel_power_well_enable [i915]] enabling always-on
>[  411.908731] [drm:intel_power_well_enable [i915]] enabling DC off
>[  411.909022] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  411.909072] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  411.909106] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  411.909162] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  411.909448] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  411.913687] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  411.913797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  411.913836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  411.913875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  411.913911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  411.913946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  411.913980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  411.914015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  411.914050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  411.914085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  411.914120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  411.914156] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  411.914192] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.914258] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  411.914292] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  411.914578] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  411.915705] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  411.916218] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  411.916252] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  411.916304] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  411.916336] [drm:hsw_audio_config_update [i915]] using automatic N
>[  411.933285] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  411.933360] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  411.933571] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  411.949863] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  411.949890] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  411.966809] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  411.966959] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  411.983226] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  411.983300] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  411.983415] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  412.001197] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  412.001360] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  412.001513] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  412.005777] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.005854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.005936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.006019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.006093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.006167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.006241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.006322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.006396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.006470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.006543] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.006627] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.006825] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.006907] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.007021] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  412.007096] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  412.007202] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  412.007311] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.007389] [drm:intel_power_well_disable [i915]] disabling DC off
>[  412.007464] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  412.007533] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  412.008185] [drm:intel_power_well_disable [i915]] disabling always-on
>[  412.009044] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.009083] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  412.009297] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  412.009372] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.009450] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  412.009522] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  412.009596] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.009669] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  412.009819] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  412.009892] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  412.009970] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.009981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.010058] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.010068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.010142] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  412.010218] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  412.010291] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  412.010366] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.010439] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  412.010520] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  412.010592] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.010667] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  412.010783] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  412.010857] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  412.010964] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  412.011058] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  412.011135] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  412.011393] [drm:intel_power_well_enable [i915]] enabling always-on
>[  412.011455] [drm:intel_power_well_enable [i915]] enabling DC off
>[  412.011852] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  412.012416] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  412.012489] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  412.012674] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  412.013351] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  412.017625] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.017785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.017830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.017873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.017911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.017951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.017991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.018031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.018070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.018108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.018149] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.018190] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.018231] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.018303] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  412.018342] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  412.018610] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  412.019768] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  412.020308] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  412.020347] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  412.020405] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  412.020442] [drm:hsw_audio_config_update [i915]] using automatic N
>[  412.037384] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.037441] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.037619] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.038192] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.038354] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  412.053982] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  412.054057] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  412.054184] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  412.070937] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  412.071100] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  412.071252] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  412.075523] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.075609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.075698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.075895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.075988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.076072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.076154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.076247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.076329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.076415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.076498] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.076594] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.076683] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.076861] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.077002] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  412.077099] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  412.077223] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  412.077355] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.077451] [drm:intel_power_well_disable [i915]] disabling DC off
>[  412.077543] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  412.077624] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  412.078254] [drm:intel_power_well_disable [i915]] disabling always-on
>[  412.079284] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.079331] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  412.079584] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  412.079674] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.079859] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  412.079955] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  412.080055] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.080151] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  412.080246] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  412.080341] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  412.080429] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.080446] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.080531] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.080544] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.080632] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  412.080781] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  412.080873] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  412.080971] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.081062] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  412.081166] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  412.081257] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.081355] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  412.081452] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  412.081550] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  412.081697] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  412.081824] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  412.081893] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  412.082139] [drm:intel_power_well_enable [i915]] enabling always-on
>[  412.082197] [drm:intel_power_well_enable [i915]] enabling DC off
>[  412.082510] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  412.082600] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  412.082668] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  412.082813] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  412.083467] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  412.087723] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.087836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.087875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.087914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.087949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.087984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.088019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.088054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.088089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.088124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.088159] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.088195] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.088231] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.088297] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  412.088330] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  412.088616] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  412.089819] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  412.090331] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  412.090366] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  412.090418] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  412.090450] [drm:hsw_audio_config_update [i915]] using automatic N
>[  412.107404] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.107475] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.107784] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.108276] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.108427] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  412.124020] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  412.124097] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  412.124218] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  412.140944] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  412.141107] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  412.141256] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  412.145510] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.145594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.145681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.145870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.145953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.146037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.146119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.146212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.146294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.146378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.146460] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.146555] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.146645] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.146786] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.146911] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  412.146997] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  412.147108] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  412.147226] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.147312] [drm:intel_power_well_disable [i915]] disabling DC off
>[  412.147394] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  412.147469] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  412.148118] [drm:intel_power_well_disable [i915]] disabling always-on
>[  412.149045] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.149086] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  412.149310] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  412.149391] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.149475] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  412.149551] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  412.149631] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.149791] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  412.149875] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  412.149958] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  412.150042] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.150059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.150140] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.150156] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.150242] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  412.150325] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  412.150413] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  412.150497] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.150583] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  412.150673] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  412.150796] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.150881] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  412.150964] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  412.151044] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  412.151166] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  412.151269] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  412.151349] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  412.151631] [drm:intel_power_well_enable [i915]] enabling always-on
>[  412.151760] [drm:intel_power_well_enable [i915]] enabling DC off
>[  412.152087] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  412.152201] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  412.152251] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  412.152326] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  412.152639] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  412.156939] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.156983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.157028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.157074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.157116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.157158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.157197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.157239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.157280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.157322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.157364] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.157407] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.157450] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.157525] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  412.157564] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  412.157893] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  412.159028] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  412.159552] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  412.159593] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  412.159653] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  412.159738] [drm:hsw_audio_config_update [i915]] using automatic N
>[  412.176613] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.176796] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.177027] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.177573] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.177815] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  412.193299] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  412.193395] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  412.193551] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  412.211210] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  412.211383] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  412.211546] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  412.213787] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.213871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.213958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.214047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.214129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.214210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.214291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.214379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.214460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.214540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.214620] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.214782] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.214873] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.214964] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.215088] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  412.215170] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  412.215280] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  412.215395] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.215477] [drm:intel_power_well_disable [i915]] disabling DC off
>[  412.215558] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  412.215632] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  412.216315] [drm:intel_power_well_disable [i915]] disabling always-on
>[  412.217295] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.217341] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  412.217583] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  412.217672] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.217840] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  412.217929] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  412.218022] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.218114] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  412.218208] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  412.218297] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  412.218388] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.218402] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.218487] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.218503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.218591] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  412.218681] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  412.218820] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  412.218907] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.218999] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  412.219094] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  412.219185] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.219276] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  412.219370] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  412.219459] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  412.219589] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  412.219702] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  412.219838] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  412.220138] [drm:intel_power_well_enable [i915]] enabling always-on
>[  412.220214] [drm:intel_power_well_enable [i915]] enabling DC off
>[  412.220550] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  412.220663] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  412.220796] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  412.220922] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  412.221901] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  412.226141] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.226210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.226249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.226289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.226326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.226362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.226398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.226434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.226470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.226505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.226542] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.226580] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.226617] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.226816] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  412.226851] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  412.227144] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  412.228245] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  412.228858] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  412.228893] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  412.228945] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  412.228978] [drm:hsw_audio_config_update [i915]] using automatic N
>[  412.245938] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.245991] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.246159] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.246502] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.246605] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  412.262528] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  412.262600] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  412.262825] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  412.279441] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  412.279601] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  412.279850] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  412.284102] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.284178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.284257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.284338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.284412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.284486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.284560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.284641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.284800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.284879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.284958] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.285051] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.285129] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.285210] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.285318] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  412.285394] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  412.285497] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  412.285605] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.285683] [drm:intel_power_well_disable [i915]] disabling DC off
>[  412.285850] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  412.285927] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  412.286518] [drm:intel_power_well_disable [i915]] disabling always-on
>[  412.287488] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.287530] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  412.287824] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  412.287905] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.287992] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  412.288069] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  412.288156] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.288238] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  412.288323] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  412.288403] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  412.288487] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.288500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.288579] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.288591] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.288670] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  412.288825] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  412.288902] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  412.288978] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.289053] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  412.289139] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  412.289214] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.289293] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  412.289371] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  412.289451] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  412.289558] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  412.289658] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  412.289774] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  412.290022] [drm:intel_power_well_enable [i915]] enabling always-on
>[  412.290083] [drm:intel_power_well_enable [i915]] enabling DC off
>[  412.290401] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  412.290499] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  412.290572] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  412.290676] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  412.291028] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  412.295217] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.295262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.295309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.295357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.295402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.295443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.295487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.295530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.295574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.295615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.295660] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.295763] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.295812] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.295889] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  412.295931] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  412.296213] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  412.297405] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  412.297989] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  412.298033] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  412.298098] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  412.298139] [drm:hsw_audio_config_update [i915]] using automatic N
>[  412.315048] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.315108] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.315293] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.315795] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.315968] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  412.331649] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  412.331781] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  412.331908] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  412.348551] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  412.348870] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  412.349052] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  412.353336] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.353428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.353525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.353624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.353714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.353914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.354006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.354116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.354205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.354295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.354384] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.354487] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.354588] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.354688] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.354880] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  412.354975] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  412.355096] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  412.355223] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.355315] [drm:intel_power_well_disable [i915]] disabling DC off
>[  412.355408] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  412.355491] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  412.356151] [drm:intel_power_well_disable [i915]] disabling always-on
>[  412.357111] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.357157] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  412.357404] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  412.357496] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.357590] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  412.357678] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  412.357853] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.357950] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  412.358045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  412.358142] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  412.358233] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.358253] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.358340] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.358357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.358453] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  412.358547] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  412.358642] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  412.358778] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.358871] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  412.358969] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  412.359063] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.359158] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  412.359253] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  412.359342] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  412.359479] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  412.359589] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  412.359678] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  412.360033] [drm:intel_power_well_enable [i915]] enabling always-on
>[  412.360107] [drm:intel_power_well_enable [i915]] enabling DC off
>[  412.360440] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  412.360539] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  412.360578] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  412.360640] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  412.360926] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  412.365167] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.365211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.365256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.365303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.365345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.365386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.365428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.365468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.365511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.365550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.365593] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.365636] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.365734] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.365809] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  412.365849] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  412.366122] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  412.367252] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  412.367815] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  412.367858] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  412.367921] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  412.367960] [drm:hsw_audio_config_update [i915]] using automatic N
>[  412.384875] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.384933] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.385113] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.385505] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.385620] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  412.401489] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  412.401569] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  412.401815] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  412.418487] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  412.418659] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  412.418937] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  412.423236] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.423329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.423425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.423525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.423615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.423705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.423899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.424006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.424096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.424187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.424275] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.424378] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.424480] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.424581] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.424781] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  412.424877] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  412.425001] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  412.425130] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.425222] [drm:intel_power_well_disable [i915]] disabling DC off
>[  412.425311] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  412.425394] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  412.426059] [drm:intel_power_well_disable [i915]] disabling always-on
>[  412.427013] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.427063] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  412.427309] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  412.427400] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.427495] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  412.427583] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  412.427675] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.427847] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  412.427940] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  412.428041] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  412.428134] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.428153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.428240] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.428259] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.428355] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  412.428450] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  412.428546] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  412.428633] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.428770] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  412.428866] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  412.428957] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.429049] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  412.429142] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  412.429233] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  412.429341] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  412.429398] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  412.429440] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  412.429596] [drm:intel_power_well_enable [i915]] enabling always-on
>[  412.429633] [drm:intel_power_well_enable [i915]] enabling DC off
>[  412.429958] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  412.430020] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  412.430062] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  412.430128] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  412.430394] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  412.434633] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.434708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.434753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.434799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.434841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.434880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.434922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.434963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.435005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.435044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.435086] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.435130] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.435172] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.435246] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  412.435285] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  412.435556] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  412.436702] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  412.437226] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  412.437267] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  412.437327] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  412.437365] [drm:hsw_audio_config_update [i915]] using automatic N
>[  412.454285] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.454348] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.454536] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.455147] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.455320] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  412.470893] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  412.470972] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  412.471102] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  412.487823] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  412.487994] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  412.488157] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  412.492416] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.492499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.492586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.492674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.492851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.492938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.493021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.493113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.493193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.493275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.493354] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.493449] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.493537] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.493627] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.493804] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  412.493890] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  412.493999] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  412.494115] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.494198] [drm:intel_power_well_disable [i915]] disabling DC off
>[  412.494277] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  412.494347] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  412.495034] [drm:intel_power_well_disable [i915]] disabling always-on
>[  412.495948] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.495994] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  412.496245] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  412.496337] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.496430] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  412.496519] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  412.496611] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.496701] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  412.496857] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  412.496950] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  412.497044] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.497062] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.497148] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.497166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.497256] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  412.497347] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  412.497441] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  412.497536] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.497629] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  412.497772] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  412.497860] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.497956] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  412.498050] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  412.498143] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  412.498272] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  412.498382] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  412.498471] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  412.498831] [drm:intel_power_well_enable [i915]] enabling always-on
>[  412.498906] [drm:intel_power_well_enable [i915]] enabling DC off
>[  412.499236] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  412.499352] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  412.499435] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  412.499555] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  412.499925] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  412.504048] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.504087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.504128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.504171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.504209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.504247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.504285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.504322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.504360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.504398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.504437] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.504479] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.504519] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.504589] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  412.504627] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  412.504942] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  412.506056] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  412.506595] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  412.506634] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  412.506727] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  412.506765] [drm:hsw_audio_config_update [i915]] using automatic N
>[  412.523655] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.523749] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.523926] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.524294] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.524404] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  412.540259] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  412.540332] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  412.540452] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  412.557068] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  412.557230] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  412.557379] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  412.561647] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.561796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.561883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.561973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.562055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.562136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.562217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.562304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.562386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.562465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.562547] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.562637] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.562800] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.562889] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.563011] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  412.563096] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  412.563207] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  412.563322] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.563406] [drm:intel_power_well_disable [i915]] disabling DC off
>[  412.563488] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  412.563560] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  412.564215] [drm:intel_power_well_disable [i915]] disabling always-on
>[  412.565118] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.565160] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  412.565384] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  412.565466] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.565551] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  412.565630] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  412.565787] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.565875] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  412.565960] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  412.566045] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  412.566131] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.566147] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.566231] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.566245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.566330] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  412.566409] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  412.566492] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  412.566572] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.566655] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  412.566783] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  412.566871] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.566954] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  412.567041] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  412.567119] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  412.567234] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  412.567336] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  412.567420] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  412.567690] [drm:intel_power_well_enable [i915]] enabling always-on
>[  412.567818] [drm:intel_power_well_enable [i915]] enabling DC off
>[  412.568150] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  412.568258] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  412.568334] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  412.568448] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  412.568795] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  412.572959] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.573002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.573047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.573092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.573134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.573174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.573215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.573255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.573296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.573336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.573379] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.573422] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.573464] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.573538] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  412.573577] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  412.573899] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  412.575049] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  412.575572] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  412.575614] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  412.575714] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  412.575755] [drm:hsw_audio_config_update [i915]] using automatic N
>[  412.592620] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.592783] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.593013] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.593536] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.593763] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  412.609237] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  412.609318] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  412.609445] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  412.625972] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  412.626134] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  412.626285] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  412.630574] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.630667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.630873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.630975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.631066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.631154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.631244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.631345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.631439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.631531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.631624] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.631755] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.631859] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.631960] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.632101] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  412.632194] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  412.632314] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  412.632442] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.632536] [drm:intel_power_well_disable [i915]] disabling DC off
>[  412.632628] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  412.632776] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  412.633379] [drm:intel_power_well_disable [i915]] disabling always-on
>[  412.634398] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.634443] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  412.634689] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  412.634869] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.634971] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  412.635063] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  412.635156] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.635245] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  412.635334] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  412.635423] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  412.635514] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.635529] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.635617] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.635630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.635778] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  412.635871] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  412.635965] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  412.636064] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.636156] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  412.636260] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  412.636351] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.636449] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  412.636539] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  412.636635] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  412.636813] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  412.636927] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  412.637022] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  412.637331] [drm:intel_power_well_enable [i915]] enabling always-on
>[  412.637406] [drm:intel_power_well_enable [i915]] enabling DC off
>[  412.637802] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  412.638343] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  412.638385] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  412.638448] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  412.638759] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  412.642997] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.643073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.643111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.643150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.643185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.643218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.643255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.643288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.643323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.643356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.643392] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.643428] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.643464] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.643529] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  412.643561] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  412.643860] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  412.644851] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  412.645364] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  412.645398] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  412.645450] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  412.645482] [drm:hsw_audio_config_update [i915]] using automatic N
>[  412.662430] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.662491] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.662778] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.663271] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.663420] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  412.679066] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  412.679147] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  412.679267] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  412.695930] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  412.696093] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  412.696243] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  412.700503] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.700586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.700674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.700862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.700943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.701024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.701103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.701196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.701279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.701364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.701445] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.701541] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.701632] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.701773] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.701899] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  412.701981] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  412.702091] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  412.702206] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.702289] [drm:intel_power_well_disable [i915]] disabling DC off
>[  412.702373] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  412.702448] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  412.703093] [drm:intel_power_well_disable [i915]] disabling always-on
>[  412.704012] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.704054] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  412.704277] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  412.704359] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.704444] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  412.704520] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  412.704601] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.704681] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  412.704846] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  412.704932] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  412.705014] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.705033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.705112] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.705129] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.705216] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  412.705299] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  412.705386] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  412.705469] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.705556] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  412.705647] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  412.705770] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.705859] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  412.705944] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  412.706027] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  412.706144] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  412.706247] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  412.706327] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  412.706601] [drm:intel_power_well_enable [i915]] enabling always-on
>[  412.706672] [drm:intel_power_well_enable [i915]] enabling DC off
>[  412.707082] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  412.707195] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  412.707277] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  412.707346] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  412.707650] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  412.711951] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.711995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.712040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.712086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.712128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.712170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.712211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.712251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.712292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.712332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.712375] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.712418] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.712462] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.712536] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  412.712575] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  412.712902] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  412.714031] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  412.714554] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  412.714595] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  412.714655] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  412.714739] [drm:hsw_audio_config_update [i915]] using automatic N
>[  412.731611] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.731786] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.732017] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.732543] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.732780] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  412.748224] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  412.748303] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  412.748432] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  412.765010] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  412.765182] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  412.765344] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  412.769632] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.769798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.769896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.769995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.770085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.770175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.770265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.770363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.770452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.770541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.770630] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.770818] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.770922] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.771025] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.771173] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  412.771263] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  412.771391] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  412.771517] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.771609] [drm:intel_power_well_disable [i915]] disabling DC off
>[  412.771697] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  412.771838] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  412.772443] [drm:intel_power_well_disable [i915]] disabling always-on
>[  412.773452] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.773497] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  412.773832] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  412.773922] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.774017] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  412.774102] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  412.774198] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.774289] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  412.774381] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  412.774470] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  412.774561] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.774575] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.774660] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.774732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.774821] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  412.774915] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  412.775010] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  412.775103] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.775197] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  412.775298] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  412.775391] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.775483] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  412.775582] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  412.775674] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  412.775854] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  412.775971] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  412.776066] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  412.776372] [drm:intel_power_well_enable [i915]] enabling always-on
>[  412.776447] [drm:intel_power_well_enable [i915]] enabling DC off
>[  412.776851] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  412.777368] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  412.777412] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  412.777479] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  412.777791] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  412.782034] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.782111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.782149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.782188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.782223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.782258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.782293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.782326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.782361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.782394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.782430] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.782467] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.782502] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.782568] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  412.782600] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  412.782938] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  412.783922] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  412.784436] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  412.784470] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  412.784522] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  412.784554] [drm:hsw_audio_config_update [i915]] using automatic N
>[  412.801512] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.801586] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.801883] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.802369] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.802519] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  412.818108] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  412.818178] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  412.818292] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  412.835031] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  412.835193] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  412.835344] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  412.839588] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.839664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.839829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.839910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.839984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.840056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.840132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.840215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.840291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.840367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.840443] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.840528] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.840609] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.840713] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.840901] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  412.840999] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  412.841125] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  412.841251] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.841343] [drm:intel_power_well_disable [i915]] disabling DC off
>[  412.841431] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  412.841510] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  412.842767] [drm:intel_power_well_disable [i915]] disabling always-on
>[  412.843744] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.843790] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  412.844043] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  412.844132] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.844225] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  412.844310] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  412.844399] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.844487] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  412.844575] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  412.844660] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  412.844836] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.844850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.844938] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.844957] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.845048] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  412.845140] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  412.845236] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  412.845329] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.845423] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  412.845524] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  412.845620] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.845715] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  412.845855] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  412.845950] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  412.846083] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  412.846196] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  412.846287] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  412.846590] [drm:intel_power_well_enable [i915]] enabling always-on
>[  412.846665] [drm:intel_power_well_enable [i915]] enabling DC off
>[  412.847039] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  412.847104] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  412.847151] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  412.847223] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  412.847513] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  412.851821] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.851857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.851896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.851934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.851969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.852004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.852037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.852072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.852107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.852140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.852176] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.852213] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.852250] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.852315] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  412.852348] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  412.852635] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  412.853621] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  412.854169] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  412.854204] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  412.854255] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  412.854288] [drm:hsw_audio_config_update [i915]] using automatic N
>[  412.871232] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.871300] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.871496] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.872066] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.872218] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  412.887864] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  412.887945] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  412.888075] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  412.904672] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  412.904905] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  412.905057] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  412.909303] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.909380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.909459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.909541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.909615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.909689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.909851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.909938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.910016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.910090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.910162] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.910247] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.910325] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.910407] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.910520] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  412.910598] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  412.910793] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  412.910930] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.911030] [drm:intel_power_well_disable [i915]] disabling DC off
>[  412.911119] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  412.911200] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  412.911856] [drm:intel_power_well_disable [i915]] disabling always-on
>[  412.912778] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.912826] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  412.913074] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  412.913165] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.913260] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  412.913348] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  412.913437] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.913527] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  412.913617] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  412.913705] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  412.913871] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.913895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.913983] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.913999] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.914088] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  412.914182] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  412.914275] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  412.914374] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.914466] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  412.914569] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  412.914662] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.914798] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  412.914889] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  412.914982] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  412.915114] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  412.915226] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  412.915319] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  412.915624] [drm:intel_power_well_enable [i915]] enabling always-on
>[  412.915763] [drm:intel_power_well_enable [i915]] enabling DC off
>[  412.916097] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  412.916214] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  412.916300] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  412.916427] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  412.916898] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  412.921145] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.921188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.921233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.921279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.921321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.921362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.921404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.921446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.921487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.921526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.921569] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.921613] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.921655] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.921782] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  412.921823] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  412.922098] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  412.923226] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  412.923787] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  412.923831] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  412.923892] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  412.923932] [drm:hsw_audio_config_update [i915]] using automatic N
>[  412.940816] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.940877] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.941063] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.941467] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.941587] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  412.957467] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  412.957549] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  412.957680] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  412.974456] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  412.974620] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  412.975232] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  412.979504] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.979587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.979679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.979873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.980264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.980345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.980426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.980518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.980599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.980678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.980842] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  412.980946] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.981036] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.981126] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.981581] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  412.981667] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  412.981833] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  412.982237] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  412.982325] [drm:intel_power_well_disable [i915]] disabling DC off
>[  412.982407] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  412.982478] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  412.983150] [drm:intel_power_well_disable [i915]] disabling always-on
>[  412.984444] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  412.984487] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  412.984717] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  412.984927] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  412.985028] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  412.985119] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  412.985220] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  412.985315] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  412.986137] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  412.986229] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  412.986314] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  412.986326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.986413] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  412.986422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  412.986510] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  412.986596] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  412.986685] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  412.986866] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  412.986962] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  412.987063] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  412.987159] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  412.987256] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  412.987351] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  412.987440] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  412.987586] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  412.988413] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  412.988508] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  412.988888] [drm:intel_power_well_enable [i915]] enabling always-on
>[  412.988967] [drm:intel_power_well_enable [i915]] enabling DC off
>[  412.989300] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  412.989417] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  412.989503] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  412.989628] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  412.990288] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  412.994523] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  412.994594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  412.994631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  412.994721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  412.994910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  412.994945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  412.994979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  412.995014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  412.995049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  412.995084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  412.995119] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  412.995157] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  412.995193] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  412.995259] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  412.995294] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  412.995546] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  412.996820] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  412.997334] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  412.997368] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  412.997420] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  412.997452] [drm:hsw_audio_config_update [i915]] using automatic N
>[  413.014413] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.014489] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.014782] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.015274] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.015428] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  413.030948] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  413.031017] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.031133] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  413.047789] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  413.047949] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  413.048100] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  413.052399] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.052492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.052589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.052687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.052886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.052982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.053077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.053184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.053275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.053368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.053459] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.053565] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.053663] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.053822] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.053959] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  413.054050] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  413.054173] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  413.054304] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.054398] [drm:intel_power_well_disable [i915]] disabling DC off
>[  413.054490] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  413.054573] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  413.055239] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.056194] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.056239] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  413.056487] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  413.056576] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.056669] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  413.056848] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  413.056944] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.057040] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  413.057135] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  413.057226] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  413.057327] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.057345] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.057432] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.057447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.057540] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  413.057629] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  413.057765] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  413.057858] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.057954] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.058051] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  413.058147] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.058241] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  413.058330] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  413.058418] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  413.058545] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  413.058655] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  413.058813] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  413.059073] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.059136] [drm:intel_power_well_enable [i915]] enabling DC off
>[  413.059453] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  413.059517] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  413.059565] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  413.059635] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  413.059959] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  413.064204] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.064247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.064292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.064338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.064380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.064419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.064462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.064501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.064542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.064582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.064625] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.064720] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.064767] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.064843] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  413.064883] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  413.065161] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  413.066289] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  413.066850] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  413.066894] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  413.066955] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  413.066995] [drm:hsw_audio_config_update [i915]] using automatic N
>[  413.083948] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.084034] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.084263] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.084882] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.085053] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  413.100557] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  413.100642] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.100930] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  413.117601] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  413.117916] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  413.118097] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  413.122383] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.122476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.122573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.122672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.122870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.122963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.123061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.123167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.123257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.123349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.123436] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.123542] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.123637] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.123790] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.123926] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  413.124016] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  413.124136] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  413.124264] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.124358] [drm:intel_power_well_disable [i915]] disabling DC off
>[  413.124450] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  413.124533] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  413.125192] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.126108] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.126155] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  413.126405] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  413.126497] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.126592] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  413.126680] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  413.126860] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.126959] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  413.127052] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  413.127150] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  413.127243] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.127264] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.127351] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.127370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.127463] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  413.127557] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  413.127646] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  413.127787] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.127877] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.127977] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  413.128065] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.128160] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  413.128254] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  413.128344] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  413.128470] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  413.128586] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  413.128631] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  413.128827] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.128863] [drm:intel_power_well_enable [i915]] enabling DC off
>[  413.129154] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  413.129214] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  413.129256] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  413.129321] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  413.129597] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  413.133852] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.133895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.133941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.133987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.134029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.134070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.134112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.134153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.134194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.134234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.134276] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.134319] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.134362] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.134436] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  413.134475] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  413.134795] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  413.135925] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  413.136447] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  413.136488] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  413.136548] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  413.136587] [drm:hsw_audio_config_update [i915]] using automatic N
>[  413.153506] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.153570] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.153878] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.154406] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.154575] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  413.170119] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  413.170198] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.170325] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  413.186997] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  413.187166] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  413.187328] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  413.191566] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.191651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.191844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.191938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.192022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.192106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.192189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.192282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.192364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.192449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.192531] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.192627] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.192763] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.192868] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.193005] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  413.193097] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  413.193223] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  413.193350] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.193444] [drm:intel_power_well_disable [i915]] disabling DC off
>[  413.193535] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  413.193614] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  413.194292] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.195221] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.195266] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  413.195514] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  413.195603] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.195696] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  413.195869] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  413.195964] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.196064] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  413.196154] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  413.196249] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  413.196343] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.196362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.196449] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.196468] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.196564] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  413.196657] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  413.196795] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  413.196890] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.196981] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.197082] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  413.197178] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.197268] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  413.197361] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  413.197451] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  413.197578] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  413.197693] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  413.197844] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  413.198148] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.198226] [drm:intel_power_well_enable [i915]] enabling DC off
>[  413.198549] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  413.198617] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  413.198667] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  413.198775] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  413.199021] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  413.203264] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.203308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.203352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.203398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.203440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.203479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.203521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.203560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.203600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.203641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.203733] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.203781] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.203829] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.203906] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  413.203947] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  413.204223] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  413.205353] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  413.205914] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  413.205957] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  413.206022] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  413.206062] [drm:hsw_audio_config_update [i915]] using automatic N
>[  413.222970] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.223039] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.223235] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.223779] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.223949] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  413.239580] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  413.239659] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.239874] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  413.256548] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  413.256826] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  413.256993] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  413.261255] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.261339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.261428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.261518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.261599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.261680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.261857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.261953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.262038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.262125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.262206] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.262299] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.262387] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.262475] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.262597] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  413.262682] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  413.262848] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  413.262970] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.263054] [drm:intel_power_well_disable [i915]] disabling DC off
>[  413.263136] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  413.263208] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  413.263846] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.264774] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.264816] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  413.265040] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  413.265121] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.265205] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  413.265282] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  413.265362] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.265441] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  413.265521] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  413.265598] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  413.265674] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.265764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.265846] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.265860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.265944] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  413.266027] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  413.266115] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  413.266199] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.266284] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.266371] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  413.266458] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.266544] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  413.266635] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  413.266760] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  413.266880] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  413.266983] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  413.267066] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  413.267335] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.267404] [drm:intel_power_well_enable [i915]] enabling DC off
>[  413.267765] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  413.268329] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  413.268378] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  413.268453] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  413.268790] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  413.273036] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.273079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.273124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.273170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.273212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.273253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.273293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.273334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.273374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.273416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.273461] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.273504] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.273546] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.273619] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  413.273658] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  413.273987] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  413.275115] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  413.275638] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  413.275718] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  413.275779] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  413.275819] [drm:hsw_audio_config_update [i915]] using automatic N
>[  413.292795] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.292882] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.293109] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.293702] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.293874] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  413.309307] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  413.309387] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.309515] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  413.326181] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  413.326358] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  413.326519] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  413.330792] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.330876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.330964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.331053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.331135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.331217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.331298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.331387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.331467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.331546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.331628] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.331802] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.331896] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.331992] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.332112] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  413.332195] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  413.332308] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  413.332424] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.332510] [drm:intel_power_well_disable [i915]] disabling DC off
>[  413.332592] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  413.332666] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  413.333377] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.334364] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.334409] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  413.334657] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  413.334839] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.334936] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  413.335031] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  413.335125] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.335223] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  413.335317] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  413.335409] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  413.335497] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.335514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.335599] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.335612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.335701] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  413.335851] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  413.335946] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  413.336042] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.336136] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.336241] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  413.336332] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.336431] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  413.336521] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  413.336617] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  413.336770] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  413.336887] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  413.336980] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  413.337284] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.337362] [drm:intel_power_well_enable [i915]] enabling DC off
>[  413.337693] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  413.338306] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  413.338353] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  413.338423] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  413.338761] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  413.343003] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.343083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.343121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.343159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.343194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.343229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.343262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.343297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.343332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.343365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.343401] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.343437] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.343473] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.343538] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  413.343571] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  413.343865] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  413.344849] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  413.345361] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  413.345396] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  413.345447] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  413.345479] [drm:hsw_audio_config_update [i915]] using automatic N
>[  413.362426] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.362495] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.362799] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.363259] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.363411] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  413.379031] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  413.379101] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.379213] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  413.395871] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  413.396031] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  413.396181] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  413.400439] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.400522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.400612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.400700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.400882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.400972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.401059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.401155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.401238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.401322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.401404] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.401499] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.401590] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.401678] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.401847] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  413.401932] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  413.402044] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  413.402160] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.402246] [drm:intel_power_well_disable [i915]] disabling DC off
>[  413.402328] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  413.402401] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  413.403056] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.403970] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.404012] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  413.404236] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  413.404318] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.404402] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  413.404479] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  413.404560] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.404639] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  413.404797] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  413.404878] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  413.404965] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.404981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.405064] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.405078] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.405164] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  413.405248] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  413.405333] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  413.405418] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.405505] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.405598] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  413.405684] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.405811] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  413.405899] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  413.405981] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  413.406103] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  413.406205] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  413.406289] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  413.406557] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.406627] [drm:intel_power_well_enable [i915]] enabling DC off
>[  413.406975] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  413.407058] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  413.407116] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  413.407199] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  413.407527] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  413.411781] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.411824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.411869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.411915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.411956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.411998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.412037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.412079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.412120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.412159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.412201] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.412245] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.412287] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.412362] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  413.412401] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  413.412723] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  413.413843] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  413.414365] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  413.414406] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  413.414466] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  413.414505] [drm:hsw_audio_config_update [i915]] using automatic N
>[  413.431426] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.431499] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.431818] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.432347] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.432521] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  413.447999] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  413.448082] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.448209] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  413.464929] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  413.465099] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  413.465261] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  413.469542] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.469637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.469842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.469947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.470039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.470133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.470224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.470327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.470416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.470510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.470601] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.470707] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.470860] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.470963] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.471099] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  413.471190] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  413.471313] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  413.471442] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.471537] [drm:intel_power_well_disable [i915]] disabling DC off
>[  413.471629] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  413.471773] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  413.472376] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.473388] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.473433] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  413.473681] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  413.473856] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.473955] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  413.474049] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  413.474144] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.474243] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  413.474337] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  413.474432] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  413.474521] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.474538] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.474623] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.474661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.474750] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  413.474840] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  413.474930] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  413.475019] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.475108] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.475214] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  413.475305] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.475402] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  413.475497] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  413.475594] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  413.475775] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  413.475889] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  413.475982] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  413.476299] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.476346] [drm:intel_power_well_enable [i915]] enabling DC off
>[  413.476645] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  413.476758] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  413.476815] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  413.476897] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  413.477218] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  413.481388] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.481431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.481477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.481523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.481565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.481606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.481646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.481742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.481788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.481833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.481877] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.481926] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.481972] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.482047] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  413.482088] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  413.482360] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  413.483487] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  413.484048] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  413.484090] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  413.484152] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  413.484192] [drm:hsw_audio_config_update [i915]] using automatic N
>[  413.501105] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.501173] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.501368] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.501943] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.502118] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  413.517762] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  413.517840] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.517970] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  413.534631] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  413.534875] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  413.535038] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  413.539298] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.539381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.539470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.539559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.539640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.539818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.539904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.539999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.540085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.540173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.540254] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.540348] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.540435] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.540523] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.540645] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  413.540820] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  413.540947] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  413.541076] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.541170] [drm:intel_power_well_disable [i915]] disabling DC off
>[  413.541260] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  413.541342] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  413.542003] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.542955] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.543002] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  413.543249] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  413.543340] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.543434] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  413.543521] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  413.543611] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.543701] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  413.543870] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  413.543966] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  413.544056] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.544075] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.544162] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.544181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.544276] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  413.544371] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  413.544468] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  413.544560] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.544657] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.544800] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  413.544900] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.544992] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  413.545088] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  413.545177] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  413.545308] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  413.545420] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  413.545511] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  413.545862] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.545939] [drm:intel_power_well_enable [i915]] enabling DC off
>[  413.546248] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  413.546305] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  413.546346] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  413.546410] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  413.546669] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  413.550950] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.550993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.551039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.551085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.551127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.551168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.551208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.551248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.551289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.551329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.551372] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.551415] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.551457] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.551531] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  413.551570] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  413.551895] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  413.553027] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  413.553550] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  413.553590] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  413.553650] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  413.553732] [drm:hsw_audio_config_update [i915]] using automatic N
>[  413.570606] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.570664] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.570979] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.571487] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.571657] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  413.587215] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  413.587295] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.587423] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  413.604100] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  413.604270] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  413.604433] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  413.608697] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.608847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.608935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.609025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.609106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.609187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.609267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.609356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.609437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.609516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.609596] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.609686] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.609850] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.609941] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.610065] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  413.610150] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  413.610260] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  413.610375] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.610459] [drm:intel_power_well_disable [i915]] disabling DC off
>[  413.610540] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  413.610613] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  413.611284] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.612191] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.612240] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  413.612487] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  413.612579] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.612676] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  413.612821] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  413.612918] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.613017] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  413.613112] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  413.613206] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  413.613295] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.613311] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.613401] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.613420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.613514] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  413.613602] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  413.613691] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  413.613830] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.613924] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.614022] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  413.614115] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.614211] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  413.614307] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  413.614402] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  413.614533] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  413.614646] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  413.614799] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  413.615106] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.615181] [drm:intel_power_well_enable [i915]] enabling DC off
>[  413.615502] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  413.615571] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  413.615624] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  413.615736] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  413.616039] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  413.620284] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.620327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.620372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.620418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.620460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.620501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.620541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.620581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.620623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.620663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.620758] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.620808] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.620855] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.620929] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  413.620973] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  413.621250] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  413.622377] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  413.622938] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  413.622981] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  413.623043] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  413.623083] [drm:hsw_audio_config_update [i915]] using automatic N
>[  413.639995] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.640066] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.640269] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.640792] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.640936] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  413.656605] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  413.656684] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.656905] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  413.673157] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  413.673303] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  413.673433] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  413.677685] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.677840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.677930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.678019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.678099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.678181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.678262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.678351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.678431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.678512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.678592] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.678683] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.678849] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.678943] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.679069] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  413.679153] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  413.679265] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  413.679383] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.679468] [drm:intel_power_well_disable [i915]] disabling DC off
>[  413.679552] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  413.679625] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  413.680247] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.681220] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.681263] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  413.681486] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  413.681567] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.681651] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  413.681816] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  413.681902] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.681991] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  413.682079] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  413.682161] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  413.682245] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.682262] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.682344] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.682358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.682439] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  413.682527] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  413.682608] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  413.682695] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.682832] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.682922] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  413.683002] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.683082] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  413.683163] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  413.683247] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  413.683362] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  413.683465] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  413.683549] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  413.683900] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.683966] [drm:intel_power_well_enable [i915]] enabling DC off
>[  413.684282] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  413.684381] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  413.684454] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  413.684559] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  413.684930] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  413.689179] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.689223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.689268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.689314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.689356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.689398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.689439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.689479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.689522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.689562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.689604] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.689648] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.689750] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.689827] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  413.689869] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  413.690147] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  413.691281] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  413.691847] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  413.691888] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  413.691950] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  413.691990] [drm:hsw_audio_config_update [i915]] using automatic N
>[  413.708940] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.709028] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.709256] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.709873] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.710045] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  413.725552] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  413.725639] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.726455] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  413.742217] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  413.742387] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  413.742550] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  413.746881] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.746974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.747071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.747171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.747262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.747351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.747440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.747537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.747627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.747833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.747927] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.748042] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.748141] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.748244] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.748378] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  413.748470] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  413.748593] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  413.748792] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.748895] [drm:intel_power_well_disable [i915]] disabling DC off
>[  413.748988] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  413.749066] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  413.749668] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.750607] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.750753] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  413.751007] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  413.751100] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.751193] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  413.751277] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  413.751366] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.751455] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  413.751543] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  413.751628] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  413.751811] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.751829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.751922] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.751938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.752032] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  413.752127] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  413.752224] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  413.752321] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.752415] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.752513] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  413.752609] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.752704] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  413.752854] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  413.752926] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  413.753028] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  413.753116] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  413.753186] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  413.753425] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.753484] [drm:intel_power_well_enable [i915]] enabling DC off
>[  413.753864] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  413.754423] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  413.754476] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  413.754558] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  413.754910] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  413.759172] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.759245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.759283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.759322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.759357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.759392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.759427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.759462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.759497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.759530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.759566] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.759602] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.759638] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.759752] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  413.759786] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  413.760074] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  413.761061] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  413.761574] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  413.761609] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  413.761660] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  413.761735] [drm:hsw_audio_config_update [i915]] using automatic N
>[  413.778645] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.778772] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.778983] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.779460] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.779608] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  413.795282] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  413.795365] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.795496] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  413.812076] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  413.812240] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  413.812392] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  413.816661] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.816809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.816897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.816986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.817068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.817148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.817229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.817317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.817398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.817477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.817557] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.817647] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.817811] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.817905] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.818034] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  413.818117] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  413.818226] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  413.818340] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.818423] [drm:intel_power_well_disable [i915]] disabling DC off
>[  413.818507] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  413.818581] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  413.819227] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.820138] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.820180] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  413.820406] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  413.820489] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.820574] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  413.820653] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  413.820817] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.820906] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  413.820990] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  413.821077] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  413.821161] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.821181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.821259] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.821273] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.821354] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  413.821442] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  413.821526] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  413.821611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.821689] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.821819] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  413.821895] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.821984] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  413.822065] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  413.822148] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  413.822268] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  413.822368] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  413.822449] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  413.822778] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.822851] [drm:intel_power_well_enable [i915]] enabling DC off
>[  413.823182] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  413.823285] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  413.823364] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  413.823476] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  413.823850] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  413.828094] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.828137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.828183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.828227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.828270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.828311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.828352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.828392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.828434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.828473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.828516] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.828559] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.828602] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.828725] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  413.828766] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  413.829049] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  413.830178] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  413.830738] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  413.830781] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  413.830842] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  413.830883] [drm:hsw_audio_config_update [i915]] using automatic N
>[  413.847822] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.847887] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.848079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.848498] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.848624] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  413.864412] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  413.864492] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.864620] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  413.881359] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  413.881532] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  413.881696] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  413.886069] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.886154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.886242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.886332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.886414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.886495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.886576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.886665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.886845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.886929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.887017] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.887116] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.887202] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.887291] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.887412] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  413.887495] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  413.887607] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  413.887820] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.887921] [drm:intel_power_well_disable [i915]] disabling DC off
>[  413.888016] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  413.888102] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  413.888762] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.889724] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.889771] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  413.890022] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  413.890113] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.890208] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  413.890295] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  413.890387] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.890477] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  413.890567] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  413.890656] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  413.890819] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.890842] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.890934] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.890950] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.891043] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  413.891135] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  413.891230] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  413.891326] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.891423] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.891521] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  413.891616] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.891711] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  413.891847] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  413.891935] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  413.892067] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  413.892179] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  413.892269] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  413.892570] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.892647] [drm:intel_power_well_enable [i915]] enabling DC off
>[  413.893042] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  413.893156] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  413.893239] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  413.893367] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  413.893813] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  413.898108] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.898150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.898193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.898237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.898277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.898316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.898356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.898393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.898435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.898473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.898514] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.898555] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.898595] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.898721] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  413.898760] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  413.899039] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  413.900164] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  413.900740] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  413.900781] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  413.900841] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  413.900880] [drm:hsw_audio_config_update [i915]] using automatic N
>[  413.917843] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.917899] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.918079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.918466] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.918578] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  413.934414] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  413.934489] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  413.934610] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  413.951318] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  413.951482] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  413.951632] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  413.956018] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.956102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.956190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.956279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.956360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.956441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.956522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.956611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.956692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.956866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.956949] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.957051] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.957144] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.957233] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.957355] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  413.957437] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  413.957545] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  413.957664] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.957808] [drm:intel_power_well_disable [i915]] disabling DC off
>[  413.957895] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  413.957974] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  413.958569] [drm:intel_power_well_disable [i915]] disabling always-on
>[  413.959546] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.959589] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  413.959893] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  413.959974] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.960059] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  413.960139] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  413.960224] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.960306] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  413.960390] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  413.960470] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  413.960551] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.960564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.960641] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.960706] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  413.960788] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  413.960872] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  413.960957] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  413.961043] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.961127] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.961217] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  413.961302] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.961385] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  413.961472] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  413.961558] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  413.961680] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  413.961832] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  413.961921] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  413.962202] [drm:intel_power_well_enable [i915]] enabling always-on
>[  413.962270] [drm:intel_power_well_enable [i915]] enabling DC off
>[  413.962594] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  413.962756] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  413.962841] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  413.962958] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  413.963341] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  413.967589] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  413.967632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  413.967727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  413.967773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  413.967814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  413.967854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  413.967897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  413.967938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  413.967981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  413.968023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  413.968065] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  413.968111] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  413.968157] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.968233] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  413.968275] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  413.968556] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  413.969709] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  413.970233] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  413.970274] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  413.970334] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  413.970372] [drm:hsw_audio_config_update [i915]] using automatic N
>[  413.987327] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  413.987412] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  413.987643] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  413.988263] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  413.988436] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  414.003962] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  414.004068] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.004232] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  414.020947] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  414.021117] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  414.021278] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  414.025557] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.025661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.025887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.025998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.026100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.026199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.026305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.026421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.026524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.026631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.026798] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.026922] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.027041] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.027155] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.027312] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  414.027414] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  414.027548] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  414.027690] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.027854] [drm:intel_power_well_disable [i915]] disabling DC off
>[  414.027959] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  414.028059] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  414.028674] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.029605] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.029753] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  414.030033] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  414.030134] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.030236] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  414.030332] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  414.030436] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.030537] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  414.030637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  414.030822] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  414.030930] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.030950] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.031051] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.031069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.031171] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  414.031279] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  414.031386] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  414.031494] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.031600] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.031714] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  414.031884] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.031976] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  414.032071] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  414.032166] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  414.032302] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  414.032416] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  414.032505] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  414.032845] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.032890] [drm:intel_power_well_enable [i915]] enabling DC off
>[  414.033190] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  414.033261] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  414.033313] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  414.033395] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  414.033807] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  414.038046] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.038121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.038159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.038198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.038233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.038266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.038302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.038335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.038372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.038405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.038442] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.038478] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.038514] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.038579] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  414.038613] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  414.038906] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  414.039891] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  414.040404] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  414.040439] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  414.040490] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  414.040522] [drm:hsw_audio_config_update [i915]] using automatic N
>[  414.057479] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.057533] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.057821] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.058304] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.058457] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  414.074076] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  414.074149] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.074265] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  414.090836] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  414.090990] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  414.091129] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  414.095379] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.095449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.095525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.095598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.095667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.095828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.095898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.095980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.096047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.096116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.096182] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.096262] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.096336] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.096411] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.096521] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  414.096592] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  414.096779] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  414.096903] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.096992] [drm:intel_power_well_disable [i915]] disabling DC off
>[  414.097072] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  414.097143] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  414.097784] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.098732] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.098776] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  414.099008] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  414.099088] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.099172] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  414.099249] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  414.099329] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.099408] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  414.099488] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  414.099564] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  414.099640] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.099733] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.099813] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.099831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.099912] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  414.099997] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  414.100086] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  414.100172] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.100259] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.100347] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  414.100432] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.100515] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  414.100602] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  414.100685] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  414.100849] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  414.100957] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  414.101042] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  414.101323] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.101390] [drm:intel_power_well_enable [i915]] enabling DC off
>[  414.101778] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  414.102354] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  414.102431] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  414.102544] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  414.102930] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  414.107176] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.107219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.107264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.107311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.107353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.107394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.107436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.107475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.107517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.107556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.107598] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.107642] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.107744] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.107821] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  414.107862] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  414.108143] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  414.109271] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  414.109834] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  414.109878] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  414.109939] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  414.109980] [drm:hsw_audio_config_update [i915]] using automatic N
>[  414.126895] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.126960] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.127152] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.127578] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.127862] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  414.143503] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  414.143583] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.143839] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  414.160521] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  414.160690] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  414.160969] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  414.165227] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.165311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.165399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.165488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.165570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.165651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.165828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.165923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.166006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.166087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.166167] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.166261] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.166347] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.166437] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.166559] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  414.166642] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  414.166819] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  414.166959] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.167053] [drm:intel_power_well_disable [i915]] disabling DC off
>[  414.167143] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  414.167221] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  414.167886] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.168841] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.168888] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  414.169133] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  414.169224] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.169319] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  414.169407] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  414.169499] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.169589] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  414.169678] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  414.169848] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  414.169941] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.169961] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.170048] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.170065] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.170158] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  414.170250] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  414.170344] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  414.170441] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.170541] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.170638] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  414.170773] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.170865] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  414.170965] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  414.171060] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  414.171188] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  414.171298] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  414.171390] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  414.171690] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.171829] [drm:intel_power_well_enable [i915]] enabling DC off
>[  414.172122] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  414.172182] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  414.172225] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  414.172290] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  414.172560] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  414.176731] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.176774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.176819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.176865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.176905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.176945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.176987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.177027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.177070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.177110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.177152] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.177195] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.177238] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.177312] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  414.177351] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  414.177622] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  414.178782] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  414.179306] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  414.179347] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  414.179408] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  414.179446] [drm:hsw_audio_config_update [i915]] using automatic N
>[  414.196401] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.196490] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.196813] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.197348] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.197521] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  414.212941] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  414.213022] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.213153] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  414.229883] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  414.230054] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  414.230217] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  414.234491] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.234584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.234682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.234887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.234982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.235081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.235172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.235275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.235366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.235459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.235550] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.235656] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.235814] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.235921] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.236057] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  414.236149] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  414.236273] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  414.236402] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.236496] [drm:intel_power_well_disable [i915]] disabling DC off
>[  414.236587] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  414.236668] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  414.237327] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.238306] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.238352] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  414.238599] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  414.238688] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.238869] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  414.238960] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  414.239057] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.239153] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  414.239250] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  414.239342] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  414.239435] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.239455] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.239548] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.239566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.239655] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  414.239801] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  414.239890] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  414.239982] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.240076] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.240173] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  414.240264] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.240358] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  414.240448] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  414.240536] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  414.240661] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  414.240819] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  414.240889] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  414.241109] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.241162] [drm:intel_power_well_enable [i915]] enabling DC off
>[  414.241471] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  414.241555] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  414.241615] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  414.241763] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  414.242076] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  414.246317] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.246360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.246405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.246451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.246493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.246535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.246574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.246616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.246657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.246750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.246795] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.246844] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.246891] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.246966] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  414.247007] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  414.247282] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  414.248415] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  414.248977] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  414.249021] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  414.249081] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  414.249122] [drm:hsw_audio_config_update [i915]] using automatic N
>[  414.266036] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.266100] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.266290] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.266817] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.266990] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  414.282596] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  414.282677] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.282886] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  414.299569] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  414.299853] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  414.300021] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  414.304286] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.304370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.304457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.304546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.304628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.304807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.304890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.304987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.305069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.305153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.305235] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.305331] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.305422] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.305509] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.305637] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  414.305778] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  414.305894] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  414.306012] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.306098] [drm:intel_power_well_disable [i915]] disabling DC off
>[  414.306181] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  414.306254] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  414.306899] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.307825] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.307867] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  414.308090] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  414.308170] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.308254] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  414.308330] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  414.308412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.308492] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  414.308571] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  414.308648] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  414.308807] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.308823] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.308904] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.308919] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.309004] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  414.309090] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  414.309178] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  414.309264] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.309351] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.309439] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  414.309526] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.309608] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  414.309709] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  414.309830] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  414.309942] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  414.310036] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  414.310112] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  414.310368] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.310433] [drm:intel_power_well_enable [i915]] enabling DC off
>[  414.310801] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  414.311384] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  414.311454] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  414.311561] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  414.311913] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  414.316164] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.316207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.316252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.316298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.316340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.316382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.316423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.316465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.316506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.316546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.316588] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.316632] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.316730] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.316807] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  414.316848] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  414.317124] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  414.318256] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  414.318818] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  414.318862] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  414.318923] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  414.318964] [drm:hsw_audio_config_update [i915]] using automatic N
>[  414.335854] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.335932] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.336145] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.336629] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.336941] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  414.352524] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  414.352610] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.352883] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  414.369569] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  414.369885] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  414.370071] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  414.374364] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.374457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.374556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.374655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.374856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.374953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.375049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.375156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.375250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.375341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.375435] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.375540] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.375643] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.375805] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.375945] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  414.376040] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  414.376163] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  414.376297] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.376392] [drm:intel_power_well_disable [i915]] disabling DC off
>[  414.376484] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  414.376567] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  414.377238] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.378196] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.378242] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  414.378497] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  414.378586] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.378680] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  414.378862] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  414.378964] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.379058] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  414.379153] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  414.379248] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  414.379341] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.379362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.379454] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.379472] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.379568] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  414.379661] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  414.379804] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  414.379871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.379932] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.380004] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  414.380069] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.380134] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  414.380196] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  414.380258] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  414.380351] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  414.380433] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  414.380497] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  414.380767] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.380824] [drm:intel_power_well_enable [i915]] enabling DC off
>[  414.381136] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  414.381220] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  414.381279] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  414.381372] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  414.381771] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  414.386031] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.386075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.386120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.386166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.386208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.386249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.386291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.386330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.386374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.386413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.386455] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.386499] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.386541] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.386616] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  414.386655] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  414.386985] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  414.388116] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  414.388638] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  414.388723] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  414.388786] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  414.388826] [drm:hsw_audio_config_update [i915]] using automatic N
>[  414.405774] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.405856] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.406076] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.406588] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.406846] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  414.422311] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  414.422391] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.422521] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  414.439155] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  414.439327] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  414.439495] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  414.443761] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.443845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.443933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.444022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.444103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.444184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.444265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.444353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.444434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.444514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.444595] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.444684] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.445709] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.446009] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.446134] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  414.446217] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  414.446327] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  414.446449] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.446535] [drm:intel_power_well_disable [i915]] disabling DC off
>[  414.446617] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  414.446690] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  414.448575] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.449716] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.449760] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  414.449991] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  414.450071] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.450155] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  414.450232] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  414.450312] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.450391] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  414.450471] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  414.450548] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  414.450624] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.450636] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.451653] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.451914] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.452023] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  414.452124] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  414.452221] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  414.452324] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.452420] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.452527] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  414.452626] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.453482] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  414.453581] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  414.453679] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  414.454239] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  414.454365] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  414.454465] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  414.455030] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.455061] [drm:intel_power_well_enable [i915]] enabling DC off
>[  414.455345] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  414.455394] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  414.455427] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  414.455481] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  414.456001] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  414.460235] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.460309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.460348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.460388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.460423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.460458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.460493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.460528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.460562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.460597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.460632] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.460722] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.460758] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.460826] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  414.460860] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  414.461445] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  414.462591] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  414.463147] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  414.463182] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  414.463234] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  414.463268] [drm:hsw_audio_config_update [i915]] using automatic N
>[  414.480223] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.480301] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.480512] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.481280] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.481433] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  414.496825] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  414.496897] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.497014] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  414.513649] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  414.513885] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  414.514038] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  414.518301] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.518380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.518462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.518544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.518618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.518692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.518864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.518953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.519325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.519400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.519476] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.519565] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.519649] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.519826] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.519968] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  414.520414] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  414.520536] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  414.520669] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.520862] [drm:intel_power_well_disable [i915]] disabling DC off
>[  414.521407] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  414.521487] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  414.523301] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.524613] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.524747] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  414.525436] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  414.525529] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.525622] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  414.525707] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  414.525885] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.525984] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  414.526077] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  414.526175] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  414.526269] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.526288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.526375] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.526391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.526484] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  414.526579] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  414.526673] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  414.526812] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.526902] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.527002] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  414.527094] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.527871] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  414.527962] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  414.528054] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  414.528198] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  414.528316] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  414.528409] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  414.528676] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.528852] [drm:intel_power_well_enable [i915]] enabling DC off
>[  414.529191] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  414.529308] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  414.529382] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  414.529436] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  414.529741] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  414.533963] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.534044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.534082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.534121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.534156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.534191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.534226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.534261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.534296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.534331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.534368] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.534404] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.534440] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.534506] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  414.534541] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  414.534810] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  414.535802] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  414.536316] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  414.536352] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  414.536403] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  414.536435] [drm:hsw_audio_config_update [i915]] using automatic N
>[  414.553394] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.553443] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.553609] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.554155] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.554309] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  414.570018] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  414.570093] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.570214] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  414.587996] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  414.588160] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  414.588312] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  414.592555] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.592640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.592841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.592934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.593017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.593102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.593185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.593278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.593360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.593446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.593528] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.593623] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.593734] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.593822] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.593950] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  414.594034] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  414.594148] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  414.594269] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.594354] [drm:intel_power_well_disable [i915]] disabling DC off
>[  414.594437] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  414.594512] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  414.595181] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.596097] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.596138] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  414.596368] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  414.596449] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.596532] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  414.596609] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  414.596689] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.596855] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  414.596942] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  414.597022] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  414.597109] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.597125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.597206] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.597222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.597308] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  414.597394] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  414.597482] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  414.597569] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.597654] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.597784] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  414.597870] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.597953] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  414.598041] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  414.598123] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  414.598247] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  414.598352] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  414.598435] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  414.598772] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.598847] [drm:intel_power_well_enable [i915]] enabling DC off
>[  414.599181] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  414.599286] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  414.599365] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  414.599563] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  414.599944] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  414.604177] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.604247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.604286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.604326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.604363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.604399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.604436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.604470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.604509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.604543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.604580] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.604618] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.604657] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.604773] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  414.604809] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  414.605065] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  414.606116] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  414.606648] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  414.606719] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  414.606776] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  414.606811] [drm:hsw_audio_config_update [i915]] using automatic N
>[  414.623746] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.623816] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.624018] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.624477] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.624614] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  414.640317] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  414.640391] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.640509] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  414.656985] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  414.657131] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  414.657259] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  414.661447] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.661512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.661579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.661649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.662036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.662100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.662163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.662235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.662298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.662361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.662424] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.662496] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.662564] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.662632] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.663322] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  414.663386] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  414.663473] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  414.663563] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.663627] [drm:intel_power_well_disable [i915]] disabling DC off
>[  414.664146] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  414.664220] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  414.665415] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.666403] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.666444] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  414.666670] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  414.666837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.666925] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  414.667012] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  414.667095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.667177] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  414.667258] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  414.667338] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  414.667417] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.667433] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.667509] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.667522] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.667601] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  414.667685] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  414.667818] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  414.667904] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.667986] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.668077] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  414.668163] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.668250] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  414.668339] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  414.668424] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  414.668543] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  414.668647] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  414.668782] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  414.668994] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.669048] [drm:intel_power_well_enable [i915]] enabling DC off
>[  414.669353] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  414.669439] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  414.669498] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  414.669658] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  414.670033] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  414.674288] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.674366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.674404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.674443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.674478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.674511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.674546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.674579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.674614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.674647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.674731] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.674769] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.674810] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.674875] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  414.674908] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  414.675193] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  414.676179] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  414.676724] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  414.676760] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  414.676814] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  414.676848] [drm:hsw_audio_config_update [i915]] using automatic N
>[  414.693848] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.693925] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.694137] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.694595] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.694812] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  414.710446] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  414.710532] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.710680] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  414.727486] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  414.727657] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  414.728324] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  414.732615] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.732708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.732922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.733039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.733132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.733226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.733317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.733420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.733513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.733609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.733700] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.733883] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.733988] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.734094] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.734234] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  414.734327] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  414.734451] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  414.734581] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.734677] [drm:intel_power_well_disable [i915]] disabling DC off
>[  414.734844] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  414.734939] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  414.735544] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.736567] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.736613] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  414.736953] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  414.737046] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.737145] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  414.737233] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  414.737330] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.737421] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  414.737513] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  414.737602] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  414.737693] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.737770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.737863] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.737882] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.737979] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  414.738071] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  414.738171] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  414.738265] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.738364] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.738462] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  414.738558] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.738655] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  414.738787] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  414.738845] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  414.738932] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  414.739007] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  414.739068] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  414.739285] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.739335] [drm:intel_power_well_enable [i915]] enabling DC off
>[  414.739641] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  414.740277] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  414.740332] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  414.740416] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  414.740825] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  414.745082] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.745158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.745198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.745236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.745272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.745307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.745342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.745377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.745412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.745445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.745481] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.745517] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.745553] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.745619] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  414.745653] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  414.746267] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  414.747385] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  414.747938] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  414.747980] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  414.748031] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  414.748065] [drm:hsw_audio_config_update [i915]] using automatic N
>[  414.765010] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.765085] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.765297] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.766082] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.766242] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  414.781615] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  414.781828] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.782000] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  414.798648] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  414.798961] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  414.799114] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  414.803405] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.803499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.803598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.803697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.803906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.804012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.804105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.804210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.804302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.804397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.804489] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.804595] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.804695] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.804870] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.805004] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  414.805097] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  414.805225] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  414.805357] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.805453] [drm:intel_power_well_disable [i915]] disabling DC off
>[  414.805546] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  414.805627] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  414.806313] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.807326] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.807372] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  414.807625] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  414.807807] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.807906] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  414.808002] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  414.808101] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.808198] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  414.808288] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  414.808380] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  414.808466] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.808484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.808570] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.808584] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.808673] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  414.808831] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  414.808923] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  414.809023] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.809115] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.809220] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  414.809312] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.809412] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  414.809509] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  414.809608] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  414.809789] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  414.809908] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  414.810001] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  414.810313] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.810391] [drm:intel_power_well_enable [i915]] enabling DC off
>[  414.810815] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  414.811320] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  414.811367] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  414.811436] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  414.811795] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  414.816043] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.816120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.816159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.816197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.816233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.816267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.816302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.816337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.816372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.816405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.816441] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.816477] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.816512] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.816579] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  414.816614] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  414.817238] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  414.818353] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  414.818904] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  414.818946] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  414.818999] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  414.819033] [drm:hsw_audio_config_update [i915]] using automatic N
>[  414.835965] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.836033] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.836233] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.837010] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.837167] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  414.852637] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  414.852803] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.852959] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  414.869591] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  414.870074] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  414.870219] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  414.874468] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.874539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.874614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.874690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.874849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.874928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.874998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.875075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.875145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.875217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.875286] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.875367] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.875441] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.875517] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.875622] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  414.875757] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  414.875853] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  414.875954] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.876027] [drm:intel_power_well_disable [i915]] disabling DC off
>[  414.876098] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  414.876157] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  414.876807] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.877616] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.877723] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  414.877981] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  414.878074] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.878173] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  414.878262] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  414.878359] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.878450] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  414.878544] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  414.878634] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  414.878803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.878820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.878914] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.878930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.879023] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  414.879118] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  414.879216] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  414.879311] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.879408] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.879504] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  414.879601] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.879697] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  414.879840] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  414.879904] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  414.879999] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  414.880083] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  414.880150] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  414.880378] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.880433] [drm:intel_power_well_enable [i915]] enabling DC off
>[  414.880826] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  414.881367] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  414.881420] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  414.881497] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  414.881948] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  414.886216] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.886258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.886303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.886347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.886387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.886427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.886466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.886505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.886545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.886585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.886624] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.886729] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.886774] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.886848] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  414.887137] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  414.887411] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  414.888717] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  414.889256] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  414.889295] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  414.889353] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  414.889389] [drm:hsw_audio_config_update [i915]] using automatic N
>[  414.906323] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.906400] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.906611] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.907454] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.907617] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  414.922929] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  414.923007] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.923136] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  414.939799] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  414.939960] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  414.940111] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  414.944394] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.944487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.944584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.944683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.944890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.944997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.945088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.945193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.945286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.945382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.945472] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.945579] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.945681] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.945863] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.945998] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  414.946091] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  414.946215] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  414.946345] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.946441] [drm:intel_power_well_disable [i915]] disabling DC off
>[  414.946534] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  414.946615] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  414.947290] [drm:intel_power_well_disable [i915]] disabling always-on
>[  414.948226] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.948272] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  414.948527] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  414.948616] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  414.948710] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  414.948887] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  414.948981] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  414.949082] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  414.949178] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  414.949268] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  414.949356] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  414.949378] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.949465] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  414.949481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  414.949577] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  414.949670] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  414.949806] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  414.949896] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  414.949993] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  414.950091] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  414.950189] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  414.950282] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  414.950376] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  414.950464] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  414.950597] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  414.950712] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  414.950880] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  414.951182] [drm:intel_power_well_enable [i915]] enabling always-on
>[  414.951263] [drm:intel_power_well_enable [i915]] enabling DC off
>[  414.951594] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  414.951678] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  414.951802] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  414.951879] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  414.952243] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  414.956495] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  414.956572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  414.956610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  414.956648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  414.956732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  414.956775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  414.956810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  414.956845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  414.956880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  414.956915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  414.956950] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  414.956992] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  414.957029] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.957099] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  414.957134] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  414.957386] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  414.958383] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  414.958934] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  414.958969] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  414.959022] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  414.959057] [drm:hsw_audio_config_update [i915]] using automatic N
>[  414.976022] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  414.976100] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  414.976312] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  414.976872] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  414.977027] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  414.992549] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  414.992619] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  414.992845] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  415.009351] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  415.009495] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  415.009625] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  415.013949] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  415.014015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  415.014086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  415.014155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  415.014218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  415.014281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  415.014344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  415.014413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  415.014476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  415.014538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  415.014600] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  415.014670] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  415.014823] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  415.014894] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  415.014994] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  415.015396] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  415.015487] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  415.015581] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  415.015648] [drm:intel_power_well_disable [i915]] disabling DC off
>[  415.015812] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  415.015893] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  415.017119] [drm:intel_power_well_disable [i915]] disabling always-on
>[  415.018350] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  415.018392] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  415.018621] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  415.018702] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  415.018876] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  415.018958] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  415.019049] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  415.019136] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  415.019223] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  415.019305] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  415.019392] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  415.019408] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  415.019490] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  415.020173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  415.020266] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  415.020347] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  415.020425] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  415.020507] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  415.020586] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  415.020671] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  415.020807] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  415.020895] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  415.020982] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  415.021070] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  415.021195] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  415.021791] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  415.021881] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  415.022162] [drm:intel_power_well_enable [i915]] enabling always-on
>[  415.022230] [drm:intel_power_well_enable [i915]] enabling DC off
>[  415.022557] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  415.022661] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  415.022821] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  415.022938] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  415.023338] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  415.027574] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  415.027648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  415.027733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  415.027773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  415.027808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  415.027843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  415.027878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  415.027912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  415.027947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  415.027983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  415.028017] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  415.028056] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  415.028095] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  415.028162] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  415.028196] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  415.028448] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  415.029431] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  415.029980] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  415.030015] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  415.030068] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  415.030102] [drm:hsw_audio_config_update [i915]] using automatic N
>[  415.047044] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  415.047118] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  415.047331] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  415.047875] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  415.048027] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  415.063650] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  415.063769] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  415.063887] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  415.080513] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  415.080673] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  415.080963] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  415.085207] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  415.085291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  415.085378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  415.085466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  415.085547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  415.085628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  415.085803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  415.085900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  415.085986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  415.086070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  415.086151] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  415.086245] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  415.086333] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  415.086420] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  415.086544] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  415.086630] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  415.086799] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  415.086916] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  415.087000] [drm:intel_power_well_disable [i915]] disabling DC off
>[  415.087082] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  415.087155] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  415.087811] [drm:intel_power_well_disable [i915]] disabling always-on
>[  415.088732] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  415.088776] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  415.089003] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  415.089086] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  415.089171] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  415.089250] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  415.089333] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  415.089416] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  415.089497] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  415.089577] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  415.089656] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  415.089723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  415.089823] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  415.089837] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  415.089938] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  415.090032] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  415.090132] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  415.090226] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  415.090321] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  415.090419] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  415.090515] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  415.090610] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  415.090708] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  415.090848] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  415.090976] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  415.091087] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  415.091185] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  415.091488] [drm:intel_power_well_enable [i915]] enabling always-on
>[  415.091565] [drm:intel_power_well_enable [i915]] enabling DC off
>[  415.091915] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  415.092485] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  415.092530] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  415.092600] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  415.092929] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  415.097172] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  415.097215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  415.097260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  415.097306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  415.097348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  415.097389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  415.097431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  415.097471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  415.097514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  415.097553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  415.097596] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  415.097640] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  415.097738] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  415.097815] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  415.097857] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  415.098133] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  415.099269] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  415.099828] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  415.099871] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  415.099935] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  415.099975] [drm:hsw_audio_config_update [i915]] using automatic N
>[  415.116928] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  415.117015] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  415.117245] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  415.117872] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  415.118046] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  415.133530] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  415.133623] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  415.134367] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  415.150218] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  415.150392] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  415.150554] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  415.154890] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  415.154983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  415.155081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  415.155180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  415.155270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  415.155360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  415.155450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  415.155547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  415.155638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  415.155842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  415.155938] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  415.156049] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  415.156148] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  415.156248] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  415.156383] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  415.156475] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  415.156598] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  415.156798] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  415.156902] [drm:intel_power_well_disable [i915]] disabling DC off
>[  415.156997] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  415.157078] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  415.157677] [drm:intel_power_well_disable [i915]] disabling always-on
>[  415.158586] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  415.158631] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  415.158989] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  415.159082] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  415.159180] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  415.159269] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  415.159364] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  415.159455] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  415.159547] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  415.159636] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  415.159792] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  415.159809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  415.159900] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  415.159918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  415.160014] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  415.160109] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  415.160207] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  415.160302] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  415.160400] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  415.160501] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  415.160597] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  415.160692] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  415.160840] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  415.160910] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  415.161012] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  415.161099] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  415.161168] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  415.161405] [drm:intel_power_well_enable [i915]] enabling always-on
>[  415.161464] [drm:intel_power_well_enable [i915]] enabling DC off
>[  415.161835] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  415.162392] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  415.162439] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  415.162513] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  415.162875] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  415.167120] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  415.167195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  415.167234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  415.167272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  415.167308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  415.167343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  415.167378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  415.167411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  415.167447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  415.167482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  415.167517] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  415.167553] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  415.167589] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  415.167655] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  415.167738] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  415.168024] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  415.169012] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  415.169525] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  415.169560] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  415.169611] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  415.169643] [drm:hsw_audio_config_update [i915]] using automatic N
>[  415.186598] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  415.186673] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  415.186960] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  415.187435] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  415.187584] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  415.203179] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  415.203266] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  415.203407] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  415.219933] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  415.220093] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  415.220244] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  415.224526] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  415.224618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  415.224827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  415.224932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  415.225024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  415.225118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  415.225210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  415.225316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  415.225407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  415.225501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  415.225591] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  415.225698] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  415.225850] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  415.225952] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  415.226093] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  415.226184] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  415.226311] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  415.226440] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  415.226536] [drm:intel_power_well_disable [i915]] disabling DC off
>[  415.226627] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  415.226771] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  415.227376] [drm:intel_power_well_disable [i915]] disabling always-on
>[  415.228395] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  415.228441] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  415.228693] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  415.228872] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  415.228975] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  415.229067] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  415.229165] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  415.229260] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  415.229358] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  415.229450] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  415.229544] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  415.229562] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  415.229650] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  415.229708] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  415.229800] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  415.229894] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  415.229989] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  415.230087] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  415.230180] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  415.230283] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  415.230372] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  415.230461] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  415.230551] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  415.230643] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  415.230826] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  415.230952] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  415.231047] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  415.231316] [drm:intel_power_well_enable [i915]] enabling always-on
>[  415.231363] [drm:intel_power_well_enable [i915]] enabling DC off
>[  415.231663] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  415.231786] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  415.231835] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  415.231909] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  415.232200] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  415.236442] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  415.236486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  415.236531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  415.236577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  415.236618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  415.236658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  415.236750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  415.236794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  415.236840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  415.236883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  415.236927] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  415.236975] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  415.237023] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  415.237096] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  415.237138] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  415.237412] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  415.238544] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  415.239107] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  415.239150] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  415.239211] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  415.239252] [drm:hsw_audio_config_update [i915]] using automatic N
>[  415.256166] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  415.256233] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  415.256429] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  415.257039] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  415.257216] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  415.272767] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  415.272847] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  415.272978] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  415.289594] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  415.289882] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  415.290047] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  415.294349] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  415.294442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  415.294539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  415.294639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  415.294841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  415.294930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  415.295022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  415.295123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  415.295217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  415.295308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  415.295401] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  415.295506] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  415.295605] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  415.295706] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  415.295901] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  415.295999] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  415.296125] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  415.296256] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  415.296349] [drm:intel_power_well_disable [i915]] disabling DC off
>[  415.296438] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  415.296516] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  415.297177] [drm:intel_power_well_disable [i915]] disabling always-on
>[  415.307503] [IGT] kms_flip: exiting, ret=0
>[  415.332655] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  415.332754] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  415.332799] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  415.332842] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  415.332878] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  415.332920] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  415.332960] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  415.332999] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  415.333037] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  415.333073] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  415.333110] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  415.333118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  415.333154] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  415.333158] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  415.333196] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  415.333232] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  415.333270] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  415.333307] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  415.333343] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  415.333386] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  415.333422] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  415.333462] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  415.333501] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  415.333539] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  415.333577] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  415.333625] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  415.333663] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  415.333727] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  415.333763] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  415.333802] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  415.333840] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  415.333877] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  415.333913] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  415.333949] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  415.333953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  415.333989] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  415.333993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  415.334031] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  415.334067] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  415.334105] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  415.334142] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  415.334178] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  415.334217] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  415.334253] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  415.334291] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  415.334330] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  415.334368] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  415.334404] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  415.334445] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  415.334495] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  415.334534] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  415.334580] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  415.334617] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  415.334813] [drm:intel_power_well_enable [i915]] enabling always-on
>[  415.334845] [drm:intel_power_well_enable [i915]] enabling DC off
>[  415.335135] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  415.335195] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  415.335314] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  415.335353] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  415.335414] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  415.335596] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  415.338700] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  415.338740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  415.338780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  415.338825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  415.338865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  415.338904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  415.338943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  415.338982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  415.339022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  415.339061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  415.339100] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  415.339142] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  415.339183] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  415.339257] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  415.339294] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  415.339513] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  415.339552] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  415.339604] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  415.339643] [drm:wait_panel_status [i915]] Wait complete
>[  415.339783] [drm:edp_panel_on [i915]] Wait for panel power on
>[  415.339829] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  415.448279] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  415.448321] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  415.448359] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  415.448454] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  415.540521] [drm:wait_panel_status [i915]] Wait complete
>[  415.540580] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  415.540632] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  415.542020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  415.542056] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  415.542098] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  415.542961] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  415.543000] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  415.544154] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  415.544411] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  415.545820] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  415.545907] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  415.545945] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  415.545989] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  415.546045] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  415.546081] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  415.546137] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  415.546174] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  415.546352] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  415.546389] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  415.546716] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  415.548078] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  415.548634] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  415.548697] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  415.548759] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  415.548795] [drm:hsw_audio_config_update [i915]] using automatic N
>[  415.565725] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  415.565778] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  415.565981] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  415.566186] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  415.566241] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  415.566436] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  415.566872] Console: switching to colour frame buffer device 240x67
>[  415.779366] Console: switching to colour dummy device 80x25
>[  415.779610] [IGT] kms_flip: executing
>[  415.794780] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  415.794836] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  415.794882] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  415.794923] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  415.794962] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  415.795003] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  415.795548] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  415.796037] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  415.796051] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  415.796057] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  415.796092] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  415.796146] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  415.796753] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  415.797156] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  415.797197] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  415.797248] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  415.805969] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.814658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.823501] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.832280] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.841121] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.849975] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.858819] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.867658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.876559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.885468] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.894425] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.903402] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.912400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.921393] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.930397] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.939392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.948384] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.957386] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.966391] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.975385] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.984399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  415.993400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  416.002415] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  416.011428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  416.020420] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  416.029422] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  416.038432] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  416.047428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  416.056432] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  416.065428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  416.074435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  416.083444] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  416.083491] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  416.083507] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  416.083585] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  416.083689] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  416.165046] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  416.169231] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  416.169345] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  416.169357] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  416.170123] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  416.170134] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  416.170143] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  416.170149] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  416.170537] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  416.170550] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  416.170560] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  416.170569] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  416.170578] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  416.170588] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  416.170598] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  416.170607] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  416.170617] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  416.170626] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  416.170810] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  416.170823] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  416.170835] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  416.170847] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  416.170868] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  416.170887] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  416.170899] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  416.170911] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  416.170923] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  416.170935] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  416.170955] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  416.170970] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  416.170982] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  416.170994] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  416.172506] [IGT] kms_flip: starting subtest basic-flip-vs-wf_vblank
>[  416.174763] [drm:drm_mode_addfb2] [FB:70]
>[  416.174850] [drm:drm_mode_addfb2] [FB:91]
>[  416.284173] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  416.284282] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  416.284472] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  416.492845] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  416.492936] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  416.497471] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  416.497534] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  416.497597] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  416.549288] [drm:wait_panel_status [i915]] Wait complete
>[  416.549349] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  416.549417] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  416.549549] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  416.549809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  416.549898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  416.549985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  416.550057] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  416.550133] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  416.550205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  416.550281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  416.550353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  416.550428] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  416.550504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  416.550580] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  416.550656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  416.550774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  416.550849] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  416.550944] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  416.551028] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  416.551116] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  416.565620] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  416.565854] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  416.566181] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  416.566404] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  416.566689] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  416.566874] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  416.567586] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  416.583233] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  416.583417] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  416.583625] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  416.588022] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  416.588115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  416.588212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  416.588310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  416.588400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  416.588490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  416.588577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  416.588673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  416.588868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  416.588967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  416.589062] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  416.589176] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  416.589278] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  416.589379] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  416.589511] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  416.589603] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  416.589789] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  416.589919] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  416.590022] [drm:intel_power_well_disable [i915]] disabling DC off
>[  416.590117] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  416.590199] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  416.590859] [drm:intel_power_well_disable [i915]] disabling always-on
>[  416.591596] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  416.592327] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  416.592372] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  416.592617] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  416.592706] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  416.592887] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  416.592994] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  416.593089] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  416.593191] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  416.593282] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  416.593375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  416.593463] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  416.593554] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  416.593640] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  416.593711] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  416.593798] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  416.593807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  416.593868] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  416.593930] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  416.593993] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  416.594055] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  416.594118] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  416.594179] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  416.594241] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  416.594303] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  416.594368] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  416.594428] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  416.594491] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  416.594555] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  416.594627] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  416.594701] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  416.595190] [drm:intel_power_well_enable [i915]] enabling always-on
>[  416.595239] [drm:intel_power_well_enable [i915]] enabling DC off
>[  416.595544] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  416.595628] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  416.595895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  416.595957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  416.596020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  416.596081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  416.596140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  416.596200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  416.596262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  416.596322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  416.596381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  416.596441] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  416.596507] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  416.596570] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  416.596671] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  416.596794] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  416.597026] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  416.597063] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  417.004895] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  417.102883] [drm:wait_panel_status [i915]] Wait complete
>[  417.102982] [drm:edp_panel_on [i915]] Wait for panel power on
>[  417.103084] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  417.211380] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  417.211419] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  417.211453] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  417.211615] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  417.304971] [drm:wait_panel_status [i915]] Wait complete
>[  417.305060] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  417.305130] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  417.306796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  417.306873] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  417.306950] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  417.307941] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  417.308016] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  417.309348] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  417.309688] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  417.312014] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  417.312147] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  417.312217] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  417.312297] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  417.312396] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  417.312467] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  417.312563] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  417.312634] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  417.329116] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  417.329213] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  417.329476] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  419.296377] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  419.296936] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  419.500953] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  419.501677] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  419.516619] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  419.516912] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  419.517033] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  419.568394] [drm:wait_panel_status [i915]] Wait complete
>[  419.568563] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  419.569020] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  419.569258] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  419.569360] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  419.569463] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  419.569682] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  419.570167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  419.570285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  419.570391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  419.570495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  419.570608] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  419.570708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  419.571108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  419.571220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  419.571327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  419.571430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  419.571536] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  419.571657] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  419.572023] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  419.572137] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  419.572373] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  419.572528] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  419.572665] [drm:intel_power_well_disable [i915]] disabling DC off
>[  419.573159] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  419.573251] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  419.574470] [drm:intel_power_well_disable [i915]] disabling always-on
>[  419.575614] [drm:drm_mode_addfb2] [FB:70]
>[  419.575772] [drm:drm_mode_addfb2] [FB:91]
>[  419.631797] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  419.632256] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  419.632904] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  419.633456] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  419.633476] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  419.633582] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  419.633616] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  419.633655] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  419.633752] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  419.633784] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  419.633820] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  419.633855] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  419.633889] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  419.633924] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  419.633957] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  419.633992] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  419.633998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  419.634029] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  419.634034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  419.634067] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  419.634101] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  419.634135] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  419.634167] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  419.634202] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  419.634239] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  419.634272] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  419.634309] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  419.634345] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  419.634381] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  419.634416] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  419.634452] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  419.634494] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  419.634529] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  419.634920] [drm:intel_power_well_enable [i915]] enabling always-on
>[  419.634950] [drm:intel_power_well_enable [i915]] enabling DC off
>[  419.635239] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  419.635289] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  419.635323] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  419.635377] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  419.635544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  419.635580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  419.635617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  419.635653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  419.635742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  419.635779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  419.635817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  419.635853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  419.635891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  419.635929] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  419.635969] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  419.636008] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  419.636076] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  419.636109] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  419.636309] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  419.636346] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  420.020858] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  420.103415] [drm:wait_panel_status [i915]] Wait complete
>[  420.103477] [drm:edp_panel_on [i915]] Wait for panel power on
>[  420.103541] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  420.212004] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  420.212062] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  420.212116] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  420.212234] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  420.304401] [drm:wait_panel_status [i915]] Wait complete
>[  420.304508] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  420.304598] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  420.306403] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  420.306484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  420.306569] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  420.307947] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  420.308027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  420.309376] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  420.309840] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  420.312004] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  420.312130] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  420.312207] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  420.312294] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  420.312402] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  420.312480] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  420.329190] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  420.329307] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  420.329615] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  421.685652] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x18001a18, pins 0x00000040
>[  421.685760] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - long
>[  421.685858] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 6 - cnt: 0
>[  421.686054] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - long
>[  421.686234] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[  421.686340] [drm:i915_hotplug_work_func [i915]] Connector DP-2 (pin 6) received hotplug event.
>[  421.686441] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  421.686538] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  421.686921] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  421.687039] [drm:i915_hotplug_work_func [i915]] Connector HDMI-A-1 (pin 6) received hotplug event.
>[  421.687141] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  421.768557] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  421.772821] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  421.772935] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  421.772948] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  421.883280] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x18001a18, pins 0x00000040
>[  421.883388] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - long
>[  421.883487] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 6 - cnt: 1
>[  421.883698] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - long
>[  421.883937] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[  421.884044] [drm:i915_hotplug_work_func [i915]] Connector DP-2 (pin 6) received hotplug event.
>[  421.884148] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  421.884241] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  421.893412] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  421.902411] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  421.911429] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  421.920460] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  421.929580] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  421.938891] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  421.947927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  421.956940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  421.966001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  421.975099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  421.984111] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  421.993235] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.002246] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.011279] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.020352] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.029350] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.038353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.047420] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.056451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.065454] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.074518] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.083553] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.092878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.101917] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.110939] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.119939] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.128974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.138001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.147019] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.156149] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.165149] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.174147] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  422.174201] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  422.174292] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  422.174409] [drm:i915_hotplug_work_func [i915]] Connector HDMI-A-1 (pin 6) received hotplug event.
>[  422.174506] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  422.256113] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  422.260298] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  422.260414] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  422.260426] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  422.296373] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  422.296709] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  422.500874] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  422.501029] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  422.513988] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  422.514101] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  422.514221] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  422.565949] [drm:wait_panel_status [i915]] Wait complete
>[  422.566080] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  422.566286] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  422.566473] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  422.566574] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  422.566673] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  422.566876] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  422.567822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  422.567944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  422.568053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  422.568155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  422.568258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  422.568359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  422.568466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  422.568567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  422.568668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  422.568851] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  422.568976] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  422.569087] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  422.569204] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  422.569354] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  422.569926] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  422.570035] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  422.570186] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  422.570297] [drm:intel_power_well_disable [i915]] disabling DC off
>[  422.570401] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  422.570491] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  422.571713] [drm:intel_power_well_disable [i915]] disabling always-on
>[  422.573198] [drm:drm_mode_addfb2] [FB:70]
>[  422.573360] [drm:drm_mode_addfb2] [FB:91]
>[  422.632022] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  422.632474] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  422.633144] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  422.633729] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  422.633750] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  422.633855] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  422.633889] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  422.633927] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  422.633967] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  422.633999] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  422.634034] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  422.634068] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  422.634103] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  422.634136] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  422.634168] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  422.634200] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  422.634206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  422.634238] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  422.634242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  422.634275] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  422.634307] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  422.634340] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  422.634372] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  422.634404] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  422.634442] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  422.634474] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  422.634510] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  422.634544] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  422.634578] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  422.634615] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  422.634657] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  422.634733] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  422.635086] [drm:intel_power_well_enable [i915]] enabling always-on
>[  422.635115] [drm:intel_power_well_enable [i915]] enabling DC off
>[  422.635397] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  422.635446] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  422.635481] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  422.635536] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  422.635660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  422.635728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  422.635769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  422.635807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  422.635843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  422.635880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  422.635921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  422.635958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  422.635995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  422.636031] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  422.636072] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  422.636111] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  422.636177] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  422.636211] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  422.636418] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  422.636455] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  423.020899] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  423.101627] [drm:wait_panel_status [i915]] Wait complete
>[  423.101776] [drm:edp_panel_on [i915]] Wait for panel power on
>[  423.101895] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  423.210254] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  423.210364] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  423.210463] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  423.210697] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  423.303944] [drm:wait_panel_status [i915]] Wait complete
>[  423.304090] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  423.304212] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  423.305986] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  423.306087] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  423.306191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  423.307483] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  423.307582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  423.309258] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  423.309671] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  423.312670] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  423.312887] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  423.312926] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  423.312972] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  423.313029] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  423.313069] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  423.329896] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  423.329996] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  423.330262] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  425.297165] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  425.297503] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  425.500863] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  425.501024] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  425.513985] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  425.514102] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  425.514222] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  425.565900] [drm:wait_panel_status [i915]] Wait complete
>[  425.566032] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  425.566237] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  425.566448] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  425.566549] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  425.566649] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  425.566829] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  425.566934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  425.567053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  425.567162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  425.567268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  425.567371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  425.567472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  425.567583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  425.567686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  425.567847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  425.567949] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  425.568076] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  425.568192] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  425.568304] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  425.568459] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  425.568604] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  425.568771] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  425.568921] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  425.569030] [drm:intel_power_well_disable [i915]] disabling DC off
>[  425.569134] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  425.569227] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  425.569924] [drm:intel_power_well_disable [i915]] disabling always-on
>[  425.572788] [drm:drm_mode_addfb2] [FB:70]
>[  425.572950] [drm:drm_mode_addfb2] [FB:91]
>[  425.629588] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  425.630091] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  425.630732] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  425.631296] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  425.631318] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  425.631423] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  425.631457] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  425.631494] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  425.631526] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  425.631561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  425.631595] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  425.631630] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  425.631706] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  425.631740] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  425.631751] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  425.631784] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  425.631791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  425.631826] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  425.631861] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  425.631896] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  425.631934] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  425.631968] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  425.632007] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  425.632043] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  425.632080] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  425.632116] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  425.632152] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  425.632189] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  425.632242] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  425.632289] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  425.632327] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  425.632738] [drm:intel_power_well_enable [i915]] enabling always-on
>[  425.632769] [drm:intel_power_well_enable [i915]] enabling DC off
>[  425.633053] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  425.633104] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  425.633137] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  425.633191] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  425.633460] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  425.637689] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  425.637801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  425.637840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  425.637879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  425.637914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  425.637949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  425.637984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  425.638019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  425.638054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  425.638088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  425.638123] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  425.638159] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  425.638195] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  425.638261] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  425.638296] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  425.638580] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  425.639580] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  425.640179] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  425.640218] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  425.640278] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  425.640316] [drm:hsw_audio_config_update [i915]] using automatic N
>[  425.640417] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  425.640456] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  425.657248] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  425.657322] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  425.657531] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  427.624261] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  427.624555] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  427.625082] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  427.626443] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  427.641044] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  427.641148] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  427.641321] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  427.641521] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  427.646211] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  427.646319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  427.646431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  427.646545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  427.646647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  427.646922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  427.647026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  427.647148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  427.647251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  427.647356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  427.647459] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  427.647583] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  427.647695] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  427.647886] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  427.648044] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  427.648149] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  427.648294] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  427.648444] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  427.648580] [drm:intel_power_well_disable [i915]] disabling DC off
>[  427.648685] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  427.648833] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  427.649444] [drm:intel_power_well_disable [i915]] disabling always-on
>[  427.651128] [drm:drm_mode_addfb2] [FB:70]
>[  427.651287] [drm:drm_mode_addfb2] [FB:91]
>[  427.709079] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  427.709541] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  427.710195] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  427.710826] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  427.710849] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  427.710962] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  427.710996] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  427.711034] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  427.711066] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  427.711100] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  427.711134] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  427.711169] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  427.711201] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  427.711233] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  427.711240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  427.711271] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  427.711275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  427.711308] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  427.711341] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  427.711374] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  427.711406] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  427.711438] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  427.711476] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  427.711508] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  427.711544] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  427.711578] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  427.711612] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  427.711647] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  427.711740] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  427.711789] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  427.711825] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  427.712168] [drm:intel_power_well_enable [i915]] enabling always-on
>[  427.712198] [drm:intel_power_well_enable [i915]] enabling DC off
>[  427.712480] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  427.712530] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  427.712564] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  427.712620] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  427.712933] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  427.717174] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  427.717244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  427.717283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  427.717323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  427.717358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  427.717393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  427.717428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  427.717463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  427.717498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  427.717533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  427.717568] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  427.717605] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  427.717640] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  427.717760] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  427.717795] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  427.718060] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  427.719048] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  427.719581] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  427.719615] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  427.719700] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  427.719736] [drm:hsw_audio_config_update [i915]] using automatic N
>[  427.736576] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  427.736641] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  427.736916] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  429.703853] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  429.704160] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  429.704287] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  429.704488] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  429.721259] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  429.721465] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  429.721710] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  429.726160] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  429.726264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  429.726377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  429.726490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  429.726590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  429.726690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  429.726926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  429.727040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  429.727150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  429.727252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  429.727359] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  429.727480] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  429.727596] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  429.727710] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  429.727942] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  429.728047] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  429.728190] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  429.728341] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  429.728456] [drm:intel_power_well_disable [i915]] disabling DC off
>[  429.728559] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  429.728651] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  429.729345] [drm:intel_power_well_disable [i915]] disabling always-on
>[  429.730967] [drm:drm_mode_addfb2] [FB:70]
>[  429.731125] [drm:drm_mode_addfb2] [FB:91]
>[  429.789059] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  429.789523] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  429.790186] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  429.790783] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  429.790804] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  429.790908] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  429.790941] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  429.790979] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  429.791011] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  429.791045] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  429.791079] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  429.791114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  429.791146] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  429.791177] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  429.791183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  429.791215] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  429.791219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  429.791252] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  429.791284] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  429.791317] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  429.791350] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  429.791382] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  429.791420] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  429.791452] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  429.791487] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  429.791522] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  429.791556] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  429.791603] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  429.791651] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  429.791735] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  429.792087] [drm:intel_power_well_enable [i915]] enabling always-on
>[  429.792117] [drm:intel_power_well_enable [i915]] enabling DC off
>[  429.792399] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  429.792448] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  429.792482] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  429.792536] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  429.792866] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  429.797121] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  429.797195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  429.797234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  429.797273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  429.797309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  429.797344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  429.797379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  429.797413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  429.797448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  429.797483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  429.797518] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  429.797554] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  429.797590] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  429.797657] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  429.797745] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  429.798035] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  429.799034] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  429.799548] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  429.799583] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  429.799634] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  429.799708] [drm:hsw_audio_config_update [i915]] using automatic N
>[  429.816639] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  429.816770] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  429.816982] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  431.783658] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  431.784061] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  431.784188] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  431.784408] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  431.801174] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  431.801380] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  431.801597] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  431.805895] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  431.806001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  431.806113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  431.806225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  431.806326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  431.806426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  431.806527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  431.806639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  431.806882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  431.806988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  431.807096] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  431.807220] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  431.807332] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  431.807443] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  431.807600] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  431.807705] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  431.807937] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  431.808093] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  431.808203] [drm:intel_power_well_disable [i915]] disabling DC off
>[  431.808307] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  431.808401] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  431.809078] [drm:intel_power_well_disable [i915]] disabling always-on
>[  431.818710] [IGT] kms_flip: exiting, ret=0
>[  431.845676] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  431.845776] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  431.845819] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  431.845863] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  431.845899] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  431.845941] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  431.845980] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  431.846019] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  431.846057] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  431.846094] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  431.846132] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  431.846138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  431.846174] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  431.846178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  431.846216] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  431.846252] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  431.846290] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  431.846326] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  431.846363] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  431.846406] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  431.846442] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  431.846482] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  431.846521] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  431.846559] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  431.846598] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  431.846643] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  431.846705] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  431.846747] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  431.846783] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  431.846822] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  431.846860] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  431.846897] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  431.846935] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  431.846971] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  431.846975] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  431.847011] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  431.847015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  431.847052] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  431.847089] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  431.847128] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  431.847164] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  431.847201] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  431.847239] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  431.847275] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  431.847314] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  431.847352] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  431.847391] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  431.847429] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  431.847469] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  431.847515] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  431.847553] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  431.847596] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  431.847634] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  431.847834] [drm:intel_power_well_enable [i915]] enabling always-on
>[  431.847866] [drm:intel_power_well_enable [i915]] enabling DC off
>[  431.848155] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  431.848215] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  431.848333] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  431.848369] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  431.848431] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  431.848613] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  431.851701] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  431.851741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  431.851780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  431.851824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  431.851864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  431.851903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  431.851943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  431.851982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  431.852021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  431.852060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  431.852099] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  431.852141] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  431.852182] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  431.852257] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  431.852294] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  431.852513] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  431.852552] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  431.852604] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  431.852643] [drm:wait_panel_status [i915]] Wait complete
>[  431.852785] [drm:edp_panel_on [i915]] Wait for panel power on
>[  431.852830] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  431.961295] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  431.961355] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  431.961412] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  431.961566] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  432.053257] [drm:wait_panel_status [i915]] Wait complete
>[  432.053391] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  432.053502] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  432.055219] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  432.055304] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  432.055397] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  432.056573] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  432.056658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  432.058234] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  432.058648] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  432.061653] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  432.061840] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  432.061926] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  432.062023] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  432.062145] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  432.062231] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  432.062350] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  432.062436] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  432.062832] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  432.062919] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  432.063411] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  432.066119] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  432.066649] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  432.066702] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  432.066756] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  432.066788] [drm:hsw_audio_config_update [i915]] using automatic N
>[  432.083779] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  432.083858] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  432.084106] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  432.084373] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  432.084448] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  432.084680] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  432.085276] Console: switching to colour frame buffer device 240x67
>[  432.307031] Console: switching to colour dummy device 80x25
>[  432.307273] [IGT] kms_flip: executing
>[  432.330337] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  432.330404] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  432.330464] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  432.330519] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  432.330570] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  432.330622] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  432.331330] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  432.331882] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  432.331900] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  432.331907] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  432.331951] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  432.332012] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  432.332603] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  432.333040] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  432.333088] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  432.333150] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  432.341797] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.350597] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.359531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.368409] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.377316] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.386181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.395075] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.404057] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.413057] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.422074] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.431136] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.440127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.449119] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.458108] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.467095] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.476067] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.485103] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.494112] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.503094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.512080] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.521066] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.530121] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.539128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.548112] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.557094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.566079] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.575058] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.584128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.593137] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.602115] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.611135] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.620126] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  432.620175] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  432.620191] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  432.620267] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  432.620370] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  432.701547] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  432.705807] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  432.705922] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  432.705934] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  432.706599] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  432.706608] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  432.706617] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  432.706623] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  432.707865] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  432.707880] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  432.707890] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  432.707899] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  432.707908] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  432.707918] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  432.707927] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  432.707937] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  432.707946] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  432.707955] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  432.707965] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  432.707974] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  432.707985] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  432.707995] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  432.708004] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  432.708013] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  432.708023] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  432.708032] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  432.708041] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  432.708050] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  432.708060] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  432.708069] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  432.708078] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  432.708087] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  432.710396] [IGT] kms_flip: starting subtest basic-plain-flip
>[  432.712162] [drm:drm_mode_addfb2] [FB:89]
>[  432.712255] [drm:drm_mode_addfb2] [FB:91]
>[  432.822712] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  432.822822] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  432.823012] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  433.028842] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  433.028934] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  433.045747] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  433.045808] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  433.045873] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  433.097540] [drm:wait_panel_status [i915]] Wait complete
>[  433.097610] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  433.097682] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  433.098170] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  433.098220] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  433.098281] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  433.098341] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  433.098508] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  433.098586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  433.098669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  433.098802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  433.098880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  433.098961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  433.099039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  433.099120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  433.099197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  433.099278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  433.099355] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  433.099445] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  433.099527] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  433.099612] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  433.100253] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  433.100366] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  433.100630] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  433.101213] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  433.101499] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  433.101584] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  433.102270] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  433.118213] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  433.118375] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  433.118546] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  433.122868] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  433.122944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  433.123027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  433.123107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  433.123181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  433.123255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  433.123328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  433.123409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  433.123483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  433.123556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  433.123629] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  433.124541] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  433.124625] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  433.124905] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  433.125018] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  433.125093] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  433.125195] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  433.125300] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  433.125378] [drm:intel_power_well_disable [i915]] disabling DC off
>[  433.125454] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  433.125522] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  433.127004] [drm:intel_power_well_disable [i915]] disabling always-on
>[  433.127954] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  433.128532] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  433.128572] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  433.129179] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  433.129271] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  433.129366] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  433.129469] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  433.129555] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  433.129645] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  433.130330] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  433.130421] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  433.130512] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  433.130601] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  433.130689] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  433.131268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  433.131366] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  433.131376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  433.131464] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  433.131551] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  433.131638] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  433.132313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  433.132403] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  433.132499] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  433.132587] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  433.132677] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  433.133121] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  433.133155] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  433.133189] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  433.133229] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  433.133273] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  433.133306] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  433.133931] [drm:intel_power_well_enable [i915]] enabling always-on
>[  433.133962] [drm:intel_power_well_enable [i915]] enabling DC off
>[  433.134247] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  433.134297] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  433.134439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  433.134475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  433.134513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  433.134548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  433.134583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  433.134618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  433.134654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  433.135115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  433.135148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  433.135183] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  433.135223] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  433.135259] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  433.135326] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  433.135361] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  433.135565] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  433.135601] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  433.548898] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  433.602398] [drm:wait_panel_status [i915]] Wait complete
>[  433.602570] [drm:edp_panel_on [i915]] Wait for panel power on
>[  433.602665] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  433.711024] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  433.711110] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  433.711190] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  433.711377] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  433.802944] [drm:wait_panel_status [i915]] Wait complete
>[  433.803165] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  433.803276] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  433.805000] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  433.805101] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  433.805206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  433.806499] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  433.806602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  433.808443] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  433.809021] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  433.811811] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  433.811979] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  433.812075] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  433.812183] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  433.812317] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  433.812412] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  433.812546] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  433.812644] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  433.828878] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  433.828926] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  433.829099] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  435.512738] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  435.513164] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  435.716882] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  435.717039] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  435.729991] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  435.730104] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  435.730223] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  435.781908] [drm:wait_panel_status [i915]] Wait complete
>[  435.782025] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  435.782146] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  435.782352] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  435.782452] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  435.782552] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  435.782651] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  435.783076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  435.783197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  435.783307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  435.783415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  435.783517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  435.783623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  435.783769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  435.783876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  435.783980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  435.784088] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  435.784214] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  435.784328] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  435.784442] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  435.784590] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  435.784836] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  435.784976] [drm:intel_power_well_disable [i915]] disabling DC off
>[  435.785081] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  435.785174] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  435.785774] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  435.786403] [drm:intel_power_well_disable [i915]] disabling always-on
>[  435.788030] [drm:drm_mode_addfb2] [FB:89]
>[  435.788193] [drm:drm_mode_addfb2] [FB:91]
>[  435.846269] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  435.846881] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  435.847328] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  435.848059] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  435.848083] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  435.848188] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  435.848222] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  435.848260] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  435.848300] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  435.848334] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  435.848369] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  435.848404] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  435.848439] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  435.848472] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  435.848505] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  435.848536] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  435.848541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  435.848573] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  435.848577] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  435.848610] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  435.848642] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  435.849287] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  435.849321] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  435.849356] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  435.849393] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  435.849426] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  435.849462] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  435.849497] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  435.849532] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  435.849566] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  435.849604] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  435.849646] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  435.850060] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  435.850434] [drm:intel_power_well_enable [i915]] enabling always-on
>[  435.850462] [drm:intel_power_well_enable [i915]] enabling DC off
>[  435.850919] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  435.851367] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  435.851399] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  435.851452] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  435.851602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  435.851638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  435.851943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  435.851978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  435.852013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  435.852048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  435.852085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  435.852120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  435.852155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  435.852189] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  435.852227] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  435.852263] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  435.852331] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  435.852365] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  435.852563] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  435.852598] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  436.236911] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  436.303110] [drm:wait_panel_status [i915]] Wait complete
>[  436.303222] [drm:edp_panel_on [i915]] Wait for panel power on
>[  436.303338] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  436.411745] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  436.411854] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  436.411953] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  436.412136] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  436.504783] [drm:wait_panel_status [i915]] Wait complete
>[  436.504887] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  436.504969] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  436.506893] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  436.506982] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  436.507075] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  436.508660] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  436.508841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  436.510598] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  436.511398] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  436.513997] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  436.514148] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  436.514234] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  436.514331] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  436.514451] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  436.514538] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  436.531156] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  436.531262] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  436.531549] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  438.214725] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  438.214857] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  438.420880] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  438.420943] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  438.431614] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  438.431656] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  438.431764] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  438.482854] [drm:wait_panel_status [i915]] Wait complete
>[  438.482945] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  438.483051] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  438.483146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  438.483187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  438.483224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  438.483259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  438.483294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  438.483329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  438.483365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  438.483400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  438.483435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  438.483470] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  438.483509] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  438.483545] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  438.483581] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  438.483641] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  438.483751] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  438.483787] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  438.483843] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  438.483882] [drm:intel_power_well_disable [i915]] disabling DC off
>[  438.483918] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  438.483947] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  438.484499] [drm:intel_power_well_disable [i915]] disabling always-on
>[  438.484544] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  438.484580] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  438.484616] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  438.484683] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  438.485860] [drm:drm_mode_addfb2] [FB:89]
>[  438.485951] [drm:drm_mode_addfb2] [FB:91]
>[  438.543106] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  438.543566] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  438.544164] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  438.544856] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  438.544880] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  438.544983] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  438.545019] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  438.545059] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  438.545100] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  438.545132] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  438.545167] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  438.545203] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  438.545237] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  438.545271] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  438.545303] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  438.545335] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  438.545339] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  438.545371] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  438.545374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  438.545407] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  438.545440] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  438.545472] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  438.545505] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  438.545538] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  438.545573] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  438.545605] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  438.545641] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  438.545723] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  438.545760] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  438.545801] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  438.545846] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  438.545887] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  438.546267] [drm:intel_power_well_enable [i915]] enabling always-on
>[  438.546298] [drm:intel_power_well_enable [i915]] enabling DC off
>[  438.546584] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  438.546636] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  438.546722] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  438.546780] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  438.546962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  438.546998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  438.547037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  438.547071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  438.547108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  438.547144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  438.547182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  438.547217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  438.547253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  438.547288] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  438.547328] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  438.547367] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  438.547437] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  438.547474] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  438.547714] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  438.547755] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  438.940856] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  439.002789] [drm:wait_panel_status [i915]] Wait complete
>[  439.002850] [drm:edp_panel_on [i915]] Wait for panel power on
>[  439.002914] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  439.111318] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  439.111397] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  439.111470] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  439.111642] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  439.204980] [drm:wait_panel_status [i915]] Wait complete
>[  439.205115] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  439.205223] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  439.206970] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  439.207069] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  439.207173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  439.208701] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  439.208892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  439.210573] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  439.211159] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  439.213843] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  439.214013] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  439.214112] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  439.214221] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  439.214357] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  439.214453] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  439.230921] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  439.231005] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  439.231242] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  440.914729] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  440.915151] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  441.116888] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  441.117048] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  441.132148] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  441.132263] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  441.132382] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  441.184141] [drm:wait_panel_status [i915]] Wait complete
>[  441.184272] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  441.184478] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  441.184668] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  441.184768] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  441.184868] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  441.185076] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  441.186032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  441.186157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  441.186265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  441.186368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  441.186470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  441.186571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  441.186678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  441.186889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  441.186996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  441.187107] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  441.187237] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  441.187354] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  441.187467] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  441.187626] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  441.187925] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  441.188032] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  441.188183] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  441.188292] [drm:intel_power_well_disable [i915]] disabling DC off
>[  441.188397] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  441.188488] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  441.189717] [drm:intel_power_well_disable [i915]] disabling always-on
>[  441.191436] [drm:drm_mode_addfb2] [FB:89]
>[  441.191507] [drm:drm_mode_addfb2] [FB:91]
>[  441.248493] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  441.249009] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  441.249604] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  441.250212] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  441.250235] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  441.250340] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  441.250374] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  441.250412] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  441.250443] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  441.250478] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  441.250512] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  441.250547] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  441.250581] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  441.250612] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  441.250617] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  441.250649] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  441.250699] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  441.250735] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  441.250769] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  441.250807] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  441.250843] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  441.250879] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  441.250918] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  441.250954] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  441.250990] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  441.251027] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  441.251063] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  441.251101] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  441.251152] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  441.251198] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  441.251233] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  441.251589] [drm:intel_power_well_enable [i915]] enabling always-on
>[  441.251620] [drm:intel_power_well_enable [i915]] enabling DC off
>[  441.251937] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  441.251992] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  441.252027] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  441.252078] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  441.252326] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  441.256569] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  441.256642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  441.256740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  441.256779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  441.256812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  441.256845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  441.256879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  441.256914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  441.256949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  441.256984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  441.257018] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  441.257057] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  441.257092] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  441.257162] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  441.257195] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  441.258067] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  441.259076] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  441.259610] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  441.259645] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  441.259740] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  441.259772] [drm:hsw_audio_config_update [i915]] using automatic N
>[  441.259865] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  441.259898] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  441.276695] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  441.276829] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  441.277040] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  442.960215] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  442.960450] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  442.960554] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  442.960880] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  442.977573] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  442.977700] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  442.978071] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  442.978321] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  442.982619] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  442.982731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  442.982970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  442.983088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  442.983192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  442.983297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  442.983400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  442.983517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  442.983619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  442.983726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  442.983879] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  442.984001] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  442.984113] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  442.984226] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  442.984378] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  442.984483] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  442.984628] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  442.984836] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  442.984975] [drm:intel_power_well_disable [i915]] disabling DC off
>[  442.985079] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  442.985172] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  442.985873] [drm:intel_power_well_disable [i915]] disabling always-on
>[  442.987340] [drm:drm_mode_addfb2] [FB:89]
>[  442.987504] [drm:drm_mode_addfb2] [FB:91]
>[  443.043919] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  443.044365] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  443.045149] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  443.045573] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  443.045596] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  443.045870] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  443.045905] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  443.045943] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  443.045975] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  443.046010] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  443.046045] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  443.046079] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  443.046112] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  443.046143] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  443.046150] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  443.046182] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  443.046185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  443.046218] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  443.046250] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  443.046283] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  443.046317] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  443.046349] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  443.046388] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  443.046419] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  443.046455] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  443.046489] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  443.046523] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  443.046557] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  443.046606] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  443.046654] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  443.047470] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  443.047935] [drm:intel_power_well_enable [i915]] enabling always-on
>[  443.047965] [drm:intel_power_well_enable [i915]] enabling DC off
>[  443.048247] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  443.048294] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  443.048327] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  443.048380] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  443.048611] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  443.052843] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  443.052919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  443.052957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  443.052996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  443.053031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  443.053066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  443.053101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  443.053136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  443.053171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  443.053206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  443.053241] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  443.053277] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  443.053313] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  443.053379] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  443.053413] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  443.054208] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  443.055376] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  443.056040] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  443.056078] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  443.056136] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  443.056172] [drm:hsw_audio_config_update [i915]] using automatic N
>[  443.073120] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  443.073194] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  443.073404] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  444.756743] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  444.757155] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  444.757282] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  444.757483] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  444.774258] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  444.774465] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  444.774710] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  444.779157] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  444.779263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  444.779375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  444.779488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  444.779589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  444.779689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  444.779921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  444.780041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  444.780144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  444.780244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  444.780348] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  444.780468] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  444.780580] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  444.780693] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  444.781142] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  444.781250] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  444.781392] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  444.781542] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  444.781654] [drm:intel_power_well_disable [i915]] disabling DC off
>[  444.781999] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  444.782092] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  444.782705] [drm:intel_power_well_disable [i915]] disabling always-on
>[  444.784301] [drm:drm_mode_addfb2] [FB:89]
>[  444.784465] [drm:drm_mode_addfb2] [FB:91]
>[  444.844023] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  444.844480] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  444.845127] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  444.845729] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  444.845751] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  444.845853] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  444.845887] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  444.845924] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  444.845956] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  444.845990] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  444.846024] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  444.846059] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  444.846091] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  444.846123] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  444.846128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  444.846160] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  444.846164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  444.846197] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  444.846230] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  444.846263] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  444.846297] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  444.846329] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  444.846367] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  444.846399] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  444.846435] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  444.846469] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  444.846504] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  444.846551] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  444.846598] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  444.846631] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  444.847012] [drm:intel_power_well_enable [i915]] enabling always-on
>[  444.847042] [drm:intel_power_well_enable [i915]] enabling DC off
>[  444.847324] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  444.847373] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  444.847407] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  444.847462] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  444.847774] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  444.852009] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  444.852083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  444.852122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  444.852161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  444.852196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  444.852231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  444.852266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  444.852301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  444.852336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  444.852371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  444.852406] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  444.852442] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  444.852478] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  444.852544] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  444.852579] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  444.853393] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  444.854512] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  444.855145] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  444.855180] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  444.855230] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  444.855263] [drm:hsw_audio_config_update [i915]] using automatic N
>[  444.872206] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  444.872278] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  444.872485] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  446.555952] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  446.556250] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  446.556377] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  446.556596] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  446.573046] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  446.573228] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  446.573403] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  446.577065] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  446.577172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  446.577286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  446.577400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  446.577502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  446.577602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  446.577703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  446.578629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  446.578983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  446.579087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  446.579189] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  446.579313] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  446.579425] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  446.579536] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  446.579696] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  446.580535] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  446.580676] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  446.581215] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  446.581328] [drm:intel_power_well_disable [i915]] disabling DC off
>[  446.581431] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  446.581526] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  446.582963] [drm:intel_power_well_disable [i915]] disabling always-on
>[  446.591686] [IGT] kms_flip: exiting, ret=0
>[  446.618605] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  446.618644] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  446.618734] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  446.618778] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  446.618814] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  446.618854] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  446.618895] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  446.618934] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  446.618972] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  446.619008] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  446.619045] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  446.619053] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  446.619091] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  446.619095] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  446.619132] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  446.619169] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  446.619206] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  446.619243] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  446.619280] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  446.619322] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  446.619358] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  446.619398] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  446.619437] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  446.619475] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  446.619513] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  446.619560] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  446.619598] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  446.619640] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  446.619699] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  446.619737] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  446.619775] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  446.619812] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  446.619848] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  446.619884] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  446.619888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  446.619924] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  446.619928] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  446.619966] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  446.620002] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  446.620040] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  446.620077] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  446.620113] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  446.620152] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  446.620188] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  446.620226] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  446.620265] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  446.620303] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  446.620340] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  446.620382] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  446.620430] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  446.620470] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  446.620514] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  446.620552] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  446.620748] [drm:intel_power_well_enable [i915]] enabling always-on
>[  446.620780] [drm:intel_power_well_enable [i915]] enabling DC off
>[  446.621069] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  446.621129] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  446.621260] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  446.621298] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  446.621359] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  446.621556] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  446.624728] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  446.624783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  446.624837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  446.624899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  446.624954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  446.625008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  446.625063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  446.625117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  446.625171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  446.625225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  446.625279] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  446.625337] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  446.625394] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  446.625489] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  446.625540] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  446.625919] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  446.625975] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  446.626044] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  446.626099] [drm:wait_panel_status [i915]] Wait complete
>[  446.626156] [drm:edp_panel_on [i915]] Wait for panel power on
>[  446.626218] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  446.734597] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  446.734665] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  446.734732] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  446.734844] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  446.827090] [drm:wait_panel_status [i915]] Wait complete
>[  446.827199] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  446.827298] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  446.828930] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  446.829006] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  446.829089] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  446.830178] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  446.830255] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  446.831649] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  446.832103] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  446.834484] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  446.834604] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  446.834669] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  446.834791] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  446.834883] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  446.834947] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  446.835036] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  446.835103] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  446.835370] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  446.835435] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  446.835887] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  446.838117] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  446.838868] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  446.838935] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  446.839038] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  446.839101] [drm:hsw_audio_config_update [i915]] using automatic N
>[  446.855925] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  446.856013] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  446.856286] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  446.856592] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  446.856679] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  446.857105] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  446.857872] Console: switching to colour frame buffer device 240x67
>[  447.068197] Console: switching to colour dummy device 80x25
>[  447.068420] [IGT] kms_force_connector_basic: executing
>[  447.091471] [IGT] kms_force_connector_basic: exiting, ret=77
>[  447.122807] Console: switching to colour frame buffer device 240x67
>[  447.334323] Console: switching to colour dummy device 80x25
>[  447.334540] [IGT] kms_force_connector_basic: executing
>[  447.359442] [IGT] kms_force_connector_basic: exiting, ret=77
>[  447.389457] Console: switching to colour frame buffer device 240x67
>[  447.607529] Console: switching to colour dummy device 80x25
>[  447.607827] [IGT] kms_force_connector_basic: executing
>[  447.632417] [IGT] kms_force_connector_basic: exiting, ret=77
>[  447.656153] Console: switching to colour frame buffer device 240x67
>[  447.879719] Console: switching to colour dummy device 80x25
>[  447.879947] [IGT] kms_force_connector_basic: executing
>[  447.904494] [IGT] kms_force_connector_basic: exiting, ret=77
>[  447.935313] Console: switching to colour frame buffer device 240x67
>[  448.144344] Console: switching to colour dummy device 80x25
>[  448.144568] [IGT] kms_frontbuffer_tracking: executing
>[  448.187098] [drm:drm_mode_addfb2] [FB:89]
>[  448.187325] [drm:drm_mode_addfb2] [FB:91]
>[  448.187551] [drm:drm_mode_addfb2] [FB:101]
>[  448.193522] [drm:drm_mode_addfb2] [FB:102]
>[  448.240420] [drm:drm_mode_addfb2] [FB:103]
>[  448.251677] [drm:drm_mode_addfb2] [FB:104]
>[  448.251896] [drm:drm_mode_addfb2] [FB:105]
>[  448.252122] [drm:drm_mode_addfb2] [FB:106]
>[  448.253444] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  448.253468] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  448.468735] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  448.469373] [IGT] kms_frontbuffer_tracking: starting subtest basic
>[  448.469879] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  448.470298] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  448.676853] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  448.676950] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  448.685623] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  448.685792] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  448.685863] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  448.737954] [drm:wait_panel_status [i915]] Wait complete
>[  448.738051] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  448.738153] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  448.738237] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  448.738318] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  448.738398] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  448.738539] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  448.738619] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  448.738940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  448.739035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  448.739128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  448.739209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  448.739290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  448.739373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  448.739454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  448.739538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  448.739619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  448.739719] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  448.739908] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  448.740007] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  448.740105] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  448.755902] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  448.756046] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  448.775924] [drm:drm_mode_addfb2] [FB:89]
>[  448.776154] [drm:drm_mode_addfb2] [FB:91]
>[  448.776379] [drm:drm_mode_addfb2] [FB:92]
>[  448.782387] [drm:drm_mode_addfb2] [FB:101]
>[  448.829733] [drm:drm_mode_addfb2] [FB:102]
>[  448.840767] [drm:drm_mode_addfb2] [FB:103]
>[  448.840984] [drm:drm_mode_addfb2] [FB:104]
>[  448.841202] [drm:drm_mode_addfb2] [FB:105]
>[  448.841241] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  448.841457] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  448.841557] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  448.841732] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  448.841781] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  448.841869] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  448.855990] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  448.856125] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  448.856255] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  448.860477] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  448.860534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  448.860595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  448.860656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  448.860791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  448.860847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  448.860903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  448.860966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  448.861021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  448.861077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  448.861131] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  448.861195] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  448.861256] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  448.861316] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  448.861401] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  448.861458] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  448.861536] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  448.861620] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  448.861719] [drm:intel_power_well_disable [i915]] disabling DC off
>[  448.861775] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  448.861824] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  448.862389] [drm:intel_power_well_disable [i915]] disabling always-on
>[  448.862611] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  448.878556] [drm:drm_mode_addfb2] [FB:97]
>[  448.883261] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  448.883281] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  448.883398] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  448.883432] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  448.883471] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  448.883511] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  448.883543] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  448.883579] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  448.883614] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  448.883649] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  448.883728] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  448.883765] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  448.883801] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  448.883809] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  448.883842] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  448.883850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  448.883886] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  448.883922] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  448.883960] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  448.883997] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  448.884034] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  448.884073] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  448.884109] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  448.884144] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  448.884182] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  448.884217] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  448.884253] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  448.884291] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  448.884334] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  448.884370] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  448.884791] [drm:intel_power_well_enable [i915]] enabling always-on
>[  448.884822] [drm:intel_power_well_enable [i915]] enabling DC off
>[  448.885103] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  448.885153] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  448.885297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  448.885333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  448.885371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  448.885406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  448.885441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  448.885476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  448.885512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  448.885547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  448.885582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  448.885616] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  448.885654] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  448.885755] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  448.885825] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  448.885859] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  448.886059] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  448.886096] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  449.188875] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  449.302499] [drm:wait_panel_status [i915]] Wait complete
>[  449.302582] [drm:edp_panel_on [i915]] Wait for panel power on
>[  449.302669] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  449.411092] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  449.411151] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  449.411205] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  449.411331] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  449.504088] [drm:wait_panel_status [i915]] Wait complete
>[  449.504200] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  449.504290] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  449.506650] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  449.506812] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  449.506906] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  449.508235] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  449.508327] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  449.510167] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  449.510554] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  449.513186] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  449.513322] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  449.513409] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  449.513506] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  449.513626] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  449.513713] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  449.514435] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  449.514526] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  449.530472] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  449.530589] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  449.531255] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  449.764201] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  449.764403] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  449.764650] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  449.765665] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  449.972936] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  449.973089] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  449.981921] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  449.982034] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  449.982150] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  450.033998] [drm:wait_panel_status [i915]] Wait complete
>[  450.034118] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  450.034240] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  450.034440] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  450.034542] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  450.034642] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  450.034742] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  450.034918] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  450.035984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  450.036106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  450.036216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  450.036319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  450.036423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  450.036526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  450.036634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  450.037535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  450.037637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  450.038068] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  450.038193] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  450.038305] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  450.038414] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  450.038561] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  450.038705] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  450.039468] [drm:intel_power_well_disable [i915]] disabling DC off
>[  450.039571] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  450.039660] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  450.041340] [drm:intel_power_well_disable [i915]] disabling always-on
>[  450.042278] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  450.043119] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  450.058385] [drm:drm_mode_addfb2] [FB:97]
>[  450.069496] [drm:drm_mode_addfb2] [FB:106]
>[  450.080564] [drm:drm_mode_addfb2] [FB:107]
>[  450.091559] [drm:drm_mode_addfb2] [FB:108]
>[  450.305822] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  450.305845] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  450.305963] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  450.305998] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  450.306037] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  450.306076] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  450.306108] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  450.306143] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  450.306178] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  450.306213] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  450.306247] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  450.306279] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  450.306310] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  450.306316] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  450.306348] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  450.306352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  450.306385] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  450.306417] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  450.306450] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  450.306482] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  450.306514] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  450.306553] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  450.306585] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  450.306621] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  450.306655] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  450.306739] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  450.306773] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  450.306813] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  450.306858] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  450.306895] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  450.307281] [drm:intel_power_well_enable [i915]] enabling always-on
>[  450.307312] [drm:intel_power_well_enable [i915]] enabling DC off
>[  450.307596] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  450.307650] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  450.307848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  450.307884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  450.307922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  450.307958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  450.307994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  450.308029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  450.308067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  450.308102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  450.308138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  450.308174] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  450.308214] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  450.308253] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  450.308323] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  450.308359] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  450.308589] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  450.308626] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  450.484855] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  450.602651] [drm:wait_panel_status [i915]] Wait complete
>[  450.602755] [drm:edp_panel_on [i915]] Wait for panel power on
>[  450.602822] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  450.711205] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  450.711263] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  450.711317] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  450.711417] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  450.804022] [drm:wait_panel_status [i915]] Wait complete
>[  450.804106] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  450.804173] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  450.805775] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  450.805850] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  450.805927] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  450.806976] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  450.807051] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  450.808413] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  450.808863] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  450.810825] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  450.810944] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  450.811014] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  450.811093] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  450.811192] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  450.811261] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  450.811357] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  450.811428] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  450.828017] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  450.828117] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  450.828380] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  451.061711] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  451.061926] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  451.061971] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  451.311885] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  451.312041] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  451.312090] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  451.561899] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  451.562045] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  451.562093] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  451.811874] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  451.812085] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  451.812326] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  451.812701] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  452.020885] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  452.021037] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  452.029936] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  452.030049] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  452.030167] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  452.081977] [drm:wait_panel_status [i915]] Wait complete
>[  452.082091] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  452.082212] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  452.082414] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  452.082512] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  452.082613] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  452.082710] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  452.082880] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  452.083311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  452.083429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  452.083538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  452.083645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  452.083821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  452.083938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  452.084048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  452.084159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  452.084265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  452.084375] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  452.084497] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  452.084608] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  452.084720] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  452.085137] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  452.085281] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  452.085415] [drm:intel_power_well_disable [i915]] disabling DC off
>[  452.085518] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  452.085608] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  452.086890] [drm:intel_power_well_disable [i915]] disabling always-on
>[  452.087875] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  452.088595] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  452.094282] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  452.094304] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  452.094414] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  452.094447] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  452.094487] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  452.094528] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  452.094560] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  452.094611] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  452.094644] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  452.094844] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  452.094879] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  452.094913] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  452.094947] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  452.094953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  452.094987] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  452.094992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  452.095027] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  452.095061] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  452.095096] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  452.095131] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  452.095166] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  452.095201] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  452.095235] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  452.095270] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  452.095305] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  452.095339] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  452.095374] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  452.095411] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  452.095455] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  452.095490] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  452.101410] [drm:intel_power_well_enable [i915]] enabling always-on
>[  452.101442] [drm:intel_power_well_enable [i915]] enabling DC off
>[  452.101966] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  452.102021] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  452.102342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  452.102377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  452.102413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  452.102447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  452.102480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  452.102514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  452.102549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  452.102583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  452.102616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  452.102649] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  452.102730] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  452.102770] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  452.103103] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  452.103138] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  452.103349] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  452.103385] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  452.532865] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  452.603276] [drm:wait_panel_status [i915]] Wait complete
>[  452.603359] [drm:edp_panel_on [i915]] Wait for panel power on
>[  452.603444] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  452.711843] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  452.711921] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  452.711993] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  452.712147] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  452.805027] [drm:wait_panel_status [i915]] Wait complete
>[  452.805156] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  452.805264] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  452.806965] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  452.807063] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  452.807167] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  452.808459] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  452.808559] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  452.810213] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  452.810633] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  452.813698] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  452.813935] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  452.813994] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  452.814034] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  452.814085] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  452.814119] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  452.814167] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  452.814200] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  452.830999] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  452.831082] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  452.831319] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  453.064709] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  453.298187] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  453.311582] [drm:drm_mode_addfb2] [FB:97]
>[  453.548099] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  453.781492] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  454.014857] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  454.248216] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  454.481580] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  454.714958] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  454.981506] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  455.215084] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  455.465175] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  455.698450] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  455.931903] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  456.165181] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  456.398583] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  456.631921] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  456.632445] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  456.632968] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  456.836889] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  456.837053] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  456.849996] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  456.850110] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  456.850229] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  456.901690] [drm:wait_panel_status [i915]] Wait complete
>[  456.901908] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  456.902033] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  456.902239] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  456.902469] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  456.902569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  456.902675] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  456.902774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  456.902873] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  456.903006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  456.903112] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  456.903214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  456.903326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  456.903432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  456.903548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  456.903657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  456.903822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  456.903930] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  456.904058] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  456.904172] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  456.904292] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  456.904450] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  456.904599] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  456.905002] [drm:intel_power_well_disable [i915]] disabling DC off
>[  456.905107] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  456.905199] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  456.906422] [drm:intel_power_well_disable [i915]] disabling always-on
>[  456.909011] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[  456.966180] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  456.966216] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  456.966254] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  456.966292] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  456.966324] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  456.966359] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  456.966392] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  456.966425] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  456.966458] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  456.966490] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  456.966522] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  456.966529] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  456.966560] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  456.966564] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  456.966597] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  456.966629] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  456.967335] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  456.967370] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  456.967403] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  456.967439] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  456.967473] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  456.967506] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  456.967541] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  456.967574] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  456.967608] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  456.967655] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  456.967750] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  456.967788] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  456.967822] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  456.967858] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  456.967893] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  456.967927] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  456.967961] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  456.967996] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  456.968004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  456.968037] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  456.968043] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  456.968076] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  456.968112] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  456.968146] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  456.968181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  456.968215] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  456.968252] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  456.968285] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  456.968319] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  456.968353] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  456.968389] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  456.968423] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  456.968461] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  456.968507] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  456.968542] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  456.968582] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  456.968617] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  456.968833] [drm:intel_power_well_enable [i915]] enabling always-on
>[  456.968863] [drm:intel_power_well_enable [i915]] enabling DC off
>[  456.969198] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  456.969251] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  456.970455] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  456.970490] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  456.970719] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  456.971825] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  456.976081] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  456.976117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  456.976151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  456.976193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  456.976227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  456.976260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  456.976293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  456.976327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  456.976360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  456.976393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  456.976427] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  456.976464] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  456.976499] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  456.976591] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  456.976624] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  456.978129] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  456.978180] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  457.356918] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  457.401658] [drm:wait_panel_status [i915]] Wait complete
>[  457.401746] [drm:edp_panel_on [i915]] Wait for panel power on
>[  457.401801] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  457.510185] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  457.510233] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  457.510279] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  457.510393] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  457.602642] [drm:wait_panel_status [i915]] Wait complete
>[  457.603012] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  457.603096] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  457.605806] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  457.605887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  457.605971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  457.607537] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  457.607618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  457.609397] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  457.610041] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  457.612518] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  457.612662] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  457.613030] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  457.613177] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  457.613290] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  457.613368] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  457.614131] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  457.614215] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  457.614520] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  457.614599] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  457.616051] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  457.617243] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  457.617888] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  457.617922] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  457.618018] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  457.618051] [drm:hsw_audio_config_update [i915]] using automatic N
>[  457.634944] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  457.635014] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  457.635232] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  457.635452] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  457.635517] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  457.636120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  457.651931] Console: switching to colour frame buffer device 240x67
>[  457.884560] Console: switching to colour dummy device 80x25
>[  457.884874] [IGT] kms_pipe_crc_basic: executing
>[  457.907395] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  457.907462] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  457.907523] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  457.907578] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  457.907630] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  457.908145] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  457.909045] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  457.909591] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  457.909608] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  457.909615] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  457.910027] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  457.910092] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  457.911144] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  457.911575] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  457.911625] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  457.911679] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  457.920744] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.929490] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.938212] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.946938] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.955666] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.964487] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.973213] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.981956] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.990673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.999460] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.008216] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.016953] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.025657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.034333] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.043075] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.051832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.060553] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.069311] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.078055] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.086795] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.095544] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.104348] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.113249] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.122085] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.130987] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.139832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.148670] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.157562] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.166387] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.175224] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.184050] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.192892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.192930] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  458.192943] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  458.193004] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  458.193084] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  458.273791] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  458.277985] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  458.278089] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  458.278101] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  458.279095] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  458.279107] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  458.279116] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  458.279121] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  458.279458] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  458.279469] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  458.279478] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  458.279486] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  458.279494] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  458.279503] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  458.279511] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  458.279520] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  458.279531] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  458.279540] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  458.279548] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  458.279556] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  458.279565] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  458.279573] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  458.279581] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  458.279590] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  458.279598] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  458.279609] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  458.279618] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  458.279626] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  458.279634] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  458.280820] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  458.280830] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  458.280839] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  458.295665] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  458.295712] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  458.295753] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  458.295787] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  458.295820] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  458.295854] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  458.296398] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  458.296870] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  458.296881] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  458.296885] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  458.297358] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  458.297403] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  458.297962] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  458.298337] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  458.298783] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  458.298828] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  458.307464] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.316084] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.324770] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.333476] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.342193] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.350920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.359640] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.368501] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.377318] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.386160] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.395077] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.404090] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.413080] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.422056] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.431117] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.440101] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.448983] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.457842] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.466772] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.475639] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.484560] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.493597] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.502869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.511848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.520824] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.529871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.538864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.547857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.556847] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.565840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.574872] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.583871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.583920] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  458.583936] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  458.585576] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  458.585697] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  458.666716] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  458.670901] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  458.671016] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  458.671029] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  458.671818] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  458.671828] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  458.671838] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  458.671844] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  458.672237] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  458.672250] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  458.672260] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  458.672272] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  458.672285] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  458.672295] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  458.672304] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  458.672313] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  458.672323] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  458.672332] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  458.672342] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  458.672351] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  458.672361] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  458.672370] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  458.672380] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  458.672389] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  458.672398] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  458.672411] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  458.672420] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  458.672430] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  458.672439] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  458.672448] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  458.672457] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  458.672467] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  458.674260] [IGT] kms_pipe_crc_basic: starting subtest bad-nb-words-1
>[  458.674668] [drm:display_crc_ctl_write [i915]] tokenize failed, a command is 3 words
>[  458.675040] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  458.701870] Console: switching to colour frame buffer device 240x67
>[  458.933589] Console: switching to colour dummy device 80x25
>[  458.934170] [IGT] kms_pipe_crc_basic: executing
>[  458.961195] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  458.961252] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  458.961302] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  458.961348] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  458.961391] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  458.961435] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  458.962397] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  458.962910] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  458.962926] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  458.962931] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  458.962974] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  458.963032] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  458.963593] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  458.964055] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  458.964099] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  458.964156] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  458.972802] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.981481] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.990147] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.998909] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.007625] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.016477] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.025235] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.034001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.042790] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.051547] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.060308] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.069070] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.077843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.086605] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.095800] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.104557] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.113401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.122279] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.131185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.140084] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.149008] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.157898] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.166777] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.175652] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.184580] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.193787] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.202699] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.211712] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.220834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.229888] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.238861] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.247840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.247887] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  459.247903] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  459.247979] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  459.248082] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  459.329314] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  459.333500] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  459.333617] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  459.333629] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  459.334859] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  459.334869] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  459.334878] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  459.334885] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  459.335273] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  459.335285] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  459.335295] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  459.335304] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  459.335314] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  459.335323] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  459.335333] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  459.335342] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  459.335351] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  459.335361] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  459.335370] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  459.335381] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  459.335391] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  459.335400] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  459.335410] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  459.335419] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  459.335428] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  459.335437] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  459.335446] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  459.335456] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  459.335465] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  459.335474] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  459.335483] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  459.335492] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  459.352866] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  459.352913] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  459.352952] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  459.352987] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  459.353019] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  459.353054] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  459.353587] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  459.354056] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  459.354069] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  459.354074] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  459.354550] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  459.354596] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  459.355146] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  459.355518] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  459.356000] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  459.356048] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  459.364709] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.373344] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.381963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.390592] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.399385] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.408106] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.416878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.425782] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.434612] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.443665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.452568] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.461408] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.470346] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.479283] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.488293] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.497230] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.506160] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.515160] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.524171] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.533172] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.542176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.551182] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.560184] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.569183] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.578183] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.587174] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.596174] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.605172] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.614181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.623192] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.632198] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.641198] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  459.641246] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  459.641262] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  459.642947] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  459.643065] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  459.723904] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  459.728092] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  459.728209] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  459.728221] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  459.729046] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  459.729056] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  459.729065] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  459.729071] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  459.729453] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  459.729466] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  459.729476] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  459.729485] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  459.729502] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  459.729512] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  459.729521] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  459.729530] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  459.729540] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  459.729550] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  459.729559] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  459.729569] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  459.729581] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  459.729594] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  459.729604] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  459.729613] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  459.729622] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  459.729632] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  459.729749] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  459.729759] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  459.729768] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  459.729782] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  459.729792] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  459.729804] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  459.731376] [IGT] kms_pipe_crc_basic: starting subtest bad-nb-words-3
>[  459.731690] [drm:display_crc_ctl_write [i915]] too many words, allowed <= 3
>[  459.731845] [drm:display_crc_ctl_write [i915]] tokenize failed, a command is 3 words
>[  459.732167] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  459.768534] Console: switching to colour frame buffer device 240x67
>[  459.994887] Console: switching to colour dummy device 80x25
>[  459.995141] [IGT] kms_pipe_crc_basic: executing
>[  460.019419] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  460.019487] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  460.019547] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  460.019602] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  460.019654] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  460.019808] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  460.020417] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  460.021019] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  460.021037] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  460.021044] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  460.021086] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  460.021147] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  460.022145] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  460.022597] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  460.022718] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  460.022783] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  460.031520] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.040384] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.049239] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.058117] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.067005] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.075892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.084799] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.093673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.102620] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.111812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.120813] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.129820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.138824] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.147818] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.156880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.165875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.174864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.183861] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.192859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.201854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.210859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.219882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.228892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.237903] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.246907] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.255915] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.264926] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.273926] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.282930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.291921] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.300922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.309931] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.309978] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  460.309994] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  460.310072] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  460.310174] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  460.391024] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  460.395210] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  460.395326] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  460.395338] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  460.396439] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  460.396450] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  460.396459] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  460.396466] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  460.397304] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  460.397318] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  460.397328] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  460.397338] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  460.397347] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  460.397356] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  460.397366] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  460.397375] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  460.397385] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  460.397394] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  460.397404] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  460.397413] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  460.397423] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  460.397432] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  460.397441] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  460.397451] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  460.397460] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  460.397469] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  460.397479] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  460.397488] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  460.397497] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  460.397506] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  460.397516] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  460.397525] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  460.412921] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  460.412983] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  460.413039] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  460.413088] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  460.413133] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  460.413180] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  460.414013] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  460.414465] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  460.414476] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  460.414481] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  460.415194] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  460.415239] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  460.415848] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  460.416220] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  460.416598] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  460.416638] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  460.425536] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.434251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.442971] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.451683] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.460463] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.469180] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.477922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.486759] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.495532] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.504323] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.513152] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.521974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.530832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.539794] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.548708] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.557676] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.566725] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.575822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.584884] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.593874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.602874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.611848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.620833] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.629928] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.638911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.647893] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.656860] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.665839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.674866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.683855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.692863] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.701856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.701902] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  460.701917] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  460.703347] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  460.703464] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  460.784797] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  460.788983] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  460.789097] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  460.789108] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  460.790053] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  460.790064] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  460.790073] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  460.790079] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  460.790467] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  460.790480] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  460.790490] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  460.790502] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  460.790512] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  460.790521] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  460.790530] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  460.790540] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  460.790549] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  460.790559] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  460.790569] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  460.790578] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  460.790590] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  460.790600] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  460.790609] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  460.790619] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  460.790628] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  460.790992] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  460.791003] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  460.791013] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  460.791022] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  460.791032] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  460.791045] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  460.791054] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  460.793049] [IGT] kms_pipe_crc_basic: starting subtest bad-pipe
>[  460.793455] [drm:display_crc_ctl_write [i915]] unknown pipe D
>[  460.794063] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  460.830297] Console: switching to colour frame buffer device 240x67
>[  461.045301] Console: switching to colour dummy device 80x25
>[  461.045543] [IGT] kms_pipe_crc_basic: executing
>[  461.071395] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  461.071462] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  461.071523] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  461.071578] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  461.071630] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  461.071759] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  461.072369] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  461.073085] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  461.073104] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  461.073111] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  461.073160] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  461.073224] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  461.074237] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  461.074747] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  461.074800] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  461.074864] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  461.083536] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.092272] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.100998] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.109740] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.118503] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.127324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.136154] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.144955] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.153763] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.162548] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.171339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.180132] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.188965] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.197760] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.206549] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.215354] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.224272] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.233150] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.242021] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.250902] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.259787] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.268656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.277585] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.286695] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.295623] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.304800] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.313671] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.322609] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.331793] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.340726] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.349717] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.358697] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.358807] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  461.358822] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  461.358891] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  461.358986] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  461.440036] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  461.444226] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  461.444341] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  461.444353] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  461.445513] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  461.445525] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  461.445534] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  461.445541] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  461.446393] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  461.446407] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  461.446417] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  461.446426] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  461.446435] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  461.446445] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  461.446454] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  461.446464] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  461.446473] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  461.446483] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  461.446492] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  461.446502] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  461.446511] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  461.446520] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  461.446530] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  461.446539] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  461.446548] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  461.446558] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  461.446567] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  461.446576] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  461.446585] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  461.446595] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  461.446604] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  461.446613] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  461.462068] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  461.462129] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  461.462186] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  461.462234] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  461.462280] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  461.462327] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  461.463022] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  461.463493] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  461.463506] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  461.463510] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  461.464274] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  461.464319] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  461.464883] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  461.465259] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  461.465929] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  461.465977] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  461.474612] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.483335] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.492060] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.500798] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.509521] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.518242] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.526954] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.535783] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.544628] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.553488] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.562321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.571156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.580013] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.588867] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.597749] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.606585] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.615653] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.624552] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.633456] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.642358] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.651289] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.660165] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.669035] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.677896] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.686783] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.695664] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.704613] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.713805] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.722680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.731653] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.740651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.749654] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.749774] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  461.749789] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  461.751290] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  461.751394] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  461.832421] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  461.836606] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  461.836724] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  461.837089] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  461.838014] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  461.838025] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  461.838034] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  461.838041] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  461.838420] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  461.838432] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  461.838442] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  461.838451] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  461.838460] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  461.838470] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  461.838479] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  461.838489] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  461.838498] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  461.838510] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  461.838519] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  461.838529] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  461.838538] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  461.838548] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  461.838557] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  461.838566] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  461.838576] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  461.838585] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  461.838594] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  461.838603] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  461.838613] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  461.838622] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  461.838631] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  461.839908] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  461.841516] [IGT] kms_pipe_crc_basic: starting subtest bad-source
>[  461.842281] [drm:intel_crtc_set_crc_source [i915]] unknown source foo
>[  461.842550] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  461.880541] Console: switching to colour frame buffer device 240x67
>[  462.112034] Console: switching to colour dummy device 80x25
>[  462.112289] [IGT] kms_pipe_crc_basic: executing
>[  462.135435] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  462.135507] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  462.135571] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  462.135629] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  462.136151] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  462.136208] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  462.136881] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  462.137435] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  462.137452] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  462.137460] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  462.137513] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  462.137577] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  462.138222] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  462.138729] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  462.138778] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  462.138840] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  462.147543] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.156351] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.165262] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.174173] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.183110] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.192053] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.201124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.210124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.219118] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.228351] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.237366] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.246376] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.255384] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.264393] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.273398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.282414] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.291425] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.300420] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.309435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.318449] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.327452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.336465] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.345492] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.354596] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.364023] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.373120] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.382126] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.391163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.400181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.409184] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.418190] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.427203] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.427253] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  462.427269] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  462.427347] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  462.427455] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  462.508616] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  462.512933] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  462.513047] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  462.513060] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  462.514185] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  462.514198] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  462.514208] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  462.514214] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  462.514602] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  462.514614] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  462.514624] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  462.514634] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  462.515460] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  462.515470] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  462.515480] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  462.515489] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  462.515499] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  462.515509] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  462.515518] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  462.515528] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  462.515537] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  462.515547] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  462.515556] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  462.515565] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  462.515575] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  462.515584] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  462.515593] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  462.515603] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  462.515612] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  462.515621] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  462.515631] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  462.517281] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  462.528906] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  462.528954] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  462.528994] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  462.529029] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  462.529061] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  462.529095] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  462.529613] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  462.530474] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  462.530488] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  462.530492] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  462.531176] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  462.531223] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  462.531824] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  462.532202] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  462.532588] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  462.532628] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  462.541322] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.550077] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.558799] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.567532] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.576267] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.585060] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.593851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.602612] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.611482] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.620254] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.629010] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.637890] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.646795] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.655678] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.664632] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.673584] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.682596] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.691656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.700661] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.709666] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.718677] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.727711] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.736868] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.745877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.754886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.763892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.772892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.781908] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.790987] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.799997] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.809007] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.818016] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  462.818065] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  462.818082] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  462.819382] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  462.819500] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  462.898818] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  462.903001] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  462.903117] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  462.903129] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  462.903913] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  462.903927] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  462.903936] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  462.903942] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  462.904331] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  462.904343] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  462.904353] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  462.904363] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  462.904372] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  462.904385] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  462.904394] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  462.904404] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  462.904413] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  462.904423] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  462.904432] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  462.904442] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  462.904451] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  462.904460] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  462.904470] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  462.904482] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  462.904491] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  462.904501] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  462.904510] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  462.904519] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  462.904529] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  462.904538] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  462.904547] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  462.904556] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  462.906443] [IGT] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-A
>[  462.908614] [drm:drm_mode_addfb2] [FB:71]
>[  462.927948] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  462.927968] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  462.946893] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  462.947068] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  462.947132] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  462.947186] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  462.947403] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  463.148881] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  463.148994] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  463.164012] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  463.164095] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  463.164180] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  463.216156] [drm:wait_panel_status [i915]] Wait complete
>[  463.216273] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  463.216390] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  463.216556] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  463.216656] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  463.216753] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  463.216931] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  463.217061] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  463.217211] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  463.217337] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  463.217566] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  463.218925] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  463.219126] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  463.219354] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  463.223633] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  463.223828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  463.223929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  463.224045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  463.224144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  463.224243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  463.224343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  463.224452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  463.224552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  463.224650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  463.224855] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  463.224971] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  463.225082] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  463.225191] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  463.225375] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  463.225477] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  463.227012] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  463.227119] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  463.668846] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  463.803004] [drm:wait_panel_status [i915]] Wait complete
>[  463.803102] [drm:edp_panel_on [i915]] Wait for panel power on
>[  463.803205] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  463.911644] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  463.911738] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  463.911825] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  463.912005] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  464.004575] [drm:wait_panel_status [i915]] Wait complete
>[  464.004715] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  464.004970] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  464.006648] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  464.006792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  464.006884] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  464.007982] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  464.008077] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  464.009542] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  464.009978] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  464.012219] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  464.012352] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  464.012438] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  464.012532] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  464.012648] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  464.012825] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  464.012943] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  464.013034] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  464.046039] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  464.046170] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  464.046500] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  464.046694] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  464.046958] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  464.047098] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  464.047242] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  464.047919] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  464.113062] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  464.113386] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  464.316883] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  464.317037] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  464.329987] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  464.330101] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  464.330218] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  464.381962] [drm:wait_panel_status [i915]] Wait complete
>[  464.382079] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  464.382196] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  464.382401] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  464.382501] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  464.382601] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  464.382698] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  464.382877] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  464.383127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  464.383246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  464.383354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  464.383460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  464.383563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  464.383668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  464.383844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  464.383947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  464.384049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  464.384154] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  464.384273] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  464.384386] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  464.384497] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  464.384646] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  464.384863] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  464.385001] [drm:intel_power_well_disable [i915]] disabling DC off
>[  464.385106] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  464.385197] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  464.385872] [drm:intel_power_well_disable [i915]] disabling always-on
>[  464.389949] [drm:drm_mode_addfb2] [FB:71]
>[  464.411202] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  464.411224] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  464.411350] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  464.411389] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  464.411430] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  464.411475] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  464.411511] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  464.411550] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  464.411588] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  464.411625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  464.411663] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  464.411958] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  464.411995] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  464.412003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  464.412039] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  464.412043] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  464.412083] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  464.412120] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  464.412159] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  464.412202] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  464.412241] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  464.412284] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  464.412324] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  464.412364] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  464.412404] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  464.412445] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  464.412484] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  464.412528] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  464.412577] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  464.412618] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  464.413109] [drm:intel_power_well_enable [i915]] enabling always-on
>[  464.413144] [drm:intel_power_well_enable [i915]] enabling DC off
>[  464.413430] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  464.413486] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  464.413640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  464.413785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  464.413830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  464.413870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  464.413910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  464.413948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  464.413989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  464.414029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  464.414070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  464.414111] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  464.414157] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  464.414199] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  464.414275] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  464.414314] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  464.414534] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  464.414575] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  464.556608] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x18001a18, pins 0x00000040
>[  464.556686] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - long
>[  464.556757] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 6 - cnt: 0
>[  464.556927] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - long
>[  464.754301] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x18001a18, pins 0x00000040
>[  464.754362] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - long
>[  464.754418] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 6 - cnt: 1
>[  464.754542] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - long
>[  464.836844] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  464.903011] [drm:wait_panel_status [i915]] Wait complete
>[  464.903101] [drm:edp_panel_on [i915]] Wait for panel power on
>[  464.903194] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  465.011628] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  465.011713] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  465.011791] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  465.011953] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  465.105237] [drm:wait_panel_status [i915]] Wait complete
>[  465.105366] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  465.105472] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  465.107175] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  465.107263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  465.107354] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  465.108697] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  465.108875] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  465.110418] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  465.110898] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  465.113518] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  465.113676] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  465.113863] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  465.113974] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  465.114112] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  465.114210] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  465.114339] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  465.114440] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  465.130627] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  465.130760] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  465.131041] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  465.131456] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[  465.131541] [drm:i915_hotplug_work_func [i915]] Connector DP-2 (pin 6) received hotplug event.
>[  465.131619] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  465.131692] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  465.131855] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  465.131962] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  465.142308] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.151365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.160365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.169330] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.178298] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.187333] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.196372] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.205326] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.214349] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.223320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.232336] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.241375] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.250382] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.259351] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.268325] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.277281] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.286305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.295297] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.304342] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.313328] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.322320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.331286] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.340333] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.349339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.358310] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.367297] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.376320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.385332] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.394349] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.403290] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.412227] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.421162] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.421211] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  465.421301] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  465.421398] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  465.421531] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  465.421643] [drm:i915_hotplug_work_func [i915]] Connector HDMI-A-1 (pin 6) received hotplug event.
>[  465.422031] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  465.422123] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  465.422233] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  465.503227] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  465.507408] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  465.507522] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  465.507535] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  465.507621] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  465.508054] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  465.508204] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[  465.508544] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  465.509023] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  465.716879] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  465.717032] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  465.732017] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  465.732130] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  465.732248] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  465.784062] [drm:wait_panel_status [i915]] Wait complete
>[  465.784177] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  465.784294] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  465.784498] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  465.784598] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  465.784698] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  465.784795] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  465.784969] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  465.785221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  465.785341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  465.785450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  465.785556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  465.785656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  465.785871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  465.785984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  465.786089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  465.786197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  465.786303] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  465.786427] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  465.786538] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  465.786653] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  465.786891] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  465.787038] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  465.787172] [drm:intel_power_well_disable [i915]] disabling DC off
>[  465.787275] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  465.787365] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  465.788060] [drm:intel_power_well_disable [i915]] disabling always-on
>[  465.792167] [drm:drm_mode_addfb2] [FB:71]
>[  465.814046] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  465.814070] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  465.814196] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  465.814235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  465.814275] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  465.814312] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  465.814350] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  465.814387] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  465.814425] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  465.814461] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  465.814498] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  465.814502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  465.814539] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  465.814543] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  465.814580] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  465.814617] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  465.814654] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  465.815176] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  465.815215] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  465.815257] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  465.815294] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  465.815333] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  465.815370] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  465.815409] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  465.815446] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  465.815505] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  465.815558] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  465.815598] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  465.816359] [drm:intel_power_well_enable [i915]] enabling always-on
>[  465.816394] [drm:intel_power_well_enable [i915]] enabling DC off
>[  465.816940] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  465.817307] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  465.817345] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  465.817403] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  465.817671] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  465.822084] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  465.822126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  465.822172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  465.822217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  465.822257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  465.822297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  465.822337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  465.822377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  465.822417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  465.822457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  465.822496] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  465.822540] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  465.822582] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  465.822655] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  465.823107] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  465.823405] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  465.824638] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  465.825205] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  465.825245] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  465.825303] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  465.825341] [drm:hsw_audio_config_update [i915]] using automatic N
>[  465.825444] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  465.825484] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  465.842255] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  465.842326] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  465.842534] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  465.925830] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  465.926010] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  465.926085] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  465.926219] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  465.943958] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  465.944036] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  465.944182] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  465.944337] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  465.948562] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  465.948627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  465.948792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  465.948864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  465.948928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  465.948994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  465.949057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  465.949129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  465.949193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  465.949258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  465.949321] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  465.949396] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  465.949465] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  465.949535] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  465.949632] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  465.949783] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  465.949898] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  465.950019] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  465.950128] [drm:intel_power_well_disable [i915]] disabling DC off
>[  465.950212] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  465.950285] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  465.950955] [drm:intel_power_well_disable [i915]] disabling always-on
>[  465.954425] [drm:drm_mode_addfb2] [FB:71]
>[  465.975615] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  465.975692] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  465.975821] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  465.975862] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  465.975905] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  465.975945] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  465.975986] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  465.976027] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  465.976066] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  465.976105] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  465.976144] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  465.976151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  465.976187] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  465.976194] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  465.976232] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  465.976271] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  465.976312] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  465.976351] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  465.976391] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  465.976431] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  465.976470] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  465.976509] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  465.976549] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  465.976588] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  465.976628] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  465.976704] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  465.976761] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  465.976805] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  465.977243] [drm:intel_power_well_enable [i915]] enabling always-on
>[  465.977276] [drm:intel_power_well_enable [i915]] enabling DC off
>[  465.977561] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  465.977616] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  465.977652] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  465.977815] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  465.978065] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  465.982278] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  465.982318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  465.982362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  465.982404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  465.982443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  465.982481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  465.982519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  465.982557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  465.982594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  465.982632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  465.982835] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  465.982900] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  465.982982] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  465.983060] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  465.983104] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  465.984089] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  465.985391] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  465.986098] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  465.986140] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  465.986202] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  465.986243] [drm:hsw_audio_config_update [i915]] using automatic N
>[  465.986356] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  465.986398] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  466.003112] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  466.003170] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  466.003353] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  466.086645] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  466.086898] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  466.086973] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  466.087094] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  466.103015] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  466.103086] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  466.103224] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  466.103367] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  466.107576] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  466.107636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  466.107781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  466.107849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  466.107909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  466.107970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  466.108029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  466.108096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  466.108155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  466.108214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  466.108271] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  466.108341] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  466.108407] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  466.108472] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  466.108558] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  466.108619] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  466.108813] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  466.108932] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  466.109041] [drm:intel_power_well_disable [i915]] disabling DC off
>[  466.109125] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  466.109198] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  466.109866] [drm:intel_power_well_disable [i915]] disabling always-on
>[  477.765540] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  477.765721] drm/i915: Resetting chip after gpu hang
>[  477.766191] [drm:i915_gem_reset_finish [i915]] context kms_pipe_crc_ba[8414]/0 marked guilty (score 10) banned? no
>[  477.766233] [drm:i915_gem_reset_finish [i915]] resetting render ring to restart from tail of request 0x15003c
>[  477.766903] [drm] RC6 on
>[  477.767162] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  477.767218] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x15003c, 0x0]
>[  477.767672] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  477.767922] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  477.768099] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  477.768208] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[  477.768224] [drm] GuC firmware load skipped
>[  477.770334] [drm:drm_mode_addfb2] [FB:71]
>[  477.788197] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  477.788216] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  477.788330] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  477.788363] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  477.788402] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  477.788442] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  477.788475] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  477.788511] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  477.788546] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  477.788580] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  477.788614] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  477.788646] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  477.789139] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  477.789145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  477.789177] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  477.789183] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  477.789216] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  477.789250] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  477.789285] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  477.789320] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  477.789353] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  477.789391] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  477.789425] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  477.789460] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  477.789496] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  477.789531] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  477.789568] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  477.789603] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  477.789645] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  477.790172] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  477.791991] [drm:intel_power_well_enable [i915]] enabling always-on
>[  477.792020] [drm:intel_power_well_enable [i915]] enabling DC off
>[  477.792302] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  477.792352] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  477.792469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  477.792505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  477.792543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  477.792577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  477.792612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  477.792645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  477.792721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  477.792754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  477.792789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  477.792824] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  477.792862] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  477.792899] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  477.792968] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  477.793002] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  477.793787] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  477.793823] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  477.793868] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  477.793903] [drm:wait_panel_status [i915]] Wait complete
>[  477.793939] [drm:edp_panel_on [i915]] Wait for panel power on
>[  477.793978] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  477.902395] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  477.902453] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  477.902507] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  477.902600] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  477.995883] [drm:wait_panel_status [i915]] Wait complete
>[  477.995966] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  477.996033] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  477.997781] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  477.997855] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  477.997932] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  477.998951] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  477.999027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  478.000361] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  478.000797] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  478.002752] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  478.002890] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  478.002962] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  478.003041] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  478.003139] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  478.003209] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  478.003306] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  478.003379] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  478.019920] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  478.020018] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  478.020283] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  478.103389] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  478.103645] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  478.308853] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  478.308970] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  478.321859] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  478.321942] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  478.322031] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  478.372099] [drm:wait_panel_status [i915]] Wait complete
>[  478.372187] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  478.372276] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  478.372443] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  478.372629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  478.372821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  478.372900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  478.372975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  478.373047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  478.373122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  478.373200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  478.373278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  478.373353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  478.373427] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  478.373516] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  478.373597] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  478.373680] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  478.373902] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  478.374039] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  478.374160] [drm:intel_power_well_disable [i915]] disabling DC off
>[  478.374253] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  478.374335] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  478.374424] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  478.374517] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  478.374613] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  478.375101] [drm:intel_power_well_disable [i915]] disabling always-on
>[  478.376028] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  478.378878] [drm:drm_mode_addfb2] [FB:71]
>[  478.398354] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  478.398374] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  478.398488] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  478.398522] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  478.398560] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  478.398601] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  478.398633] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  478.399005] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  478.399039] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  478.399073] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  478.399108] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  478.399141] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  478.399175] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  478.399181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  478.399214] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  478.399219] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  478.399252] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  478.399286] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  478.399321] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  478.399354] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  478.399386] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  478.399423] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  478.399456] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  478.399491] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  478.399525] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  478.399559] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  478.399593] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  478.399629] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  478.400286] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  478.400320] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  478.400848] [drm:intel_power_well_enable [i915]] enabling always-on
>[  478.400878] [drm:intel_power_well_enable [i915]] enabling DC off
>[  478.401162] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  478.401213] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  478.401358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  478.401394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  478.401432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  478.401467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  478.401502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  478.401537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  478.401573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  478.401608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  478.401643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  478.402143] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  478.402185] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  478.402222] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  478.402290] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  478.402325] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  478.402523] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  478.402558] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  478.828854] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  478.901410] [drm:wait_panel_status [i915]] Wait complete
>[  478.901476] [drm:edp_panel_on [i915]] Wait for panel power on
>[  478.901544] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  479.009997] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  479.010062] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  479.010119] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  479.010223] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  479.101841] [drm:wait_panel_status [i915]] Wait complete
>[  479.101930] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  479.102002] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  479.103560] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  479.103616] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  479.103677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  479.104923] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  479.104981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  479.106265] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  479.106561] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  479.108449] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  479.108555] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  479.108606] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  479.108665] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  479.108796] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  479.108850] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  479.108921] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  479.108975] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  479.125474] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  479.125547] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  479.125909] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  479.209183] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  479.209459] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  479.412881] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  479.413027] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  479.426003] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  479.426107] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  479.426213] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  479.477764] [drm:wait_panel_status [i915]] Wait complete
>[  479.477873] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  479.477982] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  479.478172] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  479.478392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  479.478493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  479.478569] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  479.478662] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  479.478750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  479.478840] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  479.479035] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  479.479860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  479.479962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  479.480064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  479.480176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  479.480278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  479.480380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  479.480481] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  479.480601] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  479.480712] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  479.480908] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  479.481066] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  479.481703] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  479.481944] [drm:intel_power_well_disable [i915]] disabling DC off
>[  479.482049] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  479.482141] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  479.483357] [drm:intel_power_well_disable [i915]] disabling always-on
>[  479.486467] [drm:drm_mode_addfb2] [FB:71]
>[  479.503732] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  479.503753] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  479.503868] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  479.503902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  479.503939] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  479.503971] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  479.504007] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  479.504041] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  479.504076] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  479.504108] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  479.504140] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  479.504144] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  479.504175] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  479.504179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  479.504212] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  479.504244] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  479.504277] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  479.504311] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  479.504343] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  479.504381] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  479.504413] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  479.504449] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  479.504483] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  479.504517] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  479.504551] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  479.504599] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  479.504646] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  479.504726] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  479.505095] [drm:intel_power_well_enable [i915]] enabling always-on
>[  479.505125] [drm:intel_power_well_enable [i915]] enabling DC off
>[  479.505408] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  479.505458] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  479.505491] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  479.505544] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  479.505983] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  479.510009] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  479.510072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  479.510114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  479.510153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  479.510189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  479.510224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  479.510259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  479.510294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  479.510329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  479.510364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  479.510398] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  479.510435] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  479.510471] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  479.510536] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  479.510571] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  479.511134] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  479.512169] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  479.512742] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  479.512776] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  479.512828] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  479.512862] [drm:hsw_audio_config_update [i915]] using automatic N
>[  479.512956] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  479.512990] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  479.529837] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  479.529900] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  479.530091] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  479.613278] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  479.613429] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  479.613489] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  479.613608] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  479.630966] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  479.631027] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  479.631150] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  479.631266] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  479.635512] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  479.635563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  479.635616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  479.635669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  479.635796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  479.635843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  479.635889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  479.635939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  479.635986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  479.636033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  479.636081] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  479.636136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  479.636187] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  479.636238] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  479.636314] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  479.636363] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  479.636433] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  479.636502] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  479.636565] [drm:intel_power_well_disable [i915]] disabling DC off
>[  479.636615] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  479.636657] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  479.637512] [drm:intel_power_well_disable [i915]] disabling always-on
>[  479.639726] [drm:drm_mode_addfb2] [FB:71]
>[  479.659319] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  479.659340] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  479.659454] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  479.659488] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  479.659525] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  479.659557] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  479.659593] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  479.659627] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  479.659660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  479.659802] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  479.659835] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  479.659841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  479.659873] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  479.659877] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  479.659910] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  479.659944] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  479.659978] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  479.660012] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  479.660045] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  479.660081] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  479.660113] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  479.660147] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  479.660181] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  479.660215] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  479.660249] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  479.660302] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  479.660349] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  479.660384] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  479.660764] [drm:intel_power_well_enable [i915]] enabling always-on
>[  479.660792] [drm:intel_power_well_enable [i915]] enabling DC off
>[  479.661074] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  479.661122] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  479.661157] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  479.661208] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  479.662743] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  479.665736] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  479.665774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  479.665815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  479.665854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  479.665890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  479.665925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  479.665960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  479.665995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  479.666030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  479.666065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  479.666100] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  479.666136] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  479.666172] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  479.666239] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  479.666273] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  479.666529] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  479.667530] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  479.668107] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  479.668143] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  479.668194] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  479.668228] [drm:hsw_audio_config_update [i915]] using automatic N
>[  479.668323] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  479.668357] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  479.685155] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  479.685209] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  479.685386] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  479.768624] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  479.768906] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  479.768979] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  479.769107] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  479.785066] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  479.785135] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  479.785269] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  479.785411] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  479.789638] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  479.789747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  479.789808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  479.789870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  479.789925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  479.789980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  479.790034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  479.790094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  479.790149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  479.790204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  479.790258] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  479.790319] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  479.790377] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  479.790434] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  479.790516] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  479.790572] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  479.790650] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  479.790785] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  479.790857] [drm:intel_power_well_disable [i915]] disabling DC off
>[  479.790914] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  479.790964] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  479.791526] [drm:intel_power_well_disable [i915]] disabling always-on
>[  479.792847] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  479.826922] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  479.826973] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  479.827027] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  479.827083] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  479.827131] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  479.827184] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  479.827234] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  479.827287] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  479.827336] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  479.827384] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  479.827431] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  479.827441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  479.827490] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  479.827495] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  479.827544] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  479.827592] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  479.827641] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  479.827723] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  479.827771] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  479.827825] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  479.827873] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  479.827925] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  479.827975] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  479.828024] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  479.828074] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  479.828134] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  479.828183] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  479.828237] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  479.828284] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  479.828334] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  479.828384] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  479.828433] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  479.828483] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  479.828530] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  479.828536] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  479.828583] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  479.828588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  479.828637] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  479.828745] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  479.828796] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  479.828848] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  479.828899] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  479.828953] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  479.829003] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  479.829056] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  479.829109] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  479.829162] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  479.829215] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  479.829270] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  479.829336] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  479.829390] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  479.829450] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  479.829502] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  479.829730] [drm:intel_power_well_enable [i915]] enabling always-on
>[  479.829774] [drm:intel_power_well_enable [i915]] enabling DC off
>[  479.830076] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  479.830156] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  479.830305] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  479.830356] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  479.830439] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  479.830675] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  479.834792] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  479.834851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  479.834909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  479.834976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  479.835034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  479.835092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  479.835150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  479.835208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  479.835265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  479.835323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  479.835381] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  479.835443] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  479.835504] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  479.835605] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  479.835661] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  479.835995] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  479.836054] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  479.932853] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  480.001778] [drm:wait_panel_status [i915]] Wait complete
>[  480.001852] [drm:edp_panel_on [i915]] Wait for panel power on
>[  480.001930] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  480.110288] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  480.110356] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  480.110423] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  480.110577] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  480.203153] [drm:wait_panel_status [i915]] Wait complete
>[  480.203257] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  480.203345] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  480.205060] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  480.205129] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  480.205206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  480.206311] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  480.206382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  480.207795] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  480.208153] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  480.210607] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  480.210763] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  480.210834] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  480.210914] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  480.211015] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  480.211084] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  480.211182] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  480.211252] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  480.211551] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  480.211622] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  480.212084] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  480.214529] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  480.215179] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  480.215252] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  480.215362] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  480.215432] [drm:hsw_audio_config_update [i915]] using automatic N
>[  480.232222] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  480.232270] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  480.232457] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  480.232637] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  480.232807] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  480.233060] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  480.233726] Console: switching to colour frame buffer device 240x67
>[  480.473356] Console: switching to colour dummy device 80x25
>[  480.473578] [IGT] kms_pipe_crc_basic: executing
>[  480.499414] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  480.499481] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  480.499540] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  480.499595] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  480.499647] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  480.499774] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  480.500414] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  480.501049] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  480.501067] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  480.501073] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  480.501121] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  480.501183] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  480.501942] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  480.502369] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  480.502417] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  480.502476] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  480.511282] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.520136] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.529008] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.537867] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.546769] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.555628] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.564514] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.573400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.582295] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.591309] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.600306] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.609303] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.618354] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.627333] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.636324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.645304] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.654339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.663318] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.672302] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.681354] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.690328] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.699332] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.708365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.717342] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.726337] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.735318] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.744298] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.753358] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.762350] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.771347] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.780327] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.789326] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.789373] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  480.789389] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  480.789467] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  480.789577] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  480.870966] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  480.875159] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  480.875274] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  480.875286] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  480.876082] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  480.876093] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  480.876102] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  480.876108] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  480.876494] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  480.876506] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  480.876517] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  480.876526] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  480.876535] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  480.876545] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  480.876554] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  480.876564] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  480.876573] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  480.876582] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  480.876592] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  480.876601] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  480.876611] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  480.876620] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  480.876630] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  480.876753] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  480.876769] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  480.876780] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  480.876792] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  480.876804] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  480.876816] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  480.876828] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  480.876840] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  480.876855] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  480.890134] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  480.890181] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  480.890221] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  480.890255] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  480.890287] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  480.890322] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  480.890854] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  480.891315] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  480.891326] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  480.891330] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  480.891868] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  480.891915] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  480.892442] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  480.892865] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  480.893277] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  480.893319] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  480.901962] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.910669] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.919456] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.928254] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.937063] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.945936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.954787] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.963679] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.972616] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.981626] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.990566] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  480.999586] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.008601] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.017899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.026825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.035792] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.044709] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.053690] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.062670] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.071642] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.080635] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.089614] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.098911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.107881] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.116860] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.125844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.134866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.143871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.152852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.161841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.170831] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.179854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  481.179903] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  481.179917] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  481.181525] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  481.181643] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  481.263049] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  481.267232] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  481.267347] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  481.267359] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  481.268142] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  481.268153] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  481.268162] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  481.268168] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  481.268546] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  481.268559] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  481.268569] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  481.268578] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  481.268587] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  481.268597] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  481.268606] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  481.268616] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  481.268625] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  481.268634] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  481.268760] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  481.268772] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  481.268788] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  481.268800] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  481.268812] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  481.268824] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  481.268836] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  481.268849] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  481.268861] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  481.268883] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  481.268895] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  481.268906] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  481.268918] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  481.268930] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  481.270543] [IGT] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-B
>[  481.273204] [drm:drm_mode_addfb2] [FB:89]
>[  481.293038] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  481.293141] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  481.293309] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  481.500879] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  481.501019] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  481.511774] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  481.511835] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  481.511898] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  481.563999] [drm:wait_panel_status [i915]] Wait complete
>[  481.564082] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  481.564167] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  481.564239] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  481.564312] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  481.564383] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  481.564510] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  481.564588] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  481.564861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  481.564951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  481.565037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  481.565116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  481.565193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  481.565273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  481.565353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  481.565429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  481.565506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  481.565581] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  481.565669] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  481.565885] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  481.565988] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  481.582148] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  481.582281] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  481.582943] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  481.582989] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  481.583256] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  481.583346] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  481.583439] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  481.583538] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  481.583624] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  481.583714] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  481.583902] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  481.583992] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  481.584090] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  481.584182] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  481.584275] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  481.584295] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  481.584387] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  481.584403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  481.584499] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  481.584593] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  481.584691] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  481.584828] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  481.584924] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  481.585024] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  481.585113] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  481.585216] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  481.585308] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  481.585401] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  481.585492] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  481.585585] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  481.585718] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  481.586080] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  481.586175] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  481.586958] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  481.587221] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  481.587335] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  481.587526] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  481.599965] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  481.600090] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  481.600150] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  481.604374] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  481.604430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  481.604483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  481.604544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  481.604598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  481.604651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  481.604816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  481.604896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  481.604964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  481.605038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  481.605107] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  481.605188] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  481.605265] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  481.605339] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  481.605452] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  481.605522] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  481.605837] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  481.605911] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  482.021006] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  482.101684] [drm:wait_panel_status [i915]] Wait complete
>[  482.101871] [drm:edp_panel_on [i915]] Wait for panel power on
>[  482.101987] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  482.210332] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  482.210436] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  482.210535] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  482.210704] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  482.303859] [drm:wait_panel_status [i915]] Wait complete
>[  482.304001] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  482.304120] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  482.305888] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  482.305986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  482.306088] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  482.307223] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  482.307325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  482.308882] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  482.309290] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  482.311859] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  482.312006] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  482.312102] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  482.312208] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  482.312337] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  482.312432] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  482.328836] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  482.329102] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  482.329254] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  482.329585] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  482.345483] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  482.412602] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  482.413091] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  482.620867] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  482.621017] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  482.629942] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  482.630055] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  482.630172] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  482.682014] [drm:wait_panel_status [i915]] Wait complete
>[  482.682138] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  482.682342] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  482.682466] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  482.682566] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  482.682664] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  482.682836] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  482.683240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  482.683361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  482.683471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  482.683574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  482.683674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  482.683863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  482.683970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  482.684086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  482.684192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  482.684299] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  482.684422] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  482.684540] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  482.684653] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  482.684877] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  482.685009] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  482.685105] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  482.685240] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  482.685339] [drm:intel_power_well_disable [i915]] disabling DC off
>[  482.685432] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  482.685514] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  482.686195] [drm:intel_power_well_disable [i915]] disabling always-on
>[  482.689891] [drm:drm_mode_addfb2] [FB:89]
>[  482.711659] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  482.711682] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  482.711809] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  482.711848] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  482.711889] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  482.711933] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  482.711969] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  482.712008] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  482.712046] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  482.712083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  482.712121] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  482.712157] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  482.712194] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  482.712198] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  482.712235] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  482.712239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  482.712276] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  482.712313] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  482.712350] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  482.712387] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  482.712424] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  482.712463] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  482.712500] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  482.712537] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  482.712574] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  482.712611] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  482.712648] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  482.713650] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  482.713814] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  482.713855] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  482.714307] [drm:intel_power_well_enable [i915]] enabling always-on
>[  482.714339] [drm:intel_power_well_enable [i915]] enabling DC off
>[  482.714623] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  482.714931] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  482.714969] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  482.715028] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  482.715208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  482.715247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  482.715288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  482.715326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  482.715364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  482.715402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  482.715442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  482.715480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  482.715518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  482.715555] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  482.715597] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  482.715638] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  482.716265] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  482.716304] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  482.716513] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  482.716553] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  483.132824] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  483.203319] [drm:wait_panel_status [i915]] Wait complete
>[  483.203366] [drm:edp_panel_on [i915]] Wait for panel power on
>[  483.203414] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  483.311875] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  483.311920] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  483.311959] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  483.312040] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  483.404648] [drm:wait_panel_status [i915]] Wait complete
>[  483.404790] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  483.404860] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  483.406330] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  483.406387] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  483.406446] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  483.407441] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  483.407505] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  483.408777] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  483.409084] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  483.411033] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  483.411138] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  483.411197] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  483.411263] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  483.411346] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  483.411405] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  483.428124] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  483.428218] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  483.428482] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  483.511624] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  483.512046] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  483.716873] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  483.717008] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  483.729972] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  483.730072] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  483.730177] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  483.781968] [drm:wait_panel_status [i915]] Wait complete
>[  483.782091] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  483.782295] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  483.782450] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  483.782550] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  483.782647] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  483.782815] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  483.783020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  483.783140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  483.783250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  483.783357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  483.783457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  483.783562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  483.783670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  483.783843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  483.783944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  483.784053] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  483.784176] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  483.784288] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  483.784401] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  483.784547] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  483.784692] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  483.784890] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  483.785046] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  483.785160] [drm:intel_power_well_disable [i915]] disabling DC off
>[  483.785264] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  483.785356] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  483.786056] [drm:intel_power_well_disable [i915]] disabling always-on
>[  483.790254] [drm:drm_mode_addfb2] [FB:89]
>[  483.811639] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  483.811682] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  483.811812] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  483.811851] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  483.811892] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  483.811928] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  483.811967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  483.812004] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  483.812041] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  483.812078] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  483.812114] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  483.812118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  483.812155] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  483.812159] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  483.812197] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  483.812233] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  483.812270] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  483.812308] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  483.812344] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  483.812384] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  483.812420] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  483.812457] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  483.812495] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  483.812531] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  483.812568] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  483.812623] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  483.812750] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  483.812795] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  483.813257] [drm:intel_power_well_enable [i915]] enabling always-on
>[  483.813291] [drm:intel_power_well_enable [i915]] enabling DC off
>[  483.813575] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  483.813630] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  483.813729] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  483.813790] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  483.814990] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  483.819189] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  483.819229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  483.819272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  483.819315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  483.819353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  483.819391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  483.819429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  483.819467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  483.819505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  483.819543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  483.819581] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  483.819622] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  483.819663] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  483.819884] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  483.819957] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  483.820241] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  483.821405] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  483.821988] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  483.822030] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  483.822093] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  483.822132] [drm:hsw_audio_config_update [i915]] using automatic N
>[  483.839033] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  483.839103] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  483.839304] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  483.922559] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  483.923030] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  483.923126] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  483.923293] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  483.938987] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  483.939160] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  483.939356] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  483.943626] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  483.943839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  483.943940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  483.944043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  483.944135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  483.944229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  483.944320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  483.944424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  483.944515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  483.944609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  483.944700] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  483.944868] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  483.944975] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  483.945079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  483.945219] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  483.945314] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  483.945441] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  483.945573] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  483.945672] [drm:intel_power_well_disable [i915]] disabling DC off
>[  483.945841] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  483.945930] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  483.946534] [drm:intel_power_well_disable [i915]] disabling always-on
>[  483.950364] [drm:drm_mode_addfb2] [FB:89]
>[  483.973311] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  483.973333] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  483.973462] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  483.973501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  483.973541] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  483.973578] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  483.973616] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  483.973654] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  483.974160] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  483.974199] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  483.974236] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  483.974243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  483.974281] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  483.974285] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  483.974323] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  483.974361] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  483.974399] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  483.974438] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  483.974474] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  483.974516] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  483.974552] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  483.974591] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  483.974629] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  483.975375] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  483.975414] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  483.975477] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  483.975529] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  483.975569] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  483.976329] [drm:intel_power_well_enable [i915]] enabling always-on
>[  483.976362] [drm:intel_power_well_enable [i915]] enabling DC off
>[  483.976647] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  483.976763] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  483.976801] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  483.976860] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  483.977409] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  483.981610] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  483.981651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  483.981758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  483.981802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  483.981841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  483.981880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  483.981919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  483.981958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  483.981997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  483.982036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  483.982075] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  483.982118] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  483.982160] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  483.982233] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  483.982272] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  483.983132] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  483.984280] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  483.984887] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  483.984925] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  483.984983] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  483.985020] [drm:hsw_audio_config_update [i915]] using automatic N
>[  484.002067] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  484.002146] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  484.002364] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  484.085451] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  484.085633] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  484.085839] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  484.085965] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  484.102041] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  484.102183] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  484.102328] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  484.106542] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  484.106602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  484.106664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  484.106821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  484.106880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  484.106939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  484.107001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  484.107067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  484.107126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  484.107186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  484.107245] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  484.107315] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  484.107381] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  484.107444] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  484.107538] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  484.107599] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  484.107779] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  484.107909] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  484.108004] [drm:intel_power_well_disable [i915]] disabling DC off
>[  484.108090] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  484.108164] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  484.108829] [drm:intel_power_well_disable [i915]] disabling always-on
>[  493.765451] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  493.765561] drm/i915: Resetting chip after gpu hang
>[  493.768171] [drm:i915_gem_reset_finish [i915]] context kms_pipe_crc_ba[8418]/0 marked guilty (score 10) banned? no
>[  493.768206] [drm:i915_gem_reset_finish [i915]] resetting render ring to restart from tail of request 0x15008d
>[  493.768733] [drm] RC6 on
>[  493.768916] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  493.768953] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x15008d, 0x0]
>[  493.769394] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  493.769523] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  493.769652] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  493.769801] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[  493.769817] [drm] GuC firmware load skipped
>[  493.770825] [drm:drm_mode_addfb2] [FB:89]
>[  493.786969] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  493.786991] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  493.787110] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  493.787144] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  493.787182] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  493.787223] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  493.787255] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  493.787290] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  493.787326] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  493.787361] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  493.787394] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  493.787426] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  493.787458] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  493.787464] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  493.787496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  493.787499] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  493.787532] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  493.787565] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  493.787598] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  493.787630] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  493.787799] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  493.787835] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  493.787869] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  493.787905] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  493.787940] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  493.787975] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  493.788011] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  493.788049] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  493.788092] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  493.788128] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  493.788616] [drm:intel_power_well_enable [i915]] enabling always-on
>[  493.788647] [drm:intel_power_well_enable [i915]] enabling DC off
>[  493.788979] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  493.789029] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  493.789063] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  493.789118] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  493.789274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  493.789310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  493.789349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  493.789384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  493.789420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  493.789455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  493.789493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  493.789528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  493.789563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  493.789598] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  493.789638] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  493.789707] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  493.789773] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  493.789806] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  493.790148] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  493.790185] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  493.790228] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  493.790263] [drm:wait_panel_status [i915]] Wait complete
>[  493.790301] [drm:edp_panel_on [i915]] Wait for panel power on
>[  493.790340] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  493.898787] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  493.898845] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  493.898900] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  493.898992] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  493.992322] [drm:wait_panel_status [i915]] Wait complete
>[  493.992408] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  493.992479] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  493.994262] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  493.994321] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  493.994381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  493.995420] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  493.995481] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  493.996797] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  493.997097] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  493.998640] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  493.998759] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  493.998811] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  493.998870] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  493.998944] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  493.998997] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  494.015759] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  494.015832] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  494.016054] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  494.099260] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  494.099512] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  494.300849] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  494.300981] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  494.315976] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  494.316069] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  494.316167] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  494.366238] [drm:wait_panel_status [i915]] Wait complete
>[  494.366353] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  494.366542] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  494.366903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  494.367010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  494.367107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  494.367201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  494.367293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  494.367387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  494.367483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  494.367576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  494.367667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  494.367856] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  494.367980] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  494.368090] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  494.368204] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  494.368351] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  494.368443] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  494.368546] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  494.368648] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  494.368841] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  494.368946] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  494.369097] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  494.369209] [drm:intel_power_well_disable [i915]] disabling DC off
>[  494.369313] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  494.369406] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  494.370089] [drm:intel_power_well_disable [i915]] disabling always-on
>[  494.370189] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  494.374166] [drm:drm_mode_addfb2] [FB:89]
>[  494.391902] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  494.391923] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  494.392041] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  494.392075] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  494.392113] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  494.392154] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  494.392186] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  494.392221] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  494.392257] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  494.392292] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  494.392326] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  494.392360] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  494.392391] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  494.392396] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  494.392427] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  494.392431] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  494.392464] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  494.392496] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  494.392529] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  494.392562] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  494.392594] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  494.392632] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  494.393405] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  494.393440] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  494.393474] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  494.393508] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  494.393542] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  494.393580] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  494.393625] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  494.393660] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  494.394326] [drm:intel_power_well_enable [i915]] enabling always-on
>[  494.394355] [drm:intel_power_well_enable [i915]] enabling DC off
>[  494.394637] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  494.395267] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  494.395302] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  494.395354] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  494.395522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  494.395558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  494.395596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  494.395631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  494.395927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  494.395961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  494.395997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  494.396032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  494.396067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  494.396103] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  494.396142] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  494.396180] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  494.396249] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  494.396284] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  494.396483] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  494.396518] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  494.820897] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  494.902219] [drm:wait_panel_status [i915]] Wait complete
>[  494.902301] [drm:edp_panel_on [i915]] Wait for panel power on
>[  494.902388] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  495.010801] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  495.010880] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  495.010952] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  495.011079] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  495.104395] [drm:wait_panel_status [i915]] Wait complete
>[  495.104504] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  495.104593] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  495.106467] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  495.106559] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  495.106652] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  495.108263] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  495.108355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  495.110173] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  495.110559] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  495.113311] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  495.113450] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  495.113536] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  495.113632] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  495.113849] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  495.114267] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  495.130448] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  495.130546] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  495.131185] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  495.214098] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  495.214398] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  495.420886] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  495.421043] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  495.431922] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  495.432035] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  495.432154] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  495.483882] [drm:wait_panel_status [i915]] Wait complete
>[  495.484009] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  495.484214] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  495.484452] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  495.484552] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  495.484652] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  495.484825] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  495.484931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  495.485054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  495.485167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  495.485279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  495.485384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  495.485495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  495.485606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  495.485712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  495.485890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  495.485998] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  495.486123] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  495.486237] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  495.486347] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  495.486495] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  495.486641] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  495.486828] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  495.486983] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  495.487095] [drm:intel_power_well_disable [i915]] disabling DC off
>[  495.487199] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  495.487291] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  495.487976] [drm:intel_power_well_disable [i915]] disabling always-on
>[  495.492214] [drm:drm_mode_addfb2] [FB:89]
>[  495.511969] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  495.511992] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  495.512119] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  495.512155] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  495.512196] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  495.512230] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  495.512269] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  495.512306] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  495.512344] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  495.512379] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  495.512414] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  495.512422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  495.512456] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  495.512460] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  495.512496] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  495.512531] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  495.512568] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  495.512604] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  495.512639] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  495.513142] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  495.513179] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  495.513217] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  495.513254] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  495.513291] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  495.513329] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  495.513389] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  495.513439] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  495.513479] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  495.514195] [drm:intel_power_well_enable [i915]] enabling always-on
>[  495.514228] [drm:intel_power_well_enable [i915]] enabling DC off
>[  495.514512] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  495.514564] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  495.514602] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  495.514659] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  495.515251] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  495.519488] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  495.519561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  495.519600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  495.519639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  495.519967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  495.520003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  495.520038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  495.520073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  495.520107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  495.520143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  495.520177] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  495.520216] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  495.520252] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  495.520321] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  495.520354] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  495.520620] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  495.521904] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  495.522439] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  495.522474] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  495.522525] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  495.522557] [drm:hsw_audio_config_update [i915]] using automatic N
>[  495.539534] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  495.539605] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  495.539912] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  495.623043] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  495.623215] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  495.623286] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  495.623408] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  495.641142] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  495.641293] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  495.641450] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  495.645687] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  495.645817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  495.645886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  495.645957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  495.646020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  495.646083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  495.646146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  495.646215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  495.646278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  495.646341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  495.646403] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  495.646475] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  495.646542] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  495.646608] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  495.646776] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  495.646843] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  495.646934] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  495.647028] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  495.647096] [drm:intel_power_well_disable [i915]] disabling DC off
>[  495.647159] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  495.647213] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  495.647888] [drm:intel_power_well_disable [i915]] disabling always-on
>[  495.651296] [drm:drm_mode_addfb2] [FB:89]
>[  495.674218] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  495.674239] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  495.674356] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  495.674389] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  495.674427] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  495.674459] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  495.674495] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  495.674529] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  495.674564] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  495.674596] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  495.674628] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  495.674632] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  495.675067] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  495.675074] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  495.675109] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  495.675143] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  495.675179] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  495.675212] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  495.675247] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  495.675284] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  495.675319] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  495.675354] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  495.675390] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  495.675424] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  495.675460] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  495.675513] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  495.675562] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  495.675598] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  495.676287] [drm:intel_power_well_enable [i915]] enabling always-on
>[  495.676320] [drm:intel_power_well_enable [i915]] enabling DC off
>[  495.676601] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  495.676648] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  495.676937] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  495.676991] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  495.677267] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  495.681387] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  495.681424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  495.681463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  495.681501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  495.681537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  495.681571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  495.681606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  495.681640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  495.681992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  495.682026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  495.682063] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  495.682102] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  495.682140] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  495.682207] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  495.682242] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  495.682498] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  495.683919] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  495.684478] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  495.684517] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  495.684575] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  495.684614] [drm:hsw_audio_config_update [i915]] using automatic N
>[  495.701548] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  495.701624] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  495.702230] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  495.785045] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  495.785215] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  495.785286] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  495.785413] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  495.803223] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  495.803380] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  495.803547] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  495.807764] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  495.807837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  495.807915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  495.807991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  495.808059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  495.808127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  495.808194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  495.808269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  495.808337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  495.808405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  495.808472] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  495.808548] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  495.808621] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  495.808692] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  495.808903] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  495.808976] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  495.809075] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  495.809181] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  495.809256] [drm:intel_power_well_disable [i915]] disabling DC off
>[  495.809326] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  495.809389] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  495.810058] [drm:intel_power_well_disable [i915]] disabling always-on
>[  495.812512] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  495.837564] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  495.837599] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  495.837637] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  495.837713] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  495.837745] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  495.837783] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  495.837819] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  495.837854] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  495.837887] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  495.837919] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  495.837950] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  495.837958] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  495.837990] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  495.837993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  495.838026] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  495.838058] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  495.838091] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  495.838123] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  495.838155] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  495.838193] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  495.838225] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  495.838261] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  495.838295] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  495.838328] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  495.838362] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  495.838403] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  495.838436] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  495.838475] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  495.838506] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  495.838540] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  495.838574] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  495.838606] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  495.838638] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  495.838786] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  495.838790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  495.838821] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  495.838825] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  495.838857] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  495.838889] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  495.838923] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  495.838955] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  495.838987] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  495.839021] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  495.839053] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  495.839087] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  495.839121] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  495.839154] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  495.839188] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  495.839225] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  495.839268] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  495.839302] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  495.839340] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  495.839373] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  495.839527] [drm:intel_power_well_enable [i915]] enabling always-on
>[  495.839554] [drm:intel_power_well_enable [i915]] enabling DC off
>[  495.839901] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  495.839955] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  495.840072] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  495.840106] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  495.840162] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  495.840385] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  495.843764] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  495.843819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  495.843874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  495.843936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  495.843991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  495.844046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  495.844100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  495.844154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  495.844208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  495.844262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  495.844316] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  495.844375] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  495.844434] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  495.844529] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  495.844581] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  495.845012] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  495.845067] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  495.940842] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  496.002152] [drm:wait_panel_status [i915]] Wait complete
>[  496.002217] [drm:edp_panel_on [i915]] Wait for panel power on
>[  496.002285] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  496.110687] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  496.110746] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  496.110802] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  496.110904] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  496.204335] [drm:wait_panel_status [i915]] Wait complete
>[  496.204445] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  496.204537] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  496.206121] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  496.206190] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  496.206267] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  496.207354] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  496.207425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  496.208983] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  496.209339] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  496.211602] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  496.211756] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  496.211820] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  496.211895] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  496.211988] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  496.212053] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  496.212143] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  496.212207] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  496.212493] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  496.212558] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  496.212999] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  496.215240] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  496.215914] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  496.215980] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  496.216082] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  496.216146] [drm:hsw_audio_config_update [i915]] using automatic N
>[  496.232989] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  496.233079] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  496.233361] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  496.233665] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  496.233823] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  496.234087] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  496.234748] Console: switching to colour frame buffer device 240x67
>[  496.466688] Console: switching to colour dummy device 80x25
>[  496.466917] [IGT] kms_pipe_crc_basic: executing
>[  496.490345] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  496.490409] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  496.490465] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  496.490517] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  496.490565] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  496.490616] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  496.491821] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  496.492369] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  496.492386] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  496.492393] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  496.492444] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  496.492498] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  496.493172] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  496.493589] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  496.493631] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  496.493768] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  496.502479] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.511205] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.519928] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.528640] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.537391] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.546099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.554822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.563531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.572341] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.581175] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.590000] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.598917] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.607822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.616793] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.625711] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.634676] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.643617] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.652731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.661884] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.670870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.679865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.688851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.697835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.706870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.715846] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.724841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.733826] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.742879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.751869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.760872] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.769868] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.778854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.778900] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  496.778916] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  496.778991] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  496.779095] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  496.859842] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  496.864034] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  496.864154] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  496.864167] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  496.864946] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  496.864956] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  496.864966] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  496.864972] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  496.865352] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  496.865365] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  496.865375] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  496.865384] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  496.865393] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  496.865403] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  496.865413] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  496.865422] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  496.865438] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  496.865451] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  496.865464] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  496.865475] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  496.865487] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  496.865499] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  496.865511] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  496.865523] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  496.865535] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  496.865547] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  496.865559] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  496.865571] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  496.865583] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  496.865595] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  496.865607] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  496.865619] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  496.878602] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  496.878650] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  496.878729] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  496.878770] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  496.878808] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  496.878845] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  496.879394] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  496.879863] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  496.879876] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  496.879880] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  496.880377] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  496.880424] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  496.881043] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  496.881429] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  496.881921] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  496.881964] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  496.890576] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.899181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.907819] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.916431] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.925018] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.933642] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.942275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.950870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.959473] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.968075] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.976705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.985317] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  496.994014] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.002721] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.011485] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.020305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.029128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.038000] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.046824] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.055659] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.064603] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.073786] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.082692] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.091666] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.100645] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.109453] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.118109] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.126829] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.135565] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.144300] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.153008] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.161743] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.161773] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  497.161783] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  497.162450] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  497.162513] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  497.242637] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  497.246864] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  497.246953] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  497.246961] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  497.247325] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  497.247330] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  497.247336] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  497.247339] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  497.247548] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  497.247555] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  497.247561] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  497.247566] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  497.247571] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  497.247576] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  497.247581] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  497.247586] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  497.247591] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  497.247596] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  497.247601] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  497.247606] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  497.247611] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  497.247616] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  497.247621] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  497.247626] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  497.247631] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  497.247946] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  497.247951] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  497.247956] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  497.247963] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  497.247968] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  497.247973] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  497.247978] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  497.249166] [IGT] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-C
>[  497.251600] [drm:drm_mode_addfb2] [FB:70]
>[  497.270721] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  497.270824] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  497.270990] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  497.476816] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  497.476899] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  497.479320] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  497.479381] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  497.479444] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  497.531213] [drm:wait_panel_status [i915]] Wait complete
>[  497.531277] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  497.531341] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  497.531471] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  497.531601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  497.531661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  497.531811] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  497.531867] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  497.531921] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  497.532324] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  497.532389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  497.532443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  497.532498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  497.532551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  497.532606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  497.532659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  497.533075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  497.533128] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  497.533195] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  497.533252] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  497.533310] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  497.549519] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  497.549605] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  497.550340] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  497.550497] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  497.551123] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  497.551194] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  497.551318] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  497.567924] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  497.568058] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  497.568186] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  497.572389] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  497.572445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  497.572503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  497.572562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  497.572615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  497.572668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  497.572800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  497.572863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  497.572918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  497.572975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  497.573030] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  497.573094] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  497.573154] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  497.573214] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  497.573297] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  497.573354] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  497.573432] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  497.573511] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  497.573570] [drm:intel_power_well_disable [i915]] disabling DC off
>[  497.573627] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  497.573692] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  497.574257] [drm:intel_power_well_disable [i915]] disabling always-on
>[  497.574612] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  497.574714] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  497.574879] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  497.574934] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  497.574995] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  497.575059] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  497.575113] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  497.575170] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  497.575225] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  497.575281] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  497.575336] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  497.575391] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  497.575445] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  497.575453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  497.575505] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  497.575511] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  497.575568] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  497.575621] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  497.575678] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  497.575817] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  497.575893] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  497.575971] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  497.576046] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  497.576117] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  497.576192] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  497.576266] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  497.576346] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  497.576431] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  497.576509] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  497.577160] [drm:intel_power_well_enable [i915]] enabling always-on
>[  497.577225] [drm:intel_power_well_enable [i915]] enabling DC off
>[  497.577547] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  497.577643] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  497.577794] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  497.577900] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  497.578122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  497.578197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  497.578276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  497.578351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  497.578425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  497.578499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  497.578577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  497.578650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  497.578796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  497.578870] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  497.578956] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  497.579036] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  497.579156] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  497.579232] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  497.580183] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  497.580229] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  497.988901] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  498.103387] [drm:wait_panel_status [i915]] Wait complete
>[  498.103486] [drm:edp_panel_on [i915]] Wait for panel power on
>[  498.103589] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  498.211922] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  498.212016] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  498.212103] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  498.212257] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  498.305388] [drm:wait_panel_status [i915]] Wait complete
>[  498.305515] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  498.305621] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  498.307477] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  498.307566] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  498.307657] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  498.309240] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  498.309328] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  498.310723] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  498.311186] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  498.313241] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  498.313322] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  498.313365] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  498.313413] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  498.313472] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  498.313515] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  498.330310] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  498.330398] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  498.330644] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  498.414003] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  498.414273] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  498.620868] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  498.621003] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  498.631869] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  498.631982] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  498.632100] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  498.683827] [drm:wait_panel_status [i915]] Wait complete
>[  498.683953] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  498.684158] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  498.684351] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  498.684452] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  498.684549] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  498.684708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  498.684808] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  498.685959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  498.686066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  498.686166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  498.686264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  498.686363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  498.686467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  498.686566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  498.686665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  498.686874] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  498.687002] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  498.687119] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  498.687232] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  498.687388] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  498.687532] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  498.687636] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  498.687860] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  498.687977] [drm:intel_power_well_disable [i915]] disabling DC off
>[  498.688081] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  498.688172] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  498.688857] [drm:intel_power_well_disable [i915]] disabling always-on
>[  498.692795] [drm:drm_mode_addfb2] [FB:70]
>[  498.716409] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  498.716431] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  498.716556] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  498.716594] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  498.716636] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  498.716789] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  498.716830] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  498.716908] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  498.716949] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  498.716989] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  498.717030] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  498.717070] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  498.717110] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  498.717117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  498.717154] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  498.717160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  498.717198] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  498.717235] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  498.717274] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  498.717313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  498.717350] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  498.717392] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  498.717429] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  498.717470] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  498.717509] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  498.717548] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  498.717592] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  498.717642] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  498.717726] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  498.718190] [drm:intel_power_well_enable [i915]] enabling always-on
>[  498.718224] [drm:intel_power_well_enable [i915]] enabling DC off
>[  498.718511] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  498.718566] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  498.718603] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  498.718773] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  498.718910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  498.718951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  498.718995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  498.719035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  498.719076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  498.719115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  498.719158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  498.719198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  498.719238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  498.719277] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  498.719322] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  498.719365] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  498.719440] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  498.719479] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  498.719768] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  498.719816] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  499.140978] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  499.203156] [drm:wait_panel_status [i915]] Wait complete
>[  499.203219] [drm:edp_panel_on [i915]] Wait for panel power on
>[  499.203286] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  499.311693] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  499.311756] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  499.311812] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  499.311949] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  499.404575] [drm:wait_panel_status [i915]] Wait complete
>[  499.404681] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  499.404930] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  499.406615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  499.406704] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  499.406956] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  499.408447] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  499.408538] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  499.410154] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  499.410537] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  499.413102] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  499.413246] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  499.413332] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  499.413427] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  499.413543] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  499.413628] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  499.430248] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  499.430351] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  499.430633] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  499.513912] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  499.514212] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  499.716878] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  499.717031] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  499.732008] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  499.732122] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  499.732240] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  499.784068] [drm:wait_panel_status [i915]] Wait complete
>[  499.784196] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  499.784401] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  499.784552] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  499.784653] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  499.784750] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  499.784920] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  499.786019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  499.786139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  499.786245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  499.786344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  499.786442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  499.786541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  499.786645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  499.786865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  499.786967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  499.787074] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  499.787195] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  499.787304] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  499.787419] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  499.787569] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  499.787711] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  499.787906] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  499.788051] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  499.788160] [drm:intel_power_well_disable [i915]] disabling DC off
>[  499.788265] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  499.788357] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  499.789053] [drm:intel_power_well_disable [i915]] disabling always-on
>[  499.792547] [drm:drm_mode_addfb2] [FB:70]
>[  499.814712] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  499.814734] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  499.814857] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  499.814895] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  499.814936] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  499.814972] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  499.815011] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  499.815048] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  499.815086] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  499.815122] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  499.815159] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  499.815163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  499.815200] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  499.815204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  499.815241] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  499.815278] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  499.815315] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  499.815352] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  499.815389] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  499.815429] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  499.815465] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  499.815502] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  499.815539] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  499.815576] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  499.815630] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  499.816327] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  499.816369] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  499.817084] [drm:intel_power_well_enable [i915]] enabling always-on
>[  499.817120] [drm:intel_power_well_enable [i915]] enabling DC off
>[  499.817409] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  499.817467] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  499.817506] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  499.817568] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  499.818186] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  499.821768] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  499.821809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  499.821853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  499.821896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  499.821934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  499.821972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  499.822010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  499.822048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  499.822086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  499.822124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  499.822161] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  499.822203] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  499.822244] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  499.822315] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  499.822352] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  499.822616] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  499.824132] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  499.824889] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  499.824927] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  499.824983] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  499.825020] [drm:hsw_audio_config_update [i915]] using automatic N
>[  499.841916] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  499.841972] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  499.842148] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  499.925468] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  499.925663] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  499.925923] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  499.926532] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  499.941853] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  499.942001] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  499.942137] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  499.946356] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  499.946420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  499.946488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  499.946557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  499.946619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  499.946679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  499.946839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  499.946911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  499.946974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  499.947035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  499.947097] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  499.947169] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  499.947240] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  499.947307] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  499.947408] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  499.947475] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  499.947567] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  499.947659] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  499.947795] [drm:intel_power_well_disable [i915]] disabling DC off
>[  499.947861] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  499.947917] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  499.948487] [drm:intel_power_well_disable [i915]] disabling always-on
>[  499.950584] [drm:drm_mode_addfb2] [FB:70]
>[  499.972250] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  499.972272] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  499.972397] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  499.972436] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  499.972476] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  499.972512] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  499.972551] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  499.972589] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  499.972626] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  499.972663] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  499.973165] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  499.973171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  499.973207] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  499.973211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  499.973249] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  499.973286] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  499.973323] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  499.973360] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  499.973397] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  499.973437] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  499.973473] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  499.973510] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  499.973547] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  499.973585] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  499.973643] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  499.974234] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  499.974274] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  499.974842] [drm:intel_power_well_enable [i915]] enabling always-on
>[  499.974874] [drm:intel_power_well_enable [i915]] enabling DC off
>[  499.975159] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  499.975212] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  499.975248] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  499.975306] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  499.975577] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  499.979754] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  499.979804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  499.979879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  499.979924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  499.979964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  499.980004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  499.980044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  499.980084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  499.980123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  499.980163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  499.980202] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  499.980246] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  499.980288] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  499.980361] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  499.980400] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  499.981424] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  499.982719] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  499.983240] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  499.983280] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  499.983339] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  499.983377] [drm:hsw_audio_config_update [i915]] using automatic N
>[  500.000227] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  500.000284] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  500.000463] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  500.083855] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  500.084036] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  500.084110] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  500.084240] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  500.102075] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  500.102222] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  500.102357] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  500.106610] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  500.106692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  500.106882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  500.106974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  500.107057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  500.107137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  500.107218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  500.107307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  500.107389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  500.107471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  500.107555] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  500.107650] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  500.107795] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  500.107884] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  500.108038] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  500.108122] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  500.108237] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  500.108359] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  500.108445] [drm:intel_power_well_disable [i915]] disabling DC off
>[  500.108529] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  500.108602] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  500.109251] [drm:intel_power_well_disable [i915]] disabling always-on
>[  511.749473] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  511.749576] drm/i915: Resetting chip after gpu hang
>[  511.752123] [drm:i915_gem_reset_finish [i915]] context kms_pipe_crc_ba[8422]/0 marked guilty (score 10) banned? no
>[  511.752159] [drm:i915_gem_reset_finish [i915]] resetting render ring to restart from tail of request 0x1500de
>[  511.752620] [drm] RC6 on
>[  511.753281] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  511.753319] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x1500de, 0x0]
>[  511.754078] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  511.754213] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  511.754344] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  511.754423] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[  511.754435] [drm] GuC firmware load skipped
>[  511.756360] [drm:drm_mode_addfb2] [FB:70]
>[  511.772720] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  511.772742] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  511.772856] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  511.772890] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  511.772927] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  511.772967] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  511.772999] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  511.773035] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  511.773070] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  511.773105] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  511.773139] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  511.773171] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  511.773203] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  511.773208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  511.773240] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  511.773246] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  511.773279] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  511.773311] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  511.773344] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  511.773376] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  511.773409] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  511.773447] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  511.773479] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  511.773514] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  511.773548] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  511.773583] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  511.773619] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  511.773660] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  511.773753] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  511.774178] [drm:intel_power_well_enable [i915]] enabling always-on
>[  511.774206] [drm:intel_power_well_enable [i915]] enabling DC off
>[  511.774490] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  511.774539] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  511.774574] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  511.774627] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  511.774825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  511.774860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  511.774897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  511.774930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  511.774965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  511.774998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  511.775035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  511.775070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  511.775105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  511.775140] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  511.775178] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  511.775213] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  511.775282] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  511.775315] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  511.777315] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  511.777354] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  511.777398] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  511.777433] [drm:wait_panel_status [i915]] Wait complete
>[  511.777469] [drm:edp_panel_on [i915]] Wait for panel power on
>[  511.777508] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  511.886038] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  511.886099] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  511.886157] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  511.886251] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  511.979441] [drm:wait_panel_status [i915]] Wait complete
>[  511.979557] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  511.979655] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  511.982147] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  511.982228] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  511.982313] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  511.983789] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  511.983864] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  511.985372] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  511.985983] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  511.988102] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  511.988233] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  511.988303] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  511.988383] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  511.988483] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  511.988555] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  512.005164] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  512.005272] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  512.005555] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  512.088923] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  512.089224] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  512.292875] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  512.293021] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  512.305986] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  512.306100] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  512.306219] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  512.357910] [drm:wait_panel_status [i915]] Wait complete
>[  512.358044] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  512.358249] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  512.358465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  512.358548] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  512.358652] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  512.358751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  512.358851] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  512.359112] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  512.360034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  512.360140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  512.360243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  512.360345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  512.360453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  512.360555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  512.360657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  512.361923] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  512.362049] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  512.362158] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  512.362265] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  512.362415] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  512.362556] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  512.362657] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  512.363709] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  512.364207] [drm:intel_power_well_disable [i915]] disabling DC off
>[  512.364311] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  512.364402] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  512.365630] [drm:intel_power_well_disable [i915]] disabling always-on
>[  512.367890] [drm:drm_mode_addfb2] [FB:70]
>[  512.385265] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  512.385285] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  512.385398] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  512.385433] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  512.385471] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  512.385511] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  512.385543] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  512.385578] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  512.385613] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  512.385646] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  512.386300] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  512.386332] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  512.386364] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  512.386370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  512.386402] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  512.386405] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  512.386439] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  512.386472] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  512.386505] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  512.386539] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  512.386571] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  512.386611] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  512.386643] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  512.387339] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  512.387374] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  512.387408] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  512.387446] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  512.387489] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  512.387523] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  512.388249] [drm:intel_power_well_enable [i915]] enabling always-on
>[  512.388278] [drm:intel_power_well_enable [i915]] enabling DC off
>[  512.388561] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  512.388609] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  512.388643] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  512.389013] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  512.389131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  512.389167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  512.389205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  512.389240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  512.389275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  512.389310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  512.389347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  512.389382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  512.389417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  512.389452] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  512.389489] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  512.389524] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  512.389592] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  512.389626] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  512.390503] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  512.390540] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  512.812854] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  512.902465] [drm:wait_panel_status [i915]] Wait complete
>[  512.902555] [drm:edp_panel_on [i915]] Wait for panel power on
>[  512.902649] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  513.011020] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  513.011116] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  513.011204] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  513.011376] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  513.102870] [drm:wait_panel_status [i915]] Wait complete
>[  513.103014] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  513.103135] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  513.105166] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  513.105269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  513.105373] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  513.107229] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  513.107331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  513.109090] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  513.109413] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  513.111538] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  513.111641] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  513.112091] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  513.112165] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  513.112258] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  513.112322] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  513.128677] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  513.128882] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  513.129190] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  513.212294] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  513.212634] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  513.420879] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  513.421040] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  513.429944] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  513.430057] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  513.430176] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  513.481439] [drm:wait_panel_status [i915]] Wait complete
>[  513.481570] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  513.482408] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  513.482504] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  513.482612] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  513.482714] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  513.482903] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  513.483235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  513.483355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  513.483465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  513.483567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  513.483670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  513.483845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  513.483957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  513.484064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  513.484167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  513.484272] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  513.484391] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  513.484505] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  513.484612] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  513.484834] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  513.484977] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  513.485079] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  513.485225] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  513.485334] [drm:intel_power_well_disable [i915]] disabling DC off
>[  513.485437] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  513.485531] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  513.486760] [drm:intel_power_well_disable [i915]] disabling always-on
>[  513.489457] [drm:drm_mode_addfb2] [FB:70]
>[  513.507987] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  513.508008] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  513.508121] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  513.508155] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  513.508192] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  513.508224] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  513.508259] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  513.508294] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  513.508329] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  513.508361] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  513.508393] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  513.508401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  513.508433] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  513.508436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  513.508469] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  513.508501] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  513.508534] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  513.508567] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  513.508599] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  513.508635] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  513.508857] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  513.508893] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  513.508926] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  513.508959] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  513.509018] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  513.509069] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  513.509105] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  513.509450] [drm:intel_power_well_enable [i915]] enabling always-on
>[  513.509480] [drm:intel_power_well_enable [i915]] enabling DC off
>[  513.509818] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  513.509868] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  513.509903] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  513.509957] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  513.510226] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  513.514348] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  513.514386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  513.514424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  513.514463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  513.514498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  513.514533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  513.514568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  513.514603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  513.514638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  513.515042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  513.515076] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  513.515117] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  513.515154] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  513.515222] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  513.515257] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  513.515518] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  513.516759] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  513.517272] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  513.517307] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  513.517358] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  513.517390] [drm:hsw_audio_config_update [i915]] using automatic N
>[  513.534287] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  513.534362] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  513.534574] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  513.617979] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  513.618209] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  513.618303] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  513.618473] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  513.635936] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  513.636125] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  513.636317] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  513.640600] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  513.640691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  513.640890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  513.640994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  513.641086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  513.641180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  513.641271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  513.641375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  513.641467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  513.641562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  513.641652] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  513.641812] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  513.641909] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  513.642010] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  513.642149] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  513.642243] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  513.642372] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  513.642504] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  513.642600] [drm:intel_power_well_disable [i915]] disabling DC off
>[  513.642693] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  513.642825] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  513.643427] [drm:intel_power_well_disable [i915]] disabling always-on
>[  513.647319] [drm:drm_mode_addfb2] [FB:70]
>[  513.667379] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  513.667401] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  513.667522] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  513.667559] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  513.667599] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  513.667634] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  513.667751] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  513.667788] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  513.667828] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  513.667867] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  513.667902] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  513.667909] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  513.667944] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  513.667951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  513.667988] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  513.668024] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  513.668062] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  513.668101] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  513.668138] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  513.668178] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  513.668216] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  513.668253] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  513.668292] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  513.668331] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  513.668393] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  513.668447] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  513.668485] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  513.668896] [drm:intel_power_well_enable [i915]] enabling always-on
>[  513.668929] [drm:intel_power_well_enable [i915]] enabling DC off
>[  513.669215] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  513.669267] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  513.669304] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  513.669361] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  513.669618] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  513.673839] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  513.673876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  513.673916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  513.673955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  513.673991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  513.674026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  513.674061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  513.674096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  513.674131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  513.674166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  513.674200] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  513.674237] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  513.674272] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  513.674339] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  513.674373] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  513.674660] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  513.676299] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  513.676925] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  513.676959] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  513.677011] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  513.677043] [drm:hsw_audio_config_update [i915]] using automatic N
>[  513.693986] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  513.694065] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  513.694278] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  513.777510] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  513.777858] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  513.777955] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  513.778122] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  513.794065] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  513.794232] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  513.794393] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  513.798652] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  513.798854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  513.798953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  513.799053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  513.799143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  513.799233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  513.799322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  513.799421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  513.799510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  513.799600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  513.799689] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  513.799880] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  513.799980] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  513.800075] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  513.800219] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  513.800314] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  513.800444] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  513.800576] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  513.800672] [drm:intel_power_well_disable [i915]] disabling DC off
>[  513.800812] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  513.800897] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  513.801499] [drm:intel_power_well_disable [i915]] disabling always-on
>[  513.804213] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  513.836579] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  513.836618] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  513.836661] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  513.836754] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  513.836790] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  513.836832] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  513.836874] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  513.836913] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  513.836950] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  513.836987] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  513.837023] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  513.837031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  513.837068] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  513.837072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  513.837109] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  513.837146] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  513.837183] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  513.837220] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  513.837257] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  513.837299] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  513.837335] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  513.837376] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  513.837414] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  513.837453] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  513.837491] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  513.837538] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  513.837577] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  513.837617] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  513.837653] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  513.837734] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  513.837773] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  513.837810] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  513.837846] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  513.837882] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  513.837886] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  513.837922] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  513.837926] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  513.837964] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  513.838000] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  513.838039] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  513.838075] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  513.838114] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  513.838154] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  513.838190] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  513.838229] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  513.838267] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  513.838306] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  513.838344] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  513.838385] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  513.838434] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  513.838472] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  513.838516] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  513.838553] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  513.838748] [drm:intel_power_well_enable [i915]] enabling always-on
>[  513.838780] [drm:intel_power_well_enable [i915]] enabling DC off
>[  513.839069] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  513.839129] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  513.839276] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  513.839314] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  513.839376] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  513.839582] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  513.842733] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  513.842792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  513.842850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  513.842916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  513.842974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  513.843032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  513.843090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  513.843148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  513.843206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  513.843264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  513.843321] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  513.843384] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  513.843445] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  513.843546] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  513.843603] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  513.844023] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  513.844072] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  513.932831] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  514.003129] [drm:wait_panel_status [i915]] Wait complete
>[  514.003191] [drm:edp_panel_on [i915]] Wait for panel power on
>[  514.003259] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  514.111673] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  514.111731] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  514.111789] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  514.111916] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  514.203823] [drm:wait_panel_status [i915]] Wait complete
>[  514.203904] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  514.203976] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  514.205447] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  514.205501] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  514.205561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  514.206500] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  514.206557] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  514.207807] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  514.208118] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  514.210093] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  514.210194] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  514.210250] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  514.210313] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  514.210394] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  514.210449] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  514.210527] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  514.210584] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  514.210856] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  514.210912] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  514.211264] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  514.213230] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  514.213876] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  514.213934] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  514.214018] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  514.214050] [drm:hsw_audio_config_update [i915]] using automatic N
>[  514.230941] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  514.230989] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  514.231179] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  514.231359] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  514.231406] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  514.231582] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  514.232214] Console: switching to colour frame buffer device 240x67
>[  514.459801] Console: switching to colour dummy device 80x25
>[  514.460054] [IGT] kms_pipe_crc_basic: executing
>[  514.486397] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  514.486464] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  514.486523] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  514.486579] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  514.486630] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  514.486781] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  514.487417] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  514.488029] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  514.488048] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  514.488055] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  514.488103] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  514.488170] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  514.488818] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  514.489271] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  514.489319] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  514.489386] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  514.498038] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.506778] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.515589] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.524533] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.533370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.542244] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.551132] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.560074] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.569086] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.578093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.587071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.596055] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.605129] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.614118] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.623119] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.632110] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.641103] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.650090] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.659102] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.668103] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.677098] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.686095] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.695095] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.704100] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.713099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.722085] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.731082] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.740072] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.749099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.758128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.767130] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.776113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.776162] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  514.776178] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  514.776256] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  514.776362] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  514.857207] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  514.861396] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  514.861513] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  514.861525] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  514.862330] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  514.862340] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  514.862349] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  514.862355] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  514.862830] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  514.862844] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  514.862854] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  514.862863] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  514.862873] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  514.862882] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  514.862896] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  514.862906] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  514.862915] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  514.862925] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  514.862934] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  514.862944] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  514.862953] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  514.862963] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  514.862972] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  514.862981] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  514.862994] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  514.863004] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  514.863013] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  514.863022] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  514.863032] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  514.863041] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  514.863050] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  514.863059] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  514.878545] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  514.878595] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  514.878636] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  514.878707] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  514.878745] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  514.878780] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  514.879479] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  514.880057] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  514.880070] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  514.880075] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  514.880558] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  514.880604] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  514.881268] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  514.881767] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  514.882151] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  514.882198] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  514.890839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.899495] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.908166] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.916920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.925671] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.934488] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.943243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.952019] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.960890] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.969799] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.978690] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.987656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  514.996681] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.005737] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.014847] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.023916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.032905] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.041893] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.050849] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.059839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.068820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.077862] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.086839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.095847] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.104862] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.113857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.122847] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.131846] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.140858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.149848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.158846] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.167840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  515.167890] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  515.167905] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  515.169256] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  515.169373] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  515.250322] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  515.254515] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  515.254631] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  515.254770] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  515.255441] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  515.255450] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  515.255459] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  515.255465] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  515.255936] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  515.255952] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  515.255966] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  515.255975] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  515.255985] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  515.255994] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  515.256004] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  515.256013] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  515.256023] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  515.256033] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  515.256042] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  515.256055] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  515.256067] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  515.256077] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  515.256086] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  515.256096] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  515.256105] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  515.256114] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  515.256124] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  515.256136] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  515.256146] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  515.256155] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  515.256167] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  515.256176] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  515.257974] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A
>[  515.259795] [drm:drm_mode_addfb2] [FB:71]
>[  515.276722] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  515.276744] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  515.310481] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  515.310649] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  515.311058] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  515.311112] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  515.311328] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  515.516852] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  515.516940] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  515.527836] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  515.527917] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  515.528004] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  515.580123] [drm:wait_panel_status [i915]] Wait complete
>[  515.580213] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  515.580308] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  515.580375] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  515.580456] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  515.580538] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  515.580616] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  515.580798] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  515.581622] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  515.581959] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  515.582659] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  515.599248] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  515.599422] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  515.599610] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  515.603917] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  515.604022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  515.604123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  515.604237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  515.604338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  515.604439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  515.604540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  515.604650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  515.605813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  515.605915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  515.606014] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  515.606131] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  515.606239] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  515.606345] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  515.606522] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  515.606621] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  515.608061] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  515.608166] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  516.036902] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  516.103171] [drm:wait_panel_status [i915]] Wait complete
>[  516.103282] [drm:edp_panel_on [i915]] Wait for panel power on
>[  516.103397] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  516.211729] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  516.211834] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  516.211933] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  516.212139] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  516.303853] [drm:wait_panel_status [i915]] Wait complete
>[  516.303997] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  516.304118] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  516.305933] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  516.306035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  516.306143] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  516.307504] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  516.307605] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  516.309233] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  516.309646] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  516.312278] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  516.312430] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  516.312526] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  516.312634] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  516.312867] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  516.312967] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  516.313098] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  516.313200] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  516.346126] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  516.346258] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  516.346592] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  516.347088] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  516.347193] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  516.347363] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  516.347508] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  516.348423] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  516.430091] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  516.430428] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  516.636881] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  516.637039] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  516.647946] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  516.648061] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  516.648180] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  516.699964] [drm:wait_panel_status [i915]] Wait complete
>[  516.700083] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  516.700203] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  516.700410] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  516.700511] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  516.700611] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  516.700710] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  516.700918] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  516.701174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  516.701291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  516.701400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  516.701506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  516.701606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  516.701712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  516.701908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  516.702017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  516.702129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  516.702234] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  516.702363] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  516.702475] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  516.702589] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  516.702831] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  516.702982] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  516.703120] [drm:intel_power_well_disable [i915]] disabling DC off
>[  516.703225] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  516.703317] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  516.704019] [drm:intel_power_well_disable [i915]] disabling always-on
>[  516.708200] [drm:drm_mode_addfb2] [FB:71]
>[  516.733102] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  516.733123] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  516.733237] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  516.733270] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  516.733308] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  516.733349] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  516.733381] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  516.733416] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  516.733451] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  516.733485] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  516.733519] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  516.733551] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  516.733583] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  516.733590] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  516.733622] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  516.733625] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  516.733658] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  516.733910] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  516.733944] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  516.733977] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  516.734010] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  516.734046] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  516.734079] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  516.734112] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  516.734147] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  516.734182] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  516.734218] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  516.734256] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  516.734299] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  516.734334] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  516.734823] [drm:intel_power_well_enable [i915]] enabling always-on
>[  516.734853] [drm:intel_power_well_enable [i915]] enabling DC off
>[  516.735134] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  516.735185] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  516.735326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  516.735361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  516.735399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  516.735434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  516.735469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  516.735503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  516.735540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  516.735574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  516.735610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  516.735644] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  516.735819] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  516.735856] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  516.735922] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  516.735956] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  516.736185] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  516.736223] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  517.156856] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  517.202331] [drm:wait_panel_status [i915]] Wait complete
>[  517.202391] [drm:edp_panel_on [i915]] Wait for panel power on
>[  517.202454] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  517.310893] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  517.310949] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  517.311003] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  517.311180] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  517.403553] [drm:wait_panel_status [i915]] Wait complete
>[  517.403658] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  517.403842] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  517.405398] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  517.405470] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  517.405548] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  517.406567] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  517.406639] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  517.408160] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  517.408498] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  517.410473] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  517.410595] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  517.410665] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  517.410826] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  517.410926] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  517.410996] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  517.411092] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  517.411165] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  517.427609] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  517.427839] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  517.428153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  517.528155] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  517.528459] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  517.732885] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  517.733048] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  517.746027] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  517.746140] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  517.746260] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  517.798095] [drm:wait_panel_status [i915]] Wait complete
>[  517.798213] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  517.798332] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  517.798539] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  517.798642] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  517.798742] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  517.798841] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  517.799045] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  517.799303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  517.799419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  517.799525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  517.799629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  517.799762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  517.799867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  517.799985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  517.800088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  517.800197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  517.800299] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  517.800421] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  517.800529] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  517.800640] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  517.800869] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  517.801016] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  517.801153] [drm:intel_power_well_disable [i915]] disabling DC off
>[  517.801259] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  517.801350] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  517.802032] [drm:intel_power_well_disable [i915]] disabling always-on
>[  517.805458] [drm:drm_mode_addfb2] [FB:71]
>[  517.825793] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  517.825815] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  517.825939] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  517.825975] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  517.826015] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  517.826050] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  517.826089] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  517.826128] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  517.826166] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  517.826201] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  517.826236] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  517.826240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  517.826275] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  517.826279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  517.826315] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  517.826350] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  517.826386] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  517.826423] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  517.826458] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  517.826499] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  517.826534] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  517.826573] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  517.826610] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  517.826645] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  517.826770] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  517.826824] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  517.826875] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  517.826913] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  517.827279] [drm:intel_power_well_enable [i915]] enabling always-on
>[  517.827311] [drm:intel_power_well_enable [i915]] enabling DC off
>[  517.827598] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  517.827652] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  517.827710] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  517.827770] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  517.828902] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  517.833168] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  517.833208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  517.833250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  517.833292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  517.833331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  517.833369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  517.833407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  517.833445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  517.833483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  517.833521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  517.833559] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  517.833598] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  517.833637] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  517.833774] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  517.833811] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  517.834096] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  517.835167] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  517.835743] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  517.835779] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  517.835837] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  517.835874] [drm:hsw_audio_config_update [i915]] using automatic N
>[  517.835970] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  517.836007] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  517.852867] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  517.852924] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  517.853106] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  517.953123] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  517.953301] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  517.953372] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  517.953498] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  517.970942] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  517.971034] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  517.971197] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  517.971381] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  517.975628] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  517.975736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  517.975818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  517.975901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  517.975976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  517.976049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  517.976123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  517.976205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  517.976279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  517.976352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  517.976425] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  517.976509] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  517.976588] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  517.976665] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  517.976915] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  517.977012] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  517.977139] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  517.977269] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  517.977391] [drm:intel_power_well_disable [i915]] disabling DC off
>[  517.977481] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  517.977563] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  517.978244] [drm:intel_power_well_disable [i915]] disabling always-on
>[  517.981037] [drm:drm_mode_addfb2] [FB:71]
>[  518.000659] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  518.000680] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  518.000792] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  518.000826] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  518.000863] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  518.000895] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  518.000931] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  518.000966] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  518.001002] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  518.001035] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  518.001067] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  518.001071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  518.001103] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  518.001107] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  518.001140] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  518.001172] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  518.001205] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  518.001240] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  518.001272] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  518.001310] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  518.001342] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  518.001377] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  518.001411] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  518.001445] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  518.001480] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  518.001529] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  518.001577] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  518.001611] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  518.002020] [drm:intel_power_well_enable [i915]] enabling always-on
>[  518.002050] [drm:intel_power_well_enable [i915]] enabling DC off
>[  518.002332] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  518.002383] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  518.002417] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  518.002469] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  518.002721] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  518.006834] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  518.006871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  518.006909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  518.006948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  518.006983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  518.007018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  518.007053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  518.007088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  518.007123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  518.007158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  518.007193] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  518.007229] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  518.007265] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  518.007331] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  518.007365] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  518.007648] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  518.008644] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  518.009256] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  518.009298] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  518.009358] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  518.009397] [drm:hsw_audio_config_update [i915]] using automatic N
>[  518.009495] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  518.009535] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  518.026268] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  518.026342] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  518.026553] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  518.126655] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  518.126916] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  518.126987] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  518.127108] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  518.143080] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  518.143165] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  518.143318] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  518.143486] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  518.147781] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  518.147852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  518.147927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  518.148004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  518.148073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  518.148140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  518.148208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  518.148283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  518.148351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  518.148419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  518.148486] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  518.148563] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  518.148635] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  518.148798] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  518.148899] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  518.148967] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  518.149067] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  518.149164] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  518.149256] [drm:intel_power_well_disable [i915]] disabling DC off
>[  518.149325] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  518.149387] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  518.150016] [drm:intel_power_well_disable [i915]] disabling always-on
>[  518.152329] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  518.177656] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  518.177727] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  518.177766] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  518.177805] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  518.177837] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  518.177873] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  518.177908] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  518.177944] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  518.177977] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  518.178009] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  518.178041] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  518.178049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  518.178080] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  518.178084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  518.178116] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  518.178148] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  518.178182] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  518.178214] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  518.178246] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  518.178284] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  518.178317] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  518.178351] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  518.178385] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  518.178419] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  518.178453] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  518.178494] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  518.178527] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  518.178564] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  518.178595] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  518.178629] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  518.178663] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  518.178749] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  518.178789] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  518.178829] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  518.178834] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  518.178873] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  518.178878] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  518.178919] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  518.178960] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  518.179002] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  518.179042] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  518.179084] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  518.179127] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  518.179167] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  518.179209] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  518.179252] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  518.179294] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  518.179334] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  518.179379] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  518.179433] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  518.179476] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  518.179524] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  518.179565] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  518.179746] [drm:intel_power_well_enable [i915]] enabling always-on
>[  518.179781] [drm:intel_power_well_enable [i915]] enabling DC off
>[  518.180073] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  518.180138] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  518.180279] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  518.180323] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  518.180390] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  518.180592] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  518.184778] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  518.184823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  518.184866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  518.184916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  518.184959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  518.185003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  518.185046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  518.185089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  518.185133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  518.185176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  518.185219] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  518.185265] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  518.185310] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  518.185389] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  518.185430] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  518.185664] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  518.185748] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  518.248853] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  518.302462] [drm:wait_panel_status [i915]] Wait complete
>[  518.302511] [drm:edp_panel_on [i915]] Wait for panel power on
>[  518.302564] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  518.410988] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  518.411051] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  518.411112] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  518.411234] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  518.503215] [drm:wait_panel_status [i915]] Wait complete
>[  518.503307] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  518.503383] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  518.505049] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  518.505109] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  518.505175] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  518.506148] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  518.506208] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  518.507486] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  518.507818] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  518.509936] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  518.510058] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  518.510118] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  518.510186] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  518.510274] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  518.510332] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  518.510416] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  518.510476] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  518.510791] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  518.510851] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  518.511225] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  518.513333] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  518.513972] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  518.514033] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  518.514119] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  518.514151] [drm:hsw_audio_config_update [i915]] using automatic N
>[  518.531059] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  518.531142] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  518.531406] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  518.531761] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  518.531844] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  518.532092] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  518.532696] Console: switching to colour frame buffer device 240x67
>[  518.760363] Console: switching to colour dummy device 80x25
>[  518.760589] [IGT] kms_pipe_crc_basic: executing
>[  518.783369] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  518.783432] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  518.783488] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  518.783540] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  518.783588] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  518.783639] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  518.784343] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  518.784891] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  518.784909] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  518.784916] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  518.784963] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  518.785029] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  518.785625] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  518.786117] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  518.786164] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  518.786228] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  518.794892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.803636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.812440] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.821280] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.830109] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.839016] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.847864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.856788] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.865710] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.874712] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.883707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.892680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.901657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.910655] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.919734] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.928880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.937871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.946855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.955841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.964883] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.973897] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.982882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  518.991866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.000844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.009875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.018864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.027869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.036857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.045857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.054852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.063837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.072908] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.072961] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  519.072977] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  519.073053] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  519.073158] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  519.154523] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  519.158707] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  519.158824] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  519.158836] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  519.159486] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  519.159496] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  519.159505] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  519.159511] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  519.160249] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  519.160262] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  519.160276] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  519.160286] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  519.160295] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  519.160305] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  519.160315] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  519.160328] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  519.160337] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  519.160347] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  519.160356] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  519.160366] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  519.160375] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  519.160385] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  519.160395] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  519.160407] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  519.160417] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  519.160426] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  519.160436] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  519.160445] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  519.160454] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  519.160464] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  519.160473] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  519.160485] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  519.174888] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  519.174935] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  519.174975] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  519.175011] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  519.175043] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  519.175077] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  519.175611] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  519.176236] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  519.176248] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  519.176253] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  519.176881] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  519.176928] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  519.177450] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  519.177935] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  519.178310] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  519.178357] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  519.187036] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.195755] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.204494] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.213203] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.221938] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.230640] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.239487] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.248343] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.257156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.265995] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.274920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.283847] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.292826] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.301821] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.310794] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.319710] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.328711] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.337690] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.346812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.355879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.364866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.373858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.382845] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.391865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.400835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.409914] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.418888] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.427863] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.436850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.445824] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.454878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.463856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  519.463902] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  519.463918] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  519.465368] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  519.465485] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  519.546126] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  519.550326] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  519.550441] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  519.550453] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  519.551385] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  519.551396] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  519.551405] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  519.551411] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  519.552043] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  519.552057] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  519.552071] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  519.552081] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  519.552093] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  519.552103] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  519.552113] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  519.552122] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  519.552132] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  519.552141] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  519.552151] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  519.552164] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  519.552174] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  519.552184] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  519.552193] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  519.552206] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  519.552215] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  519.552225] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  519.552234] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  519.552244] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  519.552253] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  519.552262] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  519.552272] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  519.552281] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  519.554191] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A-frame-sequence
>[  519.556069] [drm:drm_mode_addfb2] [FB:89]
>[  519.573036] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  519.573057] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  519.593619] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  519.593865] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  519.593930] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  519.593984] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  519.594201] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  519.796850] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  519.796939] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  519.811931] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  519.812020] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  519.812106] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  519.864216] [drm:wait_panel_status [i915]] Wait complete
>[  519.864317] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  519.864422] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  519.864511] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  519.864600] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  519.864688] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  519.864872] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  519.865074] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  519.865333] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  519.865449] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  519.865637] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  519.882249] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  519.882448] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  519.882681] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  519.887097] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  519.887201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  519.887302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  519.887417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  519.887518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  519.887618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  519.887718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  519.887944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  519.888052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  519.888162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  519.888260] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  519.888377] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  519.888485] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  519.888593] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  519.888849] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  519.888949] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  519.889365] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  519.889472] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  520.316896] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  520.401725] [drm:wait_panel_status [i915]] Wait complete
>[  520.401913] [drm:edp_panel_on [i915]] Wait for panel power on
>[  520.402029] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  520.510436] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  520.510542] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  520.510642] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  520.510845] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  520.602593] [drm:wait_panel_status [i915]] Wait complete
>[  520.602851] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  520.602975] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  520.604709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  520.604898] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  520.605003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  520.606485] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  520.606586] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  520.608430] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  520.609033] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  520.611450] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  520.611589] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  520.611675] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  520.612143] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  520.612267] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  520.612356] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  520.612474] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  520.612564] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  520.645226] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  520.645345] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  520.645655] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  520.646357] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  520.646458] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  520.646593] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  520.647200] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  520.648110] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  520.729228] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  520.729563] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  520.932905] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  520.933066] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  520.946011] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  520.946127] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  520.946247] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  520.998069] [drm:wait_panel_status [i915]] Wait complete
>[  520.998187] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  520.998308] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  520.998516] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  520.998599] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  520.998703] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  520.998805] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  520.998998] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  520.999420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  520.999543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  520.999653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  520.999841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  520.999943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  521.000049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  521.000158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  521.000264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  521.000367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  521.000472] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  521.000593] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  521.000707] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  521.000868] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  521.001021] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  521.001172] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  521.001310] [drm:intel_power_well_disable [i915]] disabling DC off
>[  521.001414] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  521.001506] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  521.002156] [drm:intel_power_well_disable [i915]] disabling always-on
>[  521.005358] [drm:drm_mode_addfb2] [FB:89]
>[  521.024628] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  521.024892] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  521.025009] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  521.025043] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  521.025082] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  521.025121] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  521.025153] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  521.025189] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  521.025224] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  521.025258] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  521.025292] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  521.025326] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  521.025358] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  521.025364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  521.025396] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  521.025401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  521.025434] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  521.025466] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  521.025501] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  521.025533] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  521.025567] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  521.025604] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  521.025638] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  521.026748] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  521.026782] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  521.026816] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  521.026850] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  521.026889] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  521.026932] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  521.026967] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  521.027342] [drm:intel_power_well_enable [i915]] enabling always-on
>[  521.027370] [drm:intel_power_well_enable [i915]] enabling DC off
>[  521.027654] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  521.028470] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  521.028611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  521.028645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  521.028928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  521.028963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  521.028998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  521.029033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  521.029070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  521.029104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  521.029139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  521.029174] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  521.029211] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  521.029247] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  521.029314] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  521.029349] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  521.029543] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  521.029579] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  521.452859] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  521.502403] [drm:wait_panel_status [i915]] Wait complete
>[  521.502494] [drm:edp_panel_on [i915]] Wait for panel power on
>[  521.502588] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  521.611023] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  521.611119] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  521.611206] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  521.611406] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  521.703806] [drm:wait_panel_status [i915]] Wait complete
>[  521.703951] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  521.704073] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  521.705886] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  521.705986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  521.706090] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  521.707288] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  521.707387] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  521.708971] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  521.709386] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  521.712056] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  521.712229] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  521.712327] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  521.712435] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  521.712568] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  521.712666] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  521.712883] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  521.712988] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  521.729212] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  521.729342] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  521.729672] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  521.829888] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  521.830229] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  522.036884] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  522.037046] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  522.047945] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  522.048058] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  522.048177] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  522.100029] [drm:wait_panel_status [i915]] Wait complete
>[  522.100148] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  522.100269] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  522.100460] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  522.100560] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  522.100659] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  522.100866] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  522.100966] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  522.101214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  522.101343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  522.101460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  522.101563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  522.101676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  522.101849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  522.101968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  522.102068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  522.102174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  522.102276] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  522.102398] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  522.102513] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  522.102628] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  522.102809] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  522.102962] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  522.103099] [drm:intel_power_well_disable [i915]] disabling DC off
>[  522.103201] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  522.103294] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  522.103986] [drm:intel_power_well_disable [i915]] disabling always-on
>[  522.108165] [drm:drm_mode_addfb2] [FB:89]
>[  522.127817] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  522.127838] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  522.127958] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  522.127993] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  522.128033] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  522.128066] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  522.128103] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  522.128139] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  522.128175] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  522.128209] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  522.128242] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  522.128247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  522.128281] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  522.128284] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  522.128319] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  522.128352] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  522.128387] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  522.128421] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  522.128454] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  522.128494] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  522.128527] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  522.128564] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  522.128600] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  522.128635] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  522.129171] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  522.129229] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  522.129279] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  522.129316] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  522.129821] [drm:intel_power_well_enable [i915]] enabling always-on
>[  522.129853] [drm:intel_power_well_enable [i915]] enabling DC off
>[  522.130137] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  522.130188] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  522.130223] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  522.130278] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  522.130544] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  522.134860] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  522.134901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  522.134945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  522.134988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  522.135026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  522.135064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  522.135101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  522.135139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  522.135177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  522.135214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  522.135252] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  522.135292] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  522.135330] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  522.135401] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  522.135439] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  522.135899] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  522.137047] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  522.137587] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  522.137625] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  522.137789] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  522.137826] [drm:hsw_audio_config_update [i915]] using automatic N
>[  522.137922] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  522.137959] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  522.154677] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  522.154774] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  522.154946] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  522.255125] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  522.255355] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  522.255480] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  522.255652] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  522.272139] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  522.272242] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  522.272413] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  522.272610] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  522.276868] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  522.276962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  522.277060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  522.277158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  522.277249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  522.277338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  522.277430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  522.277529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  522.277619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  522.277708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  522.277921] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  522.278032] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  522.278137] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  522.278237] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  522.278376] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  522.278470] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  522.278598] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  522.278820] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  522.278949] [drm:intel_power_well_disable [i915]] disabling DC off
>[  522.279042] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  522.279124] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  522.279803] [drm:intel_power_well_disable [i915]] disabling always-on
>[  522.282604] [drm:drm_mode_addfb2] [FB:89]
>[  522.302074] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  522.302095] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  522.302214] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  522.302248] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  522.302285] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  522.302317] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  522.302353] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  522.302387] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  522.302421] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  522.302453] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  522.302485] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  522.302491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  522.302523] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  522.302526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  522.302559] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  522.302592] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  522.302625] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  522.302658] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  522.303477] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  522.303514] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  522.303546] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  522.303582] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  522.303616] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  522.303649] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  522.304071] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  522.304138] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  522.304195] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  522.304235] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  522.304629] [drm:intel_power_well_enable [i915]] enabling always-on
>[  522.304986] [drm:intel_power_well_enable [i915]] enabling DC off
>[  522.305275] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  522.305334] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  522.305376] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  522.305435] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  522.306003] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  522.310242] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  522.310314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  522.310352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  522.310391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  522.310427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  522.310462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  522.310497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  522.310532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  522.310567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  522.310602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  522.310636] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  522.311229] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  522.311265] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  522.311332] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  522.311365] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  522.311622] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  522.312862] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  522.313397] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  522.313431] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  522.313483] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  522.313515] [drm:hsw_audio_config_update [i915]] using automatic N
>[  522.313602] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  522.313635] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  522.330497] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  522.330546] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  522.330832] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  522.430978] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  522.431210] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  522.431303] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  522.431462] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  522.447198] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  522.447308] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  522.447493] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  522.447710] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  522.452112] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  522.452208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  522.452305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  522.452405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  522.452495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  522.452584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  522.452674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  522.452881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  522.452976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  522.453073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  522.453169] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  522.453281] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  522.453381] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  522.453482] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  522.453617] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  522.453788] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  522.453916] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  522.454055] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  522.454177] [drm:intel_power_well_disable [i915]] disabling DC off
>[  522.454271] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  522.454352] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  522.455024] [drm:intel_power_well_disable [i915]] disabling always-on
>[  522.457544] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  522.494961] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  522.495016] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  522.495073] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  522.495133] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  522.495184] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  522.495238] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  522.495293] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  522.495346] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  522.495398] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  522.495449] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  522.495500] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  522.495510] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  522.495560] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  522.495566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  522.495618] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  522.495669] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  522.495753] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  522.495804] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  522.495855] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  522.495913] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  522.495963] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  522.496018] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  522.496071] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  522.496123] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  522.496176] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  522.496241] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  522.496293] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  522.496350] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  522.496401] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  522.496454] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  522.496507] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  522.496559] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  522.496610] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  522.496660] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  522.496790] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  522.496842] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  522.496848] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  522.496902] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  522.496955] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  522.497007] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  522.497058] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  522.497111] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  522.497165] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  522.497216] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  522.497269] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  522.497322] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  522.497374] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  522.497427] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  522.497483] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  522.497549] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  522.497602] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  522.497662] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  522.497749] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  522.497973] [drm:intel_power_well_enable [i915]] enabling always-on
>[  522.498017] [drm:intel_power_well_enable [i915]] enabling DC off
>[  522.498319] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  522.498402] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  522.498555] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  522.498606] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  522.498736] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  522.498967] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  522.502842] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  522.502893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  522.502941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  522.502996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  522.503044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  522.503092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  522.503140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  522.503188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  522.503237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  522.503285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  522.503332] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  522.503384] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  522.503434] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  522.503520] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  522.503566] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  522.503853] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  522.503902] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  522.550836] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  522.602441] [drm:wait_panel_status [i915]] Wait complete
>[  522.602523] [drm:edp_panel_on [i915]] Wait for panel power on
>[  522.602611] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  522.711019] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  522.711110] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  522.711197] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  522.711367] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  522.804564] [drm:wait_panel_status [i915]] Wait complete
>[  522.804692] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  522.804884] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  522.806822] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  522.806919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  522.807024] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  522.808279] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  522.808376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  522.809933] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  522.810382] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  522.813791] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  522.813946] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  522.814043] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  522.814151] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  522.814289] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  522.814383] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  522.814518] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  522.814615] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  522.815072] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  522.815170] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  522.815713] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  522.817148] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  522.817699] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  522.817734] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  522.817788] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  522.817820] [drm:hsw_audio_config_update [i915]] using automatic N
>[  522.834838] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  522.834912] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  522.835151] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  522.835413] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  522.835486] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  522.835749] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  522.836268] Console: switching to colour frame buffer device 240x67
>[  523.064442] Console: switching to colour dummy device 80x25
>[  523.065204] [IGT] kms_pipe_crc_basic: executing
>[  523.087395] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  523.087461] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  523.087519] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  523.087574] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  523.087626] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  523.087680] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  523.088424] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  523.089121] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  523.089140] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  523.089147] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  523.089193] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  523.089257] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  523.089926] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  523.090350] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  523.090395] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  523.090454] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  523.099209] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.108033] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.116853] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.125771] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.134619] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.143664] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.152552] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.161395] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.170335] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.179311] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.188320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.197332] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.206325] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.215333] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.224339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.233349] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.242350] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.251363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.260364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.269387] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.278395] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.287399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.296399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.305397] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.314399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.323405] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.332407] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.341421] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.350426] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.359436] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.368438] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.377439] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.377489] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  523.377504] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  523.377581] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  523.377690] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  523.459095] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  523.463272] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  523.463388] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  523.463400] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  523.464194] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  523.464205] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  523.464214] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  523.464220] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  523.464609] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  523.464622] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  523.464632] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  523.464813] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  523.464823] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  523.464835] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  523.464845] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  523.464855] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  523.464867] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  523.464881] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  523.464894] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  523.464906] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  523.464922] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  523.464934] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  523.464946] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  523.464963] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  523.464976] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  523.464988] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  523.465006] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  523.465018] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  523.465030] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  523.465042] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  523.465061] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  523.465073] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  523.480047] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  523.480093] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  523.480134] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  523.480168] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  523.480200] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  523.480234] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  523.480999] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  523.481460] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  523.481471] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  523.481476] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  523.482002] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  523.482048] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  523.482577] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  523.482953] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  523.483363] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  523.483405] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  523.492091] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.500826] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.509548] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.518274] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.526985] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.535713] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.544466] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.553181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.561916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.570632] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.579386] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.588261] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.597110] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.605973] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.614803] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.623620] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.632538] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.641369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.650264] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.659093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.667924] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.676769] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.685641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.694644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.703637] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.712622] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.721630] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.730630] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.739577] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.748615] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.757639] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.766618] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  523.766750] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  523.766765] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  523.767881] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  523.767986] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  523.848356] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  523.852541] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  523.852657] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  523.852787] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  523.853458] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  523.853468] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  523.853477] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  523.853483] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  523.853973] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  523.853987] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  523.853997] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  523.854006] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  523.854015] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  523.854025] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  523.854034] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  523.854044] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  523.854053] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  523.854063] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  523.854072] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  523.854086] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  523.854095] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  523.854105] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  523.854114] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  523.854123] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  523.854133] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  523.854142] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  523.854151] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  523.854161] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  523.854170] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  523.854184] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  523.854193] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  523.854202] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  523.856420] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-B
>[  523.858478] [drm:drm_mode_addfb2] [FB:70]
>[  523.875564] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  523.875668] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  523.875910] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  524.084791] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  524.084881] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  524.099799] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  524.099864] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  524.099928] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  524.150023] [drm:wait_panel_status [i915]] Wait complete
>[  524.150107] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  524.150196] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  524.150364] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  524.150538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  524.150619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  524.150700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  524.150927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  524.151022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  524.151117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  524.151210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  524.151303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  524.151398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  524.151490] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  524.151599] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  524.152261] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  524.152358] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  524.152449] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  524.152814] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  524.152953] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  524.153463] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  524.168083] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  524.168221] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  524.169301] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  524.169349] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  524.169619] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  524.169709] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  524.169916] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  524.170024] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  524.170470] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  524.170565] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  524.170659] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  524.170868] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  524.170972] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  524.171075] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  524.171179] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  524.171195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  524.171300] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  524.171317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  524.171418] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  524.171521] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  524.171627] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  524.171754] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  524.171854] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  524.171967] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  524.172072] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  524.172182] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  524.173000] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  524.173101] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  524.173202] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  524.173301] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  524.173456] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  524.173574] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  524.173675] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  524.174478] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  524.174848] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  524.174978] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  524.175181] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  524.185543] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  524.185662] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  524.185781] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  524.190023] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  524.190069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  524.190113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  524.190164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  524.190207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  524.190251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  524.190294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  524.190342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  524.190385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  524.190429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  524.190473] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  524.190521] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  524.190567] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  524.190612] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  524.190752] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  524.190796] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  524.191033] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  524.191080] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  524.604875] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  524.702869] [drm:wait_panel_status [i915]] Wait complete
>[  524.702952] [drm:edp_panel_on [i915]] Wait for panel power on
>[  524.703038] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  524.811403] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  524.811484] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  524.811558] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  524.811792] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  524.905040] [drm:wait_panel_status [i915]] Wait complete
>[  524.905173] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  524.905281] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  524.907258] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  524.907357] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  524.907460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  524.908874] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  524.908974] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  524.910851] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  524.911272] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  524.914101] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  524.914257] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  524.914353] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  524.914461] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  524.914596] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  524.914693] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  524.931095] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  524.931340] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  524.931478] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  524.931926] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  524.947826] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  525.031954] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  525.032294] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  525.236886] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  525.237045] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  525.250019] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  525.250133] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  525.250252] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  525.302070] [drm:wait_panel_status [i915]] Wait complete
>[  525.302202] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  525.302407] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  525.302553] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  525.302653] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  525.302752] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  525.302936] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  525.303966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  525.304090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  525.304199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  525.304301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  525.304402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  525.304503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  525.304609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  525.304709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  525.304945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  525.305047] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  525.305177] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  525.305294] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  525.305407] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  525.305559] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  525.305705] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  525.305914] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  525.306065] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  525.306179] [drm:intel_power_well_disable [i915]] disabling DC off
>[  525.306283] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  525.306374] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  525.307609] [drm:intel_power_well_disable [i915]] disabling always-on
>[  525.311204] [drm:drm_mode_addfb2] [FB:70]
>[  525.328596] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  525.328617] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  525.329008] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  525.329043] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  525.329083] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  525.329121] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  525.329153] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  525.329188] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  525.329224] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  525.329259] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  525.329293] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  525.329327] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  525.329359] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  525.329365] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  525.329397] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  525.329401] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  525.329433] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  525.329466] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  525.329499] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  525.329531] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  525.329563] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  525.329601] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  525.329633] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  525.330161] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  525.330195] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  525.330229] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  525.330264] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  525.330303] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  525.330345] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  525.330381] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  525.331047] [drm:intel_power_well_enable [i915]] enabling always-on
>[  525.331077] [drm:intel_power_well_enable [i915]] enabling DC off
>[  525.331361] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  525.331409] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  525.331442] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  525.331495] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  525.331614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  525.331648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  525.332042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  525.332078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  525.332113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  525.332148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  525.332185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  525.332219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  525.332254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  525.332289] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  525.332327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  525.332363] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  525.332430] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  525.332465] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  525.333033] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  525.333073] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  525.756852] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  525.802511] [drm:wait_panel_status [i915]] Wait complete
>[  525.802568] [drm:edp_panel_on [i915]] Wait for panel power on
>[  525.802629] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  525.911088] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  525.911144] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  525.911195] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  525.911307] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  526.003260] [drm:wait_panel_status [i915]] Wait complete
>[  526.003390] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  526.003498] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  526.005206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  526.005295] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  526.005388] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  526.006989] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  526.007081] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  526.008652] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  526.009103] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  526.011883] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  526.012022] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  526.012108] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  526.012205] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  526.012325] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  526.012412] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  526.029058] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  526.029178] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  526.029485] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  526.129421] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  526.129889] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  526.332884] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  526.333027] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  526.346119] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  526.346220] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  526.346327] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  526.397813] [drm:wait_panel_status [i915]] Wait complete
>[  526.397934] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  526.398125] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  526.398346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  526.398448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  526.398542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  526.398632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  526.398821] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  526.398914] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  526.399007] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  526.399186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  526.399275] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  526.399367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  526.399465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  526.399560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  526.399651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  526.399832] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  526.399923] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  526.400006] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  526.400088] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  526.400199] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  526.400306] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  526.400385] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  526.400494] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  526.400576] [drm:intel_power_well_disable [i915]] disabling DC off
>[  526.400652] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  526.400780] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  526.401367] [drm:intel_power_well_disable [i915]] disabling always-on
>[  526.404086] [drm:drm_mode_addfb2] [FB:70]
>[  526.423556] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  526.423577] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  526.423738] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  526.423778] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  526.423818] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  526.423851] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  526.423885] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  526.423920] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  526.423957] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  526.423993] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  526.424028] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  526.424033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  526.424066] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  526.424070] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  526.424103] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  526.424137] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  526.424170] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  526.424204] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  526.424236] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  526.424272] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  526.424306] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  526.424342] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  526.424376] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  526.424411] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  526.424445] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  526.424496] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  526.424544] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  526.424579] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  526.424966] [drm:intel_power_well_enable [i915]] enabling always-on
>[  526.424998] [drm:intel_power_well_enable [i915]] enabling DC off
>[  526.425280] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  526.425330] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  526.425363] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  526.425418] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  526.425724] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  526.429852] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  526.429896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  526.429941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  526.429987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  526.430029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  526.430071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  526.430113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  526.430154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  526.430196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  526.430238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  526.430279] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  526.430322] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  526.430365] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  526.430439] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  526.430480] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  526.430923] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  526.432068] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  526.432611] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  526.432650] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  526.432781] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  526.432820] [drm:hsw_audio_config_update [i915]] using automatic N
>[  526.449653] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  526.449793] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  526.450014] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  526.550025] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  526.550214] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  526.550289] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  526.550450] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  526.568164] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  526.568342] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  526.568545] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  526.572920] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  526.573012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  526.573113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  526.573214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  526.573305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  526.573394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  526.573484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  526.573584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  526.573674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  526.573900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  526.573992] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  526.574100] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  526.574201] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  526.574299] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  526.574440] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  526.574535] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  526.574662] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  526.574855] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  526.574956] [drm:intel_power_well_disable [i915]] disabling DC off
>[  526.575049] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  526.575132] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  526.575791] [drm:intel_power_well_disable [i915]] disabling always-on
>[  526.578382] [drm:drm_mode_addfb2] [FB:70]
>[  526.598797] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  526.598818] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  526.598931] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  526.598964] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  526.599002] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  526.599033] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  526.599070] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  526.599105] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  526.599140] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  526.599172] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  526.599204] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  526.599209] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  526.599241] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  526.599245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  526.599278] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  526.599310] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  526.599343] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  526.599377] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  526.599409] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  526.599447] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  526.599479] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  526.599515] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  526.599549] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  526.599584] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  526.599618] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  526.599752] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  526.599799] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  526.599835] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  526.600190] [drm:intel_power_well_enable [i915]] enabling always-on
>[  526.600220] [drm:intel_power_well_enable [i915]] enabling DC off
>[  526.600502] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  526.600549] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  526.600582] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  526.600636] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  526.601429] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  526.605550] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  526.605586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  526.605624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  526.605662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  526.605920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  526.605954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  526.605987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  526.606020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  526.606053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  526.606087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  526.606120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  526.606157] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  526.606193] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  526.606258] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  526.606291] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  526.606549] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  526.607875] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  526.608408] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  526.608441] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  526.608491] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  526.608523] [drm:hsw_audio_config_update [i915]] using automatic N
>[  526.625355] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  526.625405] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  526.625573] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  526.725798] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  526.725972] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  526.726043] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  526.726165] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  526.743649] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  526.743877] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  526.744061] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  526.748311] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  526.748388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  526.748469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  526.748551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  526.748625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  526.748699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  526.748881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  526.748964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  526.749043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  526.749118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  526.749195] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  526.749283] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  526.749365] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  526.749448] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  526.749564] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  526.749642] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  526.749795] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  526.749903] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  526.749986] [drm:intel_power_well_disable [i915]] disabling DC off
>[  526.750062] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  526.750130] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  526.750797] [drm:intel_power_well_disable [i915]] disabling always-on
>[  526.753022] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  526.779599] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  526.779634] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  526.779733] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  526.779772] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  526.779804] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  526.779841] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  526.779875] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  526.779910] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  526.779943] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  526.779975] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  526.780006] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  526.780013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  526.780045] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  526.780048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  526.780081] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  526.780113] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  526.780146] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  526.780178] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  526.780210] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  526.780248] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  526.780279] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  526.780315] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  526.780349] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  526.780383] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  526.780416] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  526.780458] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  526.780490] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  526.780527] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  526.780559] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  526.780593] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  526.780627] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  526.780659] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  526.780740] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  526.780778] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  526.780782] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  526.780820] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  526.780824] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  526.780864] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  526.780903] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  526.780942] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  526.780981] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  526.781019] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  526.781061] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  526.781099] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  526.781139] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  526.781179] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  526.781220] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  526.781260] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  526.781301] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  526.781353] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  526.781395] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  526.781442] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  526.781481] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  526.781654] [drm:intel_power_well_enable [i915]] enabling always-on
>[  526.781761] [drm:intel_power_well_enable [i915]] enabling DC off
>[  526.782053] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  526.782119] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  526.782237] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  526.782276] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  526.782339] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  526.782530] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  526.785757] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  526.785806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  526.785855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  526.785911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  526.785959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  526.786007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  526.786055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  526.786104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  526.786151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  526.786200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  526.786247] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  526.786299] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  526.786349] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  526.786435] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  526.786483] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  526.786851] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  526.786900] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  526.848850] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  526.902153] [drm:wait_panel_status [i915]] Wait complete
>[  526.902221] [drm:edp_panel_on [i915]] Wait for panel power on
>[  526.902296] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  527.010680] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  527.010742] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  527.010806] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  527.010915] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  527.103830] [drm:wait_panel_status [i915]] Wait complete
>[  527.103934] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  527.104018] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  527.105563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  527.105627] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  527.105733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  527.106771] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  527.106845] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  527.107958] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  527.108204] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  527.109552] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  527.109620] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  527.109657] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  527.109721] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  527.109772] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  527.109807] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  527.109858] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  527.109893] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  527.110063] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  527.110099] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  527.110381] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  527.111702] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  527.112239] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  527.112276] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  527.112335] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  527.112370] [drm:hsw_audio_config_update [i915]] using automatic N
>[  527.129356] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  527.129443] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  527.129781] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  527.130061] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  527.130143] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  527.130388] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  527.131019] Console: switching to colour frame buffer device 240x67
>[  527.368070] Console: switching to colour dummy device 80x25
>[  527.368391] [IGT] kms_pipe_crc_basic: executing
>[  527.396504] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  527.396578] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  527.396640] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  527.396783] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  527.396842] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  527.396900] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  527.397566] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  527.398250] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  527.398270] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  527.398277] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  527.398331] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  527.398399] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  527.399114] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  527.399543] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  527.399589] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  527.399646] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  527.408538] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.417377] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.426226] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.435048] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.443875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.452802] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.461618] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.470637] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.479563] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.488579] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.497829] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.506831] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.515825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.524803] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.533705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.542694] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.551703] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.560686] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.569696] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.578670] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.587644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.596656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.605662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.614662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.623662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.632651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.641639] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.650637] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.659621] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.668827] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.677831] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.686855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.686898] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  527.686912] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  527.686984] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  527.687084] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  527.747307] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x18001a18, pins 0x00000040
>[  527.747401] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - long
>[  527.747489] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 6 - cnt: 0
>[  527.747646] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - long
>[  527.768619] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  527.772913] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  527.773016] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  527.773027] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  527.773616] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  527.773625] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  527.773633] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  527.773917] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  527.774261] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  527.774272] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  527.774281] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  527.774290] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  527.774301] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  527.774309] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  527.774318] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  527.774326] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  527.774335] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  527.774343] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  527.774352] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  527.774360] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  527.774368] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  527.774377] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  527.774388] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  527.774396] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  527.774405] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  527.774413] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  527.774421] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  527.774429] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  527.774438] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  527.774446] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  527.774454] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  527.774462] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  527.774598] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[  527.774693] [drm:i915_hotplug_work_func [i915]] Connector DP-2 (pin 6) received hotplug event.
>[  527.774886] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  527.774995] [drm:i915_hotplug_work_func [i915]] Connector HDMI-A-1 (pin 6) received hotplug event.
>[  527.775085] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  527.853849] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  527.858052] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  527.858157] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  527.858168] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  527.871969] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  527.872021] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  527.872066] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  527.872105] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  527.872142] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  527.872181] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  527.873107] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  527.873585] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  527.873598] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  527.873602] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  527.874427] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  527.874481] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  527.875260] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  527.875767] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  527.876241] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  527.876288] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  527.876298] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  527.876833] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  527.876876] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  527.944976] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x18001a18, pins 0x00000040
>[  527.945037] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - long
>[  527.945094] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 6 - cnt: 1
>[  527.945195] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - long
>[  527.956076] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  527.960283] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  527.960373] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  527.960382] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  527.960962] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  527.960974] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  527.960985] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  527.960992] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  527.961281] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  527.961291] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  527.961298] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  527.961305] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  527.961312] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  527.961318] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  527.961325] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  527.961335] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  527.961342] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  527.961349] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  527.961355] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  527.961362] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  527.961369] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  527.961376] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  527.961383] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  527.961390] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  527.961396] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  527.961406] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  527.961412] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  527.961419] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  527.961426] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  527.961432] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  527.961439] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  527.961446] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  527.962821] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-B-frame-sequence
>[  527.963578] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[  527.963659] [drm:i915_hotplug_work_func [i915]] Connector DP-2 (pin 6) received hotplug event.
>[  527.963784] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  527.972605] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.981576] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.990536] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  527.999411] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.008278] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.017122] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.025981] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.034822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.043664] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.052566] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.061415] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.070272] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.079128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.087977] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.096828] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.105796] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.114652] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.123559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.132402] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.141252] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.150110] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.159024] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.167880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.176813] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.185665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.194567] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.203536] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.212398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.221248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.230086] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.239002] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.247882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  528.247923] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  528.248012] [drm:i915_hotplug_work_func [i915]] Connector HDMI-A-1 (pin 6) received hotplug event.
>[  528.248091] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  528.328457] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  528.332703] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  528.332799] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  528.332810] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  528.333756] [drm:drm_mode_addfb2] [FB:71]
>[  528.354879] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  528.354988] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  528.355179] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  528.556848] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  528.556945] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  528.561487] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  528.561553] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  528.561621] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  528.613605] [drm:wait_panel_status [i915]] Wait complete
>[  528.613695] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  528.613925] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  528.614013] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  528.614098] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  528.614182] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  528.614392] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  528.614595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  528.614680] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  528.614803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  528.614893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  528.614975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  528.615060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  528.615142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  528.615226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  528.615309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  528.615393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  528.615476] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  528.615573] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  528.615661] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  528.615805] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  528.629265] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  528.629392] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  528.630405] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  528.630451] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  528.630719] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  528.630917] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  528.631013] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  528.631119] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  528.631208] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  528.631305] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  528.631398] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  528.631494] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  528.631585] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  528.631677] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  528.631817] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  528.631831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  528.631916] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  528.631929] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  528.632018] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  528.632107] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  528.632201] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  528.632288] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  528.632381] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  528.632476] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  528.632567] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  528.632660] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  528.632806] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  528.632895] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  528.632988] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  528.633080] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  528.633214] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  528.633322] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  528.633414] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  528.634128] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  528.634955] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  528.635070] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  528.635258] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  528.646837] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  528.646968] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  528.647034] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  528.651261] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  528.651315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  528.651366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  528.651426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  528.651477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  528.651529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  528.651580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  528.651635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  528.651813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  528.651897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  528.651972] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  528.652066] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  528.652544] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  528.652629] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  528.652784] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  528.653113] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  528.653453] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  528.653528] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  529.068900] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  529.201621] [drm:wait_panel_status [i915]] Wait complete
>[  529.201827] [drm:edp_panel_on [i915]] Wait for panel power on
>[  529.201936] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  529.310325] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  529.310423] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  529.310513] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  529.310686] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  529.402295] [drm:wait_panel_status [i915]] Wait complete
>[  529.402443] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  529.402567] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  529.404276] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  529.404378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  529.404482] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  529.406015] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  529.406120] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  529.407588] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  529.408136] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  529.410659] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  529.410860] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  529.410957] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  529.411065] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  529.411198] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  529.411295] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  529.427826] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  529.428073] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  529.428212] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  529.428519] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  529.444366] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  529.528493] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  529.528966] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  529.732885] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  529.733044] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  529.745989] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  529.746106] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  529.746225] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  529.797954] [drm:wait_panel_status [i915]] Wait complete
>[  529.798085] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  529.798290] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  529.798459] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  529.798560] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  529.798661] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  529.798836] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  529.799237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  529.799358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  529.799467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  529.799574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  529.799678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  529.800035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  529.800147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  529.800252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  529.800355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  529.800461] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  529.800584] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  529.800698] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  529.800899] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  529.801054] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  529.801202] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  529.801309] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  529.801456] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  529.801569] [drm:intel_power_well_disable [i915]] disabling DC off
>[  529.801673] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  529.801850] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  529.802474] [drm:intel_power_well_disable [i915]] disabling always-on
>[  529.805735] [drm:drm_mode_addfb2] [FB:71]
>[  529.831904] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  529.831925] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  529.832041] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  529.832075] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  529.832113] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  529.832153] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  529.832186] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  529.832222] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  529.832257] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  529.832292] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  529.832325] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  529.832358] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  529.832389] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  529.832393] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  529.832425] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  529.832429] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  529.832462] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  529.832495] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  529.832528] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  529.832560] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  529.832592] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  529.832630] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  529.832662] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  529.832907] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  529.832941] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  529.832974] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  529.833007] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  529.833044] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  529.833085] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  529.833120] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  529.833497] [drm:intel_power_well_enable [i915]] enabling always-on
>[  529.833527] [drm:intel_power_well_enable [i915]] enabling DC off
>[  529.833932] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  529.834433] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  529.834466] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  529.834519] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  529.834659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  529.834825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  529.834863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  529.834899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  529.834934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  529.834970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  529.835007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  529.835042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  529.835077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  529.835113] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  529.835153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  529.835191] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  529.835259] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  529.835293] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  529.835493] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  529.835531] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  530.252858] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  530.302415] [drm:wait_panel_status [i915]] Wait complete
>[  530.302476] [drm:edp_panel_on [i915]] Wait for panel power on
>[  530.302540] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  530.410992] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  530.411056] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  530.411114] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  530.411220] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  530.502770] [drm:wait_panel_status [i915]] Wait complete
>[  530.502878] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  530.502968] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  530.504886] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  530.504979] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  530.505072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  530.506215] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  530.506306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  530.507888] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  530.508272] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  530.510994] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  530.511130] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  530.511216] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  530.511312] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  530.511431] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  530.511518] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  530.528148] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  530.528252] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  530.528540] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  530.628639] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  530.629099] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  530.836885] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  530.837044] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  530.845946] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  530.846060] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  530.846178] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  530.898015] [drm:wait_panel_status [i915]] Wait complete
>[  530.898147] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  530.898352] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  530.898471] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  530.898571] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  530.898672] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  530.898847] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  530.899073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  530.899192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  530.899301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  530.899408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  530.899512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  530.899617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  530.899726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  530.899892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  530.899995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  530.900098] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  530.900221] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  530.900333] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  530.900446] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  530.900599] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  530.900821] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  530.900929] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  530.901080] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  530.901192] [drm:intel_power_well_disable [i915]] disabling DC off
>[  530.901297] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  530.901390] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  530.902068] [drm:intel_power_well_disable [i915]] disabling always-on
>[  530.907113] [drm:drm_mode_addfb2] [FB:71]
>[  530.925335] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  530.925356] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  530.925469] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  530.925503] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  530.925540] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  530.925574] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  530.925609] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  530.925642] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  530.926172] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  530.926205] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  530.926237] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  530.926243] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  530.926275] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  530.926278] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  530.926311] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  530.926344] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  530.926377] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  530.926409] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  530.926441] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  530.926481] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  530.926513] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  530.926548] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  530.926582] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  530.926617] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  530.926649] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  530.927368] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  530.927415] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  530.927449] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  530.928029] [drm:intel_power_well_enable [i915]] enabling always-on
>[  530.928058] [drm:intel_power_well_enable [i915]] enabling DC off
>[  530.928345] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  530.928392] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  530.928426] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  530.928478] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  530.929080] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  530.933244] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  530.933286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  530.933330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  530.933374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  530.933414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  530.933454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  530.933494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  530.933533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  530.933573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  530.933612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  530.933650] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  530.934294] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  530.934337] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  530.934410] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  530.934448] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  530.935012] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  530.936237] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  530.936936] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  530.936975] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  530.937034] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  530.937070] [drm:hsw_audio_config_update [i915]] using automatic N
>[  530.953999] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  530.954074] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  530.954287] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  531.054368] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  531.054569] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  531.054649] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  531.054954] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  531.071123] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  531.071311] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  531.071531] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  531.075809] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  531.075902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  531.075999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  531.076099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  531.076189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  531.076279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  531.076369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  531.076468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  531.076559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  531.076648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  531.076835] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  531.076944] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  531.077048] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  531.077147] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  531.077285] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  531.077379] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  531.077508] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  531.077640] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  531.078042] [drm:intel_power_well_disable [i915]] disabling DC off
>[  531.078136] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  531.078218] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  531.078899] [drm:intel_power_well_disable [i915]] disabling always-on
>[  531.081561] [drm:drm_mode_addfb2] [FB:71]
>[  531.101555] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  531.101578] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  531.102022] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  531.102057] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  531.102095] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  531.102127] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  531.102161] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  531.102196] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  531.102231] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  531.102263] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  531.102295] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  531.102302] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  531.102334] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  531.102338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  531.102370] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  531.102403] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  531.102436] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  531.102468] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  531.102501] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  531.102539] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  531.102571] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  531.102607] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  531.102639] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  531.103456] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  531.103491] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  531.103547] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  531.103596] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  531.103631] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  531.104201] [drm:intel_power_well_enable [i915]] enabling always-on
>[  531.104229] [drm:intel_power_well_enable [i915]] enabling DC off
>[  531.104511] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  531.104558] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  531.104594] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  531.104646] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  531.105196] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  531.109311] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  531.109348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  531.109387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  531.109426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  531.109461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  531.109496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  531.109531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  531.109566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  531.109600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  531.109634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  531.110018] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  531.110058] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  531.110095] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  531.110164] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  531.110199] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  531.110455] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  531.111635] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  531.112197] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  531.112231] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  531.112283] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  531.112316] [drm:hsw_audio_config_update [i915]] using automatic N
>[  531.129288] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  531.129345] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  531.129524] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  531.229570] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  531.229924] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  531.230025] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  531.230190] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  531.246083] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  531.246260] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  531.246461] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  531.250812] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  531.250908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  531.251005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  531.251107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  531.251197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  531.251287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  531.251376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  531.251476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  531.251565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  531.251655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  531.251844] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  531.251951] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  531.252053] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  531.252154] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  531.252296] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  531.252389] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  531.252520] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  531.252653] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  531.252826] [drm:intel_power_well_disable [i915]] disabling DC off
>[  531.252920] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  531.253002] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  531.253607] [drm:intel_power_well_disable [i915]] disabling always-on
>[  531.256272] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  531.286104] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  531.286157] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  531.286215] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  531.286274] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  531.286325] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  531.286379] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  531.286434] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  531.286488] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  531.286567] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  531.286619] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  531.286670] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  531.286716] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  531.286767] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  531.286772] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  531.286825] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  531.286877] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  531.286929] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  531.286980] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  531.287031] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  531.287090] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  531.287140] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  531.287194] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  531.287247] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  531.287300] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  531.287353] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  531.287420] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  531.287472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  531.287529] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  531.287580] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  531.287633] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  531.287809] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  531.287861] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  531.287912] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  531.287962] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  531.287970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  531.288020] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  531.288026] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  531.288078] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  531.288130] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  531.288182] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  531.288233] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  531.288284] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  531.288340] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  531.288391] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  531.288444] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  531.288497] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  531.288550] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  531.288603] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  531.288659] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  531.288761] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  531.288814] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  531.288874] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  531.288927] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  531.289151] [drm:intel_power_well_enable [i915]] enabling always-on
>[  531.289195] [drm:intel_power_well_enable [i915]] enabling DC off
>[  531.289497] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  531.289577] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  531.289752] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  531.289803] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  531.289886] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  531.290114] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  531.293832] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  531.293889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  531.293942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  531.294005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  531.294060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  531.294114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  531.294169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  531.294223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  531.294277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  531.294331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  531.294385] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  531.294443] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  531.294500] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  531.294595] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  531.294647] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  531.294960] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  531.295015] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  531.347837] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  531.403219] [drm:wait_panel_status [i915]] Wait complete
>[  531.403306] [drm:edp_panel_on [i915]] Wait for panel power on
>[  531.403400] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  531.511811] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  531.511893] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  531.511971] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  531.512106] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  531.604418] [drm:wait_panel_status [i915]] Wait complete
>[  531.604532] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  531.604630] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  531.606287] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  531.606364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  531.606449] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  531.607559] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  531.607636] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  531.609161] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  531.609547] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  531.611766] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  531.611873] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  531.611923] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  531.611979] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  531.612052] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  531.612100] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  531.612174] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  531.612223] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  531.612438] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  531.612489] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  531.612859] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  531.614564] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  531.615148] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  531.615198] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  531.615276] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  531.615324] [drm:hsw_audio_config_update [i915]] using automatic N
>[  531.632247] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  531.632331] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  531.632599] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  531.632955] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  531.633037] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  531.633280] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  531.633898] Console: switching to colour frame buffer device 240x67
>[  531.882297] Console: switching to colour dummy device 80x25
>[  531.882547] [IGT] kms_pipe_crc_basic: executing
>[  531.905440] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  531.905510] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  531.905572] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  531.905631] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  531.905793] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  531.905853] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  531.906529] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  531.907203] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  531.907222] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  531.907229] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  531.907283] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  531.907351] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  531.907977] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  531.908407] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  531.908456] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  531.908515] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  531.917272] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  531.926061] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  531.934854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  531.943702] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  531.952569] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  531.961451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  531.970364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  531.979286] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  531.988347] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  531.997324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.006305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.015301] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.024359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.033335] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.042313] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.051354] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.060352] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.069329] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.078299] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.087350] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.096339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.105326] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.114319] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.123315] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.132364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.141336] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.150301] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.159355] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.168334] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.177321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.186364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.195337] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.195383] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  532.195399] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  532.195473] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  532.195580] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  532.277043] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  532.281231] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  532.281346] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  532.281358] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  532.282160] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  532.282170] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  532.282179] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  532.282185] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  532.282572] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  532.282584] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  532.282594] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  532.282604] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  532.282613] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  532.282622] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  532.282632] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  532.282825] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  532.282835] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  532.282845] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  532.282855] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  532.282867] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  532.282877] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  532.282886] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  532.282901] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  532.282913] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  532.282924] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  532.282936] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  532.282948] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  532.282966] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  532.282978] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  532.282990] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  532.283002] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  532.283013] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  532.297539] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  532.297586] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  532.297627] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  532.297661] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  532.297733] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  532.297768] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  532.298292] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  532.298835] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  532.298848] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  532.298852] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  532.299325] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  532.299369] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  532.299907] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  532.300270] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  532.300708] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  532.300750] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  532.309350] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.318055] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.326753] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.335456] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.344144] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.352878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.361665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.370463] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.379235] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.387984] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.396749] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.405567] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.414434] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.423334] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.432308] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.441307] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.450234] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.459151] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.468072] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.477050] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.486096] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.495085] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.504075] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.513119] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.522101] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.531084] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.540073] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.549112] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.558090] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.567062] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.576126] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.585102] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  532.585148] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  532.585164] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  532.586491] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  532.586607] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  532.667877] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  532.672060] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  532.672176] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  532.672188] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  532.672993] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  532.673004] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  532.673013] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  532.673019] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  532.673397] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  532.673410] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  532.673420] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  532.673430] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  532.673442] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  532.673455] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  532.673465] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  532.673474] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  532.673484] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  532.673493] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  532.673503] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  532.673512] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  532.673521] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  532.673531] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  532.673541] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  532.673554] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  532.673566] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  532.673576] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  532.673585] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  532.673594] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  532.673604] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  532.673613] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  532.673622] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  532.673632] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  532.675484] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-C
>[  532.677343] [drm:drm_mode_addfb2] [FB:89]
>[  532.697284] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  532.697390] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  532.697583] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  532.900889] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  532.900985] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  532.913823] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  532.913884] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  532.913948] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  532.965193] [drm:wait_panel_status [i915]] Wait complete
>[  532.965280] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  532.965369] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  532.965532] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  532.965850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  532.965949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  532.966040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  532.966125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  532.966207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  532.966292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  532.966373] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  532.966456] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  532.966537] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  532.966658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  532.966739] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  532.966821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  532.966902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  532.966984] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  532.967079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  532.967170] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  532.967257] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  532.982163] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  532.982289] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  532.983134] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  532.983395] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  532.983711] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  532.984093] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  532.984280] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  532.998948] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  532.999130] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  532.999335] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  533.003607] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  533.003702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  533.004073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  533.004175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  533.004264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  533.004354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  533.004445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  533.004546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  533.004637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  533.004982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  533.005070] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  533.005178] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  533.005278] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  533.005378] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  533.005513] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  533.005604] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  533.005975] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  533.006105] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  533.006203] [drm:intel_power_well_disable [i915]] disabling DC off
>[  533.006295] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  533.006378] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  533.007596] [drm:intel_power_well_disable [i915]] disabling always-on
>[  533.008767] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  533.008814] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  533.009074] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  533.009166] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  533.009261] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  533.009361] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  533.009446] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  533.009536] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  533.009625] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  533.009715] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  533.009918] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  533.009998] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  533.010086] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  533.010102] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  533.010185] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  533.010203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  533.010284] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  533.010372] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  533.010458] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  533.010544] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  533.010629] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  533.010737] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  533.010815] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  533.010867] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  533.010919] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  533.010971] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  533.011023] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  533.011086] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  533.011135] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  533.011597] [drm:intel_power_well_enable [i915]] enabling always-on
>[  533.011639] [drm:intel_power_well_enable [i915]] enabling DC off
>[  533.011987] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  533.012058] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  533.012106] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  533.012180] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  533.012336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  533.012386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  533.012441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  533.012490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  533.012542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  533.012591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  533.012643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  533.012745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  533.012797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  533.012848] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  533.012905] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  533.012959] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  533.013047] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  533.013096] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  533.013334] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  533.013385] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  533.420921] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  533.501624] [drm:wait_panel_status [i915]] Wait complete
>[  533.501854] [drm:edp_panel_on [i915]] Wait for panel power on
>[  533.501976] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  533.610334] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  533.610441] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  533.610540] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  533.610708] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  533.704029] [drm:wait_panel_status [i915]] Wait complete
>[  533.704172] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  533.704291] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  533.706228] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  533.706327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  533.706432] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  533.707667] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  533.707857] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  533.709461] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  533.709901] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  533.712541] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  533.712697] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  533.712888] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  533.713004] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  533.713141] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  533.713241] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  533.729693] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  533.729898] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  533.730205] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  533.830310] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  533.830647] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  534.036882] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  534.037040] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  534.047921] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  534.048033] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  534.048152] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  534.099913] [drm:wait_panel_status [i915]] Wait complete
>[  534.100043] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  534.100248] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  534.100452] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  534.100552] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  534.100651] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  534.100827] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  534.101131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  534.101251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  534.101362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  534.101467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  534.101570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  534.101675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  534.101855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  534.101970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  534.102073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  534.102181] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  534.102307] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  534.102423] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  534.102536] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  534.102688] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  534.102930] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  534.103039] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  534.103191] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  534.103300] [drm:intel_power_well_disable [i915]] disabling DC off
>[  534.103405] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  534.103496] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  534.104203] [drm:intel_power_well_disable [i915]] disabling always-on
>[  534.107608] [drm:drm_mode_addfb2] [FB:89]
>[  534.127269] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  534.127292] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  534.127422] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  534.127462] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  534.127505] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  534.127549] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  534.127586] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  534.127625] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  534.127664] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  534.128247] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  534.128282] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  534.128315] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  534.128348] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  534.128354] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  534.128387] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  534.128391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  534.128424] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  534.128458] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  534.128491] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  534.128524] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  534.128557] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  534.128593] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  534.128625] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  534.128659] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  534.129354] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  534.129389] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  534.129428] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  534.129472] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  534.129506] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  534.130179] [drm:intel_power_well_enable [i915]] enabling always-on
>[  534.130210] [drm:intel_power_well_enable [i915]] enabling DC off
>[  534.130493] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  534.130541] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  534.130575] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  534.130628] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  534.131059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  534.131096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  534.131134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  534.131169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  534.131203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  534.131238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  534.131274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  534.131309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  534.131343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  534.131378] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  534.131416] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  534.131454] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  534.131522] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  534.131555] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  534.132344] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  534.132382] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  534.556867] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  534.602421] [drm:wait_panel_status [i915]] Wait complete
>[  534.602466] [drm:edp_panel_on [i915]] Wait for panel power on
>[  534.602514] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  534.710995] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  534.711054] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  534.711107] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  534.711205] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  534.802943] [drm:wait_panel_status [i915]] Wait complete
>[  534.803029] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  534.803099] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  534.804556] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  534.804609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  534.804666] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  534.805830] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  534.805905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  534.807219] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  534.807562] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  534.809522] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  534.809659] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  534.809797] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  534.809881] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  534.809986] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  534.810059] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  534.826625] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  534.826886] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  534.827197] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  534.927171] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  534.927480] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  535.132880] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  535.133018] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  535.143911] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  535.144014] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  535.144120] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  535.196161] [drm:wait_panel_status [i915]] Wait complete
>[  535.196274] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  535.196441] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  535.196530] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  535.196618] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  535.196775] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  535.196886] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  535.197083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  535.197189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  535.197287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  535.197408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  535.197511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  535.197616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  535.197725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  535.197896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  535.198002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  535.198104] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  535.198232] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  535.198347] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  535.198461] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  535.198612] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  535.198850] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  535.198961] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  535.199115] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  535.199224] [drm:intel_power_well_disable [i915]] disabling DC off
>[  535.199328] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  535.199421] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  535.200124] [drm:intel_power_well_disable [i915]] disabling always-on
>[  535.204421] [drm:drm_mode_addfb2] [FB:89]
>[  535.223126] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  535.223147] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  535.223266] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  535.223300] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  535.223337] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  535.223369] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  535.223405] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  535.223439] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  535.223474] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  535.223506] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  535.223538] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  535.223545] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  535.223577] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  535.223581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  535.223614] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  535.223646] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  535.224358] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  535.224392] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  535.224426] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  535.224463] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  535.224496] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  535.224531] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  535.224564] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  535.224598] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  535.224653] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  535.225122] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  535.225156] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  535.225529] [drm:intel_power_well_enable [i915]] enabling always-on
>[  535.225558] [drm:intel_power_well_enable [i915]] enabling DC off
>[  535.225900] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  535.225949] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  535.225982] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  535.226036] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  535.226435] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  535.230679] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  535.230835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  535.230881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  535.230926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  535.230966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  535.231006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  535.231045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  535.231085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  535.231125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  535.231165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  535.231204] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  535.231246] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  535.231288] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  535.231361] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  535.231400] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  535.231667] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  535.232838] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  535.233387] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  535.233427] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  535.233486] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  535.233523] [drm:hsw_audio_config_update [i915]] using automatic N
>[  535.250441] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  535.250498] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  535.250736] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  535.350794] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  535.350971] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  535.351041] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  535.351167] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  535.367115] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  535.367281] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  535.367441] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  535.371680] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  535.371823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  535.371904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  535.371986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  535.372061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  535.372134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  535.372208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  535.372290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  535.372364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  535.372438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  535.372511] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  535.372595] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  535.372675] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  535.372833] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  535.372946] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  535.373024] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  535.373133] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  535.373245] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  535.373324] [drm:intel_power_well_disable [i915]] disabling DC off
>[  535.373401] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  535.373470] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  535.374138] [drm:intel_power_well_disable [i915]] disabling always-on
>[  535.377124] [drm:drm_mode_addfb2] [FB:89]
>[  535.397871] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  535.397892] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  535.398010] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  535.398045] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  535.398082] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  535.398113] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  535.398149] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  535.398184] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  535.398220] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  535.398252] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  535.398284] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  535.398288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  535.398319] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  535.398323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  535.398357] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  535.398389] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  535.398422] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  535.398456] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  535.398488] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  535.398526] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  535.398558] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  535.398594] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  535.398628] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  535.398661] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  535.399908] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  535.399963] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  535.400002] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  535.400392] [drm:intel_power_well_enable [i915]] enabling always-on
>[  535.400424] [drm:intel_power_well_enable [i915]] enabling DC off
>[  535.401007] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  535.401334] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  535.401373] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  535.401433] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  535.401938] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  535.406065] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  535.406106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  535.406150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  535.406193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  535.406233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  535.406273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  535.406312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  535.406352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  535.406391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  535.406431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  535.406470] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  535.406512] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  535.406552] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  535.406624] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  535.406662] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  535.407487] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  535.408714] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  535.409254] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  535.409293] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  535.409351] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  535.409388] [drm:hsw_audio_config_update [i915]] using automatic N
>[  535.426303] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  535.426358] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  535.426535] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  535.526503] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  535.526632] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  535.526763] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  535.526856] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  535.542921] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  535.543035] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  535.543128] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  535.547345] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  535.547406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  535.547470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  535.547536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  535.547595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  535.547653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  535.547797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  535.547862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  535.547924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  535.547983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  535.548043] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  535.548113] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  535.548178] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  535.548243] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  535.548336] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  535.548400] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  535.548485] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  535.548578] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  535.548640] [drm:intel_power_well_disable [i915]] disabling DC off
>[  535.548743] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  535.548797] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  535.549364] [drm:intel_power_well_disable [i915]] disabling always-on
>[  535.550795] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  535.589126] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  535.589188] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  535.589253] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  535.589322] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  535.589381] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  535.589443] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  535.589506] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  535.589569] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  535.589630] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  535.589688] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  535.589789] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  535.589800] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  535.589858] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  535.589865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  535.589925] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  535.589985] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  535.590044] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  535.590104] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  535.590162] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  535.590229] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  535.590288] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  535.590351] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  535.590412] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  535.590473] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  535.590533] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  535.590608] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  535.590668] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  535.590868] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  535.590927] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  535.590988] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  535.591049] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  535.591110] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  535.591169] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  535.591227] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  535.591234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  535.591292] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  535.591298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  535.591359] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  535.591418] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  535.591477] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  535.591536] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  535.591595] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  535.591657] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  535.591754] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  535.591817] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  535.591878] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  535.591938] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  535.591997] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  535.592062] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  535.592135] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  535.592196] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  535.592265] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  535.592325] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  535.592577] [drm:intel_power_well_enable [i915]] enabling always-on
>[  535.592628] [drm:intel_power_well_enable [i915]] enabling DC off
>[  535.592970] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  535.593062] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  535.593215] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  535.593274] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  535.593367] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  535.593614] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  535.596818] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  535.596868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  535.596916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  535.596972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  535.597020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  535.597068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  535.597116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  535.597164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  535.597212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  535.597260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  535.597307] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  535.597359] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  535.597410] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  535.597496] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  535.597544] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  535.597816] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  535.597867] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  535.646855] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  535.702719] [drm:wait_panel_status [i915]] Wait complete
>[  535.702865] [drm:edp_panel_on [i915]] Wait for panel power on
>[  535.702955] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  535.811322] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  535.811412] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  535.811500] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  535.811641] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  535.903801] [drm:wait_panel_status [i915]] Wait complete
>[  535.903927] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  535.904037] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  535.905808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  535.905894] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  535.905988] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  535.907153] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  535.907239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  535.908700] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  535.909188] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  535.911579] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  535.911665] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  535.911738] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  535.911791] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  535.911859] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  535.911903] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  535.911972] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  535.912019] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  535.912233] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  535.912279] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  535.912625] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  535.914299] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  535.914896] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  535.914943] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  535.915018] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  535.915063] [drm:hsw_audio_config_update [i915]] using automatic N
>[  535.932007] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  535.932096] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  535.932375] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  535.932683] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  535.932858] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  535.933122] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  535.933790] Console: switching to colour frame buffer device 240x67
>[  536.157997] Console: switching to colour dummy device 80x25
>[  536.158225] [IGT] kms_pipe_crc_basic: executing
>[  536.184347] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  536.184411] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  536.184466] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  536.184518] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  536.184566] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  536.184618] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  536.185303] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  536.185855] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  536.185874] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  536.185885] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  536.185933] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  536.185996] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  536.186631] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  536.187131] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  536.187180] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  536.187253] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  536.195988] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.204856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.213783] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.222689] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.231715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.240840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.249870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.258877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.267873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.276877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.285871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.294867] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.303884] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.312878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.321885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.330878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.339889] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.348878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.357871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.366869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.375866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.384865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.393865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.402866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.411883] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.420885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.429888] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.438878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.447862] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.456855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.465855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.474855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.474900] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  536.474915] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  536.474986] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  536.475092] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  536.556478] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  536.560736] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  536.560851] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  536.560863] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  536.561516] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  536.561525] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  536.561534] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  536.561541] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  536.562014] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  536.562028] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  536.562038] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  536.562048] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  536.562058] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  536.562067] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  536.562083] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  536.562093] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  536.562102] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  536.562112] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  536.562122] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  536.562131] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  536.562140] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  536.562150] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  536.562159] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  536.562169] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  536.562181] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  536.562194] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  536.562203] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  536.562213] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  536.562222] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  536.562231] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  536.562240] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  536.562251] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  536.576681] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  536.576729] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  536.576768] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  536.576803] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  536.576835] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  536.576869] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  536.577385] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  536.577852] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  536.577865] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  536.577869] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  536.578340] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  536.578384] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  536.578946] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  536.579329] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  536.579754] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  536.579797] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  536.588418] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.597085] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.605800] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.614472] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.623158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.631878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.640546] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.649229] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.657900] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.666617] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.675353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.684025] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.692737] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.701430] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.710121] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.718805] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.727490] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.736163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.744903] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.753571] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.762265] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.770940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.779638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.788470] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.797163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.805896] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.814633] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.823339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.832035] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.840714] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.849378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.858078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  536.858103] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  536.858112] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  536.858981] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  536.859045] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  536.936862] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  536.941012] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  536.941111] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  536.941117] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  536.941439] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  536.941444] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  536.941449] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  536.941452] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  536.942190] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  536.942200] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  536.942206] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  536.942213] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  536.942219] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  536.942225] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  536.942232] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  536.942238] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  536.942244] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  536.942251] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  536.942257] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  536.942263] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  536.942269] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  536.942276] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  536.942282] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  536.942288] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  536.942294] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  536.942300] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  536.942306] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  536.942313] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  536.942319] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  536.942325] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  536.942331] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  536.942337] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  536.944608] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-C-frame-sequence
>[  536.945956] [drm:drm_mode_addfb2] [FB:70]
>[  536.965300] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  536.965405] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  536.965594] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  537.172868] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  537.172934] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  537.179533] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  537.179605] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  537.179674] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  537.231829] [drm:wait_panel_status [i915]] Wait complete
>[  537.231900] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  537.231968] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  537.232028] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  537.232089] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  537.232149] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  537.232205] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  537.232340] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  537.232413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  537.232498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  537.232584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  537.232660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  537.232808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  537.232885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  537.232964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  537.233043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  537.233123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  537.233201] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  537.233290] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  537.233371] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  537.233457] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  537.248545] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  537.248661] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  537.249572] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  537.250030] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  537.250349] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  537.250460] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  537.250638] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  537.265523] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  537.265693] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  537.266249] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  537.270580] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  537.270685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  537.271240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  537.271353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  537.271454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  537.271555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  537.271655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  537.272575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  537.272678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  537.273180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  537.273283] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  537.273402] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  537.273509] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  537.273615] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  537.274449] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  537.274553] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  537.274688] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  537.275339] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  537.275447] [drm:intel_power_well_disable [i915]] disabling DC off
>[  537.275549] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  537.275640] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  537.277441] [drm:intel_power_well_disable [i915]] disabling always-on
>[  537.278877] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  537.278928] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  537.279205] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  537.279306] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  537.279410] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  537.279523] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  537.279619] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  537.279720] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  537.280937] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  537.280971] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  537.281005] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  537.281037] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  537.281070] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  537.281077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  537.281108] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  537.281112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  537.281145] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  537.281177] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  537.281210] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  537.281244] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  537.281277] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  537.281315] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  537.281347] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  537.281383] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  537.281417] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  537.281451] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  537.281488] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  537.281531] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  537.281566] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  537.282820] [drm:intel_power_well_enable [i915]] enabling always-on
>[  537.282851] [drm:intel_power_well_enable [i915]] enabling DC off
>[  537.283133] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  537.283181] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  537.283217] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  537.283269] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  537.283384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  537.283419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  537.283457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  537.283491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  537.283525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  537.283560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  537.283595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  537.283630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  537.284234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  537.284271] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  537.284310] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  537.284346] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  537.284413] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  537.284447] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  537.284648] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  537.285029] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  537.684863] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  537.803407] [drm:wait_panel_status [i915]] Wait complete
>[  537.803492] [drm:edp_panel_on [i915]] Wait for panel power on
>[  537.803577] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  537.911997] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  537.912056] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  537.912110] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  537.912210] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  538.004827] [drm:wait_panel_status [i915]] Wait complete
>[  538.004912] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  538.004980] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  538.006538] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  538.006613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  538.006689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  538.007814] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  538.007887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  538.009201] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  538.009538] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  538.011501] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  538.011638] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  538.011780] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  538.011865] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  538.011962] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  538.012032] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  538.028568] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  538.028664] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  538.029022] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  538.129142] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  538.129463] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  538.332882] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  538.333023] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  538.345946] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  538.346058] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  538.346177] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  538.397897] [drm:wait_panel_status [i915]] Wait complete
>[  538.398027] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  538.398233] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  538.398449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  538.398530] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  538.398632] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  538.398731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  538.398831] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  538.398996] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  538.399134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  538.399240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  538.399348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  538.399453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  538.399570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  538.399678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  538.399847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  538.399956] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  538.400080] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  538.400848] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  538.400970] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  538.401448] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  538.401589] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  538.401690] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  538.401953] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  538.402071] [drm:intel_power_well_disable [i915]] disabling DC off
>[  538.402176] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  538.402266] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  538.403457] [drm:intel_power_well_disable [i915]] disabling always-on
>[  538.406151] [drm:drm_mode_addfb2] [FB:70]
>[  538.423765] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  538.423785] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  538.423897] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  538.423930] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  538.423969] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  538.424009] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  538.424041] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  538.424076] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  538.424111] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  538.424146] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  538.424320] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  538.424354] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  538.424386] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  538.424391] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  538.424423] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  538.424426] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  538.424459] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  538.424492] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  538.424525] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  538.424559] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  538.424591] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  538.424629] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  538.424661] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  538.424737] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  538.424774] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  538.424808] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  538.424849] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  538.424894] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  538.424931] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  538.425307] [drm:intel_power_well_enable [i915]] enabling always-on
>[  538.425337] [drm:intel_power_well_enable [i915]] enabling DC off
>[  538.425620] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  538.425690] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  538.425723] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  538.425779] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  538.426034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  538.426070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  538.426109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  538.426144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  538.426179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  538.426214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  538.426251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  538.426286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  538.426322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  538.426356] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  538.426396] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  538.426433] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  538.426501] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  538.426535] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  538.426850] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  538.426889] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  538.852856] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  538.902461] [drm:wait_panel_status [i915]] Wait complete
>[  538.902526] [drm:edp_panel_on [i915]] Wait for panel power on
>[  538.902595] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  539.010998] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  539.011061] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  539.011118] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  539.011246] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  539.104385] [drm:wait_panel_status [i915]] Wait complete
>[  539.104502] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  539.104600] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  539.106440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  539.106528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  539.106621] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  539.107868] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  539.107955] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  539.109398] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  539.109858] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  539.112227] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  539.112368] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  539.112455] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  539.112551] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  539.112668] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  539.112833] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  539.129375] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  539.129492] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  539.129905] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  539.229993] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  539.230330] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  539.436879] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  539.437032] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  539.447909] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  539.448022] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  539.448142] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  539.498389] [drm:wait_panel_status [i915]] Wait complete
>[  539.498516] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  539.498720] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  539.499084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  539.499204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  539.499313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  539.499419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  539.499521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  539.499626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  539.499767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  539.499876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  539.499983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  539.500090] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  539.500218] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  539.500334] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  539.500451] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  539.500555] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  539.500659] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  539.500837] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  539.500938] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  539.501086] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  539.501231] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  539.501334] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  539.501481] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  539.501589] [drm:intel_power_well_disable [i915]] disabling DC off
>[  539.501693] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  539.501854] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  539.502474] [drm:intel_power_well_disable [i915]] disabling always-on
>[  539.506817] [drm:drm_mode_addfb2] [FB:70]
>[  539.526034] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  539.526056] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  539.526169] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  539.526203] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  539.526240] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  539.526272] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  539.526308] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  539.526343] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  539.526377] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  539.526409] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  539.526441] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  539.526448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  539.526480] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  539.526483] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  539.526516] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  539.526549] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  539.526582] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  539.526616] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  539.526648] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  539.526734] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  539.526767] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  539.526805] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  539.526839] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  539.526873] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  539.526924] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  539.526972] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  539.527006] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  539.527368] [drm:intel_power_well_enable [i915]] enabling always-on
>[  539.527398] [drm:intel_power_well_enable [i915]] enabling DC off
>[  539.527709] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  539.527759] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  539.527793] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  539.527849] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  539.528338] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  539.532472] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  539.532518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  539.532564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  539.532611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  539.532651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  539.532842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  539.532885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  539.532927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  539.532970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  539.533011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  539.533054] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  539.533101] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  539.533147] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  539.533226] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  539.533267] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  539.533798] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  539.534928] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  539.535467] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  539.535507] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  539.535565] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  539.535602] [drm:hsw_audio_config_update [i915]] using automatic N
>[  539.552544] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  539.552602] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  539.552941] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  539.652883] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  539.653070] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  539.653146] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  539.653275] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  539.669110] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  539.669273] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  539.669433] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  539.673667] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  539.673837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  539.673935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  539.674034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  539.674124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  539.674214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  539.674303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  539.674402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  539.674492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  539.674581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  539.674670] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  539.674856] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  539.674963] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  539.675064] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  539.675211] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  539.675307] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  539.675434] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  539.675565] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  539.675661] [drm:intel_power_well_disable [i915]] disabling DC off
>[  539.675811] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  539.675902] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  539.676505] [drm:intel_power_well_disable [i915]] disabling always-on
>[  539.680418] [drm:drm_mode_addfb2] [FB:70]
>[  539.699601] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  539.699622] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  539.699993] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  539.700028] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  539.700065] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  539.700097] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  539.700132] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  539.700167] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  539.700201] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  539.700234] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  539.700265] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  539.700272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  539.700304] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  539.700308] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  539.700341] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  539.700373] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  539.700406] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  539.700438] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  539.700471] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  539.700509] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  539.700542] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  539.700577] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  539.700611] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  539.700644] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  539.701155] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  539.701204] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  539.701240] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  539.701602] [drm:intel_power_well_enable [i915]] enabling always-on
>[  539.701631] [drm:intel_power_well_enable [i915]] enabling DC off
>[  539.702177] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  539.702227] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  539.702260] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  539.702313] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  539.702545] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  539.706666] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  539.706733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  539.706772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  539.706810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  539.706845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  539.706880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  539.706915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  539.706950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  539.706985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  539.707020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  539.707055] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  539.707091] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  539.707127] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  539.707193] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  539.707227] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  539.707517] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  539.709172] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  539.709841] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  539.709879] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  539.709936] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  539.709973] [drm:hsw_audio_config_update [i915]] using automatic N
>[  539.726891] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  539.726973] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  539.727193] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  539.827231] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  539.827415] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  539.827491] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  539.827619] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  539.844123] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  539.844291] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  539.844451] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  539.848727] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  539.848891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  539.848990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  539.849089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  539.849180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  539.849270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  539.849359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  539.849458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  539.849548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  539.849637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  539.849818] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  539.849925] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  539.850032] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  539.850140] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  539.850283] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  539.850378] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  539.850506] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  539.850635] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  539.850794] [drm:intel_power_well_disable [i915]] disabling DC off
>[  539.850892] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  539.850975] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  539.851583] [drm:intel_power_well_disable [i915]] disabling always-on
>[  539.853567] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  539.878807] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  539.878850] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  539.878898] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  539.878945] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  539.878985] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  539.879029] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  539.879072] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  539.879115] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  539.879157] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  539.879197] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  539.879237] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  539.879246] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  539.879286] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  539.879290] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  539.879331] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  539.879372] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  539.879413] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  539.879454] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  539.879494] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  539.879541] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  539.879582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  539.879625] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  539.879667] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  539.879847] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  539.879890] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  539.879942] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  539.879985] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  539.880029] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  539.880069] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  539.880112] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  539.880154] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  539.880195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  539.880235] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  539.880275] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  539.880279] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  539.880319] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  539.880323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  539.880365] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  539.880405] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  539.880447] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  539.880488] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  539.880528] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  539.880571] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  539.880611] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  539.880653] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  539.880770] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  539.880813] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  539.880855] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  539.880899] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  539.880953] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  539.880996] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  539.881045] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  539.881087] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  539.881262] [drm:intel_power_well_enable [i915]] enabling always-on
>[  539.881297] [drm:intel_power_well_enable [i915]] enabling DC off
>[  539.881589] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  539.881655] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  539.881832] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  539.881873] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  539.881940] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  539.882136] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  539.885783] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  539.885828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  539.885872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  539.885921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  539.885965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  539.886008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  539.886052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  539.886095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  539.886138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  539.886182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  539.886225] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  539.886271] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  539.886316] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  539.886397] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  539.886439] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  539.886712] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  539.886758] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  539.950846] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  540.003351] [drm:wait_panel_status [i915]] Wait complete
>[  540.003414] [drm:edp_panel_on [i915]] Wait for panel power on
>[  540.003482] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  540.111894] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  540.111953] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  540.112010] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  540.112109] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  540.204216] [drm:wait_panel_status [i915]] Wait complete
>[  540.204304] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  540.204376] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  540.205901] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  540.205956] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  540.206017] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  540.207016] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  540.207071] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  540.208318] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  540.208634] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  540.210729] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  540.210823] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  540.210879] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  540.210945] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  540.211025] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  540.211079] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  540.211159] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  540.211217] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  540.211458] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  540.211514] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  540.211906] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  540.213851] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  540.214385] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  540.214422] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  540.214481] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  540.214516] [drm:hsw_audio_config_update [i915]] using automatic N
>[  540.231466] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  540.231553] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  540.231863] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  540.232138] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  540.232214] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  540.232452] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  540.233055] Console: switching to colour frame buffer device 240x67
>[  540.462169] Console: switching to colour dummy device 80x25
>[  540.462508] [IGT] kms_pipe_crc_basic: executing
>[  540.487386] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  540.487452] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  540.487512] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  540.487566] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  540.487618] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  540.487671] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  540.488669] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  540.489313] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  540.489331] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  540.489338] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  540.489388] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  540.489449] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  540.490193] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  540.490620] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  540.490723] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  540.490784] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  540.499558] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.508343] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.517132] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.525963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.534749] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.543530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.552332] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.561112] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.569965] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.578826] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.587775] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.596661] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.605636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.614590] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.623593] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.632630] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.641602] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.650620] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.659624] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.668624] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.677672] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.686711] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.695827] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.704851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.713870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.722850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.731847] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.740842] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.749848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.758825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.767838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.776880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.776927] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  540.776944] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  540.777021] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  540.777129] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  540.858323] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  540.862504] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  540.862618] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  540.862630] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  540.863352] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  540.863362] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  540.863371] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  540.863377] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  540.863858] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  540.863872] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  540.863885] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  540.863895] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  540.863904] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  540.863916] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  540.863926] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  540.863935] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  540.863944] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  540.863954] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  540.863963] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  540.863977] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  540.863990] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  540.864000] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  540.864009] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  540.864018] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  540.864028] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  540.864037] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  540.864047] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  540.864056] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  540.864068] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  540.864081] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  540.864090] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  540.864099] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  540.877117] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  540.877170] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  540.877217] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  540.877259] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  540.877297] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  540.877337] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  540.877907] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  540.878390] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  540.878403] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  540.878408] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  540.879034] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  540.879085] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  540.879677] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  540.880074] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  540.880434] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  540.880473] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  540.889061] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.897778] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.906512] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.915279] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.924027] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.932780] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.941536] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.950283] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.959025] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.967767] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.976611] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.985557] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  540.994416] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.003263] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.012122] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.020988] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.029869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.038777] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.047678] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.056657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.065627] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.074624] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.083688] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.092718] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.101810] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.110846] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.119871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.128845] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.137857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.146835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.155852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.164843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  541.164887] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  541.164902] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  541.166166] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  541.166282] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  541.247395] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  541.251572] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  541.251684] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  541.251807] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  541.252479] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  541.252488] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  541.252497] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  541.252503] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  541.252987] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  541.253000] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  541.253010] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  541.253023] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  541.253032] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  541.253041] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  541.253055] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  541.253064] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  541.253074] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  541.253083] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  541.253093] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  541.253106] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  541.253115] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  541.253124] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  541.253134] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  541.253143] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  541.253156] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  541.253165] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  541.253175] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  541.253187] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  541.253196] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  541.253206] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  541.253215] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  541.253224] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  541.255089] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-A
>[  541.256958] [drm:drm_mode_addfb2] [FB:71]
>[  541.275352] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  541.275372] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  541.294455] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  541.294624] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  541.294761] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  541.294818] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  541.295031] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  541.500838] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  541.500924] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  541.511841] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  541.511923] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  541.512010] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  541.563291] [drm:wait_panel_status [i915]] Wait complete
>[  541.563396] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  541.563502] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  541.563688] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  541.563988] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  541.564116] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  541.564330] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  541.564432] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  541.564537] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  541.564642] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  541.565140] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  541.581734] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  541.582009] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  541.582216] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  541.586529] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  541.586634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  541.586861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  541.586980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  541.587084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  541.587190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  541.587293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  541.587411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  541.587514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  541.587621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  541.587724] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  541.587911] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  541.588027] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  541.588145] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  541.588337] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  541.588441] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  541.589051] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  541.589157] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  542.020961] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  542.101795] [drm:wait_panel_status [i915]] Wait complete
>[  542.101906] [drm:edp_panel_on [i915]] Wait for panel power on
>[  542.102023] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  542.210332] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  542.210440] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  542.210540] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  542.210705] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  542.304008] [drm:wait_panel_status [i915]] Wait complete
>[  542.304151] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  542.304273] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  542.305965] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  542.306063] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  542.306167] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  542.307470] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  542.307574] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  542.309214] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  542.309631] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  542.312246] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  542.312398] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  542.312494] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  542.312601] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  542.312824] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  542.312924] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  542.313059] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  542.313162] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  542.346121] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  542.346255] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  542.346588] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  542.346918] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  542.347023] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  542.347161] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  542.347313] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  542.348046] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  542.413106] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  542.413437] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  542.620881] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  542.621037] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  542.629944] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  542.630059] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  542.630178] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  542.682020] [drm:wait_panel_status [i915]] Wait complete
>[  542.682136] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  542.682255] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  542.682453] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  542.682554] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  542.682653] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  542.682829] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  542.683139] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  542.683389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  542.683510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  542.683619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  542.683725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  542.683906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  542.684009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  542.684121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  542.684224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  542.684331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  542.684433] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  542.684555] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  542.684664] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  542.684864] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  542.685016] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  542.685168] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  542.685304] [drm:intel_power_well_disable [i915]] disabling DC off
>[  542.685409] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  542.685501] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  542.686208] [drm:intel_power_well_disable [i915]] disabling always-on
>[  542.690391] [drm:drm_mode_addfb2] [FB:71]
>[  542.709136] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  542.709157] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  542.709272] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  542.709306] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  542.709345] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  542.709386] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  542.709418] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  542.709453] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  542.709488] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  542.709523] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  542.709557] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  542.709589] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  542.709620] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  542.709625] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  542.709656] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  542.710311] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  542.710359] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  542.710393] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  542.710426] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  542.710460] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  542.710494] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  542.710531] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  542.710563] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  542.710597] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  542.710631] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  542.711186] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  542.711221] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  542.711262] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  542.711304] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  542.711338] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  542.711866] [drm:intel_power_well_enable [i915]] enabling always-on
>[  542.711896] [drm:intel_power_well_enable [i915]] enabling DC off
>[  542.712179] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  542.712230] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  542.712361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  542.712397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  542.712435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  542.712470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  542.712505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  542.712539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  542.712576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  542.712610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  542.712643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  542.712840] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  542.712880] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  542.712917] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  542.712984] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  542.713017] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  542.713428] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  542.713466] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  543.132829] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  543.201489] [drm:wait_panel_status [i915]] Wait complete
>[  543.201572] [drm:edp_panel_on [i915]] Wait for panel power on
>[  543.201657] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  543.310031] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  543.310136] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  543.310236] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  543.310415] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  543.403538] [drm:wait_panel_status [i915]] Wait complete
>[  543.403668] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  543.404483] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  543.406264] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  543.406363] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  543.406467] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  543.407696] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  543.407862] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  543.409457] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  543.409896] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  543.412550] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  543.412717] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  543.412910] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  543.413021] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  543.413161] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  543.413262] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  543.413396] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  543.413498] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  543.429678] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  543.429857] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  543.430141] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  543.513318] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  543.513654] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  543.716881] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  543.717036] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  543.729979] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  543.730093] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  543.730213] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  543.781925] [drm:wait_panel_status [i915]] Wait complete
>[  543.782043] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  543.782162] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  543.782366] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  543.782466] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  543.782567] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  543.782666] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  543.782839] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  543.783296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  543.783417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  543.783526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  543.783634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  543.783824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  543.783924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  543.784042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  543.784146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  543.784254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  543.784357] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  543.784483] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  543.784592] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  543.784707] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  543.784934] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  543.785080] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  543.785218] [drm:intel_power_well_disable [i915]] disabling DC off
>[  543.785322] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  543.785414] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  543.786113] [drm:intel_power_well_disable [i915]] disabling always-on
>[  543.790269] [drm:drm_mode_addfb2] [FB:71]
>[  543.812320] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  543.812342] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  543.812469] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  543.812507] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  543.812549] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  543.812587] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  543.812628] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  543.812665] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  543.813217] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  543.813254] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  543.813290] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  543.813298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  543.813334] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  543.813338] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  543.813376] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  543.813413] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  543.813451] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  543.813488] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  543.813525] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  543.813570] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  543.813606] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  543.813644] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  543.814403] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  543.814442] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  543.814481] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  543.814543] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  543.814597] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  543.814636] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  543.815345] [drm:intel_power_well_enable [i915]] enabling always-on
>[  543.815374] [drm:intel_power_well_enable [i915]] enabling DC off
>[  543.815654] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  543.816294] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  543.816328] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  543.816379] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  543.816638] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  543.820744] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  543.820780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  543.820821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  543.820860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  543.820896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  543.820930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  543.820965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  543.821000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  543.821035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  543.821070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  543.821105] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  543.821141] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  543.821176] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  543.821243] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  543.821278] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  543.821563] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  543.823169] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  543.823821] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  543.823854] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  543.823906] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  543.823940] [drm:hsw_audio_config_update [i915]] using automatic N
>[  543.824028] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  543.824062] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  543.840898] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  543.840970] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  543.841181] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  543.924374] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  543.924549] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  543.924619] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  543.924903] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  543.941127] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  543.941221] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  543.941383] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  543.941565] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  543.945901] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  543.945985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  543.946073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  543.946165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  543.946246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  543.946328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  543.946408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  543.946498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  543.946579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  543.946660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  543.946843] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  543.946945] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  543.947039] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  543.947129] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  543.947255] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  543.947339] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  543.947456] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  543.947577] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  543.947687] [drm:intel_power_well_disable [i915]] disabling DC off
>[  543.947835] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  543.947912] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  543.948517] [drm:intel_power_well_disable [i915]] disabling always-on
>[  543.952135] [drm:drm_mode_addfb2] [FB:71]
>[  543.971424] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  543.971447] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  543.971561] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  543.971595] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  543.971630] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  543.971662] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  543.972038] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  543.972073] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  543.972107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  543.972139] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  543.972171] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  543.972178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  543.972210] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  543.972213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  543.972246] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  543.972279] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  543.972312] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  543.972346] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  543.972378] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  543.972417] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  543.972448] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  543.972484] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  543.972519] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  543.972553] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  543.972587] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  543.972638] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  543.973513] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  543.973547] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  543.974076] [drm:intel_power_well_enable [i915]] enabling always-on
>[  543.974105] [drm:intel_power_well_enable [i915]] enabling DC off
>[  543.974388] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  543.974436] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  543.974469] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  543.974521] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  543.975011] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  543.979141] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  543.979179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  543.979219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  543.979258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  543.979293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  543.979328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  543.979363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  543.979398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  543.979433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  543.979467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  543.979502] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  543.979538] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  543.979574] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  543.979639] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  543.980215] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  543.980485] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  543.981811] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  543.982372] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  543.982411] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  543.982469] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  543.982506] [drm:hsw_audio_config_update [i915]] using automatic N
>[  543.982603] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  543.982641] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  543.999431] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  543.999498] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  543.999774] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  544.082979] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  544.083143] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  544.083209] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  544.083319] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  544.101192] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  544.101261] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  544.101391] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  544.101521] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  544.105803] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  544.105859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  544.105917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  544.105975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  544.106028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  544.106080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  544.106131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  544.106188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  544.106240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  544.106291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  544.106342] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  544.106402] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  544.106456] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  544.106510] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  544.106590] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  544.106644] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  544.106784] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  544.106863] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  544.106933] [drm:intel_power_well_disable [i915]] disabling DC off
>[  544.106990] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  544.107035] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  544.107594] [drm:intel_power_well_disable [i915]] disabling always-on
>[  544.109329] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  544.140992] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  544.141047] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  544.141104] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  544.141164] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  544.141215] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  544.141270] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  544.141324] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  544.141378] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  544.141430] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  544.141481] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  544.141532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  544.141542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  544.141592] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  544.141598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  544.141650] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  544.141743] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  544.141794] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  544.141846] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  544.141899] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  544.141956] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  544.142006] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  544.142061] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  544.142114] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  544.142167] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  544.142220] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  544.142285] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  544.142339] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  544.142395] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  544.142445] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  544.142499] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  544.142552] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  544.142603] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  544.142654] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  544.142733] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  544.142738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  544.142789] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  544.142794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  544.142847] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  544.142898] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  544.142951] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  544.143002] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  544.143053] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  544.143107] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  544.143158] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  544.143211] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  544.143264] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  544.143317] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  544.143371] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  544.143426] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  544.143491] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  544.143545] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  544.143605] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  544.143657] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  544.143920] [drm:intel_power_well_enable [i915]] enabling always-on
>[  544.143964] [drm:intel_power_well_enable [i915]] enabling DC off
>[  544.144267] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  544.144348] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  544.144503] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  544.144555] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  544.144638] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  544.144918] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  544.148785] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  544.148841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  544.148895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  544.148957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  544.149012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  544.149066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  544.149120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  544.149175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  544.149229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  544.149283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  544.149336] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  544.149396] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  544.149454] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  544.149548] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  544.149602] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  544.149919] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  544.149974] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  544.236835] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  544.301399] [drm:wait_panel_status [i915]] Wait complete
>[  544.301488] [drm:edp_panel_on [i915]] Wait for panel power on
>[  544.301582] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  544.409920] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  544.410010] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  544.410100] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  544.410244] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  544.503369] [drm:wait_panel_status [i915]] Wait complete
>[  544.503493] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  544.503600] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  544.505456] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  544.505541] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  544.505634] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  544.506866] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  544.506951] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  544.508379] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  544.508801] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  544.511235] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  544.511359] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  544.511430] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  544.511509] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  544.511611] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  544.511679] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  544.511820] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  544.511892] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  544.512195] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  544.512265] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  544.512686] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  544.515172] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  544.515823] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  544.515895] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  544.516006] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  544.516075] [drm:hsw_audio_config_update [i915]] using automatic N
>[  544.532910] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  544.532967] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  544.533174] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  544.533387] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  544.533441] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  544.533633] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  544.534072] Console: switching to colour frame buffer device 240x67
>[  544.764060] Console: switching to colour dummy device 80x25
>[  544.764297] [IGT] kms_pipe_crc_basic: executing
>[  544.782517] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  544.782573] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  544.782617] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  544.782656] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  544.782777] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  544.782821] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  544.783377] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  544.784142] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  544.784157] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  544.784162] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  544.784201] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  544.784254] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  544.784835] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  544.785222] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  544.785262] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  544.785311] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  544.794003] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.802820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.811602] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.820523] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.829383] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.838298] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.847210] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.856138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.865050] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.874014] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.883016] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.892016] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.901009] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.909989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.918965] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.927966] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.936949] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.945936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.954918] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.963896] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.972887] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.981865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.990839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  544.999890] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.008874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.017851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.026902] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.035890] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.044888] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.053860] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.062843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.071875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.071922] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  545.071938] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  545.072013] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  545.072119] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  545.153387] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  545.157569] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  545.157685] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  545.157820] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  545.158477] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  545.158487] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  545.158495] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  545.158502] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  545.158983] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  545.158999] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  545.159009] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  545.159019] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  545.159028] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  545.159037] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  545.159047] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  545.159057] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  545.159069] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  545.159082] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  545.159092] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  545.159101] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  545.159111] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  545.159120] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  545.159130] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  545.159140] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  545.159149] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  545.159166] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  545.159176] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  545.159185] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  545.159194] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  545.159203] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  545.159212] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  545.159223] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  545.175078] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  545.175125] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  545.175166] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  545.175201] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  545.175233] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  545.175267] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  545.175811] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  545.176277] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  545.176289] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  545.176294] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  545.176820] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  545.176866] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  545.177388] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  545.177753] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  545.178144] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  545.178187] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  545.186889] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.195589] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.204303] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.213052] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.221801] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.230620] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.239584] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.248614] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.257617] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.266692] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.275725] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.284823] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.293869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.302839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.311856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.320837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.329860] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.338839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.347874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.356858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.365830] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.374857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.383817] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.392834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.401843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.410870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.419839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.428852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.437824] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.446847] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.455850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.464866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  545.464911] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  545.464927] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  545.466191] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  545.466309] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  545.546559] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  545.550813] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  545.550927] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  545.550940] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  545.551593] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  545.551603] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  545.551612] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  545.551618] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  545.552098] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  545.552111] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  545.552121] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  545.552131] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  545.552140] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  545.552150] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  545.552160] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  545.552169] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  545.552186] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  545.552196] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  545.552205] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  545.552215] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  545.552224] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  545.552233] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  545.552243] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  545.552252] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  545.552265] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  545.552275] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  545.552287] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  545.552296] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  545.552306] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  545.552315] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  545.552324] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  545.552334] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  545.554188] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-A-frame-sequence
>[  545.555984] [drm:drm_mode_addfb2] [FB:89]
>[  545.573363] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  545.573384] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  545.594949] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  545.595126] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  545.595190] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  545.595243] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  545.595451] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  545.796926] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  545.797042] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  545.812205] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  545.812306] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  545.812414] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  545.863975] [drm:wait_panel_status [i915]] Wait complete
>[  545.864095] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  545.864215] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  545.864421] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  545.864561] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  545.864683] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  545.864765] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  545.864873] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  545.864972] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  545.865189] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  545.865371] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  545.866924] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  545.867128] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  545.867358] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  545.870808] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  545.870881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  545.870949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  545.871028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  545.871096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  545.871164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  545.871231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  545.871306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  545.871374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  545.871442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  545.871509] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  545.871584] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  545.871656] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  545.871795] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  545.871923] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  545.871992] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  545.872291] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  545.872362] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  546.316891] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  546.403159] [drm:wait_panel_status [i915]] Wait complete
>[  546.403274] [drm:edp_panel_on [i915]] Wait for panel power on
>[  546.403390] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  546.511748] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  546.511855] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  546.511955] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  546.512150] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  546.605243] [drm:wait_panel_status [i915]] Wait complete
>[  546.605385] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  546.605505] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  546.607229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  546.607327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  546.607431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  546.608621] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  546.608722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  546.610198] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  546.610518] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  546.612264] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  546.612369] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  546.612434] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  546.612507] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  546.612596] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  546.612660] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  546.612810] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  546.612882] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  546.646062] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  546.646180] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  546.646487] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  546.646667] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  546.647057] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  546.647182] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  546.647316] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  546.648101] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  546.713132] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  546.713470] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  546.916901] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  546.917060] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  546.930234] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  546.930348] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  546.930467] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  546.982143] [drm:wait_panel_status [i915]] Wait complete
>[  546.982261] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  546.982380] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  546.982587] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  546.982827] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  546.982938] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  546.983049] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  546.983349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  546.983470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  546.983578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  546.983685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  546.983840] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  546.983943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  546.984055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  546.984165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  546.984277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  546.984383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  546.984491] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  546.984616] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  546.984823] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  546.984940] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  546.985090] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  546.985241] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  546.985378] [drm:intel_power_well_disable [i915]] disabling DC off
>[  546.985484] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  546.985577] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  546.986281] [drm:intel_power_well_disable [i915]] disabling always-on
>[  546.990461] [drm:drm_mode_addfb2] [FB:89]
>[  547.015309] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  547.015330] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  547.015446] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  547.015480] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  547.015519] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  547.015559] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  547.015591] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  547.015626] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  547.015662] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  547.016050] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  547.016085] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  547.016119] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  547.016151] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  547.016158] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  547.016190] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  547.016195] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  547.016228] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  547.016262] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  547.016297] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  547.016333] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  547.016367] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  547.016405] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  547.016439] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  547.016475] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  547.016509] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  547.016543] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  547.016577] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  547.016614] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  547.016657] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  547.017074] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  547.017449] [drm:intel_power_well_enable [i915]] enabling always-on
>[  547.017478] [drm:intel_power_well_enable [i915]] enabling DC off
>[  547.017995] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  547.018386] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  547.018511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  547.018547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  547.018585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  547.018620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  547.018655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  547.018954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  547.018991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  547.019026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  547.019060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  547.019094] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  547.019131] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  547.019170] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  547.019237] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  547.019271] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  547.019472] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  547.019507] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  547.436934] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  547.503174] [drm:wait_panel_status [i915]] Wait complete
>[  547.503235] [drm:edp_panel_on [i915]] Wait for panel power on
>[  547.503301] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  547.611725] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  547.611820] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  547.611911] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  547.612067] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  547.704417] [drm:wait_panel_status [i915]] Wait complete
>[  547.704562] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  547.704681] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  547.706565] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  547.706666] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  547.706928] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  547.708208] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  547.708316] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  547.709897] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  547.710311] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  547.713005] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  547.713159] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  547.713255] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  547.713363] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  547.713494] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  547.713590] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  547.713721] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  547.713922] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  547.730128] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  547.730233] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  547.730518] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  547.813880] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  547.814224] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  548.020874] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  548.021035] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  548.031924] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  548.032037] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  548.032156] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  548.083722] [drm:wait_panel_status [i915]] Wait complete
>[  548.083925] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  548.084044] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  548.084250] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  548.084452] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  548.084552] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  548.084651] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  548.084828] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  548.085167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  548.085288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  548.085397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  548.085504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  548.085605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  548.085711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  548.085884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  548.085990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  548.086096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  548.086200] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  548.086326] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  548.086440] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  548.086554] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  548.086703] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  548.087111] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  548.087250] [drm:intel_power_well_disable [i915]] disabling DC off
>[  548.087356] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  548.087450] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  548.088151] [drm:intel_power_well_disable [i915]] disabling always-on
>[  548.092309] [drm:drm_mode_addfb2] [FB:89]
>[  548.111342] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  548.111364] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  548.111495] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  548.111534] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  548.111576] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  548.111612] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  548.111652] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  548.111737] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  548.111780] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  548.111820] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  548.111860] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  548.111870] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  548.111907] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  548.111915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  548.111956] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  548.111997] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  548.112040] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  548.112080] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  548.112121] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  548.112166] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  548.112207] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  548.112247] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  548.112289] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  548.112329] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  548.112371] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  548.112432] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  548.112485] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  548.112527] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  548.112950] [drm:intel_power_well_enable [i915]] enabling always-on
>[  548.112984] [drm:intel_power_well_enable [i915]] enabling DC off
>[  548.113270] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  548.113327] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  548.113365] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  548.113422] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  548.113752] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  548.117992] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  548.118067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  548.118105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  548.118144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  548.118179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  548.118214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  548.118249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  548.118284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  548.118319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  548.118353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  548.118388] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  548.118424] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  548.118460] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  548.118526] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  548.118560] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  548.118863] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  548.119858] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  548.120391] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  548.120426] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  548.120477] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  548.120509] [drm:hsw_audio_config_update [i915]] using automatic N
>[  548.120599] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  548.120633] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  548.137481] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  548.137555] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  548.137843] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  548.221005] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  548.221187] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  548.221262] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  548.221392] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  548.239286] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  548.239381] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  548.239542] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  548.239869] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  548.244173] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  548.244267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  548.244364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  548.244464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  548.244555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  548.244645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  548.244855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  548.244959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  548.245050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  548.245140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  548.245230] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  548.245335] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  548.245434] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  548.245532] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  548.245663] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  548.245837] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  548.245965] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  548.246101] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  548.246221] [drm:intel_power_well_disable [i915]] disabling DC off
>[  548.246313] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  548.246393] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  548.247071] [drm:intel_power_well_disable [i915]] disabling always-on
>[  548.250976] [drm:drm_mode_addfb2] [FB:89]
>[  548.278321] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  548.278341] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  548.278460] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  548.278493] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  548.278530] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  548.278562] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  548.278599] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  548.278633] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  548.278817] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  548.278850] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  548.278883] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  548.278888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  548.278920] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  548.278927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  548.278960] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  548.278994] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  548.279030] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  548.279064] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  548.279098] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  548.279135] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  548.279170] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  548.279205] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  548.279240] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  548.279276] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  548.279311] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  548.279365] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  548.279414] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  548.279449] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  548.279948] [drm:intel_power_well_enable [i915]] enabling always-on
>[  548.279976] [drm:intel_power_well_enable [i915]] enabling DC off
>[  548.280260] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  548.280309] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  548.280341] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  548.280392] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  548.280645] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  548.284995] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  548.285071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  548.285109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  548.285148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  548.285183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  548.285218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  548.285253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  548.285288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  548.285323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  548.285357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  548.285392] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  548.285428] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  548.285464] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  548.285530] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  548.285563] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  548.285988] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  548.287028] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  548.287561] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  548.287596] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  548.287647] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  548.287773] [drm:hsw_audio_config_update [i915]] using automatic N
>[  548.288135] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  548.288171] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  548.304632] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  548.304759] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  548.304961] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  548.388132] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  548.388308] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  548.388378] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  548.388500] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  548.406276] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  548.406370] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  548.406530] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  548.406852] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  548.411126] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  548.411210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  548.411298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  548.411389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  548.411471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  548.411552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  548.411633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  548.411827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  548.411911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  548.411998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  548.412083] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  548.412178] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  548.412266] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  548.412354] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  548.412476] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  548.412561] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  548.412677] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  548.412866] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  548.412978] [drm:intel_power_well_disable [i915]] disabling DC off
>[  548.413059] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  548.413130] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  548.414336] [drm:intel_power_well_disable [i915]] disabling always-on
>[  548.417069] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  548.441611] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  548.441645] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  548.441727] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  548.441766] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  548.441797] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  548.441834] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  548.441869] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  548.441903] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  548.441936] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  548.441968] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  548.442000] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  548.442007] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  548.442039] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  548.442042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  548.442075] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  548.442107] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  548.442140] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  548.442172] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  548.442204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  548.442242] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  548.442273] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  548.442309] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  548.442343] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  548.442377] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  548.442411] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  548.442452] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  548.442487] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  548.442522] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  548.442554] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  548.442588] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  548.442622] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  548.442654] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  548.442722] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  548.442753] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  548.442757] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  548.442788] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  548.442792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  548.442825] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  548.442857] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  548.442891] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  548.442923] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  548.442954] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  548.442988] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  548.443020] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  548.443054] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  548.443088] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  548.443121] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  548.443155] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  548.443192] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  548.443236] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  548.443271] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  548.443309] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  548.443342] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  548.443494] [drm:intel_power_well_enable [i915]] enabling always-on
>[  548.443522] [drm:intel_power_well_enable [i915]] enabling DC off
>[  548.443872] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  548.443926] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  548.444067] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  548.444101] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  548.444156] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  548.444324] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  548.447755] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  548.447803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  548.447852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  548.447907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  548.447956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  548.448004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  548.448052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  548.448100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  548.448148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  548.448196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  548.448244] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  548.448297] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  548.448348] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  548.448434] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  548.448480] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  548.448844] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  548.448893] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  548.540920] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  548.601656] [drm:wait_panel_status [i915]] Wait complete
>[  548.601798] [drm:edp_panel_on [i915]] Wait for panel power on
>[  548.601886] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  548.710293] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  548.710357] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  548.710418] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  548.710535] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  548.803273] [drm:wait_panel_status [i915]] Wait complete
>[  548.803363] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  548.803442] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  548.804990] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  548.805050] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  548.805116] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  548.806100] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  548.806160] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  548.807446] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  548.807778] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  548.809896] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  548.810020] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  548.810080] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  548.810148] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  548.810235] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  548.810293] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  548.810378] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  548.810439] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  548.810753] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  548.810814] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  548.811190] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  548.813296] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  548.813943] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  548.814005] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  548.814099] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  548.814158] [drm:hsw_audio_config_update [i915]] using automatic N
>[  548.831025] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  548.831109] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  548.831376] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  548.831665] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  548.831817] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  548.832066] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  548.832681] Console: switching to colour frame buffer device 240x67
>[  549.060224] Console: switching to colour dummy device 80x25
>[  549.060448] [IGT] kms_pipe_crc_basic: executing
>[  549.086389] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  549.086456] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  549.086515] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  549.086570] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  549.086622] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  549.086674] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  549.087380] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  549.088005] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  549.088023] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  549.088030] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  549.088076] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  549.088138] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  549.088956] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  549.089389] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  549.089432] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  549.089489] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  549.098191] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.107015] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.115838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.124650] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.133522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.142417] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.151344] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.160306] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.169302] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.178585] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.187851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.196871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.205843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.214879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.223839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.232855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.241910] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.250887] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.259873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.268856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.277834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.286898] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.295878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.304853] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.313821] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.322881] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.331866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.340861] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.349848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.358822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.367877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.376856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.376903] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  549.376918] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  549.376992] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  549.377099] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  549.458349] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  549.462531] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  549.462646] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  549.462787] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  549.463457] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  549.463466] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  549.463475] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  549.463481] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  549.463974] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  549.463988] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  549.463998] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  549.464008] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  549.464017] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  549.464027] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  549.464040] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  549.464052] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  549.464062] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  549.464071] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  549.464081] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  549.464090] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  549.464100] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  549.464109] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  549.464121] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  549.464130] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  549.464140] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  549.464153] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  549.464162] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  549.464171] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  549.464180] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  549.464190] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  549.464202] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  549.464211] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  549.477233] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  549.477279] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  549.477319] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  549.477354] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  549.477386] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  549.477420] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  549.478029] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  549.478477] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  549.478489] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  549.478493] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  549.479029] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  549.479077] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  549.479618] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  549.480064] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  549.480481] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  549.480525] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  549.489133] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.497747] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.506373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.514990] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.523603] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.532293] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.541022] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.549778] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.558501] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.567236] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.575967] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.584690] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.593479] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.602206] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.610928] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.619674] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.628483] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.637208] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.646029] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.654857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.663778] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.672593] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.681628] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.690673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.699578] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.708550] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.717554] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.726477] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.735401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.744370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.753364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.762350] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  549.762397] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  549.762413] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  549.764047] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  549.764164] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  549.844523] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  549.848783] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  549.848901] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  549.848914] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  549.849586] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  549.849595] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  549.849604] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  549.849610] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  549.850108] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  549.850122] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  549.850135] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  549.850145] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  549.850158] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  549.850167] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  549.850177] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  549.850186] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  549.850196] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  549.850205] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  549.850218] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  549.850227] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  549.850237] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  549.850250] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  549.850259] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  549.850268] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  549.850278] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  549.850287] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  549.850299] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  549.850308] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  549.850318] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  549.850327] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  549.850336] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  549.850349] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  549.852094] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-B
>[  549.853585] [drm:drm_mode_addfb2] [FB:70]
>[  549.873867] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  549.873974] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  549.874161] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  550.076850] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  550.076950] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  550.095973] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  550.096042] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  550.096107] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  550.147467] [drm:wait_panel_status [i915]] Wait complete
>[  550.147547] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  550.147629] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  550.148026] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  550.148221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  550.148314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  550.148403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  550.148470] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  550.148551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  550.148633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  550.148711] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  550.148797] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  550.148967] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  550.149056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  550.149137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  550.149216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  550.149296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  550.149380] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  550.149478] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  550.149566] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  550.149657] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  550.164240] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  550.164364] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  550.165093] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  550.165137] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  550.165377] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  550.165457] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  550.165542] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  550.165632] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  550.165967] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  550.166053] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  550.166137] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  550.166219] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  550.166301] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  550.166381] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  550.166462] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  550.166476] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  550.166555] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  550.166567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  550.166646] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  550.167014] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  550.167104] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  550.167197] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  550.167287] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  550.167383] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  550.167472] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  550.167569] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  550.167661] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  550.167983] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  550.168073] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  550.168166] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  550.168297] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  550.168402] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  550.168494] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  550.169384] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  550.169614] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  550.169984] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  550.170879] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  550.180928] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  550.181050] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  550.181109] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  550.185339] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  550.185387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  550.185433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  550.185485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  550.185532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  550.185578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  550.185624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  550.185674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  550.186005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  550.186080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  550.186156] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  550.186244] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  550.186327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  550.186407] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  550.186529] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  550.186605] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  550.187141] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  550.187220] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  550.604934] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  550.703029] [drm:wait_panel_status [i915]] Wait complete
>[  550.703128] [drm:edp_panel_on [i915]] Wait for panel power on
>[  550.703233] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  550.811625] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  550.811722] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  550.811813] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  550.812017] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  550.904821] [drm:wait_panel_status [i915]] Wait complete
>[  550.904964] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  550.905085] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  550.906918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  550.907019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  550.907124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  550.908420] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  550.908522] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  550.910195] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  550.910612] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  550.913186] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  550.913339] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  550.913435] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  550.913543] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  550.913674] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  550.913871] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  550.930187] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  550.930411] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  550.930535] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  550.930927] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  550.946828] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  551.014054] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  551.014387] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  551.220887] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  551.221045] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  551.231945] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  551.232061] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  551.232180] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  551.283973] [drm:wait_panel_status [i915]] Wait complete
>[  551.284109] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  551.284315] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  551.284453] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  551.284553] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  551.284652] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  551.284859] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  551.285033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  551.285154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  551.285268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  551.285372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  551.285475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  551.285578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  551.285689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  551.285858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  551.285967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  551.286072] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  551.286195] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  551.286310] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  551.286424] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  551.286575] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  551.286817] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  551.286929] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  551.287076] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  551.287189] [drm:intel_power_well_disable [i915]] disabling DC off
>[  551.287294] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  551.287386] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  551.288091] [drm:intel_power_well_disable [i915]] disabling always-on
>[  551.292129] [drm:drm_mode_addfb2] [FB:70]
>[  551.311971] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  551.311991] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  551.312107] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  551.312142] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  551.312183] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  551.312225] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  551.312258] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  551.312294] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  551.312332] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  551.312368] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  551.312403] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  551.312437] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  551.312470] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  551.312475] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  551.312509] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  551.312512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  551.312547] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  551.312580] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  551.312615] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  551.312649] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  551.313138] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  551.313177] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  551.313210] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  551.313247] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  551.313282] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  551.313317] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  551.313352] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  551.313392] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  551.313438] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  551.313475] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  551.314185] [drm:intel_power_well_enable [i915]] enabling always-on
>[  551.314217] [drm:intel_power_well_enable [i915]] enabling DC off
>[  551.314501] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  551.314552] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  551.314587] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  551.314644] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  551.315067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  551.315103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  551.315142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  551.315179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  551.315215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  551.315252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  551.315290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  551.315326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  551.315362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  551.315398] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  551.315437] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  551.315474] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  551.315542] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  551.315578] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  551.316145] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  551.316186] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  551.740854] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  551.801427] [drm:wait_panel_status [i915]] Wait complete
>[  551.801518] [drm:edp_panel_on [i915]] Wait for panel power on
>[  551.801613] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  551.910018] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  551.910098] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  551.910171] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  551.910331] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  552.002366] [drm:wait_panel_status [i915]] Wait complete
>[  552.002493] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  552.002601] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  552.004510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  552.004598] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  552.004691] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  552.006148] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  552.006240] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  552.007843] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  552.008231] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  552.010942] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  552.011092] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  552.011179] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  552.011276] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  552.011394] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  552.011481] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  552.028114] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  552.028220] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  552.028505] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  552.111688] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  552.112143] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  552.316887] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  552.317045] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  552.329995] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  552.330112] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  552.330231] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  552.381917] [drm:wait_panel_status [i915]] Wait complete
>[  552.382046] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  552.382252] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  552.382451] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  552.382552] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  552.382651] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  552.382860] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  552.382968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  552.383098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  552.383208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  552.383319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  552.383427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  552.383537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  552.383645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  552.383834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  552.383934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  552.384040] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  552.384157] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  552.384269] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  552.384396] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  552.384556] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  552.384700] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  552.384881] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  552.385034] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  552.385147] [drm:intel_power_well_disable [i915]] disabling DC off
>[  552.385251] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  552.385342] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  552.386028] [drm:intel_power_well_disable [i915]] disabling always-on
>[  552.390291] [drm:drm_mode_addfb2] [FB:70]
>[  552.410058] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  552.410080] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  552.410197] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  552.410232] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  552.410271] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  552.410305] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  552.410342] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  552.410378] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  552.410414] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  552.410448] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  552.410481] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  552.410487] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  552.410520] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  552.410524] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  552.410558] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  552.410592] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  552.410627] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  552.410662] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  552.411482] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  552.411520] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  552.411554] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  552.411591] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  552.411626] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  552.411662] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  552.412019] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  552.412076] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  552.412124] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  552.412159] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  552.412523] [drm:intel_power_well_enable [i915]] enabling always-on
>[  552.412553] [drm:intel_power_well_enable [i915]] enabling DC off
>[  552.413184] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  552.413486] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  552.413521] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  552.413576] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  552.414066] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  552.418196] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  552.418232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  552.418270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  552.418309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  552.418344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  552.418379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  552.418414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  552.418450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  552.418485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  552.418519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  552.418554] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  552.418590] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  552.418626] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  552.419265] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  552.419299] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  552.419556] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  552.420739] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  552.421272] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  552.421307] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  552.421358] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  552.421390] [drm:hsw_audio_config_update [i915]] using automatic N
>[  552.438356] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  552.438426] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  552.438630] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  552.522088] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  552.522331] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  552.522434] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  552.522609] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  552.539086] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  552.539227] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  552.539376] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  552.543628] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  552.543811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  552.543906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  552.543998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  552.544084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  552.544166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  552.544250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  552.544343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  552.544426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  552.544510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  552.544592] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  552.544689] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  552.544836] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  552.544926] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  552.545059] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  552.545145] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  552.545260] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  552.545379] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  552.545468] [drm:intel_power_well_disable [i915]] disabling DC off
>[  552.545553] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  552.545627] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  552.546228] [drm:intel_power_well_disable [i915]] disabling always-on
>[  552.549823] [drm:drm_mode_addfb2] [FB:70]
>[  552.570820] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  552.570842] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  552.570962] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  552.570999] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  552.571039] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  552.571074] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  552.571113] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  552.571151] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  552.571189] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  552.571224] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  552.571259] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  552.571265] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  552.571300] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  552.571304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  552.571340] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  552.571375] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  552.571411] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  552.571448] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  552.571483] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  552.571524] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  552.571559] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  552.571598] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  552.571634] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  552.571795] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  552.571830] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  552.571879] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  552.571926] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  552.571960] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  552.572326] [drm:intel_power_well_enable [i915]] enabling always-on
>[  552.572356] [drm:intel_power_well_enable [i915]] enabling DC off
>[  552.572640] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  552.572729] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  552.572766] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  552.572819] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  552.573059] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  552.577308] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  552.577376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  552.577416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  552.577455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  552.577491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  552.577526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  552.577561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  552.577596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  552.577631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  552.577757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  552.577792] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  552.577832] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  552.577869] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  552.577938] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  552.577972] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  552.578227] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  552.579232] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  552.579798] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  552.579835] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  552.579887] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  552.579921] [drm:hsw_audio_config_update [i915]] using automatic N
>[  552.596901] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  552.596978] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  552.597190] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  552.680453] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  552.680679] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  552.680945] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  552.681127] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  552.697082] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  552.697269] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  552.697486] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  552.701783] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  552.701881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  552.701980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  552.702080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  552.702171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  552.702260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  552.702350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  552.702449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  552.702538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  552.702628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  552.702717] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  552.702970] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  552.703068] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  552.703169] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  552.703307] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  552.703400] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  552.703529] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  552.703662] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  552.703847] [drm:intel_power_well_disable [i915]] disabling DC off
>[  552.703939] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  552.704024] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  552.704629] [drm:intel_power_well_disable [i915]] disabling always-on
>[  552.707508] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  552.741993] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  552.742047] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  552.742104] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  552.742164] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  552.742215] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  552.742269] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  552.742324] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  552.742377] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  552.742430] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  552.742481] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  552.742532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  552.742541] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  552.742592] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  552.742597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  552.742650] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  552.742742] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  552.742795] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  552.742847] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  552.742898] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  552.742956] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  552.743007] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  552.743061] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  552.743115] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  552.743168] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  552.743221] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  552.743285] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  552.743337] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  552.743395] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  552.743445] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  552.743498] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  552.743552] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  552.743603] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  552.743654] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  552.743733] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  552.743738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  552.743789] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  552.743794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  552.743847] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  552.743898] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  552.743950] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  552.744001] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  552.744052] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  552.744106] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  552.744157] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  552.744210] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  552.744263] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  552.744316] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  552.744369] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  552.744424] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  552.744489] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  552.744544] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  552.744605] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  552.744657] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  552.744916] [drm:intel_power_well_enable [i915]] enabling always-on
>[  552.744960] [drm:intel_power_well_enable [i915]] enabling DC off
>[  552.745263] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  552.745343] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  552.745497] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  552.745548] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  552.745632] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  552.745912] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  552.749787] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  552.749842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  552.749896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  552.749959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  552.750013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  552.750067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  552.750122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  552.750176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  552.750230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  552.750284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  552.750338] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  552.750396] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  552.750453] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  552.750548] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  552.750601] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  552.750919] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  552.750976] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  552.836870] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  552.901540] [drm:wait_panel_status [i915]] Wait complete
>[  552.901619] [drm:edp_panel_on [i915]] Wait for panel power on
>[  552.901766] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  553.010112] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  553.010187] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  553.010259] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  553.010401] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  553.102357] [drm:wait_panel_status [i915]] Wait complete
>[  553.102466] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  553.102556] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  553.104338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  553.104424] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  553.104517] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  553.105681] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  553.105822] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  553.107292] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  553.107707] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  553.110708] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  553.110896] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  553.110984] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  553.111081] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  553.111204] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  553.111289] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  553.111409] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  553.111496] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  553.111905] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  553.111992] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  553.112487] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  553.115153] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  553.115701] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  553.115736] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  553.115790] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  553.115822] [drm:hsw_audio_config_update [i915]] using automatic N
>[  553.132847] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  553.132924] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  553.133174] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  553.133445] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  553.133522] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  553.133795] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  553.134350] Console: switching to colour frame buffer device 240x67
>[  553.383612] Console: switching to colour dummy device 80x25
>[  553.383933] [IGT] kms_pipe_crc_basic: executing
>[  553.409165] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  553.409212] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  553.409251] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  553.409287] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  553.409319] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  553.409353] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  553.409998] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  553.410539] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  553.410557] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  553.410563] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  553.410610] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  553.410673] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  553.411359] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  553.411795] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  553.411844] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  553.411904] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  553.420616] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.429467] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.438167] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.446887] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.455698] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.464572] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.473395] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.482298] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.491212] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.500319] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.509312] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.518328] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.527316] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.536360] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.545339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.554325] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.563311] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.572372] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.581338] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.590305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.599357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.608334] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.617314] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.626319] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.635352] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.644333] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.653321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.662310] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.671370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.680368] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.689341] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.698311] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.698357] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  553.698373] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  553.698450] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  553.698558] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  553.779893] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  553.784074] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  553.784188] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  553.784200] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  553.784987] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  553.784997] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  553.785006] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  553.785016] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  553.785397] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  553.785410] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  553.785420] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  553.785429] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  553.785439] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  553.785452] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  553.785461] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  553.785471] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  553.785480] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  553.785490] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  553.785499] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  553.785509] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  553.785518] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  553.785528] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  553.785537] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  553.785550] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  553.785559] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  553.785568] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  553.785578] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  553.785587] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  553.785596] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  553.785606] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  553.785615] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  553.785624] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  553.800250] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  553.800297] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  553.800338] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  553.800372] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  553.800405] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  553.800439] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  553.801038] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  553.801491] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  553.801501] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  553.801506] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  553.802029] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  553.802075] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  553.802605] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  553.802993] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  553.803383] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  553.803427] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  553.812070] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.820799] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.829513] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.838221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.846933] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.855782] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.864616] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.873575] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.882435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.891332] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.900288] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.909250] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.918227] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.927210] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.936198] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.945169] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.954161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.963132] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.972106] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.981089] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.990086] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  553.999075] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  554.008095] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  554.017070] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  554.026088] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  554.035066] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  554.044094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  554.053064] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  554.062084] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  554.071098] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  554.080088] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  554.089072] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  554.089117] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  554.089132] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  554.090442] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  554.090560] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  554.171801] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  554.175984] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  554.176100] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  554.176112] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  554.176892] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  554.176903] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  554.176912] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  554.176918] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  554.177310] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  554.177323] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  554.177333] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  554.177343] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  554.177352] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  554.177365] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  554.177375] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  554.177384] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  554.177394] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  554.177403] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  554.177416] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  554.177426] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  554.177435] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  554.177449] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  554.177458] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  554.177467] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  554.177477] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  554.177486] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  554.177495] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  554.177510] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  554.177519] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  554.177532] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  554.177542] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  554.177551] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  554.179337] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-B-frame-sequence
>[  554.181228] [drm:drm_mode_addfb2] [FB:71]
>[  554.201229] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  554.201335] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  554.201527] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  554.404851] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  554.404938] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  554.411520] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  554.411580] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  554.411644] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  554.463427] [drm:wait_panel_status [i915]] Wait complete
>[  554.463490] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  554.463556] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  554.463840] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  554.464021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  554.464095] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  554.464169] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  554.464247] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  554.464359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  554.464447] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  554.464528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  554.464607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  554.464680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  554.464817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  554.464894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  554.464974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  554.465053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  554.465133] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  554.465223] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  554.465305] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  554.465393] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  554.465982] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  554.466094] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  554.466598] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  554.466634] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  554.466942] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  554.467019] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  554.467095] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  554.467180] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  554.467253] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  554.467329] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  554.467403] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  554.467474] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  554.467546] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  554.467618] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  554.467688] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  554.467778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  554.467860] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  554.467875] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  554.467938] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  554.468002] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  554.468070] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  554.468133] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  554.468200] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  554.468271] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  554.468337] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  554.468404] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  554.468473] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  554.468540] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  554.468610] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  554.468674] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  554.468798] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  554.468877] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  554.468942] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  554.469451] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  554.469620] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  554.469792] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  554.469933] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  554.484398] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  554.484533] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  554.484603] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  554.488854] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  554.488931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  554.489006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  554.489089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  554.489163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  554.489237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  554.489310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  554.489391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  554.489465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  554.489538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  554.489611] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  554.489693] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  554.489876] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  554.489964] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  554.490087] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  554.490162] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  554.490498] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  554.490576] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  554.916987] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  555.001810] [drm:wait_panel_status [i915]] Wait complete
>[  555.001920] [drm:edp_panel_on [i915]] Wait for panel power on
>[  555.002037] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  555.110440] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  555.110545] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  555.110644] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  555.110875] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  555.202597] [drm:wait_panel_status [i915]] Wait complete
>[  555.202871] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  555.203000] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  555.204703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  555.204891] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  555.204997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  555.206235] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  555.206338] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  555.207806] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  555.208112] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  555.209770] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  555.209868] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  555.209927] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  555.209995] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  555.210078] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  555.210137] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  555.226839] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  555.227063] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  555.227188] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  555.227476] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  555.243394] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  555.310516] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  555.311046] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  555.516884] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  555.517040] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  555.527936] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  555.528049] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  555.528168] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  555.579896] [drm:wait_panel_status [i915]] Wait complete
>[  555.580027] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  555.580232] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  555.580471] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  555.580572] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  555.580671] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  555.580853] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  555.581174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  555.581296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  555.581406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  555.581512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  555.581615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  555.581721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  555.581906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  555.582012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  555.582127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  555.582234] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  555.582357] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  555.582469] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  555.582583] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  555.582947] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  555.583093] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  555.583198] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  555.583350] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  555.583464] [drm:intel_power_well_disable [i915]] disabling DC off
>[  555.583570] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  555.583662] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  555.584374] [drm:intel_power_well_disable [i915]] disabling always-on
>[  555.588546] [drm:drm_mode_addfb2] [FB:71]
>[  555.607755] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  555.607776] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  555.607892] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  555.607925] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  555.607963] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  555.608002] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  555.608035] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  555.608072] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  555.608107] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  555.608141] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  555.608175] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  555.608207] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  555.608239] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  555.608245] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  555.608277] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  555.608280] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  555.608313] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  555.608345] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  555.608378] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  555.608411] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  555.608443] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  555.608480] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  555.608512] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  555.608548] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  555.608582] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  555.608616] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  555.608650] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  555.609938] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  555.609980] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  555.610013] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  555.610391] [drm:intel_power_well_enable [i915]] enabling always-on
>[  555.610420] [drm:intel_power_well_enable [i915]] enabling DC off
>[  555.611050] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  555.611348] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  555.611381] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  555.611433] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  555.611575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  555.611611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  555.611649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  555.612006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  555.612039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  555.612073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  555.612108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  555.612143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  555.612178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  555.612212] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  555.612250] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  555.612285] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  555.612353] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  555.612388] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  555.612583] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  555.612618] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  556.036858] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  556.102856] [drm:wait_panel_status [i915]] Wait complete
>[  556.102938] [drm:edp_panel_on [i915]] Wait for panel power on
>[  556.103024] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  556.211417] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  556.211496] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  556.211568] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  556.211801] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  556.303523] [drm:wait_panel_status [i915]] Wait complete
>[  556.303651] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  556.303883] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  556.305888] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  556.305980] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  556.306073] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  556.307713] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  556.307883] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  556.309659] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  556.310128] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  556.312872] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  556.313010] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  556.313095] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  556.313191] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  556.313312] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  556.313399] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  556.330054] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  556.330162] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  556.330449] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  556.413578] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  556.414113] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  556.620887] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  556.621043] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  556.631937] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  556.632052] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  556.632171] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  556.683842] [drm:wait_panel_status [i915]] Wait complete
>[  556.683973] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  556.684179] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  556.684424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  556.684524] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  556.684624] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  556.684723] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  556.684905] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  556.685290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  556.685400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  556.685508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  556.685607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  556.685713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  556.685903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  556.686006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  556.686119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  556.686225] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  556.686350] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  556.686466] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  556.686578] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  556.686930] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  556.687208] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  556.687312] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  556.687460] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  556.687576] [drm:intel_power_well_disable [i915]] disabling DC off
>[  556.687680] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  556.687866] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  556.688488] [drm:intel_power_well_disable [i915]] disabling always-on
>[  556.692926] [drm:drm_mode_addfb2] [FB:71]
>[  556.712021] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  556.712041] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  556.712156] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  556.712190] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  556.712227] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  556.712259] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  556.712295] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  556.712330] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  556.712365] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  556.712397] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  556.712429] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  556.712436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  556.712468] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  556.712472] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  556.712505] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  556.712537] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  556.712570] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  556.712603] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  556.712635] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  556.712722] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  556.712754] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  556.712789] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  556.712823] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  556.712858] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  556.712893] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  556.712944] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  556.712993] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  556.713029] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  556.713387] [drm:intel_power_well_enable [i915]] enabling always-on
>[  556.713417] [drm:intel_power_well_enable [i915]] enabling DC off
>[  556.713721] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  556.713772] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  556.713806] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  556.713862] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  556.714131] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  556.718368] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  556.718439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  556.718479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  556.718518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  556.718555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  556.718590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  556.718627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  556.718662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  556.718754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  556.718789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  556.718826] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  556.718866] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  556.718904] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  556.718975] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  556.719009] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  556.719262] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  556.720266] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  556.720836] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  556.720869] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  556.720921] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  556.720953] [drm:hsw_audio_config_update [i915]] using automatic N
>[  556.737910] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  556.737958] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  556.738124] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  556.821400] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  556.821575] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  556.821645] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  556.821891] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  556.837968] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  556.838108] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  556.838246] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  556.842469] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  556.842526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  556.842585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  556.842647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  556.842778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  556.842835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  556.842892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  556.842955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  556.843011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  556.843068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  556.843123] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  556.843189] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  556.843251] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  556.843312] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  556.843400] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  556.843457] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  556.843539] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  556.843624] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  556.843741] [drm:intel_power_well_disable [i915]] disabling DC off
>[  556.843804] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  556.843854] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  556.844468] [drm:intel_power_well_disable [i915]] disabling always-on
>[  556.847731] [drm:drm_mode_addfb2] [FB:71]
>[  556.868147] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  556.868168] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  556.868283] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  556.868316] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  556.868354] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  556.868386] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  556.868421] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  556.868456] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  556.868490] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  556.868522] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  556.868554] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  556.868561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  556.868593] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  556.868597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  556.868630] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  556.868662] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  556.868746] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  556.868789] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  556.868822] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  556.868862] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  556.868897] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  556.868933] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  556.868969] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  556.869004] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  556.869040] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  556.869092] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  556.869139] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  556.869173] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  556.869537] [drm:intel_power_well_enable [i915]] enabling always-on
>[  556.869567] [drm:intel_power_well_enable [i915]] enabling DC off
>[  556.869879] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  556.869929] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  556.869963] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  556.870018] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  556.870311] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  556.874547] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  556.874618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  556.874654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  556.874740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  556.874774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  556.874809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  556.874843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  556.874879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  556.874914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  556.874950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  556.874985] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  556.875024] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  556.875061] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  556.875129] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  556.875164] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  556.875416] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  556.876415] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  556.876982] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  556.877019] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  556.877071] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  556.877105] [drm:hsw_audio_config_update [i915]] using automatic N
>[  556.894081] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  556.894157] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  556.894369] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  556.977546] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  556.977889] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  556.977981] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  556.978131] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  556.994113] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  556.994287] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  556.994485] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  556.998786] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  556.998878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  556.998976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  556.999076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  556.999166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  556.999255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  556.999345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  556.999444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  556.999534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  556.999624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  556.999713] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  556.999938] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  557.000041] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  557.000146] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  557.000281] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  557.000375] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  557.000504] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  557.000637] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  557.000813] [drm:intel_power_well_disable [i915]] disabling DC off
>[  557.000906] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  557.000988] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  557.001596] [drm:intel_power_well_disable [i915]] disabling always-on
>[  557.004254] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  557.035991] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  557.036048] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  557.036106] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  557.036168] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  557.036220] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  557.036274] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  557.036329] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  557.036383] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  557.036435] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  557.036487] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  557.036537] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  557.036547] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  557.036598] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  557.036603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  557.036656] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  557.036747] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  557.036800] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  557.036851] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  557.036902] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  557.036960] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  557.037010] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  557.037065] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  557.037118] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  557.037171] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  557.037224] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  557.037289] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  557.037341] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  557.037398] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  557.037449] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  557.037502] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  557.037555] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  557.037606] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  557.037658] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  557.037736] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  557.037742] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  557.037793] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  557.037798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  557.037851] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  557.037904] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  557.037957] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  557.038008] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  557.038059] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  557.038115] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  557.038165] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  557.038219] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  557.038272] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  557.038325] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  557.038378] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  557.038434] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  557.038499] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  557.038553] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  557.038615] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  557.038667] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  557.038899] [drm:intel_power_well_enable [i915]] enabling always-on
>[  557.038943] [drm:intel_power_well_enable [i915]] enabling DC off
>[  557.039244] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  557.039325] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  557.039474] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  557.039525] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  557.039607] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  557.039847] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  557.043784] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  557.043840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  557.043894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  557.043956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  557.044011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  557.044066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  557.044120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  557.044174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  557.044228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  557.044282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  557.044336] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  557.044394] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  557.044451] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  557.044546] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  557.044598] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  557.044915] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  557.044970] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  557.140860] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  557.201418] [drm:wait_panel_status [i915]] Wait complete
>[  557.201472] [drm:edp_panel_on [i915]] Wait for panel power on
>[  557.201530] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  557.309988] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  557.310039] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  557.310086] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  557.310198] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  557.402376] [drm:wait_panel_status [i915]] Wait complete
>[  557.402448] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  557.402508] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  557.404077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  557.404137] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  557.404202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  557.405177] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  557.405236] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  557.406514] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  557.406847] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  557.408965] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  557.409086] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  557.409146] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  557.409214] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  557.409302] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  557.409360] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  557.409446] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  557.409506] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  557.409822] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  557.409883] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  557.410258] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  557.412363] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  557.413001] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  557.413063] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  557.413149] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  557.413181] [drm:hsw_audio_config_update [i915]] using automatic N
>[  557.430025] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  557.430107] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  557.430359] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  557.430629] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  557.430772] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  557.431008] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  557.431550] Console: switching to colour frame buffer device 240x67
>[  557.655866] Console: switching to colour dummy device 80x25
>[  557.656090] [IGT] kms_pipe_crc_basic: executing
>[  557.679205] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  557.679254] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  557.679292] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  557.679326] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  557.679359] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  557.679391] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  557.680095] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  557.680631] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  557.680675] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  557.680683] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  557.680728] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  557.680791] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  557.681396] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  557.681816] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  557.681861] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  557.681923] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  557.690592] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.699493] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.708276] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.717143] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.725997] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.734912] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.743819] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.752838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.761846] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.770862] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.779859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.788847] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.797836] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.806860] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.815840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.824858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.833849] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.842864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.851830] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.860850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.869835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.878869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.887865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.896879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.905851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.914850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.923846] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.932859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.941841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.950845] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.959853] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.968843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  557.968890] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  557.968904] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  557.968976] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  557.969081] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  558.050356] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  558.054537] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  558.054653] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  558.054779] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  558.055459] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  558.055469] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  558.055477] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  558.055484] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  558.055968] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  558.055981] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  558.055992] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  558.056002] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  558.056014] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  558.056024] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  558.056033] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  558.056043] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  558.056052] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  558.056065] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  558.056075] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  558.056084] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  558.056097] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  558.056106] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  558.056115] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  558.056125] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  558.056134] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  558.056143] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  558.056153] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  558.056166] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  558.056175] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  558.056185] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  558.056194] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  558.056207] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  558.068800] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  558.068849] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  558.068888] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  558.068923] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  558.068955] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  558.068989] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  558.069502] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  558.069991] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  558.070003] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  558.070008] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  558.070476] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  558.070523] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  558.071073] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  558.071453] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  558.071889] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  558.071931] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  558.080523] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.090317] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.098993] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.107636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.116287] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.124913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.133572] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.142285] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.150930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.159571] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.168239] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.176875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.185535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.194781] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.203587] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.212471] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.221229] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.229989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.238758] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.247535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.256310] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.265066] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.273851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.282615] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.291470] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.300235] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.309001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.317789] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.326540] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.335303] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.344078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.352891] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  558.352925] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  558.352935] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  558.353749] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  558.353821] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  558.433825] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  558.437976] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  558.438074] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  558.438081] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  558.438478] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  558.438483] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  558.438488] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  558.438492] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  558.438794] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  558.438802] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  558.438810] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  558.438817] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  558.438824] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  558.438831] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  558.438838] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  558.438845] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  558.438852] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  558.438859] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  558.438866] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  558.438873] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  558.438880] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  558.438887] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  558.438894] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  558.438900] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  558.438907] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  558.438914] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  558.438921] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  558.438927] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  558.438934] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  558.438941] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  558.438948] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  558.438954] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  558.440082] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-C
>[  558.441389] [drm:drm_mode_addfb2] [FB:89]
>[  558.459671] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  558.459780] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  558.459966] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  558.668839] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  558.668957] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  558.677660] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  558.677788] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  558.677857] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  558.729918] [drm:wait_panel_status [i915]] Wait complete
>[  558.730013] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  558.730111] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  558.730237] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  558.730317] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  558.730397] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  558.730566] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  558.730646] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  558.731017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  558.731122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  558.731226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  558.731318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  558.731412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  558.731504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  558.731597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  558.731689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  558.731831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  558.731922] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  558.732031] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  558.732135] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  558.732242] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  558.746671] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  558.746879] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  558.747486] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  558.748013] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  558.748334] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  558.748446] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  558.748633] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  558.763595] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  558.763941] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  558.764177] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  558.768475] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  558.768581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  558.768691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  558.769094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  558.769198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  558.769303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  558.769406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  558.769522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  558.769625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  558.769923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  558.770026] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  558.770148] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  558.770263] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  558.770372] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  558.770526] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  558.770631] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  558.771029] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  558.771176] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  558.771286] [drm:intel_power_well_disable [i915]] disabling DC off
>[  558.771387] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  558.771479] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  558.772699] [drm:intel_power_well_disable [i915]] disabling always-on
>[  558.774011] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  558.774062] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  558.774345] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  558.774447] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  558.774553] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  558.774665] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  558.775013] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  558.775093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  558.775169] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  558.775245] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  558.775318] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  558.775393] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  558.775465] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  558.775480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  558.775549] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  558.775560] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  558.775635] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  558.775923] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  558.775997] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  558.776073] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  558.776146] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  558.776226] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  558.776298] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  558.776374] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  558.776450] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  558.776527] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  558.776605] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  558.776691] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  558.776975] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  558.777547] [drm:intel_power_well_enable [i915]] enabling always-on
>[  558.777610] [drm:intel_power_well_enable [i915]] enabling DC off
>[  558.778073] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  558.778534] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  558.778579] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  558.778646] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  558.778876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  558.778913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  558.778952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  558.778988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  558.779024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  558.779059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  558.779097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  558.779132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  558.779168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  558.779203] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  558.779243] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  558.779283] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  558.779350] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  558.779384] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  558.779579] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  558.779615] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  559.180887] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  559.301542] [drm:wait_panel_status [i915]] Wait complete
>[  559.301631] [drm:edp_panel_on [i915]] Wait for panel power on
>[  559.301824] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  559.410114] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  559.410199] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  559.410280] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  559.410505] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  559.503832] [drm:wait_panel_status [i915]] Wait complete
>[  559.503960] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  559.504067] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  559.506007] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  559.506108] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  559.506214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  559.507464] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  559.507565] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  559.509191] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  559.509604] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  559.512271] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  559.512424] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  559.512520] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  559.512628] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  559.512858] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  559.512959] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  559.529396] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  559.529502] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  559.529898] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  559.613078] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  559.613416] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  559.820900] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  559.821057] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  559.829941] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  559.830056] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  559.830176] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  559.882009] [drm:wait_panel_status [i915]] Wait complete
>[  559.882140] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  559.882345] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  559.882451] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  559.882552] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  559.882650] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  559.882832] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  559.883237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  559.883361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  559.883471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  559.883579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  559.883681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  559.883848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  559.883969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  559.884073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  559.884184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  559.884292] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  559.884418] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  559.884528] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  559.884641] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  559.884999] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  559.885129] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  559.885223] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  559.885356] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  559.885454] [drm:intel_power_well_disable [i915]] disabling DC off
>[  559.885547] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  559.885630] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  559.886335] [drm:intel_power_well_disable [i915]] disabling always-on
>[  559.890075] [drm:drm_mode_addfb2] [FB:89]
>[  559.910029] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  559.910050] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  559.910165] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  559.910199] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  559.910237] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  559.910277] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  559.910309] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  559.910345] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  559.910380] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  559.910414] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  559.910448] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  559.910481] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  559.910512] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  559.910518] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  559.910550] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  559.910553] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  559.910586] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  559.910619] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  559.910652] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  559.910887] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  559.910920] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  559.910957] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  559.910989] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  559.911023] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  559.911056] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  559.911090] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  559.911125] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  559.911169] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  559.911204] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  559.911581] [drm:intel_power_well_enable [i915]] enabling always-on
>[  559.911610] [drm:intel_power_well_enable [i915]] enabling DC off
>[  559.912034] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  559.912518] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  559.912553] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  559.912607] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  559.912882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  559.912917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  559.912954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  559.912990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  559.913024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  559.913059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  559.913095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  559.913130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  559.913164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  559.913199] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  559.913237] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  559.913273] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  559.913341] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  559.913374] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  559.913568] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  559.913604] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  560.332868] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  560.402975] [drm:wait_panel_status [i915]] Wait complete
>[  560.403037] [drm:edp_panel_on [i915]] Wait for panel power on
>[  560.403101] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  560.511496] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  560.511555] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  560.511608] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  560.511820] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  560.604078] [drm:wait_panel_status [i915]] Wait complete
>[  560.604188] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  560.604278] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  560.605963] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  560.606052] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  560.606144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  560.607399] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  560.607488] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  560.609116] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  560.609499] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  560.612180] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  560.612335] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  560.612421] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  560.612517] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  560.612636] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  560.613233] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  560.629334] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  560.629440] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  560.629839] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  560.713068] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  560.713404] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  560.916904] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  560.917061] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  560.930025] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  560.930140] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  560.930259] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  560.982096] [drm:wait_panel_status [i915]] Wait complete
>[  560.982231] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  560.982437] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  560.982554] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  560.982654] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  560.982753] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  560.982937] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  560.983729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  560.983919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  560.984028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  560.984134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  560.984236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  560.984341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  560.984449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  560.984556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  560.984657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  560.984829] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  560.984948] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  560.985060] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  560.985173] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  560.985327] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  560.985472] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  560.985579] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  560.985725] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  560.985892] [drm:intel_power_well_disable [i915]] disabling DC off
>[  560.985998] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  560.986089] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  560.987663] [drm:intel_power_well_disable [i915]] disabling always-on
>[  560.991941] [drm:drm_mode_addfb2] [FB:89]
>[  561.011090] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  561.011111] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  561.011226] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  561.011261] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  561.011298] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  561.011330] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  561.011366] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  561.011400] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  561.011435] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  561.011467] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  561.011499] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  561.011507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  561.011538] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  561.011542] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  561.011575] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  561.011607] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  561.011640] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  561.012284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  561.012317] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  561.012356] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  561.012389] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  561.012426] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  561.012462] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  561.012496] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  561.012549] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  561.012596] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  561.012631] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  561.013297] [drm:intel_power_well_enable [i915]] enabling always-on
>[  561.013326] [drm:intel_power_well_enable [i915]] enabling DC off
>[  561.013610] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  561.013657] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  561.013877] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  561.013933] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  561.014193] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  561.017795] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  561.017831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  561.017870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  561.017909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  561.017944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  561.017979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  561.018014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  561.018049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  561.018084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  561.018119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  561.018153] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  561.018190] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  561.018225] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  561.018292] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  561.018326] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  561.018613] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  561.020241] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  561.020875] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  561.020918] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  561.020976] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  561.021013] [drm:hsw_audio_config_update [i915]] using automatic N
>[  561.037922] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  561.037996] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  561.038205] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  561.121435] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  561.121610] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  561.121680] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  561.121927] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  561.137946] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  561.138112] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  561.138272] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  561.142504] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  561.142586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  561.142669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  561.142864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  561.142940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  561.143012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  561.143087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  561.143171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  561.143246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  561.143324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  561.143399] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  561.143488] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  561.143573] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  561.143653] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  561.143848] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  561.143927] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  561.144033] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  561.144145] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  561.144224] [drm:intel_power_well_disable [i915]] disabling DC off
>[  561.144301] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  561.144370] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  561.145014] [drm:intel_power_well_disable [i915]] disabling always-on
>[  561.148266] [drm:drm_mode_addfb2] [FB:89]
>[  561.169724] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  561.169745] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  561.169859] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  561.169893] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  561.169930] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  561.169962] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  561.169998] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  561.170033] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  561.170067] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  561.170099] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  561.170131] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  561.170136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  561.170168] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  561.170172] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  561.170205] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  561.170237] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  561.170270] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  561.170302] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  561.170334] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  561.170373] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  561.170405] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  561.170440] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  561.170475] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  561.170509] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  561.170556] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  561.170606] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  561.170640] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  561.171047] [drm:intel_power_well_enable [i915]] enabling always-on
>[  561.171076] [drm:intel_power_well_enable [i915]] enabling DC off
>[  561.171358] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  561.171407] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  561.171441] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  561.171497] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  561.171834] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  561.175835] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  561.175878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  561.175923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  561.175967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  561.176007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  561.176047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  561.176086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  561.176126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  561.176166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  561.176205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  561.176245] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  561.176286] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  561.176327] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  561.176398] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  561.176438] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  561.176753] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  561.177883] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  561.178425] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  561.178465] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  561.178523] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  561.178559] [drm:hsw_audio_config_update [i915]] using automatic N
>[  561.195494] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  561.195570] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  561.196166] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  561.279111] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  561.279322] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  561.279409] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  561.279550] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  561.297193] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  561.297381] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  561.297574] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  561.301878] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  561.301974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  561.302074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  561.302175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  561.302266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  561.302356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  561.302446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  561.302546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  561.302636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  561.302880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  561.302971] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  561.303080] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  561.303179] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  561.303277] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  561.303415] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  561.303509] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  561.303635] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  561.303829] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  561.303924] [drm:intel_power_well_disable [i915]] disabling DC off
>[  561.304021] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  561.304101] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  561.304702] [drm:intel_power_well_disable [i915]] disabling always-on
>[  561.307320] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  561.332813] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  561.332854] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  561.332899] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  561.332945] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  561.332983] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  561.333024] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  561.333067] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  561.333107] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  561.333147] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  561.333185] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  561.333223] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  561.333232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  561.333269] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  561.333274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  561.333313] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  561.333351] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  561.333391] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  561.333431] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  561.333469] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  561.333514] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  561.333551] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  561.333594] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  561.333634] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  561.333698] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  561.333736] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  561.333784] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  561.333824] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  561.333867] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  561.333905] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  561.333946] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  561.333986] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  561.334024] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  561.334063] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  561.334100] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  561.334105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  561.334143] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  561.334147] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  561.334186] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  561.334224] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  561.334264] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  561.334305] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  561.334343] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  561.334383] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  561.334421] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  561.334462] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  561.334502] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  561.334542] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  561.334582] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  561.334626] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  561.334776] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  561.334816] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  561.334863] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  561.334902] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  561.335053] [drm:intel_power_well_enable [i915]] enabling always-on
>[  561.335088] [drm:intel_power_well_enable [i915]] enabling DC off
>[  561.335377] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  561.335440] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  561.335600] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  561.335640] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  561.335744] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  561.335934] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  561.339774] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  561.339824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  561.339873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  561.339927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  561.339976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  561.340024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  561.340070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  561.340117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  561.340165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  561.340213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  561.340261] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  561.340312] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  561.340364] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  561.340452] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  561.340497] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  561.340780] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  561.340829] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  561.436903] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  561.503345] [drm:wait_panel_status [i915]] Wait complete
>[  561.503455] [drm:edp_panel_on [i915]] Wait for panel power on
>[  561.503572] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  561.611937] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  561.612042] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  561.612141] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  561.612314] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  561.703869] [drm:wait_panel_status [i915]] Wait complete
>[  561.703986] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  561.704085] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  561.705797] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  561.705875] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  561.705959] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  561.707121] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  561.707198] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  561.708602] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  561.709067] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  561.711800] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  561.711928] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  561.712006] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  561.712093] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  561.712203] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  561.712279] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  561.712386] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  561.712463] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  561.712847] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  561.712925] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  561.713384] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  561.715451] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  561.715999] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  561.716034] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  561.716088] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  561.716120] [drm:hsw_audio_config_update [i915]] using automatic N
>[  561.733092] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  561.733169] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  561.733422] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  561.733683] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  561.733812] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  561.734049] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  561.734593] Console: switching to colour frame buffer device 240x67
>[  561.961248] Console: switching to colour dummy device 80x25
>[  561.961473] [IGT] kms_pipe_crc_basic: executing
>[  561.985377] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  561.985440] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  561.985499] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  561.985550] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  561.985599] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  561.985647] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  561.986354] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  561.986921] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  561.986940] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  561.986947] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  561.986994] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  561.987058] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  561.987661] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  561.988154] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  561.988199] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  561.988265] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  561.996980] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.005748] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.014529] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.023314] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.032119] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.041029] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.049899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.058805] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.067666] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.076592] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.085831] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.094822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.103866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.112868] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.121846] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.130835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.139886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.148875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.157863] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.166843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.175872] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.184857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.193842] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.202841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.211885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.220889] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.229896] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.238878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.247860] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.256826] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.265882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.274874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.274920] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  562.274935] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  562.275010] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  562.275118] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  562.356450] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  562.360637] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  562.360806] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  562.360820] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  562.361477] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  562.361487] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  562.361496] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  562.361502] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  562.361997] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  562.362011] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  562.362021] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  562.362034] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  562.362043] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  562.362052] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  562.362062] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  562.362071] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  562.362081] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  562.362090] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  562.362100] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  562.362109] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  562.362120] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  562.362129] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  562.362142] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  562.362151] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  562.362161] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  562.362170] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  562.362179] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  562.362188] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  562.362198] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  562.362207] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  562.362217] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  562.362229] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  562.375544] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  562.375597] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  562.375641] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  562.375722] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  562.375766] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  562.375804] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  562.376369] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  562.376835] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  562.376848] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  562.376853] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  562.377406] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  562.377456] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  562.378179] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  562.378548] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  562.379051] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  562.379095] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  562.387718] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.396387] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.405101] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.413852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.422594] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.431528] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.440275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.449020] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.457797] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.466547] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.475320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.484178] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.493062] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.502020] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.510884] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.519790] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.528695] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.537705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.546711] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.555832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.564889] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.573898] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.582898] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.591885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.600874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.609863] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.618854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.627857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.636851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.645846] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.654892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.663882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  562.663932] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  562.663948] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  562.665720] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  562.665838] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  562.747065] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  562.751248] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  562.751364] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  562.751376] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  562.752198] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  562.752208] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  562.752217] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  562.752223] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  562.752612] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  562.752625] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  562.752635] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  562.752770] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  562.752780] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  562.752789] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  562.752798] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  562.752808] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  562.752818] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  562.752827] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  562.752837] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  562.752846] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  562.752855] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  562.752865] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  562.752874] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  562.752887] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  562.752899] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  562.752908] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  562.752918] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  562.752927] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  562.752936] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  562.752946] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  562.752955] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  562.752964] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  562.754792] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-C-frame-sequence
>[  562.756583] [drm:drm_mode_addfb2] [FB:70]
>[  562.773770] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  562.773878] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  562.774069] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  562.980846] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  562.980932] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  562.997781] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  562.997842] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  562.997906] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  563.050007] [drm:wait_panel_status [i915]] Wait complete
>[  563.050094] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  563.050183] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  563.050257] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  563.050330] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  563.050403] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  563.050531] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  563.050604] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  563.050921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  563.051017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  563.051108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  563.051190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  563.051272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  563.051357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  563.051439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  563.051522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  563.051607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  563.051689] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  563.051866] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  563.051966] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  563.052067] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  563.066373] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  563.066509] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  563.067455] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  563.067705] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  563.068368] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  563.068482] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  563.068666] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  563.083694] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  563.083963] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  563.084170] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  563.088494] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  563.088599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  563.088708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  563.089306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  563.089408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  563.089508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  563.089609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  563.089720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  563.090345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  563.090448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  563.090549] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  563.090669] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  563.091227] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  563.091334] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  563.091481] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  563.091583] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  563.092206] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  563.092358] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  563.092467] [drm:intel_power_well_disable [i915]] disabling DC off
>[  563.092569] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  563.092659] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  563.094395] [drm:intel_power_well_disable [i915]] disabling always-on
>[  563.095569] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  563.095610] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  563.096130] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  563.096213] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  563.096298] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  563.096388] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  563.096465] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  563.096546] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  563.096626] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  563.096706] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  563.097424] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  563.097504] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  563.097584] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  563.097597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  563.097674] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  563.098098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  563.098184] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  563.098262] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  563.098340] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  563.098419] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  563.098497] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  563.098581] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  563.098658] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  563.099366] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  563.099450] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  563.099509] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  563.099547] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  563.099589] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  563.099625] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  563.100219] [drm:intel_power_well_enable [i915]] enabling always-on
>[  563.100248] [drm:intel_power_well_enable [i915]] enabling DC off
>[  563.100531] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  563.100578] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  563.100611] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  563.100865] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  563.101006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  563.101042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  563.101079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  563.101114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  563.101149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  563.101184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  563.101219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  563.101256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  563.101291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  563.101325] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  563.101362] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  563.101397] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  563.101464] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  563.101498] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  563.101871] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  563.101909] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  563.500883] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  563.602948] [drm:wait_panel_status [i915]] Wait complete
>[  563.603048] [drm:edp_panel_on [i915]] Wait for panel power on
>[  563.603152] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  563.711513] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  563.711599] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  563.711680] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  563.711826] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  563.804704] [drm:wait_panel_status [i915]] Wait complete
>[  563.804888] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  563.804988] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  563.806726] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  563.806966] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  563.807071] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  563.808924] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  563.809025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  563.810865] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  563.811283] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  563.814246] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  563.814396] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  563.814492] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  563.814599] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  563.815220] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  563.815320] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  563.831360] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  563.831457] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  563.831838] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  563.915087] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  563.915423] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  564.116842] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  564.116969] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  564.131969] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  564.132085] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  564.132204] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  564.183978] [drm:wait_panel_status [i915]] Wait complete
>[  564.184111] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  564.184316] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  564.184451] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  564.184551] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  564.184650] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  564.184829] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  564.185010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  564.185132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  564.185243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  564.185346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  564.185452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  564.185554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  564.185664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  564.185835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  564.185943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  564.186042] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  564.186167] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  564.186281] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  564.186392] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  564.186551] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  564.186695] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  564.186869] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  564.187020] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  564.187129] [drm:intel_power_well_disable [i915]] disabling DC off
>[  564.187230] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  564.187324] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  564.188002] [drm:intel_power_well_disable [i915]] disabling always-on
>[  564.191800] [drm:drm_mode_addfb2] [FB:70]
>[  564.210837] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  564.210858] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  564.210973] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  564.211007] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  564.211045] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  564.211085] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  564.211117] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  564.211153] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  564.211188] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  564.211223] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  564.211257] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  564.211289] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  564.211321] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  564.211325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  564.211357] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  564.211360] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  564.211393] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  564.211425] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  564.211458] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  564.211491] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  564.211523] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  564.211561] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  564.211593] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  564.211628] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  564.211661] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  564.211777] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  564.211816] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  564.211862] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  564.211898] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  564.212270] [drm:intel_power_well_enable [i915]] enabling always-on
>[  564.212300] [drm:intel_power_well_enable [i915]] enabling DC off
>[  564.212582] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  564.212630] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  564.212674] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  564.212726] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  564.212982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  564.213018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  564.213054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  564.213089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  564.213124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  564.213180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  564.213218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  564.213254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  564.213290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  564.213326] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  564.213366] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  564.213404] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  564.213475] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  564.213511] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  564.213867] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  564.213905] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  564.636862] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  564.702113] [drm:wait_panel_status [i915]] Wait complete
>[  564.702164] [drm:edp_panel_on [i915]] Wait for panel power on
>[  564.702219] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  564.810684] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  564.810733] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  564.810778] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  564.810893] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  564.904244] [drm:wait_panel_status [i915]] Wait complete
>[  564.904333] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  564.904407] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  564.906109] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  564.906184] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  564.906260] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  564.907346] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  564.907418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  564.908932] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  564.909269] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  564.911351] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  564.911463] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  564.911533] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  564.911613] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  564.911907] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  564.911980] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  564.928414] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  564.928520] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  564.928902] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  565.012133] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  565.012440] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  565.220891] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  565.221050] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  565.229888] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  565.230002] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  565.230120] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  565.281923] [drm:wait_panel_status [i915]] Wait complete
>[  565.282053] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  565.282261] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  565.282353] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  565.282451] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  565.282549] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  565.282707] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  565.282980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  565.283104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  565.283214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  565.283320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  565.283422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  565.283530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  565.283638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  565.283820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  565.283927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  565.284038] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  565.284164] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  565.284279] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  565.284397] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  565.284555] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  565.284702] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  565.284892] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  565.285046] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  565.285155] [drm:intel_power_well_disable [i915]] disabling DC off
>[  565.285260] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  565.285355] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  565.286587] [drm:intel_power_well_disable [i915]] disabling always-on
>[  565.291075] [drm:drm_mode_addfb2] [FB:70]
>[  565.310449] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  565.310470] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  565.310592] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  565.310628] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  565.310958] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  565.310995] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  565.311037] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  565.311076] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  565.311115] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  565.311151] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  565.311187] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  565.311193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  565.311229] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  565.311234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  565.311271] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  565.311308] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  565.311346] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  565.311382] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  565.311418] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  565.311459] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  565.311495] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  565.311534] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  565.311573] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  565.311611] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  565.312287] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  565.312337] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  565.312374] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  565.312906] [drm:intel_power_well_enable [i915]] enabling always-on
>[  565.312938] [drm:intel_power_well_enable [i915]] enabling DC off
>[  565.313226] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  565.313280] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  565.313317] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  565.313374] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  565.313645] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  565.318113] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  565.318151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  565.318190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  565.318231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  565.318267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  565.318302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  565.318337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  565.318372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  565.318407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  565.318441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  565.318476] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  565.318512] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  565.318548] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  565.319181] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  565.319216] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  565.319479] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b5d28
>[  565.320604] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  565.321217] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  565.321253] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  565.321305] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  565.321338] [drm:hsw_audio_config_update [i915]] using automatic N
>[  565.338292] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  565.338367] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  565.338579] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  565.421877] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  565.422070] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  565.422144] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  565.422267] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  565.440087] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  565.440252] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  565.440414] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  565.444663] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  565.444808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  565.444889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  565.444972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  565.445047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  565.445121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  565.445195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  565.445277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  565.445351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  565.445425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  565.445498] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  565.445581] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  565.445660] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  565.445843] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  565.445968] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  565.446051] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  565.446165] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  565.446283] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  565.446367] [drm:intel_power_well_disable [i915]] disabling DC off
>[  565.446451] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  565.446525] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  565.447173] [drm:intel_power_well_disable [i915]] disabling always-on
>[  565.450933] [drm:drm_mode_addfb2] [FB:70]
>[  565.469733] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  565.469753] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  565.469870] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  565.469903] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  565.469940] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  565.469972] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  565.470009] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  565.470044] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  565.470079] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  565.470111] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  565.470143] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  565.470149] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  565.470180] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  565.470184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  565.470217] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  565.470249] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  565.470282] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  565.470315] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  565.470347] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  565.470384] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  565.470416] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  565.470452] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  565.470486] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  565.470520] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  565.470568] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  565.470618] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  565.470651] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  565.471095] [drm:intel_power_well_enable [i915]] enabling always-on
>[  565.471126] [drm:intel_power_well_enable [i915]] enabling DC off
>[  565.471409] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  565.471457] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  565.471492] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  565.471546] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  565.471915] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  565.476031] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  565.476067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  565.476106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  565.476145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  565.476180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  565.476215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  565.476250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  565.476285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  565.476320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  565.476355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  565.476389] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  565.476426] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  565.476461] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  565.476528] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  565.476562] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  565.476989] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  565.477980] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  565.478494] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  565.478528] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  565.478580] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  565.478612] [drm:hsw_audio_config_update [i915]] using automatic N
>[  565.495537] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  565.495605] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  565.495868] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  565.579072] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  565.579246] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  565.579317] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  565.579438] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  565.597195] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  565.597338] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  565.597470] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  565.601780] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  565.601857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  565.601937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  565.602019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  565.602094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  565.602167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  565.602239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  565.602319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  565.602393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  565.602466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  565.602539] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  565.602623] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  565.602784] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  565.602873] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  565.602993] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  565.603070] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  565.603176] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  565.603284] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  565.603364] [drm:intel_power_well_disable [i915]] disabling DC off
>[  565.603440] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  565.603507] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  565.604150] [drm:intel_power_well_disable [i915]] disabling always-on
>[  565.606439] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  565.631769] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  565.631808] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  565.631851] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  565.631894] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  565.631930] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  565.631970] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  565.632010] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  565.632049] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  565.632087] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  565.632123] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  565.632159] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  565.632168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  565.632204] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  565.632208] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  565.632245] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  565.632282] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  565.632320] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  565.632356] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  565.632393] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  565.632435] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  565.632471] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  565.632511] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  565.632550] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  565.632588] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  565.632627] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  565.632698] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  565.632736] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  565.632775] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  565.632811] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  565.632849] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  565.632888] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  565.632925] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  565.632961] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  565.632997] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  565.633001] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  565.633037] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  565.633042] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  565.633079] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  565.633116] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  565.633154] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  565.633190] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  565.633227] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  565.633266] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  565.633302] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  565.633340] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  565.633379] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  565.633417] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  565.633456] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  565.633495] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  565.633545] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  565.633584] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  565.633628] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  565.633665] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  565.633854] [drm:intel_power_well_enable [i915]] enabling always-on
>[  565.633886] [drm:intel_power_well_enable [i915]] enabling DC off
>[  565.634175] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  565.634237] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  565.634352] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  565.634391] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  565.634454] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  565.634637] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  565.638791] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  565.638847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  565.638902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  565.638963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  565.639018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  565.639072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  565.639127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  565.639181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  565.639235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  565.639289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  565.639343] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  565.639401] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  565.639459] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  565.639553] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  565.639605] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  565.639923] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  565.639978] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  565.732883] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  565.802935] [drm:wait_panel_status [i915]] Wait complete
>[  565.803023] [drm:edp_panel_on [i915]] Wait for panel power on
>[  565.803119] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  565.911505] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  565.911579] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  565.911651] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  565.911779] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  566.004778] [drm:wait_panel_status [i915]] Wait complete
>[  566.004888] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  566.004978] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  566.006674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  566.006802] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  566.006886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  566.008037] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  566.008114] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  566.009518] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  566.009907] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  566.012576] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  566.012766] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  566.012844] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  566.012931] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  566.013043] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  566.013118] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  566.013231] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  566.013309] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  566.013640] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  566.013766] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  566.014222] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  566.016900] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  566.017430] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  566.017465] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  566.017519] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  566.017551] [drm:hsw_audio_config_update [i915]] using automatic N
>[  566.034523] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  566.034600] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  566.034918] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  566.035194] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  566.035271] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  566.035513] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  566.036092] Console: switching to colour frame buffer device 240x67
>[  566.259136] Console: switching to colour dummy device 80x25
>[  566.259362] [IGT] kms_pipe_crc_basic: executing
>[  566.270676] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  566.270731] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  566.270780] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  566.270824] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  566.270865] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  566.270906] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  566.271469] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  566.272398] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  566.272413] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  566.272419] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  566.272457] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  566.272512] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  566.273125] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  566.273552] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  566.273595] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  566.273645] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  566.282374] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.291149] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.299948] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.308754] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.317549] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.326396] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.335261] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.344176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.353083] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.362099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.371081] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.380378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.389369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.398343] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.407324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.416370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.425353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.434329] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.443305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.452365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.461352] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.470321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.479357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.488327] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.497297] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.506369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.515346] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.524322] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.533359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.542332] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.551310] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.560372] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.560418] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  566.560433] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  566.560506] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  566.560610] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  566.640800] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  566.644992] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  566.645107] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  566.645119] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  566.645927] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  566.645938] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  566.645946] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  566.645956] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  566.646343] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  566.646356] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  566.646370] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  566.646379] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  566.646388] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  566.646398] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  566.646407] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  566.646417] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  566.646426] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  566.646436] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  566.646445] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  566.646458] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  566.646468] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  566.646477] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  566.646487] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  566.646496] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  566.646505] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  566.646514] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  566.646524] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  566.646533] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  566.646542] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  566.646556] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  566.646565] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  566.646574] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  566.661800] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  566.661847] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  566.661886] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  566.661920] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  566.661952] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  566.661987] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  566.662497] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  566.662997] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  566.663009] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  566.663014] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  566.663506] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  566.663551] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  566.664084] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  566.664456] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  566.664882] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  566.664925] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  566.673575] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.682288] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.690992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.699760] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.708537] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.717329] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.726110] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.734887] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.743687] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.752514] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.761302] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.770151] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.779063] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.788027] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.797029] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.806005] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.814988] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.823969] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.832947] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.841919] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.850885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.859859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.868831] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.877855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.886822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.895840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.904852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.913829] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.922845] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.931858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.940829] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.949844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  566.949889] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  566.949904] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  566.951170] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  566.951288] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  567.032396] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  567.036574] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  567.036688] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  567.036807] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  567.037477] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  567.037487] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  567.037496] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  567.037502] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  567.037973] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  567.037989] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  567.037999] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  567.038008] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  567.038018] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  567.038027] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  567.038037] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  567.038047] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  567.038063] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  567.038072] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  567.038082] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  567.038091] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  567.038101] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  567.038110] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  567.038120] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  567.038129] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  567.038138] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  567.038148] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  567.038161] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  567.038174] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  567.038183] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  567.038193] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  567.038202] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  567.038211] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  567.040079] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-A
>[  567.145272] PM: Syncing filesystems ... done.
>[  567.146970] PM: Preparing system for sleep (mem)
>[  567.154400] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  567.156160] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  567.157605] PM: Suspending system (mem)
>[  567.157721] Suspending console(s) (use no_console_suspend to debug)
>[  567.549485] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  567.551525] sd 0:0:0:0: [sda] Stopping disk
>[  567.752052] ACPI : EC: event blocked
>[  567.767545] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  567.767580] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  567.767619] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  567.767657] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  567.767717] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  567.767752] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  567.767788] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  567.767821] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  567.767854] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  567.767886] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  567.767917] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  567.767924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  567.767956] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  567.767959] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  567.767992] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  567.768024] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  567.768057] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  567.768089] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  567.768121] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  567.768159] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  567.768191] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  567.768226] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  567.768260] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  567.768293] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  567.768327] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  567.768360] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  567.768402] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  567.768435] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  567.768470] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  567.768502] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  567.768536] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  567.768570] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  567.768602] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  567.768633] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  567.768723] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  567.768727] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  567.768759] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  567.768762] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  567.768795] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  567.768828] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  567.768861] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  567.768893] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  567.768924] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  567.768960] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  567.768993] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  567.769027] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  567.769059] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  567.769093] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  567.769127] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  567.769159] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  567.769204] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  567.769248] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  567.769281] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  567.769319] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  567.769351] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  567.769516] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  567.887476] igb 0000:01:00.0: System wakeup enabled by ACPI
>[  567.972751] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  567.972808] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  567.981214] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  567.981253] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  567.981295] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  568.032009] [drm:wait_panel_status [i915]] Wait complete
>[  568.032046] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  568.032087] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  568.032190] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  568.032283] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  568.032335] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  568.033704] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  568.033737] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  568.033770] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  568.034424] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  568.034524] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  568.034608] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  568.038739] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  568.038773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  568.038807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  568.038846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  568.038879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  568.038912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  568.038945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  568.038978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  568.039011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  568.039044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  568.039077] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  568.039114] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  568.039150] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  568.039216] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  568.039256] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  568.039304] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  568.039348] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  568.039387] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  568.039434] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  568.040513] PM: suspend of devices complete after 495.096 msecs
>[  568.060213] hpet1: lost 7161 rtc interrupts
>[  568.085657] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  568.085714] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  568.085746] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  568.085795] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  568.085827] [drm:intel_power_well_disable [i915]] disabling DC off
>[  568.085861] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  568.085893] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  568.086431] [drm:intel_power_well_disable [i915]] disabling always-on
>[  568.086461] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  568.086519] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 19200 kHz (VCO 0 kHz)
>[  568.089777] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  568.089807] [drm:intel_power_well_disable [i915]] disabling power well 1
>[  568.089846] [drm:skl_set_power_well [i915]] Disabling power well 1
>[  568.089879] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC
>[  568.089917] [drm:bxt_enable_dc9 [i915]] Enabling DC9
>[  568.089951] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08
>[  568.101796] PM: late suspend of devices complete after 61.276 msecs
>[  568.104885] ACPI : EC: interrupt blocked
>[  568.106748] xhci_hcd 0000:00:15.0: System wakeup enabled by ACPI
>[  568.106773] pcieport 0000:00:13.0: invalid power transition (from state 4 to 3)
>[  568.127965] PM: noirq suspend of devices complete after 26.160 msecs
>[  568.128132] ACPI: Preparing to enter system sleep state S3
>[  568.132514] ACPI : EC: EC stopped
>[  568.132517] PM: Saving platform NVS memory
>[  568.134726] Disabling non-boot CPUs ...
>[  568.150529] smpboot: CPU 1 is now offline
>[  568.165019] Broke affinity for irq 374
>[  568.166217] smpboot: CPU 2 is now offline
>[  568.183203] Broke affinity for irq 1
>[  568.183225] Broke affinity for irq 8
>[  568.183241] Broke affinity for irq 9
>[  568.183262] Broke affinity for irq 14
>[  568.183294] Broke affinity for irq 122
>[  568.183300] Broke affinity for irq 123
>[  568.183589] Broke affinity for irq 374
>[  568.184808] smpboot: CPU 3 is now offline
>[  568.190645] ACPI: Low-level resume complete
>[  568.191920] ACPI : EC: EC started
>[  568.191928] PM: Restoring platform NVS memory
>[  568.193509] Suspended for 14.906 seconds
>[  568.193964] Enabling non-boot CPUs ...
>[  568.195059] x86: Booting SMP configuration:
>[  568.195067] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  568.196576] Skipped synchronization checks as TSC is reliable.
>[  568.206095]  cache: parent cpu1 should not be sleeping
>[  568.215954] CPU1 is up
>[  568.216865] smpboot: Booting Node 0 Processor 2 APIC 0x4
>[  568.217686] Skipped synchronization checks as TSC is reliable.
>[  568.224108]  cache: parent cpu2 should not be sleeping
>[  568.230728] CPU2 is up
>[  568.231199] smpboot: Booting Node 0 Processor 3 APIC 0x6
>[  568.231858] Skipped synchronization checks as TSC is reliable.
>[  568.236951]  cache: parent cpu3 should not be sleeping
>[  568.242490] CPU3 is up
>[  568.248498] ACPI: Waking up from system sleep state S3
>[  568.774833] acpi LNXPOWER:04: Turning ON
>[  568.809712] acpi LNXPOWER:14: Turning OFF
>[  568.846451] acpi LNXPOWER:11: Turning OFF
>[  568.852259] acpi LNXPOWER:09: Turning OFF
>[  568.855918] acpi LNXPOWER:07: Turning OFF
>[  568.859448] acpi LNXPOWER:06: Turning OFF
>[  568.874470] ACPI : EC: interrupt unblocked
>[  568.887998] xhci_hcd 0000:00:15.0: System wakeup disabled by ACPI
>[  568.900700] PM: noirq resume of devices complete after 27.221 msecs
>[  568.901406] [drm:gen9_sanitize_dc_state [i915]] Resetting DC state tracking from 08 to 00
>[  568.901454] [drm:bxt_disable_dc9 [i915]] Disabling DC9
>[  568.901500] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  568.901625] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 4
>[  568.901806] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  568.901864] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  568.901938] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  568.904330] [drm:intel_power_well_enable [i915]] enabling always-on
>[  568.904375] [drm:intel_power_well_enable [i915]] enabling DC off
>[  568.904422] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  568.904483] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  568.904534] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  568.905578] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  568.905859] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  568.906060] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 1 already enabled, won't reprogram it
>[  568.906201] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>[  568.921864] PM: early resume of devices complete after 20.763 msecs
>[  568.922823] ACPI : EC: event unblocked
>[  568.924569] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x79df2018
>[  568.925318] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  568.925321] sd 0:0:0:0: [sda] Starting disk
>[  568.925362] [drm:intel_opregion_setup [i915]] ASLE supported
>[  568.925364] igb 0000:01:00.0: System wakeup disabled by ACPI
>[  568.925468] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA)
>[  568.925622] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001010 hp_port:38
>[  568.925689] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  568.925738] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  568.926615] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 11.8
>[  568.930298] rtc_cmos 00:04: System wakeup disabled by ACPI
>[  569.092326] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 165 ms
>[  569.092882] [drm:drm_dp_i2c_do_msg] native defer
>[  569.094157] [drm:drm_dp_i2c_do_msg] native defer
>[  569.095431] [drm:drm_dp_i2c_do_msg] native defer
>[  569.096721] [drm:drm_dp_i2c_do_msg] native defer
>[  569.097991] [drm:drm_dp_i2c_do_msg] native defer
>[  569.098822] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  569.099142] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  569.099283] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  569.099383] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  569.099481] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  569.099541] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[  569.099549] [drm] GuC firmware load skipped
>[  569.099599] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  569.099652] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:1800181a hp_port:38
>[  569.099732] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:33:pipe A] hw state readout: disabled
>[  569.099777] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:42:pipe B] hw state readout: disabled
>[  569.099822] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:49:pipe C] hw state readout: disabled
>[  569.099861] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0
>[  569.099898] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0
>[  569.099935] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0
>[  569.099972] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI A] hw state readout: disabled, pipe A
>[  569.100009] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI B] hw state readout: disabled, pipe A
>[  569.100043] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A
>[  569.100076] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B
>[  569.100109] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C
>[  569.100146] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:63:DDI C] hw state readout: disabled, pipe A
>[  569.100179] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST A] hw state readout: disabled, pipe A
>[  569.100212] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST B] hw state readout: disabled, pipe B
>[  569.100245] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:67:DP-MST C] hw state readout: disabled, pipe C
>[  569.100307] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:eDP-1] hw state readout: disabled
>[  569.100348] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-1] hw state readout: disabled
>[  569.100386] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:64:DP-2] hw state readout: disabled
>[  569.100427] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:68:HDMI-A-1] hw state readout: disabled
>[  569.100466] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][setup_hw_state]
>[  569.100499] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  569.100531] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  569.100562] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  569.100567] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  569.100598] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  569.100602] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  569.100634] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  569.100666] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  569.100700] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  569.100732] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  569.100764] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  569.100800] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  569.100831] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  569.100866] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  569.100899] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  569.100933] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  569.100967] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  569.101001] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  569.101037] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][setup_hw_state]
>[  569.101069] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  569.101101] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  569.101133] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  569.101136] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  569.101168] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  569.101171] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  569.101203] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  569.101235] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  569.101292] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  569.101324] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  569.101356] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  569.101389] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  569.101421] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  569.101456] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  569.101488] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  569.101524] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  569.101558] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  569.101592] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  569.101628] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][setup_hw_state]
>[  569.101660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  569.101692] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  569.101724] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  569.101727] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  569.101758] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  569.101762] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  569.101794] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  569.101826] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  569.101858] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  569.101890] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  569.101922] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  569.101955] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  569.101987] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  569.102019] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  569.102052] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  569.102084] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  569.102283] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  569.102319] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  569.102351] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  569.102403] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  569.102438] [drm:intel_power_well_disable [i915]] disabling DC off
>[  569.102474] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  569.102509] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  569.102877] [drm:intel_power_well_disable [i915]] disabling always-on
>[  569.102953] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  569.102986] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  569.103026] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  569.103064] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  569.103096] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  569.103130] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  569.103164] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  569.103198] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  569.103230] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  569.103283] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  569.103315] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  569.103319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  569.103350] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  569.103353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  569.103386] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  569.103418] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  569.103450] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  569.103482] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  569.103514] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  569.103548] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  569.103580] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  569.103613] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  569.103646] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  569.103678] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  569.103710] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  569.103742] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  569.103781] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  569.103814] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  569.103850] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  569.103882] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  569.103916] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  569.103948] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  569.103980] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  569.104012] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  569.104044] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  569.104047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  569.104079] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  569.104082] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  569.104115] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  569.104147] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  569.104179] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  569.104211] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  569.104243] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  569.104301] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  569.104332] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  569.104365] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  569.104398] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  569.104430] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  569.104462] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  569.104494] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  569.104531] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  569.104575] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  569.104609] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  569.104649] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  569.104682] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  569.104838] [drm:intel_power_well_enable [i915]] enabling always-on
>[  569.104865] [drm:intel_power_well_enable [i915]] enabling DC off
>[  569.105056] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  569.105108] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  569.105285] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  569.105317] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  569.105370] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  569.105528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  569.105562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  569.105600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  569.105633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  569.105666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  569.105701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  569.105734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  569.105766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  569.105799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  569.105835] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:59:DP-1]
>[  569.105874] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:64:DP-2]
>[  569.105913] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  569.105949] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  569.105985] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  569.106052] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  569.106085] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  569.106379] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  569.106427] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  569.106485] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000062
>[  569.106531] [drm:wait_panel_status [i915]] Wait complete
>[  569.106578] [drm:edp_panel_on [i915]] Wait for panel power on
>[  569.106630] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  569.155296] atkbd serio0: Failed to deactivate keyboard on isa0060/serio0
>[  569.214987] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  569.215033] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  569.215078] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  569.215157] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  569.307539] [drm:wait_panel_status [i915]] Wait complete
>[  569.307610] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  569.307666] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  569.309132] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  569.309184] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  569.309240] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  569.310183] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  569.310235] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  569.311477] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  569.311774] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  569.313473] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  569.313583] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  569.313636] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  569.313695] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  569.313771] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  569.313821] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  569.313897] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  569.313950] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  569.314177] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  569.314232] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  569.314615] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  569.316302] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  569.316880] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  569.316933] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  569.317015] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  569.317065] [drm:hsw_audio_config_update [i915]] using automatic N
>[  569.333889] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  569.333969] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  569.334222] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  569.334530] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  569.334614] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  569.334854] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  569.334998] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  569.335400] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  569.335485] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  569.335550] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  569.335612] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  569.335671] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  569.335731] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  569.335868] [drm:intel_opregion_register [i915]] 4 outputs detected
>[  569.337689] PM: resume of devices complete after 415.815 msecs
>[  569.339010] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  569.339598] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:eDP-1] status updated from connected to connected
>[  569.339673] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  569.340211] PM: Finishing wakeup.
>[  569.340215] Restarting tasks ... 
>[  569.340386] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  569.346585] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-1] status updated from disconnected to disconnected
>[  569.346645] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  569.346967] done.
>[  569.357383] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.366074] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.374816] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.383507] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.392381] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.401059] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.409711] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.418357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.419339] atkbd serio0: Failed to enable keyboard on isa0060/serio0
>[  569.427101] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.435841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.444578] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.453317] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.462069] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.470798] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.479567] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.488321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.497128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.505989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.515014] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.523978] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.532919] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.541870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.550812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.559769] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.568707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.577679] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.586703] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.595721] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.604721] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.613727] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.622741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.631772] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  569.631827] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  569.631843] [drm:drm_helper_hpd_irq_event] [CONNECTOR:64:DP-2] status updated from disconnected to disconnected
>[  569.631948] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  569.675368] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  569.677563] ata1.00: supports DRM functions and may not be fully accessible
>[  569.678039] ata1.00: NCQ Send/Recv Log not supported
>[  569.678967] ata1.00: supports DRM functions and may not be fully accessible
>[  569.679536] ata1.00: NCQ Send/Recv Log not supported
>[  569.679553] ata1.00: configured for UDMA/133
>[  569.715462] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  569.719254] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  569.719300] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  569.719306] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  569.719312] [drm:drm_helper_hpd_irq_event] [CONNECTOR:68:HDMI-A-1] status updated from connected to connected
>[  569.719999] [drm:drm_mode_addfb2] [FB:71]
>[  569.736402] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  569.736423] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  569.763799] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  569.763946] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  569.764001] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  569.764043] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  569.764224] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  569.971435] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  569.971514] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  569.982216] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  569.982355] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  569.982415] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  570.034028] [drm:wait_panel_status [i915]] Wait complete
>[  570.034100] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  570.034170] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  570.034427] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  570.034535] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  570.034629] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  570.034759] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  570.034836] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  570.034916] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  570.034988] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  570.035122] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  570.051504] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  570.051664] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  570.051836] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  570.056118] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  570.056211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  570.056301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  570.056516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  570.056608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  570.056702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  570.056794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  570.056899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  570.056991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  570.057086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  570.057177] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  570.057283] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  570.057448] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  570.057552] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  570.057725] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  570.057819] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  570.058215] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  570.058410] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  570.491530] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  570.605244] [drm:wait_panel_status [i915]] Wait complete
>[  570.605434] [drm:edp_panel_on [i915]] Wait for panel power on
>[  570.605551] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  570.713945] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  570.714051] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  570.714150] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  570.714440] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  570.763822] [drm] RC6 on
>[  570.806804] [drm:wait_panel_status [i915]] Wait complete
>[  570.806949] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  570.807073] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  570.808850] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  570.808950] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  570.809054] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  570.810263] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  570.810457] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  570.812104] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  570.812636] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016d8d5d28
>[  570.815285] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  570.815495] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  570.815592] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  570.815701] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  570.815834] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  570.815929] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  570.816059] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  570.816157] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  570.849218] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  570.849385] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  570.849719] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  570.849915] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  570.850016] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  570.850149] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  570.850294] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  570.851223] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  570.916117] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  570.916658] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  571.123475] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  571.123634] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  571.134522] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  571.134635] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  571.134754] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  571.186443] [drm:wait_panel_status [i915]] Wait complete
>[  571.186560] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  571.186680] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  571.186887] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  571.187087] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  571.187189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  571.187296] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  571.187396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  571.187494] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  571.187669] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  571.188547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  571.188653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  571.188759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  571.188862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  571.188974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  571.189077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  571.189183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  571.189285] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  571.189495] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  571.189611] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  571.189723] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  571.190646] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  571.190798] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  571.190935] [drm:intel_power_well_disable [i915]] disabling DC off
>[  571.191041] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  571.191135] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  571.192436] [drm:intel_power_well_disable [i915]] disabling always-on
>[  571.196535] [drm:drm_mode_addfb2] [FB:71]
>[  571.214634] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  571.214655] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  571.214772] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  571.214805] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  571.214844] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  571.214882] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  571.214916] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  571.214951] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  571.214986] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  571.215021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  571.215055] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  571.215087] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  571.215119] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  571.215125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  571.215157] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  571.215160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  571.215193] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  571.215225] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  571.215459] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  571.215493] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  571.215527] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  571.215564] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  571.215598] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  571.215633] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  571.215668] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  571.215702] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  571.215736] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  571.215774] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  571.215817] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  571.215853] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  571.216229] [drm:intel_power_well_enable [i915]] enabling always-on
>[  571.216399] [drm:intel_power_well_enable [i915]] enabling DC off
>[  571.216684] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  571.216735] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  571.216881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  571.216917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  571.216955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  571.216990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  571.217025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  571.217060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  571.217096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  571.217131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  571.217166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  571.217200] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  571.217237] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  571.217330] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  571.217399] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  571.217433] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  571.217630] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  571.217667] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  571.643442] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  571.705128] [drm:wait_panel_status [i915]] Wait complete
>[  571.705230] [drm:edp_panel_on [i915]] Wait for panel power on
>[  571.705449] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  571.734025] igb 0000:01:00.0 enp1s0: igb: enp1s0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX
>[  571.813749] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  571.813855] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  571.813955] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  571.814153] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  571.905547] [drm:wait_panel_status [i915]] Wait complete
>[  571.905690] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  571.905810] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  571.907725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  571.907829] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  571.907933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  571.909206] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  571.909305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  571.911126] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  571.911729] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016d8d4138
>[  571.914596] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  571.914750] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  571.914846] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  571.914954] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  571.915087] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  571.915185] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  571.915315] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  571.916224] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  571.931729] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  571.931836] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  571.932121] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  572.014989] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  572.015124] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  572.219441] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  572.219518] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  572.232244] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  572.232345] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  572.232398] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  572.283282] [drm:wait_panel_status [i915]] Wait complete
>[  572.283375] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  572.283432] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  572.283551] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  572.283667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  572.283717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  572.283763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  572.283807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  572.283850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  572.283894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  572.283940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  572.283983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  572.284026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  572.284070] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  572.284119] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  572.284164] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  572.284210] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  572.284330] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  572.284396] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  572.284456] [drm:intel_power_well_disable [i915]] disabling DC off
>[  572.284502] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  572.284543] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  572.285102] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  572.285146] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  572.285190] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  572.285781] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  572.285836] [drm:intel_power_well_disable [i915]] disabling always-on
>[  572.288583] [drm:drm_mode_addfb2] [FB:71]
>[  572.308371] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  572.308393] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  572.308509] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  572.308542] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  572.308579] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  572.308613] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  572.308648] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  572.308683] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  572.308718] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  572.308750] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  572.308781] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  572.308785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  572.308817] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  572.308821] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  572.308854] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  572.308886] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  572.308919] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  572.308953] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  572.308985] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  572.309024] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  572.309055] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  572.309091] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  572.309126] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  572.309160] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  572.309194] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  572.309242] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  572.309338] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  572.309377] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  572.309735] [drm:intel_power_well_enable [i915]] enabling always-on
>[  572.309763] [drm:intel_power_well_enable [i915]] enabling DC off
>[  572.310046] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  572.310097] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  572.310131] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  572.310184] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  572.310988] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  572.315114] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  572.315151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  572.315191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  572.315231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  572.315508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  572.315543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  572.315578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  572.315613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  572.315648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  572.315683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  572.315718] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  572.315756] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  572.315791] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  572.315857] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  572.315892] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  572.316149] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  572.317469] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  572.318027] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  572.318066] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  572.318124] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  572.318161] [drm:hsw_audio_config_update [i915]] using automatic N
>[  572.318642] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  572.318684] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  572.335088] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  572.335165] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  572.335738] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  572.418496] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  572.418622] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  572.418672] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  572.418756] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  572.436567] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  572.436628] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  572.436750] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  572.436867] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  572.440346] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  572.440414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  572.440484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  572.440555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  572.440618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  572.440681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  572.440744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  572.440813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  572.440877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  572.440939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  572.441002] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  572.441074] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  572.441141] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  572.441207] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  572.441376] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  572.441443] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  572.441538] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  572.441632] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  572.441716] [drm:intel_power_well_disable [i915]] disabling DC off
>[  572.441782] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  572.441837] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  572.442502] [drm:intel_power_well_disable [i915]] disabling always-on
>[  572.445387] [drm:drm_mode_addfb2] [FB:71]
>[  572.465803] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  572.465826] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  572.465940] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  572.465973] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  572.466011] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  572.466043] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  572.466078] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  572.466113] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  572.466148] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  572.466180] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  572.466212] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  572.466216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  572.466247] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  572.466337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  572.466373] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  572.466410] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  572.466447] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  572.466482] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  572.466515] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  572.466550] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  572.466585] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  572.466618] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  572.466653] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  572.466686] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  572.466720] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  572.466773] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  572.466821] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  572.466856] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  572.467213] [drm:intel_power_well_enable [i915]] enabling always-on
>[  572.467243] [drm:intel_power_well_enable [i915]] enabling DC off
>[  572.467570] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  572.467624] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  572.467661] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  572.467717] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  572.468012] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  572.472128] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  572.472166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  572.472206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  572.472245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  572.472326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  572.472364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  572.472404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  572.472441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  572.472480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  572.472518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  572.472557] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  572.472599] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  572.472636] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  572.472705] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  572.472739] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  572.472997] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  572.474051] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  572.474667] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  572.474703] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  572.474755] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  572.474790] [drm:hsw_audio_config_update [i915]] using automatic N
>[  572.474880] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  572.474916] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  572.491733] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  572.491801] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  572.492002] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  572.575215] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  572.575558] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  572.575647] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  572.575788] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  572.591662] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  572.591745] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  572.591897] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  572.592065] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  572.596381] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  572.596465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  572.596552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  572.596642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  572.596724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  572.596805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  572.596886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  572.596975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  572.597056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  572.597138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  572.597218] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  572.597387] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  572.597484] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  572.597580] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  572.597702] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  572.597786] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  572.597900] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  572.598019] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  572.598127] [drm:intel_power_well_disable [i915]] disabling DC off
>[  572.598211] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  572.598285] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  572.598927] [drm:intel_power_well_disable [i915]] disabling always-on
>[  572.601490] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  572.627414] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  572.627454] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  572.627499] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  572.627545] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  572.627583] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  572.627624] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  572.627666] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  572.627707] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  572.627746] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  572.627784] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  572.627822] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  572.627831] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  572.627868] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  572.627873] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  572.627912] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  572.627951] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  572.627990] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  572.628028] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  572.628067] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  572.628111] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  572.628149] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  572.628192] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  572.628230] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  572.628293] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  572.628332] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  572.628379] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  572.628419] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  572.628464] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  572.628504] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  572.628543] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  572.628584] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  572.628622] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  572.628660] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  572.628698] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  572.628704] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  572.628741] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  572.628745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  572.628785] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  572.628823] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  572.628863] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  572.628902] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  572.628940] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  572.628980] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  572.629018] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  572.629059] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  572.629099] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  572.629139] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  572.629179] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  572.629222] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  572.629338] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  572.629378] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  572.629424] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  572.629464] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  572.629640] [drm:intel_power_well_enable [i915]] enabling always-on
>[  572.629673] [drm:intel_power_well_enable [i915]] enabling DC off
>[  572.629964] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  572.630026] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  572.630144] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  572.630183] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  572.630247] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  572.630476] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  572.634369] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  572.634421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  572.634473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  572.634531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  572.634582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  572.634633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  572.634684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  572.634734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  572.634785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  572.634836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  572.634887] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  572.634942] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  572.634996] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  572.635086] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  572.635137] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  572.635451] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  572.635505] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  572.739443] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  572.804968] [drm:wait_panel_status [i915]] Wait complete
>[  572.805035] [drm:edp_panel_on [i915]] Wait for panel power on
>[  572.805106] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  572.913490] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  572.913550] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  572.913607] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  572.913782] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  573.006465] [drm:wait_panel_status [i915]] Wait complete
>[  573.006592] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  573.006702] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  573.008477] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  573.008562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  573.008655] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  573.009823] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  573.009908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  573.011462] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  573.011875] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  573.014857] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  573.015010] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  573.015096] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  573.015194] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  573.015376] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  573.015460] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  573.015579] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  573.015666] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  573.016026] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  573.016112] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  573.016587] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  573.018935] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  573.019486] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  573.019520] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  573.019574] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  573.019606] [drm:hsw_audio_config_update [i915]] using automatic N
>[  573.036528] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  573.036606] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  573.036858] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  573.037117] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  573.037200] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  573.037511] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  573.038062] Console: switching to colour frame buffer device 240x67
>[  573.334371] Console: switching to colour dummy device 80x25
>[  573.334742] [IGT] kms_pipe_crc_basic: executing
>[  573.356587] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  573.356658] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  573.356721] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  573.356780] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  573.356835] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  573.356892] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  573.357798] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  573.358464] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  573.358483] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  573.358490] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  573.358541] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  573.358606] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  573.359205] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  573.359731] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  573.359778] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  573.359844] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  573.368537] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.377286] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.386130] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.395017] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.403970] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.412920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.421927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.430936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.439940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.449176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.458285] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.467425] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.476470] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.485464] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.494456] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.503450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.512466] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.521480] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.530476] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.539461] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.548449] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.557450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.566451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.575464] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.584458] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.593452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.602461] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.611467] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.620475] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.629489] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.638476] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.647474] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.647520] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  573.647534] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  573.647609] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  573.647714] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  573.728414] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  573.732605] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  573.732719] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  573.732731] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  573.733543] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  573.733553] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  573.733562] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  573.733568] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  573.733949] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  573.733961] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  573.733971] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  573.733984] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  573.733993] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  573.734003] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  573.734013] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  573.734022] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  573.734032] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  573.734041] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  573.734051] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  573.734060] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  573.734070] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  573.734084] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  573.734093] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  573.734102] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  573.734112] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  573.734121] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  573.734130] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  573.734139] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  573.734149] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  573.734158] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  573.734167] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  573.734176] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  573.747156] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  573.747206] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  573.747252] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  573.747338] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  573.747378] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  573.747422] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  573.747967] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  573.748438] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  573.748452] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  573.748457] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  573.748999] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  573.749047] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  573.749656] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  573.750030] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  573.750482] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  573.750525] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  573.759122] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.767841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.776567] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.785267] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.794069] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.802854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.811684] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.820484] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.829367] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.838167] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.846989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.855798] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.864621] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.873432] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.882229] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.891094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.899904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.908726] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.917588] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.926399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.935209] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.944094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.952975] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.961911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.970901] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.979900] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.988813] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  573.997748] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  574.006661] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  574.015669] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  574.024654] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  574.033659] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  574.033702] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  574.033716] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  574.034863] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  574.034968] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  574.115973] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  574.120168] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  574.120270] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  574.120393] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  574.120981] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  574.120990] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  574.120999] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  574.121004] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  574.121433] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  574.121444] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  574.121453] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  574.121462] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  574.121470] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  574.121481] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  574.121490] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  574.121498] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  574.121507] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  574.121518] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  574.121527] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  574.121535] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  574.121544] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  574.121552] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  574.121561] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  574.121569] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  574.121580] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  574.121589] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  574.121597] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  574.121605] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  574.121617] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  574.121625] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  574.121633] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  574.121642] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  574.123208] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-B
>[  574.209954] PM: Syncing filesystems ... done.
>[  574.222589] PM: Preparing system for sleep (mem)
>[  574.223669] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  574.225487] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  574.227034] PM: Suspending system (mem)
>[  574.227137] Suspending console(s) (use no_console_suspend to debug)
>[  574.616874] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  574.617972] sd 0:0:0:0: [sda] Stopping disk
>[  574.822425] ACPI : EC: event blocked
>[  574.833976] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  574.834011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  574.834048] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  574.834087] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  574.834119] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  574.834154] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  574.834187] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  574.834222] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  574.834281] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  574.834313] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  574.834344] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  574.834352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  574.834384] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  574.834387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  574.834420] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  574.834452] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  574.834486] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  574.834518] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  574.834550] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  574.834588] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  574.834620] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  574.834655] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  574.834688] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  574.834721] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  574.834754] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  574.834787] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  574.834829] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  574.834862] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  574.834896] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  574.834927] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  574.834962] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  574.834994] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  574.835026] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  574.835058] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  574.835090] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  574.835093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  574.835125] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  574.835128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  574.835161] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  574.835193] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  574.835227] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  574.835296] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  574.835328] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  574.835362] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  574.835394] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  574.835429] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  574.835462] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  574.835496] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  574.835530] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  574.835564] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  574.835608] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  574.835650] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  574.835685] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  574.835723] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  574.835755] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  574.835907] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  574.860053] igb 0000:01:00.0: System wakeup enabled by ACPI
>[  575.043345] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  575.043405] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  575.049884] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  575.049922] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  575.049964] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  575.100609] [drm:wait_panel_status [i915]] Wait complete
>[  575.100646] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  575.100688] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  575.100798] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  575.100893] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  575.100945] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  575.103034] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  575.103133] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  575.103218] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  575.107356] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  575.107389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  575.107423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  575.107461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  575.107495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  575.107528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  575.107561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  575.107594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  575.107627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  575.107660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  575.107693] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  575.107729] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  575.107765] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  575.107831] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  575.107872] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  575.107919] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  575.107962] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  575.108002] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  575.108048] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  575.110300] hpet1: lost 7161 rtc interrupts
>[  575.110870] PM: suspend of devices complete after 494.907 msecs
>[  575.258044] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  575.258080] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  575.258112] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  575.258160] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  575.258192] [drm:intel_power_well_disable [i915]] disabling DC off
>[  575.258226] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  575.258284] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  575.258823] [drm:intel_power_well_disable [i915]] disabling always-on
>[  575.258854] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  575.258909] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 19200 kHz (VCO 0 kHz)
>[  575.263025] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  575.263054] [drm:intel_power_well_disable [i915]] disabling power well 1
>[  575.263090] [drm:skl_set_power_well [i915]] Disabling power well 1
>[  575.263123] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC
>[  575.263164] [drm:bxt_enable_dc9 [i915]] Enabling DC9
>[  575.263195] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08
>[  575.281030] PM: late suspend of devices complete after 170.042 msecs
>[  575.285773] ACPI : EC: interrupt blocked
>[  575.288169] xhci_hcd 0000:00:15.0: System wakeup enabled by ACPI
>[  575.288188] pcieport 0000:00:13.0: invalid power transition (from state 4 to 3)
>[  575.309207] PM: noirq suspend of devices complete after 28.058 msecs
>[  575.309503] ACPI: Preparing to enter system sleep state S3
>[  575.314640] ACPI : EC: EC stopped
>[  575.314644] PM: Saving platform NVS memory
>[  575.314656] Disabling non-boot CPUs ...
>[  575.330916] smpboot: CPU 1 is now offline
>[  575.350568] Broke affinity for irq 374
>[  575.351755] smpboot: CPU 2 is now offline
>[  575.361710] Broke affinity for irq 1
>[  575.361727] Broke affinity for irq 8
>[  575.361739] Broke affinity for irq 9
>[  575.361756] Broke affinity for irq 14
>[  575.361779] Broke affinity for irq 122
>[  575.361783] Broke affinity for irq 123
>[  575.362004] Broke affinity for irq 374
>[  575.363206] smpboot: CPU 3 is now offline
>[  575.367585] ACPI: Low-level resume complete
>[  575.368199] ACPI : EC: EC started
>[  575.368207] PM: Restoring platform NVS memory
>[  575.369472] Suspended for 14.829 seconds
>[  575.370732] Enabling non-boot CPUs ...
>[  575.373552] x86: Booting SMP configuration:
>[  575.373563] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  575.374698] Skipped synchronization checks as TSC is reliable.
>[  575.385096]  cache: parent cpu1 should not be sleeping
>[  575.393206] CPU1 is up
>[  575.393956] smpboot: Booting Node 0 Processor 2 APIC 0x4
>[  575.394768] Skipped synchronization checks as TSC is reliable.
>[  575.400852]  cache: parent cpu2 should not be sleeping
>[  575.406971] CPU2 is up
>[  575.407511] smpboot: Booting Node 0 Processor 3 APIC 0x6
>[  575.408216] Skipped synchronization checks as TSC is reliable.
>[  575.412912]  cache: parent cpu3 should not be sleeping
>[  575.418868] CPU3 is up
>[  575.422361] ACPI: Waking up from system sleep state S3
>[  575.458914] acpi LNXPOWER:04: Turning ON
>[  575.498338] acpi LNXPOWER:14: Turning OFF
>[  575.537235] acpi LNXPOWER:11: Turning OFF
>[  575.543044] acpi LNXPOWER:09: Turning OFF
>[  575.546726] acpi LNXPOWER:07: Turning OFF
>[  575.550256] acpi LNXPOWER:06: Turning OFF
>[  575.565156] ACPI : EC: interrupt unblocked
>[  575.578371] xhci_hcd 0000:00:15.0: System wakeup disabled by ACPI
>[  575.587822] PM: noirq resume of devices complete after 23.645 msecs
>[  575.588568] [drm:gen9_sanitize_dc_state [i915]] Resetting DC state tracking from 08 to 00
>[  575.588608] [drm:bxt_disable_dc9 [i915]] Disabling DC9
>[  575.588647] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  575.588703] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 4
>[  575.588990] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  575.589040] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  575.589103] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  575.591118] [drm:intel_power_well_enable [i915]] enabling always-on
>[  575.591155] [drm:intel_power_well_enable [i915]] enabling DC off
>[  575.591194] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  575.591245] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  575.591288] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  575.592212] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  575.592375] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  575.592586] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 1 already enabled, won't reprogram it
>[  575.592708] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>[  575.608826] PM: early resume of devices complete after 20.535 msecs
>[  575.609821] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x79df2018
>[  575.609862] ACPI : EC: event unblocked
>[  575.609924] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  575.609965] [drm:intel_opregion_setup [i915]] ASLE supported
>[  575.610076] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA)
>[  575.610235] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001010 hp_port:38
>[  575.610301] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  575.610351] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  575.611864] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 15.10
>[  575.612153] igb 0000:01:00.0: System wakeup disabled by ACPI
>[  575.614325] rtc_cmos 00:04: System wakeup disabled by ACPI
>[  575.620091] sd 0:0:0:0: [sda] Starting disk
>[  575.840536] atkbd serio0: Failed to deactivate keyboard on isa0060/serio0
>[  576.096509] atkbd serio0: Failed to enable keyboard on isa0060/serio0
>[  576.263643] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 652 ms
>[  576.264222] [drm:drm_dp_i2c_do_msg] native defer
>[  576.265626] [drm:drm_dp_i2c_do_msg] native defer
>[  576.267010] [drm:drm_dp_i2c_do_msg] native defer
>[  576.268382] [drm:drm_dp_i2c_do_msg] native defer
>[  576.269769] [drm:drm_dp_i2c_do_msg] native defer
>[  576.270759] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  576.271188] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  576.271406] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  576.271625] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  576.271812] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  576.271932] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[  576.271948] [drm] GuC firmware load skipped
>[  576.272045] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  576.272141] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:1800181a hp_port:38
>[  576.272291] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:33:pipe A] hw state readout: disabled
>[  576.272379] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:42:pipe B] hw state readout: disabled
>[  576.272466] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:49:pipe C] hw state readout: disabled
>[  576.272585] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0
>[  576.272658] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0
>[  576.272731] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0
>[  576.272806] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI A] hw state readout: disabled, pipe A
>[  576.272881] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI B] hw state readout: disabled, pipe A
>[  576.272950] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A
>[  576.273015] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B
>[  576.273081] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C
>[  576.273155] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:63:DDI C] hw state readout: disabled, pipe A
>[  576.273222] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST A] hw state readout: disabled, pipe A
>[  576.273289] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST B] hw state readout: disabled, pipe B
>[  576.273357] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:67:DP-MST C] hw state readout: disabled, pipe C
>[  576.273437] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:eDP-1] hw state readout: disabled
>[  576.273563] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-1] hw state readout: disabled
>[  576.273640] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:64:DP-2] hw state readout: disabled
>[  576.273719] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:68:HDMI-A-1] hw state readout: disabled
>[  576.273793] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][setup_hw_state]
>[  576.273859] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  576.273923] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  576.273986] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  576.273996] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  576.274059] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  576.274066] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  576.274131] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  576.274195] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  576.274260] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  576.274324] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  576.274388] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  576.274459] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  576.274594] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  576.274645] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  576.274694] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  576.274744] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  576.274795] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  576.274843] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  576.274897] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][setup_hw_state]
>[  576.274945] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  576.274993] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  576.275040] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  576.275045] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  576.275092] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  576.275097] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  576.275146] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  576.275194] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  576.275242] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  576.275290] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  576.275338] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  576.275388] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  576.275436] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  576.275509] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  576.275557] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  576.275607] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  576.275657] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  576.275705] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  576.275758] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][setup_hw_state]
>[  576.275806] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  576.275853] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  576.275901] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  576.275905] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  576.275953] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  576.275957] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  576.276006] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  576.276054] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  576.276102] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  576.276150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  576.276199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  576.276249] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  576.276297] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  576.276347] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  576.276398] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  576.276447] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  576.276717] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  576.276767] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  576.276814] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  576.276888] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  576.276936] [drm:intel_power_well_disable [i915]] disabling DC off
>[  576.276987] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  576.277031] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  576.277414] [drm:intel_power_well_disable [i915]] disabling always-on
>[  576.277546] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  576.277595] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  576.277649] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  576.277705] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  576.277753] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  576.277804] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  576.277854] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  576.277902] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  576.277951] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  576.277999] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  576.278046] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  576.278052] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  576.278099] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  576.278104] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  576.278154] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  576.278203] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  576.278251] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  576.278299] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  576.278347] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  576.278398] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  576.278445] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  576.278524] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  576.278573] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  576.278621] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  576.278669] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  576.278717] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  576.278777] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  576.278826] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  576.278879] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  576.278927] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  576.278976] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  576.279024] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  576.279072] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  576.279120] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  576.279167] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  576.279172] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  576.279220] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  576.279225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  576.279274] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  576.279322] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  576.279370] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  576.279418] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  576.279466] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  576.279542] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  576.279589] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  576.279639] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  576.279688] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  576.279736] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  576.279784] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  576.279832] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  576.279885] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  576.279946] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  576.279995] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  576.280053] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  576.280102] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  576.280315] [drm:intel_power_well_enable [i915]] enabling always-on
>[  576.280356] [drm:intel_power_well_enable [i915]] enabling DC off
>[  576.280600] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  576.280672] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  576.280847] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  576.280894] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  576.280967] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  576.281242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  576.281292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  576.281348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  576.281397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  576.281446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  576.281538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  576.281587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  576.281636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  576.281685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  576.281736] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:59:DP-1]
>[  576.281794] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:64:DP-2]
>[  576.281851] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  576.281905] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  576.281958] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  576.282046] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  576.282095] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  576.282348] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  576.282400] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  576.282461] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000062
>[  576.282554] [drm:wait_panel_status [i915]] Wait complete
>[  576.282609] [drm:edp_panel_on [i915]] Wait for panel power on
>[  576.282668] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  576.368524] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  576.370650] ata1.00: supports DRM functions and may not be fully accessible
>[  576.371082] ata1.00: NCQ Send/Recv Log not supported
>[  576.371776] ata1.00: supports DRM functions and may not be fully accessible
>[  576.372199] ata1.00: NCQ Send/Recv Log not supported
>[  576.372206] ata1.00: configured for UDMA/133
>[  576.391084] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  576.391153] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  576.391218] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  576.391349] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  576.482937] [drm:wait_panel_status [i915]] Wait complete
>[  576.483051] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  576.483151] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  576.484883] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  576.484960] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  576.485042] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  576.486156] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  576.486233] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  576.487621] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  576.487998] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  576.490465] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  576.490641] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  576.490719] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  576.490806] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  576.490915] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  576.490992] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  576.491099] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  576.491177] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  576.491498] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  576.491622] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  576.492060] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  576.494067] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  576.494609] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  576.494644] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  576.494697] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  576.494729] [drm:hsw_audio_config_update [i915]] using automatic N
>[  576.511683] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  576.511761] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  576.511999] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  576.512249] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  576.512339] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  576.512617] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  576.512757] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  576.513100] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  576.513179] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  576.513239] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  576.513297] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  576.513354] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  576.513409] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  576.513573] [drm:intel_opregion_register [i915]] 4 outputs detected
>[  576.516562] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  576.516576] PM: resume of devices complete after 907.741 msecs
>[  576.517071] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:eDP-1] status updated from connected to connected
>[  576.517134] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  576.517770] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  576.518200] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-1] status updated from disconnected to disconnected
>[  576.518252] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  576.519054] PM: Finishing wakeup.
>[  576.519057] Restarting tasks ... done.
>[  576.532273] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.541117] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.549935] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.558630] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.567335] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.576024] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.584760] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.593605] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.602253] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.610909] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.619529] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.628255] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.636988] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.645717] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.654441] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.663259] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.672004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.680839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.689691] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.698579] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.707460] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.716425] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.725435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.734452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.743460] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.752473] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.761610] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.770640] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.779667] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.788696] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.797735] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.806765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  576.806821] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  576.806838] [drm:drm_helper_hpd_irq_event] [CONNECTOR:64:DP-2] status updated from disconnected to disconnected
>[  576.806943] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  576.888270] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  576.892520] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  576.892637] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  576.892651] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  576.892664] [drm:drm_helper_hpd_irq_event] [CONNECTOR:68:HDMI-A-1] status updated from connected to connected
>[  576.894530] [drm:drm_mode_addfb2] [FB:89]
>[  576.914250] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  576.914358] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  576.914593] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  577.120572] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  577.120633] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  577.125005] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  577.125045] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  577.125085] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  577.176002] [drm:wait_panel_status [i915]] Wait complete
>[  577.176054] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  577.176108] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  577.176231] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  577.176335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  577.176382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  577.176426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  577.176543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  577.176585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  577.176629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  577.176673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  577.176717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  577.176760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  577.176804] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  577.176855] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  577.176899] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  577.176946] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  577.177488] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  577.177548] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  577.177607] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  577.177728] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  577.178184] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  577.178268] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  577.178740] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  577.178769] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  577.178939] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  577.178993] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  577.179053] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  577.179115] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  577.179166] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  577.179223] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  577.179277] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  577.179331] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  577.179384] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  577.179435] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  577.179552] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  577.179563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  577.179621] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  577.179634] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  577.179693] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  577.179750] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  577.179810] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  577.179867] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  577.179926] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  577.179988] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  577.180044] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  577.180103] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  577.180167] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  577.180225] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  577.180283] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  577.180336] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  577.180419] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  577.180526] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  577.180583] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  577.181051] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  577.181199] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  577.181271] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  577.181394] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  577.195855] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  577.195990] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  577.196061] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  577.200306] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  577.200377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  577.200445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  577.200712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  577.200782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  577.200853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  577.200921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  577.200999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  577.201068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  577.201139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  577.201207] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  577.201288] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  577.201363] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  577.201438] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  577.201754] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  577.201820] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  577.202111] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  577.202180] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  577.632665] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  577.690378] [drm:wait_panel_status [i915]] Wait complete
>[  577.690469] [drm:edp_panel_on [i915]] Wait for panel power on
>[  577.690735] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  577.798975] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  577.799074] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  577.799162] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  577.799423] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  577.809026] [drm] RC6 on
>[  577.892074] [drm:wait_panel_status [i915]] Wait complete
>[  577.892220] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  577.892341] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  577.894115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  577.894220] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  577.894325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  577.895521] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  577.895700] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  577.897310] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  577.897762] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016d8d37e8
>[  577.900300] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  577.900453] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  577.900653] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  577.900761] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  577.900898] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  577.900999] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  577.917313] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  577.917856] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  577.917987] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  577.918307] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  577.933941] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  578.001048] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  578.001381] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  578.208662] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  578.208818] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  578.217722] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  578.217835] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  578.217955] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  578.269639] [drm:wait_panel_status [i915]] Wait complete
>[  578.269767] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  578.269973] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  578.270209] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  578.270309] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  578.270409] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  578.270590] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  578.271667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  578.271793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  578.271900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  578.272004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  578.272105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  578.272208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  578.272314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  578.272417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  578.272518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  578.272923] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  578.273032] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  578.273131] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  578.273229] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  578.273362] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  578.273490] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  578.273803] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  578.273933] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  578.274033] [drm:intel_power_well_disable [i915]] disabling DC off
>[  578.274125] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  578.274206] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  578.275418] [drm:intel_power_well_disable [i915]] disabling always-on
>[  578.279093] [drm:drm_mode_addfb2] [FB:89]
>[  578.297862] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  578.297883] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  578.298000] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  578.298034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  578.298073] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  578.298111] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  578.298144] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  578.298179] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  578.298214] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  578.298249] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  578.298283] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  578.298315] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  578.298347] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  578.298353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  578.298385] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  578.298388] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  578.298421] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  578.298501] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  578.298537] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  578.298574] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  578.298608] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  578.298645] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  578.298679] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  578.298715] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  578.298751] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  578.298785] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  578.298821] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  578.298859] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  578.298901] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL A
>[  578.298936] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe B
>[  578.299312] [drm:intel_power_well_enable [i915]] enabling always-on
>[  578.299343] [drm:intel_power_well_enable [i915]] enabling DC off
>[  578.299654] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  578.299704] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  578.299738] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  578.299794] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  578.299973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  578.300009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  578.300046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  578.300081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  578.300115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  578.300149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  578.300184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  578.300219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  578.300253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  578.300287] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  578.300326] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  578.300363] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  578.300430] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 2, on? 0) for crtc 42
>[  578.300500] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  578.300719] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  578.300756] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  578.435214] igb 0000:01:00.0 enp1s0: igb: enp1s0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX
>[  578.720578] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  578.789014] [drm:wait_panel_status [i915]] Wait complete
>[  578.789090] [drm:edp_panel_on [i915]] Wait for panel power on
>[  578.789170] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  578.897581] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  578.897679] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  578.897767] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  578.897933] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  578.989822] [drm:wait_panel_status [i915]] Wait complete
>[  578.989966] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  578.990086] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  578.991791] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  578.991890] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  578.991995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  578.993271] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  578.993374] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  578.995235] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  578.995727] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016d8d6fc8
>[  578.998383] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  578.998731] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  578.998805] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  578.998860] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  578.998929] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  578.998976] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  579.015552] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  579.015638] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  579.015879] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  579.098957] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  579.099176] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  579.304666] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  579.304821] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  579.315709] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  579.315823] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  579.315942] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  579.367682] [drm:wait_panel_status [i915]] Wait complete
>[  579.367816] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 2, on? 1) for crtc 42
>[  579.368020] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  579.368210] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  579.368312] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  579.368413] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  579.368586] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  579.368942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  579.369066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  579.369176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  579.369282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  579.369386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  579.369491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  579.369676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  579.369785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  579.369892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  579.369996] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  579.370122] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  579.370233] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  579.370347] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  579.370495] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  579.370732] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  579.370838] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  579.370990] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  579.371105] [drm:intel_power_well_disable [i915]] disabling DC off
>[  579.371210] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  579.371302] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  579.372002] [drm:intel_power_well_disable [i915]] disabling always-on
>[  579.376235] [drm:drm_mode_addfb2] [FB:89]
>[  579.395639] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  579.395660] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  579.395780] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  579.395815] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  579.395853] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  579.395886] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  579.395924] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  579.395960] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  579.395996] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  579.396029] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  579.396062] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  579.396068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  579.396101] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  579.396105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  579.396140] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  579.396173] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  579.396208] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  579.396244] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  579.396277] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  579.396317] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  579.396350] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  579.396387] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  579.396422] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  579.396509] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  579.396548] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  579.396605] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  579.396657] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  579.396695] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  579.397070] [drm:intel_power_well_enable [i915]] enabling always-on
>[  579.397102] [drm:intel_power_well_enable [i915]] enabling DC off
>[  579.397386] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  579.397439] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  579.397516] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  579.397574] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  579.397864] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  579.402022] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  579.402065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  579.402108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  579.402153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  579.402193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  579.402233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  579.402272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  579.402312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  579.402352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  579.402392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  579.402429] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  579.402526] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  579.402570] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  579.402646] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  579.402686] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  579.402964] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016dc0c138
>[  579.404111] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  579.404708] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  579.404748] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  579.404807] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  579.404846] [drm:hsw_audio_config_update [i915]] using automatic N
>[  579.421793] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  579.421867] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  579.422079] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  579.505275] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  579.505448] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  579.505632] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  579.505752] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  579.521920] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  579.522098] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  579.522297] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  579.526577] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  579.526656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  579.526737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  579.526820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  579.526895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  579.526969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  579.527043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  579.527125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  579.527198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  579.527272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  579.527346] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  579.527429] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  579.527583] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  579.527665] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  579.527780] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  579.527858] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  579.527968] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  579.528078] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  579.528161] [drm:intel_power_well_disable [i915]] disabling DC off
>[  579.528238] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  579.528306] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  579.528957] [drm:intel_power_well_disable [i915]] disabling always-on
>[  579.532168] [drm:drm_mode_addfb2] [FB:89]
>[  579.552239] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  579.552260] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  579.552382] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  579.552417] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  579.552454] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  579.552534] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  579.552578] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  579.552615] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  579.552653] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  579.552692] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  579.552728] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  579.552737] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  579.552771] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  579.552778] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  579.552816] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  579.552853] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  579.552891] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  579.552927] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  579.552963] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  579.553004] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  579.553043] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  579.553080] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  579.553118] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  579.553155] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  579.553192] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  579.553247] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  579.553297] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  579.553334] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  579.553754] [drm:intel_power_well_enable [i915]] enabling always-on
>[  579.553786] [drm:intel_power_well_enable [i915]] enabling DC off
>[  579.554075] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  579.554125] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  579.554158] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  579.554216] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  579.554565] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  579.558815] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  579.558858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  579.558902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  579.558946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  579.558986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  579.559026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  579.559066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  579.559105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  579.559145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  579.559185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  579.559224] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  579.559266] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  579.559307] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  579.559379] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  579.559419] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  579.559924] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  579.561082] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  579.561682] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  579.561723] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  579.561784] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  579.561823] [drm:hsw_audio_config_update [i915]] using automatic N
>[  579.578765] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  579.578838] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  579.579052] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  579.662237] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  579.662411] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  579.662585] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  579.662707] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  579.678916] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  579.679080] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  579.679264] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  579.683572] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  579.683648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  579.683728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  579.683810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  579.683885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  579.683958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  579.684032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  579.684114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  579.684187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  579.684261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  579.684334] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  579.684418] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  579.684572] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  579.684653] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  579.684766] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  579.684847] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  579.684955] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  579.685065] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  579.685146] [drm:intel_power_well_disable [i915]] disabling DC off
>[  579.685246] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  579.685321] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  579.685981] [drm:intel_power_well_disable [i915]] disabling always-on
>[  579.688366] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  579.722530] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  579.722576] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  579.722625] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  579.722675] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  579.722717] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  579.722763] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  579.722809] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  579.722854] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  579.722898] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  579.722940] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  579.722982] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  579.722991] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  579.723034] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  579.723038] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  579.723082] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  579.723125] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  579.723168] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  579.723211] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  579.723253] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  579.723303] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  579.723345] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  579.723391] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  579.723436] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  579.723551] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  579.723604] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  579.723669] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  579.723721] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  579.723780] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  579.723831] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  579.723884] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  579.723939] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  579.723990] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  579.724041] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  579.724094] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  579.724099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  579.724150] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  579.724155] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  579.724207] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  579.724258] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  579.724311] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  579.724363] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  579.724414] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  579.724468] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  579.724546] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  579.724599] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  579.724652] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  579.724705] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  579.724758] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  579.724815] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  579.724878] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  579.724933] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  579.724994] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  579.725046] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  579.725276] [drm:intel_power_well_enable [i915]] enabling always-on
>[  579.725321] [drm:intel_power_well_enable [i915]] enabling DC off
>[  579.725669] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  579.725751] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  579.725903] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  579.725956] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  579.726038] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  579.726285] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  579.729589] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  579.729644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  579.729699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  579.729761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  579.729815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  579.729869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  579.729923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  579.729978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  579.730031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  579.730086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  579.730139] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  579.730198] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  579.730255] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  579.730350] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  579.730404] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  579.730719] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  579.730774] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  579.824640] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  579.889378] [drm:wait_panel_status [i915]] Wait complete
>[  579.889457] [drm:edp_panel_on [i915]] Wait for panel power on
>[  579.889605] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  579.997960] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  579.998040] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  579.998119] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  579.998251] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  580.091150] [drm:wait_panel_status [i915]] Wait complete
>[  580.091263] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  580.091362] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  580.092988] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  580.093065] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  580.093149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  580.094313] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  580.094390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  580.095922] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  580.096305] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b53d8
>[  580.098500] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  580.098600] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  580.098647] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  580.098700] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  580.098768] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  580.098814] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  580.098879] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  580.098925] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  580.099136] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  580.099182] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  580.099546] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  580.101179] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  580.101774] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  580.101822] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  580.101895] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  580.101940] [drm:hsw_audio_config_update [i915]] using automatic N
>[  580.118875] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  580.118965] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  580.119245] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  580.119622] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  580.119711] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  580.119973] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  580.120627] Console: switching to colour frame buffer device 240x67
>[  580.427526] Console: switching to colour dummy device 80x25
>[  580.427869] [IGT] kms_pipe_crc_basic: executing
>[  580.453216] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  580.453284] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  580.453345] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  580.453400] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  580.453452] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  580.453580] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  580.454428] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  580.455031] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  580.455049] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  580.455056] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  580.455102] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  580.455165] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  580.455899] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  580.456340] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  580.456386] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  580.456442] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  580.465276] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.474132] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.483054] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.491942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.500828] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.509722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.518638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.527585] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.536468] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.545652] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.554624] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.563698] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.572688] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.581703] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.590701] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.599711] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.608692] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.617747] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.626741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.635715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.644693] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.653671] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.662641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.671611] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.680674] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.689670] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.698679] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.707653] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.716623] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.725700] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.734731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.743731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.743782] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  580.743798] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  580.743875] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  580.743983] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  580.826576] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  580.830787] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  580.830902] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  580.830915] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  580.831720] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  580.831731] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  580.831740] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  580.831749] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  580.832147] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  580.832162] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  580.832175] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  580.832187] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  580.832198] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  580.832210] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  580.832222] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  580.832234] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  580.832253] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  580.832265] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  580.832277] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  580.832289] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  580.832301] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  580.832313] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  580.832325] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  580.832343] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  580.832355] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  580.832367] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  580.832379] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  580.832391] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  580.832403] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  580.832415] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  580.832427] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  580.832546] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  580.847187] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  580.847234] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  580.847275] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  580.847309] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  580.847342] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  580.847374] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  580.847909] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  580.848377] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  580.848388] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  580.848392] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  580.848898] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  580.848942] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  580.849500] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  580.849872] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  580.850238] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  580.850275] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  580.858956] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.867692] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.876414] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.885276] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.894072] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.902925] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.911804] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.920713] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.929591] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.938460] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.947491] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.956606] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.965654] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.974643] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.983639] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  580.992617] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  581.001669] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  581.010657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  581.019630] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  581.028675] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  581.037657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  581.046650] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  581.055638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  581.064663] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  581.073645] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  581.082626] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  581.091658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  581.100655] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  581.109630] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  581.118672] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  581.127653] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  581.136629] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  581.136675] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  581.136690] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  581.138015] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  581.138131] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  581.219434] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  581.223693] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  581.223809] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  581.223822] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  581.224600] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  581.224611] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  581.224620] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  581.224626] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  581.225005] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  581.225017] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  581.225027] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  581.225037] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  581.225046] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  581.225060] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  581.225069] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  581.225082] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  581.225091] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  581.225101] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  581.225110] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  581.225120] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  581.225129] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  581.225139] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  581.225148] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  581.225165] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  581.225174] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  581.225183] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  581.225193] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  581.225202] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  581.225212] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  581.225221] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  581.225230] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  581.225239] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  581.227063] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-C
>[  581.316892] PM: Syncing filesystems ... done.
>[  581.320780] PM: Preparing system for sleep (mem)
>[  581.321571] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  581.323367] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  581.324981] PM: Suspending system (mem)
>[  581.325081] Suspending console(s) (use no_console_suspend to debug)
>[  581.714545] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  581.715337] sd 0:0:0:0: [sda] Stopping disk
>[  581.915660] ACPI : EC: event blocked
>[  581.930191] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  581.930226] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  581.930264] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  581.930302] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  581.930334] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  581.930368] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  581.930403] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  581.930436] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  581.930495] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  581.930527] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  581.930558] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  581.930566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  581.930598] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  581.930601] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  581.930634] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  581.930666] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  581.930699] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  581.930733] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  581.930765] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  581.930802] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  581.930834] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  581.930870] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  581.930902] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  581.930936] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  581.930970] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  581.931003] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  581.931045] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  581.931078] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  581.931113] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  581.931145] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  581.931179] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  581.931213] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  581.931245] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  581.931276] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  581.931308] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  581.931312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  581.931343] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  581.931346] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  581.931379] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  581.931411] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  581.931444] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  581.931503] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  581.931536] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  581.931570] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  581.931601] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  581.931636] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  581.931669] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  581.931703] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  581.931737] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  581.931769] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  581.931812] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 144000
>[  581.931855] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  581.931889] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  581.931928] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  581.931961] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  581.932122] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  581.951388] igb 0000:01:00.0: System wakeup enabled by ACPI
>[  582.136520] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  582.136575] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  582.151103] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  582.151140] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  582.151181] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  582.201891] [drm:wait_panel_status [i915]] Wait complete
>[  582.201928] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  582.201967] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  582.202070] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  582.202161] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  582.202213] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  582.210703] hpet1: lost 7161 rtc interrupts
>[  582.210855] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  582.210891] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  582.210925] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  582.211010] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  582.220520] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  582.220620] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  582.220705] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  582.224816] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  582.224852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  582.224887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  582.224924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  582.224959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  582.224994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  582.225027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  582.225062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  582.225096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  582.225131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  582.225164] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  582.225200] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  582.225237] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  582.225302] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  582.225342] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  582.225391] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  582.225434] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  582.225508] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  582.225554] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  582.226297] PM: suspend of devices complete after 517.075 msecs
>[  582.375498] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  582.375535] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  582.375567] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  582.375614] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  582.375646] [drm:intel_power_well_disable [i915]] disabling DC off
>[  582.375681] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  582.375711] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  582.376249] [drm:intel_power_well_disable [i915]] disabling always-on
>[  582.376279] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  582.376336] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 19200 kHz (VCO 0 kHz)
>[  582.380492] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  582.380521] [drm:intel_power_well_disable [i915]] disabling power well 1
>[  582.380557] [drm:skl_set_power_well [i915]] Disabling power well 1
>[  582.380590] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC
>[  582.380629] [drm:bxt_enable_dc9 [i915]] Enabling DC9
>[  582.380660] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08
>[  582.399257] PM: late suspend of devices complete after 172.841 msecs
>[  582.403758] ACPI : EC: interrupt blocked
>[  582.406103] xhci_hcd 0000:00:15.0: System wakeup enabled by ACPI
>[  582.406125] pcieport 0000:00:13.0: invalid power transition (from state 4 to 3)
>[  582.427865] PM: noirq suspend of devices complete after 28.492 msecs
>[  582.428060] ACPI: Preparing to enter system sleep state S3
>[  582.433280] ACPI : EC: EC stopped
>[  582.433283] PM: Saving platform NVS memory
>[  582.433295] Disabling non-boot CPUs ...
>[  582.447938] smpboot: CPU 1 is now offline
>[  582.463170] Broke affinity for irq 374
>[  582.464309] smpboot: CPU 2 is now offline
>[  582.474138] Broke affinity for irq 1
>[  582.474156] Broke affinity for irq 8
>[  582.474168] Broke affinity for irq 9
>[  582.474185] Broke affinity for irq 14
>[  582.474210] Broke affinity for irq 122
>[  582.474215] Broke affinity for irq 123
>[  582.474448] Broke affinity for irq 374
>[  582.475633] smpboot: CPU 3 is now offline
>[  582.480179] ACPI: Low-level resume complete
>[  582.480798] ACPI : EC: EC started
>[  582.480806] PM: Restoring platform NVS memory
>[  582.482076] Suspended for 14.892 seconds
>[  582.482544] Enabling non-boot CPUs ...
>[  582.484349] x86: Booting SMP configuration:
>[  582.484359] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  582.485464] Skipped synchronization checks as TSC is reliable.
>[  582.496442]  cache: parent cpu1 should not be sleeping
>[  582.505098] CPU1 is up
>[  582.505877] smpboot: Booting Node 0 Processor 2 APIC 0x4
>[  582.506750] Skipped synchronization checks as TSC is reliable.
>[  582.512789]  cache: parent cpu2 should not be sleeping
>[  582.519061] CPU2 is up
>[  582.519513] smpboot: Booting Node 0 Processor 3 APIC 0x6
>[  582.520192] Skipped synchronization checks as TSC is reliable.
>[  582.525063]  cache: parent cpu3 should not be sleeping
>[  582.530551] CPU3 is up
>[  582.533793] ACPI: Waking up from system sleep state S3
>[  582.569063] acpi LNXPOWER:04: Turning ON
>[  582.608913] acpi LNXPOWER:14: Turning OFF
>[  582.646261] acpi LNXPOWER:11: Turning OFF
>[  582.652107] acpi LNXPOWER:09: Turning OFF
>[  582.655807] acpi LNXPOWER:07: Turning OFF
>[  582.659328] acpi LNXPOWER:06: Turning OFF
>[  582.674419] ACPI : EC: interrupt unblocked
>[  582.685201] xhci_hcd 0000:00:15.0: System wakeup disabled by ACPI
>[  582.700129] PM: noirq resume of devices complete after 26.878 msecs
>[  582.700864] [drm:gen9_sanitize_dc_state [i915]] Resetting DC state tracking from 08 to 00
>[  582.700910] [drm:bxt_disable_dc9 [i915]] Disabling DC9
>[  582.700954] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  582.701016] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 4
>[  582.701321] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  582.701377] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  582.701445] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  582.703635] [drm:intel_power_well_enable [i915]] enabling always-on
>[  582.703677] [drm:intel_power_well_enable [i915]] enabling DC off
>[  582.703743] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  582.703801] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  582.703848] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  582.704007] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  582.704201] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  582.704384] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 1 already enabled, won't reprogram it
>[  582.704514] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>[  582.720727] PM: early resume of devices complete after 20.155 msecs
>[  582.721695] ACPI : EC: event unblocked
>[  582.721768] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x79df2018
>[  582.723345] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  582.723384] [drm:intel_opregion_setup [i915]] ASLE supported
>[  582.723402] igb 0000:01:00.0: System wakeup disabled by ACPI
>[  582.723936] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA)
>[  582.724094] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:10001010 hp_port:38
>[  582.724157] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  582.724205] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  582.724669] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 11.10
>[  582.729747] rtc_cmos 00:04: System wakeup disabled by ACPI
>[  582.732158] sd 0:0:0:0: [sda] Starting disk
>[  582.957846] atkbd serio0: Failed to deactivate keyboard on isa0060/serio0
>[  583.221817] atkbd serio0: Failed to enable keyboard on isa0060/serio0
>[  583.383905] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 659 ms
>[  583.384501] [drm:drm_dp_i2c_do_msg] native defer
>[  583.386302] [drm:drm_dp_i2c_do_msg] native defer
>[  583.387882] [drm:drm_dp_i2c_do_msg] native defer
>[  583.389373] [drm:drm_dp_i2c_do_msg] native defer
>[  583.390862] [drm:drm_dp_i2c_do_msg] native defer
>[  583.391942] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  583.392527] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  583.392866] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  583.393108] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  583.393348] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  583.393505] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[  583.393525] [drm] GuC firmware load skipped
>[  583.394427] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  583.394553] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:1800181a hp_port:38
>[  583.394825] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:33:pipe A] hw state readout: disabled
>[  583.394944] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:42:pipe B] hw state readout: disabled
>[  583.395059] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:49:pipe C] hw state readout: disabled
>[  583.395159] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0
>[  583.395257] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0
>[  583.395354] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0
>[  583.395453] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI A] hw state readout: disabled, pipe A
>[  583.395551] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI B] hw state readout: disabled, pipe A
>[  583.395640] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A
>[  583.395727] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B
>[  583.396031] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C
>[  583.396134] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:63:DDI C] hw state readout: disabled, pipe A
>[  583.396223] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST A] hw state readout: disabled, pipe A
>[  583.396312] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST B] hw state readout: disabled, pipe B
>[  583.396400] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:67:DP-MST C] hw state readout: disabled, pipe C
>[  583.396504] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:eDP-1] hw state readout: disabled
>[  583.396609] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-1] hw state readout: disabled
>[  583.396713] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:64:DP-2] hw state readout: disabled
>[  583.396876] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:68:HDMI-A-1] hw state readout: disabled
>[  583.396960] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][setup_hw_state]
>[  583.396999] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  583.397035] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  583.397072] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  583.397078] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  583.397114] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  583.397118] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  583.397155] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  583.397192] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  583.397229] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  583.397266] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  583.397302] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  583.397343] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  583.397379] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  583.397420] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  583.397458] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  583.397495] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  583.397532] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  583.397569] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  583.397610] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][setup_hw_state]
>[  583.397647] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  583.397683] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  583.397740] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  583.397744] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  583.397780] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  583.397784] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  583.397821] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  583.397858] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  583.397896] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  583.397933] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  583.397969] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  583.398008] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  583.398044] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  583.398082] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  583.398119] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  583.398156] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  583.398194] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  583.398230] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  583.398271] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][setup_hw_state]
>[  583.398308] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  583.398344] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  583.398380] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  583.398384] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  583.398420] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  583.398423] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  583.398461] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  583.398497] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  583.398534] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  583.398570] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  583.398607] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  583.398645] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  583.398681] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  583.398738] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  583.398778] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  583.398815] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  583.399003] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  583.399041] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  583.399078] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  583.399137] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  583.399175] [drm:intel_power_well_disable [i915]] disabling DC off
>[  583.399217] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  583.399251] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  583.399624] [drm:intel_power_well_disable [i915]] disabling always-on
>[  583.399792] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  583.399829] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  583.399872] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  583.399916] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  583.399952] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  583.399992] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  583.400031] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  583.400069] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  583.400106] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  583.400143] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  583.400179] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  583.400185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  583.400221] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  583.400225] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  583.400263] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  583.400299] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  583.400336] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  583.400373] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  583.400409] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  583.400448] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  583.400484] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  583.400522] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  583.400559] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  583.400596] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  583.400632] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  583.400669] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  583.400738] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  583.400776] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  583.400818] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  583.400854] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  583.400893] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  583.400930] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  583.400966] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  583.401003] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  583.401039] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  583.401043] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  583.401079] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  583.401083] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  583.401121] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  583.401157] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  583.401194] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  583.401230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  583.401267] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  583.401307] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  583.401343] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  583.401381] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  583.401418] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  583.401455] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  583.401491] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  583.401528] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  583.401567] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  583.401615] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  583.401654] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  583.401722] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  583.401759] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  583.401931] [drm:intel_power_well_enable [i915]] enabling always-on
>[  583.401963] [drm:intel_power_well_enable [i915]] enabling DC off
>[  583.402158] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  583.402215] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  583.403017] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  583.403057] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  583.403117] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  583.403316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  583.403354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  583.403401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  583.403440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  583.403480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  583.403519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  583.403557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  583.403598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  583.403637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  583.403677] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:59:DP-1]
>[  583.403828] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:64:DP-2]
>[  583.403875] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  583.403917] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  583.403957] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  583.404031] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  583.404070] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  583.404883] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  583.404924] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  583.404974] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000062
>[  583.405015] [drm:wait_panel_status [i915]] Wait complete
>[  583.405057] [drm:edp_panel_on [i915]] Wait for panel power on
>[  583.405101] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  583.477825] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  583.479965] ata1.00: supports DRM functions and may not be fully accessible
>[  583.480389] ata1.00: NCQ Send/Recv Log not supported
>[  583.480808] ata1.00: supports DRM functions and may not be fully accessible
>[  583.481227] ata1.00: NCQ Send/Recv Log not supported
>[  583.481233] ata1.00: configured for UDMA/133
>[  583.513489] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  583.513545] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  583.513598] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  583.513707] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  583.606875] [drm:wait_panel_status [i915]] Wait complete
>[  583.606982] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  583.607070] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  583.608640] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  583.608710] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  583.608842] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  583.609903] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  583.609973] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  583.611373] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  583.611793] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  583.614032] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  583.614146] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  583.614217] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  583.614297] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  583.614397] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  583.614468] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  583.614567] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  583.614638] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  583.614959] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  583.615030] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  583.616528] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  583.618790] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  583.619403] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  583.619474] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  583.619579] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  583.619649] [drm:hsw_audio_config_update [i915]] using automatic N
>[  583.636469] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  583.636573] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  583.636940] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  583.637244] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  583.637345] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  583.637616] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  583.637830] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  583.638263] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  583.638368] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  583.638445] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  583.638519] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  583.638589] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  583.638661] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  583.638914] [drm:intel_opregion_register [i915]] 4 outputs detected
>[  583.642209] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  583.642581] PM: resume of devices complete after 921.845 msecs
>[  583.642733] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:eDP-1] status updated from connected to connected
>[  583.642787] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  583.643396] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  583.643859] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-1] status updated from disconnected to disconnected
>[  583.643913] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  583.644871] PM: Finishing wakeup.
>[  583.644875] Restarting tasks ... done.
>[  583.662825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.673053] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.681876] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.690551] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.699824] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.708651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.717506] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.726281] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.735081] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.743849] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.752587] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.761370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.770114] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.778809] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.787561] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.796321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.805065] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.813834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.822573] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.831321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.839962] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.848674] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.857498] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.866232] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.874967] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.883807] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.892649] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.901807] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.910688] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.919613] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.928585] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.937461] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  583.937503] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  583.937516] [drm:drm_helper_hpd_irq_event] [CONNECTOR:64:DP-2] status updated from disconnected to disconnected
>[  583.937593] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  584.017730] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  584.021933] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  584.022036] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  584.022048] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  584.022060] [drm:drm_helper_hpd_irq_event] [CONNECTOR:68:HDMI-A-1] status updated from connected to connected
>[  584.024327] [drm:drm_mode_addfb2] [FB:70]
>[  584.045804] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  584.045911] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  584.046098] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  584.253828] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  584.253922] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  584.264646] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  584.264706] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  584.264900] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  584.316585] [drm:wait_panel_status [i915]] Wait complete
>[  584.316681] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  584.316935] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  584.317126] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  584.317212] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  584.317305] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  584.317396] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  584.317572] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  584.317665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  584.317846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  584.317953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  584.318047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  584.318145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  584.318240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  584.318339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  584.318435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  584.318536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  584.318629] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  584.318740] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  584.318886] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  584.318989] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  584.319669] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  584.319914] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  584.320556] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  584.320904] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  584.321105] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  584.321185] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  584.321321] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  584.338121] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  584.338291] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  584.338478] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  584.342833] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  584.342928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  584.343025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  584.343125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  584.343215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  584.343305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  584.343394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  584.343492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  584.343582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  584.343671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  584.343850] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  584.343958] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  584.344060] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  584.344160] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  584.344509] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  584.344602] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  584.344726] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  584.344942] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  584.345048] [drm:intel_power_well_disable [i915]] disabling DC off
>[  584.345140] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  584.345222] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  584.345892] [drm:intel_power_well_disable [i915]] disabling always-on
>[  584.346923] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  584.346969] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  584.347220] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  584.347311] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  584.347407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  584.347509] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  584.347594] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  584.347684] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  584.347864] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  584.347957] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  584.348057] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  584.348151] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  584.348245] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  584.348263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  584.348353] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  584.348372] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  584.348467] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  584.348563] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  584.348661] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  584.348797] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  584.348890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  584.348988] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  584.349087] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  584.349174] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  584.349273] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  584.349366] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  584.349464] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  584.349567] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  584.349663] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  584.350410] [drm:intel_power_well_enable [i915]] enabling always-on
>[  584.350470] [drm:intel_power_well_enable [i915]] enabling DC off
>[  584.350843] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  584.351421] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  584.351486] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  584.351580] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  584.351841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  584.351912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  584.351988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  584.352058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  584.352129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  584.352197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  584.352271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  584.352340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  584.352411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  584.352479] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  584.352557] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  584.352633] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  584.352812] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  584.352884] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  584.353114] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  584.353149] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  584.773887] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  584.790472] [drm] RC6 on
>[  584.901677] [drm:wait_panel_status [i915]] Wait complete
>[  584.901863] [drm:edp_panel_on [i915]] Wait for panel power on
>[  584.901968] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  585.010318] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  585.010414] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  585.010502] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  585.010681] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  585.103292] [drm:wait_panel_status [i915]] Wait complete
>[  585.103437] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  585.103558] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  585.105329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  585.105428] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  585.105533] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  585.106765] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  585.106954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  585.108515] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  585.108962] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  585.111687] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  585.111902] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  585.111998] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  585.112107] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  585.112243] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  585.112341] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  585.129002] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  585.129137] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  585.129467] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  585.212489] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  585.213035] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  585.421911] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  585.422068] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  585.430967] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  585.431079] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  585.431197] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  585.482981] [drm:wait_panel_status [i915]] Wait complete
>[  585.483111] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  585.483316] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  585.483459] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  585.483560] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  585.483660] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  585.483868] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  585.483996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  585.484122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  585.484234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  585.484343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  585.484450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  585.484555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  585.484667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  585.484840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  585.484944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  585.485053] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  585.485175] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  585.485289] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  585.485403] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  585.485556] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  585.485700] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  585.485897] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  585.486048] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  585.486159] [drm:intel_power_well_disable [i915]] disabling DC off
>[  585.486263] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  585.486355] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  585.487052] [drm:intel_power_well_disable [i915]] disabling always-on
>[  585.491271] [drm:drm_mode_addfb2] [FB:70]
>[  585.510830] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  585.510852] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  585.510974] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  585.511011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  585.511052] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  585.511096] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  585.511130] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  585.511169] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  585.511207] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  585.511244] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  585.511281] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  585.511316] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  585.511351] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  585.511359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  585.511393] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  585.511397] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  585.511433] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  585.511468] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  585.511504] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  585.511539] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  585.511574] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  585.511616] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  585.511650] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  585.511688] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  585.511778] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  585.511815] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  585.511855] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  585.511901] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL A
>[  585.511939] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe C
>[  585.512330] [drm:intel_power_well_enable [i915]] enabling always-on
>[  585.512363] [drm:intel_power_well_enable [i915]] enabling DC off
>[  585.512647] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  585.512724] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  585.512762] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  585.512818] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  585.513014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  585.513054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  585.513096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  585.513135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  585.513175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  585.513214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  585.513258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  585.513297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  585.513339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  585.513379] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  585.513425] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  585.513468] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  585.513542] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 4, on? 0) for crtc 49
>[  585.513580] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  585.514278] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  585.514320] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  585.569434] igb 0000:01:00.0 enp1s0: igb: enp1s0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX
>[  585.933903] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  586.002306] [drm:wait_panel_status [i915]] Wait complete
>[  586.002366] [drm:edp_panel_on [i915]] Wait for panel power on
>[  586.002431] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  586.110906] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  586.110985] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  586.111057] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  586.111211] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  586.204243] [drm:wait_panel_status [i915]] Wait complete
>[  586.204372] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  586.204480] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  586.206234] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  586.206323] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  586.206416] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  586.207969] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  586.208060] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  586.209749] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  586.210211] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  586.212835] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  586.212980] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  586.213065] [drm:intel_panel_enable_backlight [i915]] pipe C
>[  586.213162] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  586.213281] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  586.213368] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  586.229974] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  586.230085] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  586.230371] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  586.313506] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  586.313929] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  586.517871] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  586.517993] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  586.530923] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  586.531014] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  586.531111] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  586.583210] [drm:wait_panel_status [i915]] Wait complete
>[  586.583317] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 4, on? 1) for crtc 49
>[  586.583459] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  586.583539] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  586.583619] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  586.583795] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  586.583874] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  586.584048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  586.584148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  586.584236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  586.584319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  586.584423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  586.584515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  586.584612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  586.584706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  586.584866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  586.584957] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  586.585067] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  586.585163] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  586.585264] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  586.585405] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  586.585535] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  586.585629] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  586.585821] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  586.585921] [drm:intel_power_well_disable [i915]] disabling DC off
>[  586.586016] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  586.586098] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  586.586698] [drm:intel_power_well_disable [i915]] disabling always-on
>[  586.590571] [drm:drm_mode_addfb2] [FB:70]
>[  586.612754] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  586.612777] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  586.612899] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  586.612936] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  586.612976] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  586.613011] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  586.613050] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  586.613088] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  586.613125] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  586.613160] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  586.613195] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  586.613201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  586.613236] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  586.613240] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  586.613276] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  586.613311] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  586.613347] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  586.613384] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  586.613419] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  586.613460] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  586.613495] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  586.613533] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  586.613571] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  586.613608] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  586.613660] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  586.614575] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  586.614613] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  586.615151] [drm:intel_power_well_enable [i915]] enabling always-on
>[  586.615183] [drm:intel_power_well_enable [i915]] enabling DC off
>[  586.615469] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  586.615520] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  586.615556] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  586.615613] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  586.615913] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  586.620153] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  586.620222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  586.620261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  586.620300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  586.620335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  586.620370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  586.620405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  586.620440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  586.620475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  586.620510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  586.620545] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  586.620582] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  586.620617] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  586.620682] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  586.620780] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  586.621079] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016ce48958
>[  586.622081] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  586.622595] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  586.622630] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  586.622682] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  586.622754] [drm:hsw_audio_config_update [i915]] using automatic N
>[  586.639688] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  586.639816] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  586.640030] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  586.723165] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  586.723342] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  586.723413] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  586.723529] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  586.741227] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  586.741392] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  586.741550] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  586.745821] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  586.745901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  586.745984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  586.746068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  586.746142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  586.746216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  586.746290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  586.746372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  586.746446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  586.746519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  586.746593] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  586.746678] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  586.746854] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  586.746934] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  586.747054] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  586.747132] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  586.747237] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  586.747347] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  586.747426] [drm:intel_power_well_disable [i915]] disabling DC off
>[  586.747501] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  586.747572] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  586.748820] [drm:intel_power_well_disable [i915]] disabling always-on
>[  586.752462] [drm:drm_mode_addfb2] [FB:70]
>[  586.772070] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  586.772090] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  586.772205] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  586.772239] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  586.772276] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  586.772308] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  586.772344] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  586.772379] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][modeset]
>[  586.772414] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  586.772446] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  586.772478] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  586.772486] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  586.772517] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  586.772521] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  586.772555] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  586.772587] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  586.772620] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  586.772653] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  586.772685] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  586.772773] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  586.772811] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  586.772846] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  586.772883] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  586.772919] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  586.772972] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  586.773023] [drm:bxt_get_dpll [i915]] [CRTC:49:pipe C] using pre-allocated PORT PLL C
>[  586.773060] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  586.773423] [drm:intel_power_well_enable [i915]] enabling always-on
>[  586.773453] [drm:intel_power_well_enable [i915]] enabling DC off
>[  586.773837] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  586.774362] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  586.774394] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  586.774448] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  586.774751] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  586.778863] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  586.778900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  586.778938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  586.778977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  586.779012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  586.779047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  586.779082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  586.779117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  586.779152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  586.779187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  586.779222] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  586.779258] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  586.779294] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  586.779360] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 49
>[  586.779395] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  586.779679] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016dc0b7e8
>[  586.780744] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  586.781259] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  586.781294] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 32 bytes ELD
>[  586.781346] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  586.781378] [drm:hsw_audio_config_update [i915]] using automatic N
>[  586.798337] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  586.798413] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  586.798627] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  586.881969] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  586.882168] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  586.882248] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  586.882390] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  586.898199] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 49
>[  586.898363] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  586.898525] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  586.902827] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  586.902920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  586.903018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  586.903119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  586.903209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  586.903299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  586.903389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  586.903488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  586.903578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  586.903667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  586.903859] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  586.903967] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  586.904067] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  586.904170] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  586.904310] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  586.904403] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  586.904569] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  586.904700] [drm:intel_atomic_commit_tail [i915]] [CRTC:49:pipe C]
>[  586.904894] [drm:intel_power_well_disable [i915]] disabling DC off
>[  586.904985] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  586.905069] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  586.905674] [drm:intel_power_well_disable [i915]] disabling always-on
>[  586.908274] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  586.935284] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  586.935337] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  586.935391] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  586.935448] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  586.935495] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  586.935547] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  586.935598] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  586.935648] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  586.935697] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  586.935777] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  586.935825] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  586.935835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  586.935883] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  586.935888] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  586.935937] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  586.935985] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  586.936035] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  586.936085] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  586.936133] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  586.936188] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  586.936236] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  586.936286] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  586.936336] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  586.936386] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  586.936435] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  586.936496] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  586.936545] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  586.936598] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  586.936646] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  586.936695] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  586.936770] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  586.936818] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  586.936866] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  586.936913] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  586.936918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  586.936966] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  586.936970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  586.937019] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  586.937067] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  586.937117] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  586.937167] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  586.937215] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  586.937265] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  586.937313] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  586.937364] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  586.937414] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  586.937464] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  586.937514] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  586.937566] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  586.937628] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  586.937678] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  586.937771] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  586.937821] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  586.938028] [drm:intel_power_well_enable [i915]] enabling always-on
>[  586.938069] [drm:intel_power_well_enable [i915]] enabling DC off
>[  586.938369] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  586.938445] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  586.938597] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  586.938645] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  586.938771] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  586.938988] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  586.942840] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  586.942895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  586.942949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  586.943012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  586.943066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  586.943121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  586.943175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  586.943229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  586.943283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  586.943338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  586.943391] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  586.943450] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  586.943507] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  586.943601] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  586.943653] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  586.943972] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  586.944027] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  587.037924] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  587.102393] [drm:wait_panel_status [i915]] Wait complete
>[  587.102506] [drm:edp_panel_on [i915]] Wait for panel power on
>[  587.102625] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  587.210935] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  587.211040] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  587.211138] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  587.211326] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  587.303940] [drm:wait_panel_status [i915]] Wait complete
>[  587.304069] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  587.304178] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  587.305923] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  587.306008] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  587.306102] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  587.307299] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  587.307386] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  587.308937] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  587.309350] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016d8d0958
>[  587.312344] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  587.312485] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  587.312570] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  587.312667] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  587.312842] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  587.312926] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  587.313044] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  587.313131] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  587.313492] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  587.313579] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  587.314126] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016d8d5d28
>[  587.315853] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  587.316383] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  587.316418] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  587.316472] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  587.316504] [drm:hsw_audio_config_update [i915]] using automatic N
>[  587.333471] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  587.333545] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  587.333830] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  587.334091] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  587.334165] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  587.334398] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  587.334965] Console: switching to colour frame buffer device 240x67
>[  587.586300] Console: switching to colour dummy device 80x25
>[  587.586528] [IGT] kms_setmode: executing
>[  587.610397] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
>[  587.610821] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  587.610958] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  587.611216] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  587.813982] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  587.814124] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  587.830932] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  587.831033] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  587.831144] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  587.883052] [drm:wait_panel_status [i915]] Wait complete
>[  587.883171] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  587.883290] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  587.883495] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  587.883591] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  587.883695] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  587.883797] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  587.883978] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  587.884986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  587.885107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  587.885221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  587.885324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  587.885425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  587.885524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  587.885625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  587.885728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  587.885933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  587.886041] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  587.886165] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  587.886282] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  587.886394] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  587.900119] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  587.900272] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  587.900624] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  587.901040] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  587.901338] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  587.901466] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  587.901664] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  587.918571] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  587.918879] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  587.919086] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  587.923405] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  587.923509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  587.923619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  587.923730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  587.923950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  587.924057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  587.924160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  587.924278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  587.924381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  587.924486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  587.924587] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  587.924707] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  587.924867] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  587.924976] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  587.925124] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  587.925227] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  587.925367] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  587.925511] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  587.925620] [drm:intel_power_well_disable [i915]] disabling DC off
>[  587.925723] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  587.925869] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  587.926479] [drm:intel_power_well_disable [i915]] disabling always-on
>[  587.927330] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  587.928486] [drm:drm_mode_addfb2] [FB:70]
>[  588.009139] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  588.009601] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  588.010202] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  588.010993] [drm:drm_mode_addfb2] [FB:91]
>[  588.036371] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  588.036867] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  588.037425] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  588.038223] [drm:drm_mode_addfb2] [FB:92]
>[  588.063886] [IGT] kms_setmode: exiting, ret=0
>[  588.086131] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  588.086168] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  588.086205] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  588.086244] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  588.086276] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  588.086311] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  588.086343] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  588.086376] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  588.086409] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  588.086442] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  588.086473] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  588.086480] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  588.086511] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  588.086515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  588.086549] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  588.086581] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  588.086614] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  588.086646] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  588.086678] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  588.086792] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  588.086826] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  588.086862] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  588.086895] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  588.086929] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  588.086964] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  588.087007] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  588.087042] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  588.087079] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  588.087113] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  588.087149] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  588.087183] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  588.087217] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  588.087251] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  588.087286] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  588.087290] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  588.087325] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  588.087330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  588.087365] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  588.087399] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  588.087434] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  588.087468] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  588.087503] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  588.087539] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  588.087575] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  588.087608] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  588.087643] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  588.087677] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  588.087734] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  588.087772] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  588.087817] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  588.087852] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  588.087893] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  588.087929] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  588.088309] [drm:intel_power_well_enable [i915]] enabling always-on
>[  588.088339] [drm:intel_power_well_enable [i915]] enabling DC off
>[  588.088620] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  588.088671] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  588.089477] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  588.089514] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  588.089568] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  588.089934] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  588.093763] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  588.093801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  588.093835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  588.093877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  588.093910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  588.093945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  588.093980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  588.094015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  588.094050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  588.094085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  588.094120] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  588.094157] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  588.094193] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  588.094261] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  588.094295] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  588.095182] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  588.095221] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  588.333903] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  588.402316] [drm:wait_panel_status [i915]] Wait complete
>[  588.402364] [drm:edp_panel_on [i915]] Wait for panel power on
>[  588.402414] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 00000063
>[  588.510893] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  588.510956] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  588.511014] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  588.511178] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  588.603485] [drm:wait_panel_status [i915]] Wait complete
>[  588.603578] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  588.603654] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  588.605408] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  588.605487] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  588.605571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  588.606940] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  588.607022] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  588.608499] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  588.608895] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6678
>[  588.611230] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  588.611370] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  588.611448] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  588.611534] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  588.611647] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  588.611725] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  588.611918] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  588.612002] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  588.612310] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  588.612392] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  588.612939] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  588.614978] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  588.615507] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  588.615542] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  588.615594] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  588.615626] [drm:hsw_audio_config_update [i915]] using automatic N
>[  588.632598] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  588.632647] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  588.633075] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  588.633255] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  588.633300] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  588.633465] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  588.649398] Console: switching to colour frame buffer device 240x67
>[  588.957812] Console: switching to colour dummy device 80x25
>[  588.958159] [IGT] kms_sink_crc_basic: executing
>[  588.997154] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  588.997201] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  588.997240] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  588.997274] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  588.997307] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  588.997340] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  588.998092] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  588.998580] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  588.998592] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  588.998597] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  588.999156] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  588.999204] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  589.000117] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  589.000511] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  589.000998] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  589.001048] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  589.010176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.018849] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.027510] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.036183] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.044876] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.053491] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.062132] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.070781] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.079461] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.088138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.096789] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.105474] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.114161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.122967] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.131779] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.140519] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.149256] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.158012] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.166767] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.175501] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.184253] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.192988] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.201810] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.210638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.219620] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.228623] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.237613] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.246591] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.255583] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.264495] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.273396] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.282310] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  589.282352] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  589.282367] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  589.283928] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  589.284046] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  589.365126] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  589.369317] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  589.369433] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  589.369445] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  589.370385] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  589.370396] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  589.370405] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  589.370412] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  589.371048] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  589.371062] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  589.371076] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  589.371089] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  589.371099] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  589.371108] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  589.371117] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  589.371127] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  589.371136] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  589.371147] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  589.371157] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  589.371172] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  589.371182] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  589.371191] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  589.371201] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  589.371210] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  589.371219] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  589.371230] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  589.371239] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  589.371252] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  589.371261] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  589.371274] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  589.371283] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  589.371292] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  589.389088] [drm:drm_mode_addfb2] [FB:89]
>[  589.404050] [drm:drm_mode_addfb2] [FB:97]
>[  589.409401] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  589.409421] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  589.428304] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  589.428482] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  589.428547] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  589.428600] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  589.429020] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  589.637955] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  589.638079] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  589.646870] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  589.646960] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  589.647056] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  589.697303] [drm:wait_panel_status [i915]] Wait complete
>[  589.697406] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  589.697514] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  589.697707] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  589.698515] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  589.698629] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  589.699357] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  589.699449] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  589.699537] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  589.699653] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  589.699755] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  589.717153] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  589.717354] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  589.717584] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  589.721962] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  589.722068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  589.722169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  589.722285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  589.722387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  589.722488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  589.722589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  589.722700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  589.723485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  589.723568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  589.723653] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  589.724186] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  589.724275] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  589.724360] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  589.724512] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  589.724591] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  589.725413] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  589.725500] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  590.149924] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  590.201864] [drm:wait_panel_status [i915]] Wait complete
>[  590.201975] [drm:edp_panel_on [i915]] Wait for panel power on
>[  590.202091] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  590.310389] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  590.310450] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  590.310504] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  590.310626] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  590.402610] [drm:wait_panel_status [i915]] Wait complete
>[  590.402719] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  590.402923] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  590.404509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  590.404581] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  590.404658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  590.405918] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  590.406008] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  590.407583] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  590.408049] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  590.410315] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  590.410450] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  590.410536] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  590.410632] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  590.410833] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  590.410919] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  590.411041] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  590.411131] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  590.444258] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  590.444377] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  590.444683] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  590.445498] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  590.445600] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  590.445734] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  590.445991] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  590.446645] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  590.644581] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  590.650394] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  590.650442] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  590.877971] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  590.878333] [IGT] kms_sink_crc_basic: exiting, ret=0
>[  590.901185] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  590.901239] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  590.901296] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  590.901347] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  590.901401] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  590.901455] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  590.901509] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  590.901560] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  590.901610] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  590.901621] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  590.901671] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  590.901710] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  590.901763] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  590.901815] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  590.901866] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  590.901920] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  590.901973] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  590.902030] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  590.902080] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  590.902135] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  590.902187] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  590.902240] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  590.902293] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  590.902359] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  590.902426] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  590.902479] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  590.902539] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  590.902592] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  590.902931] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  591.109905] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  591.110534] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  591.129583] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  591.129691] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  591.129892] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  591.180121] [drm:wait_panel_status [i915]] Wait complete
>[  591.180293] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  591.180455] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  591.180737] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  591.180938] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  591.181034] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  591.181178] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  591.181490] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  591.182060] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  591.182159] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  591.182257] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  591.182444] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  591.185851] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  591.185953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  591.186054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  591.186167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  591.186267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  591.186367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  591.186467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  591.186567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  591.186667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  591.186825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  591.186924] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  591.187033] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  591.187140] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  591.187295] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  591.187393] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  591.187893] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  591.187995] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  591.637928] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  591.702242] [drm:wait_panel_status [i915]] Wait complete
>[  591.702350] [drm:edp_panel_on [i915]] Wait for panel power on
>[  591.702466] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  591.810837] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  591.810940] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  591.811038] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  591.811222] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  591.902735] [drm:wait_panel_status [i915]] Wait complete
>[  591.902958] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  591.903081] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  591.904945] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  591.905041] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  591.905147] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  591.906468] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  591.906565] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  591.908193] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  591.908646] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  591.910821] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  591.910896] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  591.910940] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  591.910990] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  591.911056] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  591.911100] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  591.911164] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  591.911207] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  591.927860] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  591.927926] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  591.928322] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  591.930636] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  591.931325] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  591.931391] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  591.931494] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  591.931557] [drm:hsw_audio_config_update [i915]] using automatic N
>[  591.948465] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  591.948605] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  591.948995] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  591.949344] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  591.949450] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  591.949793] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  591.950510] Console: switching to colour frame buffer device 240x67
>[  592.216027] Console: switching to colour dummy device 80x25
>[  592.216298] [IGT] pm_backlight: executing
>[  592.217197] [IGT] pm_backlight: starting subtest basic-brightness
>[  592.217456] [drm:intel_backlight_device_update_status [i915]] updating intel_backlight, brightness=0/96000
>[  592.217515] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  592.217589] [drm:intel_edp_backlight_power [i915]] panel power control backlight disable
>[  592.423521] [drm:intel_backlight_device_get_brightness [i915]] get backlight PWM = 0
>[  592.423949] [drm:intel_backlight_device_update_status [i915]] updating intel_backlight, brightness=96000/96000
>[  592.424009] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  592.424085] [drm:intel_edp_backlight_power [i915]] panel power control backlight enable
>[  592.425664] [drm:intel_backlight_device_get_brightness [i915]] get backlight PWM = 96000
>[  592.426024] [drm:intel_backlight_device_update_status [i915]] updating intel_backlight, brightness=48000/96000
>[  592.426082] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 48000
>[  592.426868] [drm:intel_backlight_device_get_brightness [i915]] get backlight PWM = 48000
>[  592.427282] [drm:intel_backlight_device_update_status [i915]] updating intel_backlight, brightness=96000/96000
>[  592.427342] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  592.428054] [IGT] pm_backlight: exiting, ret=0
>[  592.444639] Console: switching to colour frame buffer device 240x67
>[  592.690513] Console: switching to colour dummy device 80x25
>[  592.690963] [IGT] pm_rpm: executing
>[  592.715526] [drm:drm_mode_addfb2] [FB:70]
>[  592.799118] [drm:drm_mode_addfb2] [FB:97]
>[  593.829750] [IGT] pm_rpm: starting subtest basic-pci-d3-state
>[  593.829885] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  593.830054] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  593.830346] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  594.037872] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  594.038002] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  594.046923] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  594.047024] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  594.047118] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  594.098960] [drm:wait_panel_status [i915]] Wait complete
>[  594.099078] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  594.099196] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  594.099398] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  594.099499] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  594.099600] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  594.099697] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  594.099901] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  594.100152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  594.100272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  594.100388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  594.100489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  594.100594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  594.100695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  594.100880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  594.100985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  594.101090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  594.101193] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  594.101319] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  594.101439] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  594.101553] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  594.115008] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  594.115159] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  594.115538] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  594.115951] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  594.116313] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  594.116446] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  594.116659] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  594.133140] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  594.133344] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  594.133573] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  594.137961] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  594.138066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  594.138177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  594.138290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  594.138391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  594.138491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  594.138592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  594.138702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  594.138938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  594.139042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  594.139144] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  594.139268] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  594.139379] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  594.139491] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  594.139639] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  594.139809] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  594.139947] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  594.140096] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  594.140206] [drm:intel_power_well_disable [i915]] disabling DC off
>[  594.140309] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  594.140402] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  594.141078] [drm:intel_power_well_disable [i915]] disabling always-on
>[  594.142485] [drm:intel_runtime_suspend [i915]] Suspending device
>[  594.143783] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  594.144184] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  594.144738] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 19200 kHz (VCO 0 kHz)
>[  594.149217] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  594.149280] [drm:intel_power_well_disable [i915]] disabling power well 1
>[  594.149355] [drm:skl_set_power_well [i915]] Disabling power well 1
>[  594.149393] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC
>[  594.149433] [drm:bxt_enable_dc9 [i915]] Enabling DC9
>[  594.149469] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08
>[  594.149528] [drm:intel_runtime_suspend [i915]] Device suspended
>[  594.254273] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  594.254307] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  594.254505] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  594.254574] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  594.254645] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  594.254720] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  594.255002] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  594.255038] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  594.255075] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  594.255110] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  594.255145] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  594.255180] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  594.255213] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  594.255221] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  594.255253] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  594.255258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  594.255291] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  594.255327] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  594.255361] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  594.255396] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  594.255430] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  594.255468] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  594.255502] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  594.255536] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  594.255572] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  594.255606] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  594.255641] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  594.256085] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  594.256130] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  594.256164] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  594.268136] [drm:intel_runtime_resume [i915]] Resuming device
>[  594.268194] [drm:bxt_disable_dc9 [i915]] Disabling DC9
>[  594.268244] [drm:gen9_set_dc_state [i915]] Setting DC state from 08 to 00
>[  594.268311] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  594.268437] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  594.268548] [drm:skl_set_power_well [i915]] Enabling power well 1
>[  594.268614] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  594.268669] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os
>[  594.269273] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  594.273212] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  594.276212] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  594.276262] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  594.278715] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  594.280257] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  594.280288] [drm:intel_runtime_resume [i915]] Device resumed
>[  594.281172] [drm:intel_runtime_suspend [i915]] Suspending device
>[  594.281525] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  594.281585] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 19200 kHz (VCO 0 kHz)
>[  594.285827] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  594.285896] [drm:intel_power_well_disable [i915]] disabling power well 1
>[  594.285935] [drm:skl_set_power_well [i915]] Disabling power well 1
>[  594.285971] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC
>[  594.286009] [drm:bxt_enable_dc9 [i915]] Enabling DC9
>[  594.286044] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08
>[  594.286097] [drm:intel_runtime_suspend [i915]] Device suspended
>[  594.310017] [drm:intel_runtime_resume [i915]] Resuming device
>[  594.310073] [drm:bxt_disable_dc9 [i915]] Disabling DC9
>[  594.310123] [drm:gen9_set_dc_state [i915]] Setting DC state from 08 to 00
>[  594.310189] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  594.310259] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  594.310317] [drm:skl_set_power_well [i915]] Enabling power well 1
>[  594.310384] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  594.310439] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os
>[  594.310493] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  594.316813] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  594.319479] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  594.319527] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  594.321343] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  594.321899] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  594.321993] [drm:intel_runtime_resume [i915]] Device resumed
>[  594.322053] [drm:intel_power_well_enable [i915]] enabling always-on
>[  594.322098] [drm:intel_power_well_enable [i915]] enabling DC off
>[  594.322508] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  594.322584] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  594.322821] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  594.327078] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  594.327141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  594.327200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  594.327263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  594.327321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  594.327378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  594.327435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  594.327496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  594.327554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  594.327612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  594.327670] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  594.327814] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  594.327877] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  594.327982] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  594.328041] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  594.328326] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  594.328402] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  594.328462] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  594.549942] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  594.602122] [drm:wait_panel_status [i915]] Wait complete
>[  594.602224] [drm:edp_panel_on [i915]] Wait for panel power on
>[  594.602328] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  594.710749] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  594.710857] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  594.710956] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  594.711152] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  594.802534] [drm:wait_panel_status [i915]] Wait complete
>[  594.802677] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  594.802940] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  594.804653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  594.804757] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  594.804989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  594.806283] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  594.806390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  594.808000] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  594.808417] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b2548
>[  594.811110] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  594.811264] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  594.811362] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  594.811469] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  594.811600] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  594.811695] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  594.811923] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  594.812029] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  594.828248] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  594.828379] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  594.828707] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  594.829379] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  594.829487] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  594.829589] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  594.829686] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  594.829901] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  594.830721] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  594.831541] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:eDP-1] status updated from connected to connected
>[  594.831657] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  594.831855] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  594.832108] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  594.832628] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  594.836092] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  594.837129] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  594.837230] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  594.837492] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  594.837521] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-1] status updated from disconnected to disconnected
>[  594.837623] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  594.837712] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  594.838227] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  594.838356] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  594.848135] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  594.856796] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  594.865436] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  594.874067] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  594.882750] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  594.891401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  594.900066] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  594.908755] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  594.917408] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  594.926036] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  594.934766] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  594.943500] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  594.952246] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  594.960986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  594.969797] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  594.978535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  594.987277] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  594.996017] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.004772] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.013537] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.022331] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.031138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.040043] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.048938] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.057795] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.066667] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.075614] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.084583] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.093464] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.102322] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.111210] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.120094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.120135] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  595.120201] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  595.120275] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  595.120378] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  595.120397] [drm:drm_helper_hpd_irq_event] [CONNECTOR:64:DP-2] status updated from disconnected to disconnected
>[  595.120473] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  595.120537] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  595.120604] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  595.201949] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  595.206159] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  595.206261] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  595.206272] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  595.206353] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  595.206478] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  595.206502] [drm:drm_helper_hpd_irq_event] [CONNECTOR:68:HDMI-A-1] status updated from connected to connected
>[  595.206631] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  595.206724] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  595.206945] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  595.207036] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  595.207129] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  595.208026] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  595.208668] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:eDP-1] status updated from connected to connected
>[  595.208886] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  595.208969] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  595.209060] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  595.209178] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  595.210345] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  595.211034] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  595.211095] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  595.211182] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  595.211199] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-1] status updated from disconnected to disconnected
>[  595.211261] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  595.211316] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  595.211373] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  595.211451] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  595.220397] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.229318] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.238367] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.247329] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.256364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.265366] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.274423] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.283440] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.292433] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.301438] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.310454] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.319528] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.328626] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.337741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.346918] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.355925] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.364939] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.373990] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.382993] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.391995] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.401071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.410195] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.419258] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.428265] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.437273] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.446298] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.455346] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.464363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.473395] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.482452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.491450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.500164] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  595.500189] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  595.500221] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  595.500257] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  595.500309] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  595.500320] [drm:drm_helper_hpd_irq_event] [CONNECTOR:64:DP-2] status updated from disconnected to disconnected
>[  595.500356] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  595.500386] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  595.500417] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  595.580515] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  595.584764] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  595.584830] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  595.584837] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  595.584886] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  595.584965] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  595.585012] [drm:drm_helper_hpd_irq_event] [CONNECTOR:68:HDMI-A-1] status updated from connected to connected
>[  595.585526] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  595.586939] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  595.789985] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  595.790575] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  595.796662] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  595.796833] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  595.796923] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  595.848625] [drm:wait_panel_status [i915]] Wait complete
>[  595.848873] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  595.849120] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  595.849258] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  595.849334] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  595.849408] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  595.849567] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  595.849641] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  595.849982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  595.850075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  595.850153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  595.850232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  595.850307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  595.850385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  595.850461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  595.850536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  595.850608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  595.850683] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  595.850829] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  595.850910] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  595.850997] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  595.851171] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  595.851413] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  595.851539] [drm:intel_power_well_disable [i915]] disabling DC off
>[  595.851619] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  595.851686] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  595.852338] [drm:intel_power_well_disable [i915]] disabling always-on
>[  595.853493] [drm:intel_runtime_suspend [i915]] Suspending device
>[  595.853831] [IGT] pm_rpm: exiting, ret=0
>[  595.854543] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  595.855200] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 19200 kHz (VCO 0 kHz)
>[  595.859345] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  595.859386] [drm:intel_power_well_disable [i915]] disabling power well 1
>[  595.859433] [drm:skl_set_power_well [i915]] Disabling power well 1
>[  595.859476] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC
>[  595.859523] [drm:bxt_enable_dc9 [i915]] Enabling DC9
>[  595.859565] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08
>[  595.859625] [drm:intel_runtime_suspend [i915]] Device suspended
>[  595.884183] [drm:intel_runtime_resume [i915]] Resuming device
>[  595.884253] [drm:bxt_disable_dc9 [i915]] Disabling DC9
>[  595.884315] [drm:gen9_set_dc_state [i915]] Setting DC state from 08 to 00
>[  595.884396] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  595.884549] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  595.884685] [drm:skl_set_power_well [i915]] Enabling power well 1
>[  595.884848] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  595.884921] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os
>[  595.884993] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  595.889453] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  595.892696] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  595.892794] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  595.894635] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  595.895770] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  595.895839] [drm:intel_runtime_resume [i915]] Device resumed
>[  595.899236] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  595.899272] [drm:intel_power_well_enable [i915]] enabling always-on
>[  595.899302] [drm:intel_power_well_enable [i915]] enabling DC off
>[  595.899620] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  595.899666] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  595.900626] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  595.900666] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  595.900876] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  595.900911] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  595.900971] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  595.901046] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  595.901082] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  596.301890] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  596.401294] [drm:wait_panel_status [i915]] Wait complete
>[  596.401372] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000068
>[  596.401436] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[  596.509860] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  596.509954] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  596.510042] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  596.510246] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  596.606626] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  596.607415] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:eDP-1] status updated from connected to connected
>[  596.607530] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  596.607621] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  596.607716] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  596.607989] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  596.609049] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  596.609691] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  596.609917] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  596.610055] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  596.610084] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-1] status updated from disconnected to disconnected
>[  596.610189] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  596.610281] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  596.610376] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  596.610533] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  596.619738] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.628677] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.637609] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.646637] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.655638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.664636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.673688] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.682719] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.691767] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.700881] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.709843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.718876] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.727840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.736888] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.745859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.754892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.763853] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.772885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.781850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.790880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.799838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.808872] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.817882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.826840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.835892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.844863] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.853881] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.862841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.871876] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.880840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.889874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.898889] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  596.898939] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  596.899030] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  596.899129] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  596.899265] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  596.899289] [drm:drm_helper_hpd_irq_event] [CONNECTOR:64:DP-2] status updated from disconnected to disconnected
>[  596.899393] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  596.899482] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  596.899574] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  596.980982] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  596.985169] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  596.985284] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  596.985297] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  596.985388] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  596.985525] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  596.985550] [drm:drm_helper_hpd_irq_event] [CONNECTOR:68:HDMI-A-1] status updated from connected to connected
>[  596.986332] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  596.986437] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  596.986549] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  596.986668] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  596.986864] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  596.986978] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  596.987082] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  596.987192] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  596.987300] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  596.987408] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  596.987513] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  596.987535] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  596.987633] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  596.987652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  596.987751] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  596.987921] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  596.988023] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  596.988127] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  596.988225] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  596.988335] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  596.988436] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  596.988538] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  596.988642] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  596.988745] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  596.988931] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  596.989063] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  596.989168] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  596.989280] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  596.989385] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  596.989490] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  596.989593] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  596.989702] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  596.989863] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  596.989962] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  596.989988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  596.990086] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  596.990106] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  596.990208] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  596.990309] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  596.990420] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  596.990525] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  596.990634] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  596.990746] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  596.990929] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  596.991032] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  596.991132] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  596.991234] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  596.991337] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  596.991449] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  596.991572] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  596.991675] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  596.991883] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  596.991927] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  596.992127] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  596.992173] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  596.992239] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  596.993223] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  596.997476] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  596.997522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  596.997564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  596.997614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  596.997657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  596.997698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  596.997814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  596.997856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  596.997899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  596.997941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  596.997984] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  596.998032] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  596.998077] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  596.998157] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  596.998198] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  596.998504] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  596.998548] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  596.998601] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000068
>[  596.998643] [drm:wait_panel_status [i915]] Wait complete
>[  596.998689] [drm:edp_panel_on [i915]] Wait for panel power on
>[  596.998835] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 0000006b
>[  597.199505] [drm:wait_panel_status [i915]] Wait complete
>[  597.201167] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  597.201250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  597.201335] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  597.202443] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  597.202527] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  597.203929] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  597.204291] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  597.206606] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  597.206812] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  597.206893] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  597.206986] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  597.207098] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  597.207178] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  597.207288] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  597.207370] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  597.207672] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  597.207832] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  597.208272] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b12a8
>[  597.210587] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  597.211315] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  597.211398] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  597.211539] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  597.211597] [drm:hsw_audio_config_update [i915]] using automatic N
>[  597.228315] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  597.228373] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  597.228567] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  597.228941] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  597.229039] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  597.229313] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  597.245378] Console: switching to colour frame buffer device 240x67
>[  597.492091] Console: switching to colour dummy device 80x25
>[  597.492316] [IGT] pm_rpm: executing
>[  597.516283] [drm:drm_mode_addfb2] [FB:91]
>[  597.600075] [drm:drm_mode_addfb2] [FB:97]
>[  598.627454] [IGT] pm_rpm: starting subtest basic-rte
>[  598.627636] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  598.628204] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  598.628646] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  598.837966] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  598.838121] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  598.840755] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  598.840940] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  598.841058] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  598.892199] [drm:wait_panel_status [i915]] Wait complete
>[  598.892318] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  598.892438] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  598.892640] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  598.893217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  598.893337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  598.893434] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  598.893538] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  598.893639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  598.893742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  598.893843] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  598.894020] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  598.894132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  598.894236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  598.894343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  598.894447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  598.894553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  598.894655] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  598.895037] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  598.895152] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  598.895261] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  598.911623] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  598.911919] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  598.912320] [drm:drm_mode_setcrtc] [CRTC:42:pipe B]
>[  598.912589] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  598.913050] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  598.913179] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  598.914091] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  598.928707] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  598.928980] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  598.929187] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  598.933471] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  598.933565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  598.933666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  598.933887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  598.933980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  598.934074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  598.934166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  598.934271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  598.934362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  598.934455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  598.934546] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  598.934653] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  598.934841] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  598.934951] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  598.935099] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  598.935203] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  598.935342] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  598.935487] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  598.935596] [drm:intel_power_well_disable [i915]] disabling DC off
>[  598.935699] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  598.935855] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  598.936444] [drm:intel_power_well_disable [i915]] disabling always-on
>[  598.936563] [drm:intel_runtime_suspend [i915]] Suspending device
>[  598.937729] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  598.937881] [drm:drm_mode_setcrtc] [CRTC:49:pipe C]
>[  598.938301] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 19200 kHz (VCO 0 kHz)
>[  598.942563] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  598.942635] [drm:intel_power_well_disable [i915]] disabling power well 1
>[  598.942718] [drm:skl_set_power_well [i915]] Disabling power well 1
>[  598.942893] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC
>[  598.942978] [drm:bxt_enable_dc9 [i915]] Enabling DC9
>[  598.943055] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08
>[  598.943161] [drm:intel_runtime_suspend [i915]] Device suspended
>[  599.038598] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  599.038650] [drm:drm_mode_setcrtc] [CONNECTOR:51:eDP-1]
>[  599.039083] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  599.039188] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  599.039296] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  599.039408] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  599.039508] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  599.039611] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  599.039714] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  599.039921] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  599.040023] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  599.040129] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  599.040234] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  599.040256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  599.040353] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  599.040375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  599.040482] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  599.040582] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  599.040685] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  599.040848] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  599.040959] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  599.041073] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  599.041178] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  599.041287] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  599.041395] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  599.041497] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  599.041607] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  599.041757] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  599.041960] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  599.042065] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  599.054039] [drm:intel_runtime_resume [i915]] Resuming device
>[  599.054113] [drm:bxt_disable_dc9 [i915]] Disabling DC9
>[  599.054180] [drm:gen9_set_dc_state [i915]] Setting DC state from 08 to 00
>[  599.054267] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  599.054358] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  599.054434] [drm:skl_set_power_well [i915]] Enabling power well 1
>[  599.054521] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  599.054595] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os
>[  599.054666] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  599.059034] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  599.062647] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  599.062708] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  599.065214] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  599.065872] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  599.066089] [drm:intel_runtime_resume [i915]] Device resumed
>[  599.066489] [drm:intel_runtime_suspend [i915]] Suspending device
>[  599.067682] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  599.068235] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 19200 kHz (VCO 0 kHz)
>[  599.072450] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  599.072518] [drm:intel_power_well_disable [i915]] disabling power well 1
>[  599.072559] [drm:skl_set_power_well [i915]] Disabling power well 1
>[  599.072596] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC
>[  599.072637] [drm:bxt_enable_dc9 [i915]] Enabling DC9
>[  599.072672] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08
>[  599.072784] [drm:intel_runtime_suspend [i915]] Device suspended
>[  599.096919] [drm:intel_runtime_resume [i915]] Resuming device
>[  599.096970] [drm:bxt_disable_dc9 [i915]] Disabling DC9
>[  599.097014] [drm:gen9_set_dc_state [i915]] Setting DC state from 08 to 00
>[  599.097074] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  599.097137] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  599.097188] [drm:skl_set_power_well [i915]] Enabling power well 1
>[  599.097248] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  599.097296] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os
>[  599.097343] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  599.103625] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  599.106354] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  599.106404] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  599.108233] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  599.108849] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  599.108899] [drm:intel_runtime_resume [i915]] Device resumed
>[  599.108959] [drm:intel_power_well_enable [i915]] enabling always-on
>[  599.109009] [drm:intel_power_well_enable [i915]] enabling DC off
>[  599.109385] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  599.109466] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  599.109665] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  599.113963] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  599.114024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  599.114083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  599.114147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  599.114206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  599.114264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  599.114322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  599.114383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  599.114441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  599.114499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  599.114557] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  599.114620] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  599.114681] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  599.114859] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  599.114918] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  599.115203] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  599.115277] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  599.115337] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  599.349900] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  599.402042] [drm:wait_panel_status [i915]] Wait complete
>[  599.402126] [drm:edp_panel_on [i915]] Wait for panel power on
>[  599.402212] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  599.510618] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  599.510698] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  599.510770] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  599.510907] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  599.603219] [drm:wait_panel_status [i915]] Wait complete
>[  599.603338] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  599.603438] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  599.605196] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  599.605277] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  599.605362] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  599.606475] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  599.606565] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  599.608048] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  599.608409] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b6fc8
>[  599.610996] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  599.611129] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  599.611206] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  599.611293] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  599.611398] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  599.611475] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  599.611579] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  599.611657] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  599.627926] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  599.627974] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  599.628146] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  599.628381] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  599.628419] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  599.628454] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  599.628486] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  599.628521] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  599.629154] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  599.629635] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:eDP-1] status updated from connected to connected
>[  599.629687] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  599.629780] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  599.629847] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  599.629904] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  599.631373] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  599.631794] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  599.631834] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  599.631894] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  599.631910] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-1] status updated from disconnected to disconnected
>[  599.631949] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  599.631985] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  599.632022] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  599.632076] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  599.640834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.649607] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.658373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.667272] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.676154] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.685044] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.693979] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.702916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.711854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.720873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.729869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.738945] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.747971] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.756980] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.765976] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.775045] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.784131] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.793133] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.802162] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.811185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.820191] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.829217] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.838239] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.847242] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.856442] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.865455] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.874486] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.883513] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.892651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.901751] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.910931] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.919950] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  599.920005] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  599.920098] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  599.920210] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  599.920349] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  599.920373] [drm:drm_helper_hpd_irq_event] [CONNECTOR:64:DP-2] status updated from disconnected to disconnected
>[  599.920476] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  599.920564] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  599.920656] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  600.002151] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  600.006340] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  600.006456] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  600.006468] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  600.006557] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  600.006695] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  600.006846] [drm:drm_helper_hpd_irq_event] [CONNECTOR:68:HDMI-A-1] status updated from connected to connected
>[  600.007226] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  600.007588] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  600.213907] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  600.214068] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  600.228652] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  600.228912] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  600.229036] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  600.280682] [drm:wait_panel_status [i915]] Wait complete
>[  600.280891] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  600.281013] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  600.281219] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  600.281316] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  600.281423] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  600.281525] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  600.281694] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  600.281794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  600.281969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  600.282079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  600.282183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  600.282289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  600.282393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  600.282505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  600.282608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  600.282715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  600.282870] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  600.282993] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  600.283101] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  600.283215] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  600.283359] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  600.283509] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  600.283646] [drm:intel_power_well_disable [i915]] disabling DC off
>[  600.283831] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  600.283921] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  600.284538] [drm:intel_power_well_disable [i915]] disabling always-on
>[  600.286131] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  600.286231] [drm:intel_power_well_enable [i915]] enabling always-on
>[  600.286318] [drm:intel_power_well_enable [i915]] enabling DC off
>[  600.286457] [IGT] pm_rpm: exiting, ret=0
>[  600.286663] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  600.287693] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  600.288487] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  600.288657] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  600.288755] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  600.288913] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  600.289209] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  600.289250] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  600.733930] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  600.802187] [drm:wait_panel_status [i915]] Wait complete
>[  600.802310] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000068
>[  600.802413] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[  600.910742] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  600.910855] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  600.910954] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  600.911129] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  601.006685] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  601.007416] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:eDP-1] status updated from connected to connected
>[  601.007528] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  601.007620] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  601.007715] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  601.007948] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  601.008965] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  601.009610] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  601.009709] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  601.009970] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  601.009999] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-1] status updated from disconnected to disconnected
>[  601.010101] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  601.010194] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  601.010290] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  601.010415] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  601.019535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.028391] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.037317] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.046250] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.055189] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.064186] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.073192] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.082195] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.091199] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.100198] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.109203] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.118212] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.127219] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.136223] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.145226] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.154229] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.163235] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.172240] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.181244] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.190248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.199257] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.208260] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.217258] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.226379] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.235383] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.244386] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.253390] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.262395] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.271397] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.280401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.289401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.298405] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  601.298454] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  601.298544] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  601.298644] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  601.298905] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  601.298935] [drm:drm_helper_hpd_irq_event] [CONNECTOR:64:DP-2] status updated from disconnected to disconnected
>[  601.299039] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  601.299130] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  601.299224] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  601.380510] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  601.384761] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  601.384874] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  601.384887] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  601.384974] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  601.385113] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  601.385139] [drm:drm_helper_hpd_irq_event] [CONNECTOR:68:HDMI-A-1] status updated from connected to connected
>[  601.385903] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  601.386015] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  601.386127] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  601.386246] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  601.386348] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  601.386461] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  601.386566] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  601.386673] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  601.386840] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  601.386947] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  601.387047] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  601.387071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  601.387168] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  601.387182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  601.387286] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  601.387392] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  601.387497] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  601.387601] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  601.387701] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  601.387886] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  601.387986] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  601.388091] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  601.388199] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  601.388306] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  601.388412] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  601.388539] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  601.388642] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  601.388747] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  601.388921] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  601.389029] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  601.389133] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  601.389240] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  601.389347] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  601.389445] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  601.389469] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  601.389566] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  601.389588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  601.389694] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  601.389846] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  601.389947] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  601.390050] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  601.390155] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  601.390265] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  601.390364] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  601.390462] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  601.390563] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  601.390663] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  601.390834] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  601.390946] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  601.391068] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  601.391175] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  601.391296] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  601.391403] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  601.391665] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  601.391748] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  601.391816] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  601.391985] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  601.396217] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  601.396265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  601.396311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  601.396364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  601.396410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  601.396456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  601.396501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  601.396547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  601.396593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  601.396639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  601.396684] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  601.396794] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  601.396844] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  601.396930] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  601.396975] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  601.397204] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  601.397254] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  601.397312] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000068
>[  601.397359] [drm:wait_panel_status [i915]] Wait complete
>[  601.397410] [drm:edp_panel_on [i915]] Wait for panel power on
>[  601.397464] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 0000006b
>[  601.598314] [drm:wait_panel_status [i915]] Wait complete
>[  601.599909] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  601.599979] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  601.600049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  601.601155] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  601.601236] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  601.602590] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  601.602957] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b1bf8
>[  601.605234] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  601.605368] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  601.605447] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  601.605534] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  601.605642] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  601.605719] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  601.605898] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  601.605986] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  601.606299] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  601.606381] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  601.606906] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0008
>[  601.609042] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  601.609571] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  601.609606] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  601.609658] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  601.609690] [drm:hsw_audio_config_update [i915]] using automatic N
>[  601.626647] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  601.626827] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  601.627053] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  601.627298] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  601.627369] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  601.627588] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  601.643530] Console: switching to colour frame buffer device 240x67
>[  601.918446] Console: switching to colour dummy device 80x25
>[  601.918921] [IGT] pm_rps: executing
>[  601.955448] [IGT] pm_rps: starting subtest basic-api
>[  601.962954] [IGT] pm_rps: exiting, ret=0
>[  602.010144] Console: switching to colour frame buffer device 240x67
>[  602.260316] Console: switching to colour dummy device 80x25
>[  602.260572] [IGT] prime_busy: executing
>[  602.376296] [IGT] prime_busy: starting subtest basic-after-default
>[  603.400018] [IGT] prime_busy: exiting, ret=0
>[  603.456202] Console: switching to colour frame buffer device 240x67
>[  603.717179] Console: switching to colour dummy device 80x25
>[  603.717525] [IGT] prime_busy: executing
>[  603.760239] [IGT] prime_busy: starting subtest basic-before-default
>[  604.117832] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  604.117903] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  604.912998] [IGT] prime_busy: exiting, ret=0
>[  604.960192] Console: switching to colour frame buffer device 240x67
>[  605.211448] Console: switching to colour dummy device 80x25
>[  605.211916] [IGT] prime_busy: executing
>[  605.387417] [IGT] prime_busy: starting subtest basic-wait-after-default
>[  606.366138] [IGT] prime_busy: exiting, ret=0
>[  606.410283] Console: switching to colour frame buffer device 240x67
>[  606.658590] Console: switching to colour dummy device 80x25
>[  606.658918] [IGT] prime_busy: executing
>[  606.747101] [IGT] prime_busy: starting subtest basic-wait-before-default
>[  607.825153] [IGT] prime_busy: exiting, ret=0
>[  607.877080] Console: switching to colour frame buffer device 240x67
>[  608.127393] Console: switching to colour dummy device 80x25
>[  608.127804] [IGT] prime_self_import: executing
>[  608.128199] [IGT] prime_self_import: starting subtest basic-llseek-bad
>[  608.153480] [IGT] prime_self_import: exiting, ret=0
>[  608.210328] Console: switching to colour frame buffer device 240x67
>[  608.473115] Console: switching to colour dummy device 80x25
>[  608.473461] [IGT] prime_self_import: executing
>[  608.473947] [IGT] prime_self_import: starting subtest basic-llseek-size
>[  608.500813] [IGT] prime_self_import: exiting, ret=0
>[  608.560389] Console: switching to colour frame buffer device 240x67
>[  608.812502] Console: switching to colour dummy device 80x25
>[  608.812980] [IGT] prime_self_import: executing
>[  608.813383] [IGT] prime_self_import: starting subtest basic-with_fd_dup
>[  608.855732] [IGT] prime_self_import: exiting, ret=0
>[  608.910196] Console: switching to colour frame buffer device 240x67
>[  609.160297] Console: switching to colour dummy device 80x25
>[  609.160592] [IGT] prime_self_import: executing
>[  609.161096] [IGT] prime_self_import: starting subtest basic-with_one_bo
>[  609.250956] [IGT] prime_self_import: exiting, ret=0
>[  609.290338] Console: switching to colour frame buffer device 240x67
>[  609.547866] Console: switching to colour dummy device 80x25
>[  609.548157] [IGT] prime_self_import: executing
>[  609.548484] [IGT] prime_self_import: starting subtest basic-with_one_bo_two_files
>[  609.575880] [IGT] prime_self_import: exiting, ret=0
>[  609.626933] Console: switching to colour frame buffer device 240x67
>[  609.878760] Console: switching to colour dummy device 80x25
>[  609.879154] [IGT] prime_self_import: executing
>[  609.879572] [IGT] prime_self_import: starting subtest basic-with_two_bos
>[  609.921486] [IGT] prime_self_import: exiting, ret=0
>[  609.960180] Console: switching to colour frame buffer device 240x67
>[  610.218987] Console: switching to colour dummy device 80x25
>[  610.219327] [IGT] prime_vgem: executing
>[  610.276421] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  610.316372] [IGT] prime_vgem: starting subtest basic-busy-default
>[  610.332000] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  610.335186] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  610.335527] [IGT] prime_vgem: exiting, ret=0
>[  610.393662] Console: switching to colour frame buffer device 240x67
>[  610.645318] Console: switching to colour dummy device 80x25
>[  610.645568] [IGT] prime_vgem: executing
>[  610.701480] [IGT] prime_vgem: starting subtest basic-fence-flip
>[  610.701603] [drm:vgem_gem_dumb_create [vgem]] Created object of size 3145728
>[  610.709850] [drm:drm_mode_addfb2] [FB:70]
>[  610.709940] [drm:vgem_gem_dumb_create [vgem]] Created object of size 3145728
>[  610.715964] [drm:drm_mode_addfb2] [FB:89]
>[  610.716057] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  610.716103] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  610.716142] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  610.716176] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  610.716209] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  610.716243] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  610.716292] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  610.716333] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  610.716915] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  610.717466] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  610.717479] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  610.717484] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  610.717511] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  610.717555] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  610.718337] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  610.718736] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  610.718753] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  610.718793] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  610.727465] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.736175] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.744819] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.753475] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.762101] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.770810] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.779540] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.788356] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.797208] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.806090] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.814944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.823804] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.832687] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.841701] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.850681] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.859656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.868843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.877753] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.886770] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.895895] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.904897] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.913867] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.922864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.931910] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.940883] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.949866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.958915] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.967891] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.976870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.985936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  610.994919] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  611.003912] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  611.003959] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  611.003975] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  611.004014] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  611.004122] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  611.085294] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  611.089473] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  611.089589] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  611.089601] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  611.091013] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  611.091025] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  611.091034] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  611.091040] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  611.091425] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  611.091437] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  611.091447] [drm:drm_mode_debug_printmodeline] Modeline 96:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  611.091456] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  611.091466] [drm:drm_mode_debug_printmodeline] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  611.091475] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  611.091485] [drm:drm_mode_debug_printmodeline] Modeline 80:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  611.091494] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  611.091504] [drm:drm_mode_debug_printmodeline] Modeline 77:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  611.091513] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  611.091523] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  611.091532] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  611.091542] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  611.091551] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  611.091560] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  611.091570] [drm:drm_mode_debug_printmodeline] Modeline 83:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  611.091579] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  611.091588] [drm:drm_mode_debug_printmodeline] Modeline 99:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  611.091598] [drm:drm_mode_debug_printmodeline] Modeline 75:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  611.091607] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  611.091616] [drm:drm_mode_debug_printmodeline] Modeline 100:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  611.091625] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  611.091635] [drm:drm_mode_debug_printmodeline] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  611.091644] [drm:drm_mode_debug_printmodeline] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  611.093080] [drm:drm_mode_setcrtc] [CRTC:33:pipe A]
>[  611.093131] [drm:drm_mode_setcrtc] [CONNECTOR:68:HDMI-A-1]
>[  611.093470] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  611.093574] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  611.093689] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  611.093881] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  611.093987] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  611.094092] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  611.094194] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  611.094298] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  611.094396] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  611.094414] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  611.094511] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  611.094525] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  611.094633] [drm:intel_dump_pipe_config [i915]] crtc timings: 75000 1024 1048 1184 1328 768 771 777 806, type: 0x40 flags: 0xa
>[  611.094732] [drm:intel_dump_pipe_config [i915]] port clock: 75000, pipe src size: 1024x768
>[  611.094875] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  611.094977] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  611.095082] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  611.095190] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  611.095291] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  611.095399] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  611.095503] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  611.095603] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  611.095707] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  611.095855] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  611.095915] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  611.095978] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL C
>[  611.096025] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe A
>[  611.097622] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  611.301891] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  611.301966] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  611.308535] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  611.308593] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  611.308649] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  611.360293] [drm:wait_panel_status [i915]] Wait complete
>[  611.360367] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  611.360442] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  611.360586] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  611.360677] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  611.361042] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  611.361112] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  611.361182] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  611.361271] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  611.361362] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  611.361524] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  611.378068] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  611.378241] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  611.378429] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  611.382033] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  611.382122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  611.382216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  611.382306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  611.382387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  611.382469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  611.382550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  611.382631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  611.382712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  611.383589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  611.383671] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  611.384009] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  611.384099] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  611.384184] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  611.384339] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 1, on? 0) for crtc 33
>[  611.384418] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  611.385341] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016dc0c138
>[  611.387530] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  611.388375] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  611.388444] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  611.388541] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] HDMI audio pixel clock setting for 75000 not found, falling back to defaults
>[  611.388609] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  611.388673] [drm:hsw_audio_config_update [i915]] using automatic N
>[  611.389226] [drm:intel_fbc_enable [i915]] reserved 6291456 bytes of contiguous stolen space for FBC, threshold: 1
>[  611.389293] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  611.417090] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  611.417283] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  611.417390] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  611.417635] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  611.418238] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  611.760341] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  611.760638] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  611.760916] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  611.761118] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  611.777984] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  611.778035] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 1, on? 1) for crtc 33
>[  611.778146] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  611.778249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  611.778291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  611.778334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  611.778372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  611.778410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  611.778448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  611.778490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  611.778528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  611.778566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  611.778603] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  611.778646] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  611.778685] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  611.778803] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  611.778863] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  611.778902] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  611.778959] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  611.779017] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  611.779068] [drm:intel_power_well_disable [i915]] disabling DC off
>[  611.779108] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  611.779141] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  611.779686] [drm:intel_power_well_disable [i915]] disabling always-on
>[  611.780429] [drm:intel_runtime_suspend [i915]] Suspending device
>[  611.780598] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  611.780884] [IGT] prime_vgem: exiting, ret=0
>[  611.780995] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  611.781532] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 19200 kHz (VCO 0 kHz)
>[  611.784738] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  611.784773] [drm:intel_power_well_disable [i915]] disabling power well 1
>[  611.784814] [drm:skl_set_power_well [i915]] Disabling power well 1
>[  611.784853] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC
>[  611.784894] [drm:bxt_enable_dc9 [i915]] Enabling DC9
>[  611.784932] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 08
>[  611.784988] [drm:intel_runtime_suspend [i915]] Device suspended
>[  611.808990] [drm:intel_runtime_resume [i915]] Resuming device
>[  611.809041] [drm:bxt_disable_dc9 [i915]] Disabling DC9
>[  611.809086] [drm:gen9_set_dc_state [i915]] Setting DC state from 08 to 00
>[  611.809145] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  611.809208] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  611.809259] [drm:skl_set_power_well [i915]] Enabling power well 1
>[  611.809319] [drm:intel_update_cdclk [i915]] Current CD clock rate: 19200 kHz, VCO: 0 kHz, ref: 19200 kHz
>[  611.809368] [drm:bxt_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os
>[  611.809416] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  611.815838] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  611.818141] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  611.818186] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  611.819986] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  611.820046] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  611.820086] [drm:intel_runtime_resume [i915]] Device resumed
>[  611.820253] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  611.820298] [drm:intel_power_well_enable [i915]] enabling always-on
>[  611.820337] [drm:intel_power_well_enable [i915]] enabling DC off
>[  611.820556] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  611.820616] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  611.820820] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  611.820875] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  611.820922] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  611.820971] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  611.821254] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  611.821310] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  611.821360] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  611.821425] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  611.902237] [drm:wait_panel_status [i915]] Wait complete
>[  611.902322] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000068
>[  611.902391] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[  612.010792] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  612.010879] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  612.010961] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  612.011117] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  612.110624] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  612.111630] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:eDP-1] status updated from connected to connected
>[  612.111747] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  612.111945] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  612.112047] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  612.112216] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  612.113314] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  612.114056] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  612.114156] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  612.114290] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  612.114316] [drm:drm_helper_hpd_irq_event] [CONNECTOR:59:DP-1] status updated from disconnected to disconnected
>[  612.114419] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  612.114508] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  612.114599] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  612.114863] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  612.123977] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.132786] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.141566] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.150453] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.159354] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.168337] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.177243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.186182] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.195158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.204131] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.213102] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.222130] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.231087] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.240137] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.249102] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.258127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.267090] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.276138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.285101] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.294136] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.303104] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.312130] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.321097] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.330145] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.339101] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.348130] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.357094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.366149] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.375113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.384112] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.393091] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.402125] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  612.402176] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  612.402267] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  612.402367] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  612.402502] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  612.402526] [drm:drm_helper_hpd_irq_event] [CONNECTOR:64:DP-2] status updated from disconnected to disconnected
>[  612.402629] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  612.402717] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  612.402953] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  612.484180] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  612.488366] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  612.488481] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  612.488493] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  612.488582] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  612.488719] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  612.488866] [drm:drm_helper_hpd_irq_event] [CONNECTOR:68:HDMI-A-1] status updated from connected to connected
>[  612.489487] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  612.489591] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  612.489698] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  612.489925] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  612.490037] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  612.490141] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  612.490247] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  612.490345] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  612.490452] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  612.490551] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  612.490654] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  612.490672] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  612.490865] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  612.490886] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  612.490995] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  612.491098] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  612.491206] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  612.491310] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  612.491415] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  612.491527] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8400, ebb4: 0x2000,pll0: 0x1e, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x30b05, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x47
>[  612.491635] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  612.491742] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  612.491896] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  612.491999] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  612.492109] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  612.492239] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  612.492344] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  612.492455] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  612.492559] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  612.492665] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  612.492821] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  612.492923] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  612.493030] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  612.493136] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  612.493152] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  612.493252] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  612.493266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  612.493365] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  612.493470] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  612.493572] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  612.493676] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  612.493857] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  612.493969] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  612.494075] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  612.494187] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] FB:90, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  612.494297] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>[  612.494404] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  612.494515] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  612.494620] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  612.494736] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  612.494910] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  612.495014] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  612.495139] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  612.495242] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  612.495593] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  612.495693] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  612.495923] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  612.496095] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  612.500332] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  612.500400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  612.500436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  612.500478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  612.500515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  612.500552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  612.500588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  612.500624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  612.500660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  612.500719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  612.500758] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  612.500801] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  612.500843] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  612.501129] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  612.501166] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  612.501373] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  612.501410] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  612.501456] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000068
>[  612.501493] [drm:wait_panel_status [i915]] Wait complete
>[  612.501530] [drm:edp_panel_on [i915]] Wait for panel power on
>[  612.501571] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 0000006b
>[  612.703818] [drm:wait_panel_status [i915]] Wait complete
>[  612.705465] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  612.705544] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  612.705628] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  612.706873] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  612.706959] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  612.708417] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  612.708892] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016d528958
>[  612.711139] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  612.711267] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  612.711344] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  612.711431] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  612.711539] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  612.711615] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  612.711722] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  612.711885] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  612.712183] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  612.712263] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  612.712733] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016d52a548
>[  612.715014] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  612.715571] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  612.715610] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  612.715669] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  612.715748] [drm:hsw_audio_config_update [i915]] using automatic N
>[  612.732629] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  612.732714] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  612.733053] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  612.733308] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  612.733384] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  612.733601] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  612.749551] Console: switching to colour frame buffer device 240x67
>[  612.999348] Console: switching to colour dummy device 80x25
>[  612.999782] [IGT] prime_vgem: executing
>[  613.066315] [IGT] prime_vgem: starting subtest basic-fence-mmap
>[  613.066521] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  613.090018] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  613.090234] [IGT] prime_vgem: exiting, ret=0
>[  613.145259] Console: switching to colour frame buffer device 240x67
>[  613.390203] Console: switching to colour dummy device 80x25
>[  613.390470] [IGT] prime_vgem: executing
>[  613.439592] [IGT] prime_vgem: starting subtest basic-fence-read
>[  613.440139] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  613.475718] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  613.475937] [IGT] prime_vgem: exiting, ret=0
>[  613.528513] Console: switching to colour frame buffer device 240x67
>[  613.769075] Console: switching to colour dummy device 80x25
>[  613.769298] [IGT] prime_vgem: executing
>[  613.822293] [IGT] prime_vgem: starting subtest basic-fence-wait-default
>[  613.837999] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  614.843985] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  614.844509] [IGT] prime_vgem: exiting, ret=0
>[  614.899782] Console: switching to colour frame buffer device 240x67
>[  615.137178] Console: switching to colour dummy device 80x25
>[  615.137509] [IGT] prime_vgem: executing
>[  615.193366] [IGT] prime_vgem: starting subtest basic-gtt
>[  615.193475] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  615.215833] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  615.216033] [IGT] prime_vgem: exiting, ret=0
>[  615.253832] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  615.253903] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  615.266212] Console: switching to colour frame buffer device 240x67
>[  615.493829] Console: switching to colour dummy device 80x25
>[  615.494053] [IGT] prime_vgem: executing
>[  615.539224] [IGT] prime_vgem: starting subtest basic-read
>[  615.539307] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  615.562798] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  615.562998] [IGT] prime_vgem: exiting, ret=0
>[  615.616303] Console: switching to colour frame buffer device 240x67
>[  615.837165] Console: switching to colour dummy device 80x25
>[  615.837394] [IGT] prime_vgem: executing
>[  615.894354] [IGT] prime_vgem: starting subtest basic-sync-default
>[  615.909970] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  615.913213] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  615.913529] [IGT] prime_vgem: exiting, ret=0
>[  615.966314] Console: switching to colour frame buffer device 240x67
>[  616.186916] Console: switching to colour dummy device 80x25
>[  616.187178] [IGT] prime_vgem: executing
>[  616.242458] [IGT] prime_vgem: starting subtest basic-wait-default
>[  616.261903] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  616.264079] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  616.264298] [IGT] prime_vgem: exiting, ret=0
>[  616.316221] Console: switching to colour frame buffer device 240x67
>[  616.531169] Console: switching to colour dummy device 80x25
>[  616.531399] [IGT] prime_vgem: executing
>[  616.575211] [IGT] prime_vgem: starting subtest basic-write
>[  616.575297] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  616.596184] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  616.596384] [IGT] prime_vgem: exiting, ret=0
>[  616.649539] Console: switching to colour frame buffer device 240x67
>[  616.870430] Console: switching to colour dummy device 80x25
>[  616.870736] [IGT] vgem_basic: executing
>[  616.899636] [IGT] vgem_basic: starting subtest create
>[  616.899909] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  616.900060] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1048576
>[  616.900191] [drm:vgem_gem_dumb_create [vgem]] Created object of size 2147483648
>[  616.900492] [IGT] vgem_basic: exiting, ret=0
>[  616.916250] Console: switching to colour frame buffer device 240x67
>[  617.133162] Console: switching to colour dummy device 80x25
>[  617.133389] [IGT] vgem_basic: executing
>[  617.162599] [IGT] vgem_basic: starting subtest debugfs
>[  617.163640] [IGT] vgem_basic: exiting, ret=0
>[  617.179047] Console: switching to colour frame buffer device 240x67
>[  617.404150] Console: switching to colour dummy device 80x25
>[  617.404375] [IGT] vgem_basic: executing
>[  617.433038] [IGT] vgem_basic: starting subtest dmabuf-export
>[  617.462202] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  617.462655] [IGT] vgem_basic: exiting, ret=0
>[  617.516191] Console: switching to colour frame buffer device 240x67
>[  617.741147] Console: switching to colour dummy device 80x25
>[  617.741402] [IGT] vgem_basic: executing
>[  617.766209] [IGT] vgem_basic: starting subtest dmabuf-fence
>[  617.766320] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  617.767963] [IGT] vgem_basic: exiting, ret=0
>[  617.782930] Console: switching to colour frame buffer device 240x67
>[  618.002624] Console: switching to colour dummy device 80x25
>[  618.002942] [IGT] vgem_basic: executing
>[  618.033043] [IGT] vgem_basic: starting subtest dmabuf-fence-before
>[  618.033177] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  618.033489] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  618.033955] [IGT] vgem_basic: exiting, ret=0
>[  618.049542] Console: switching to colour frame buffer device 240x67
>[  618.267561] Console: switching to colour dummy device 80x25
>[  618.267875] [IGT] vgem_basic: executing
>[  618.296038] [IGT] vgem_basic: starting subtest dmabuf-mmap
>[  618.296175] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  618.296965] [IGT] vgem_basic: exiting, ret=0
>[  618.316206] Console: switching to colour frame buffer device 240x67
>[  618.531972] Console: switching to colour dummy device 80x25
>[  618.532231] [IGT] vgem_basic: executing
>[  618.562730] [IGT] vgem_basic: starting subtest mmap
>[  618.562862] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  618.563320] [IGT] vgem_basic: exiting, ret=0
>[  618.579311] Console: switching to colour frame buffer device 240x67
>[  618.796902] Console: switching to colour dummy device 80x25
>[  618.797178] [IGT] vgem_basic: executing
>[  618.816200] [IGT] vgem_basic: starting subtest second-client
>[  618.882842] [IGT] vgem_basic: exiting, ret=0
>[  618.899561] Console: switching to colour frame buffer device 240x67
>[  619.115592] Console: switching to colour dummy device 80x25
>[  619.115975] [IGT] vgem_basic: executing
>[  619.146201] [IGT] vgem_basic: starting subtest sysfs
>[  619.147654] [IGT] vgem_basic: exiting, ret=0
>[  619.166201] Console: switching to colour frame buffer device 240x67
>[  619.390754] Console: switching to colour dummy device 80x25
>[  619.391058] [IGT] vgem_basic: executing
>[  619.391397] [IGT] vgem_basic: starting subtest unload
>[  619.437421] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  619.462352] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  619.509216] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  619.529389] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  619.585923] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  619.599356] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  619.646158] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  619.666377] [IGT] vgem_basic: exiting, ret=0
>[  619.682831] Console: switching to colour frame buffer device 240x67
>[  619.911958] Console: switching to colour dummy device 80x25
>[  619.912221] [IGT] drv_module_reload: executing
>[  619.913163] [IGT] drv_module_reload: starting subtest basic-reload
>[  620.024420] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  620.024459] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  620.024502] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  620.024545] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  620.024579] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  620.024614] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  620.024648] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  620.024683] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  620.072974] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  620.074426] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  620.277960] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  620.278416] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  620.280944] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  620.281040] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  620.282931] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  620.283044] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  620.283131] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  620.333342] [drm:wait_panel_status [i915]] Wait complete
>[  620.333470] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  620.333715] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  620.334153] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  620.334468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  620.334570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  620.334670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  620.334950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  620.335164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  620.335259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  620.335352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  620.335445] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  620.335535] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  620.335628] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  620.335854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  620.335952] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  620.336051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  620.336142] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  620.336261] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  620.336361] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  620.336460] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  620.349282] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  620.349527] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  620.350282] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  620.350650] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  620.350989] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  620.367729] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  620.368016] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  620.368254] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  620.372965] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  620.373075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  620.373188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  620.373302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  620.373404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  620.373504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  620.373605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  620.373716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  620.373966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  620.374072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  620.374180] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  620.374307] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  620.374423] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  620.374533] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  620.374695] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  620.375161] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  620.375647] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  620.375919] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  620.376036] [drm:intel_power_well_disable [i915]] disabling DC off
>[  620.376140] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  620.376232] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  620.377454] [drm:intel_power_well_disable [i915]] disabling always-on
>[  620.378720] [drm:intel_runtime_pm_get_noresume [i915]] RPM wakelock ref not held during HW access
>[  620.396645] [drm:intel_uncore_forcewake_get [i915]] RPM wakelock ref not held during HW access
>[  620.400820] [drm:intel_power_well_enable [i915]] enabling always-on
>[  620.400869] [drm:intel_power_well_enable [i915]] enabling DC off
>[  620.401172] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  620.401237] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  620.401288] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  620.401603] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  620.401790] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  620.483143] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 0
>[  620.720886] [drm:i915_driver_load [i915]] No PCH found.
>[  620.720938] [drm:intel_power_domains_init [i915]] Allowed DC state mask 09
>[  620.723873] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROXTON gen=9 pciid=0x5a84 rev=0x0a
>[  620.723915] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  620.723955] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: yes
>[  620.723994] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  620.724032] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  620.724071] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  620.724110] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  620.724148] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  620.724187] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: yes
>[  620.724226] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  620.724265] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  620.724303] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  620.724342] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  620.724380] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  620.724419] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  620.724458] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  620.724496] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  620.724535] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  620.724573] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  620.724612] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  620.724650] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: no
>[  620.724689] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  620.724779] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  620.724820] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  620.724859] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  620.724901] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: no
>[  620.724942] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  620.724984] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  620.725024] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  620.725066] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  620.725105] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  620.725147] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  620.725188] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  620.725229] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  620.725270] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  620.729563] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001
>[  620.729608] [drm:intel_device_info_runtime_init [i915]] slice total: 1
>[  620.729647] [drm:intel_device_info_runtime_init [i915]] subslice total: 3
>[  620.729686] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  620.729807] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  620.729850] [drm:intel_device_info_runtime_init [i915]] EU total: 18
>[  620.729898] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 6
>[  620.729938] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n
>[  620.729982] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: y
>[  620.730026] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[  620.730072] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  620.730115] [drm:i915_driver_load [i915]] use GPU sempahores? no
>[  620.730201] [drm] Memory usable by graphics device = 4096M
>[  620.730247] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  620.730291] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  620.730309] [drm] Replacing VGA console driver
>[  620.730451] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  620.730513] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 0
>[  620.730861] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x79df2018
>[  620.730971] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  620.731016] [drm:intel_opregion_setup [i915]] ASLE supported
>[  620.731083] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA)
>[  620.731536] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  620.731553] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  620.731555] [drm] Driver supports precise vblank timestamp query.
>[  620.731601] [drm:intel_bios_init [i915]] Set default to SSC at 100000 kHz
>[  620.731646] [drm:intel_bios_init [i915]] VBT signature "$VBT BROXTON        ", BDB version 207
>[  620.731691] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[  620.731794] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  620.731846] [drm:intel_opregion_get_panel_type [i915]] Failed to get panel details from OpRegion (-19)
>[  620.731894] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  620.731943] [drm:intel_bios_init [i915]] DRRS supported mode is seamless
>[  620.732006] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  620.732017] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  620.732062] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  620.732108] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 180, controller 0
>[  620.732158] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[  620.732205] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 207 not known; assuming 38
>[  620.732261] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  620.732308] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  620.732356] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  620.732401] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  620.732447] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8
>[  620.732493] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  620.732539] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8
>[  620.733154] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  620.733220] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  620.733421] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  620.733491] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  620.733553] [drm:intel_power_well_enable [i915]] enabling always-on
>[  620.733593] [drm:intel_power_well_enable [i915]] enabling DC off
>[  620.733634] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  620.733688] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  620.733933] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  620.734018] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 1 already enabled, won't reprogram it
>[  620.734061] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  620.734174] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>[  620.734221] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  620.734393] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 1 already enabled, won't reprogram it
>[  620.734515] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>[  620.734571] [drm:intel_csr_ucode_init [i915]] Loading i915/bxt_dmc_ver1_07.bin
>[  620.737811] [drm] Finished loading DMC firmware i915/bxt_dmc_ver1_07.bin (v1.7)
>[  620.738028] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  620.740812] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  620.740874] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 7 (7.0 usec)
>[  620.740914] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 7 (7.0 usec)
>[  620.740953] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 8 (8.0 usec)
>[  620.740992] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 22 (22.0 usec)
>[  620.741031] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 22 (22.0 usec)
>[  620.741071] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 22 (22.0 usec)
>[  620.741110] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 22 (22.0 usec)
>[  620.741149] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 22 (22.0 usec)
>[  620.741194] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  620.741845] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  620.741893] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 624000 kHz
>[  620.741940] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 624000 kHz
>[  620.742337] [drm:intel_dp_init_connector [i915]] Adding eDP connector on port A
>[  620.742483] [drm:intel_dp_init_connector [i915]] using AUX A for port A (VBT)
>[  620.742788] [drm:intel_pps_dump_state [i915]] cur t1_t3 2000 t8 1 t9 1 t10 500 t11_t12 5000
>[  620.742834] [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
>[  620.742881] [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 50, power cycle delay 500
>[  620.742930] [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 1, off delay 200
>[  620.742985] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  620.743143] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  620.743189] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  621.245885] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  621.245936] [drm:wait_panel_status [i915]] Wait complete
>[  621.245987] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000068
>[  621.246032] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[  621.454645] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  621.455502] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  621.456255] [drm:intel_dp_init_connector [i915]] Detected EDP PSR Panel.
>[  621.456980] [drm:intel_dp_init_connector [i915]] EDP DPCD : 02 fb c7
>[  621.463822] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  621.463955] [drm:intel_dp_init_connector [i915]] Downclock mode is not found. DRRS not supported
>[  621.464239] [drm:intel_panel_setup_backlight [i915]] Connector eDP-1 backlight initialized, disabled, brightness 0/96000
>[  621.464499] [drm:intel_ddi_init [i915]] VBT says port B has lspcon
>[  621.464646] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B
>[  621.465185] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT)
>[  621.465714] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  621.466392] [drm:drm_dp_i2c_do_msg] native defer
>[  621.467823] [drm:drm_dp_i2c_do_msg] native defer
>[  621.469335] [drm:drm_dp_i2c_do_msg] native defer
>[  621.470630] [drm:drm_dp_i2c_do_msg] native defer
>[  621.472051] [drm:drm_dp_i2c_do_msg] native defer
>[  621.472916] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  621.473387] [drm:drm_dp_i2c_do_msg] native defer
>[  621.474892] [drm:drm_dp_i2c_do_msg] native defer
>[  621.476530] [drm:drm_dp_i2c_do_msg] native defer
>[  621.477881] [drm:drm_dp_i2c_do_msg] native defer
>[  621.479251] [drm:drm_dp_i2c_do_msg] native defer
>[  621.480095] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: a8 (err 0)
>[  621.480187] [drm:lspcon_init [i915]] LSPCON detected
>[  621.480745] [drm:drm_dp_i2c_do_msg] native defer
>[  621.482085] [drm:drm_dp_i2c_do_msg] native defer
>[  621.483505] [drm:drm_dp_i2c_do_msg] native defer
>[  621.484851] [drm:drm_dp_i2c_do_msg] native defer
>[  621.486252] [drm:drm_dp_i2c_do_msg] native defer
>[  621.487195] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  621.487923] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  621.488557] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.1 SW-rev 1.39
>[  621.488646] [drm:lspcon_init [i915]] Success: LSPCON init
>[  621.488737] [drm:intel_ddi_init [i915]] LSPCON init success on port B
>[  621.488992] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  621.489187] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  621.489401] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[  621.489556] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x2 for port C (VBT)
>[  621.489691] [drm:intel_dsi_init [i915]] 
>[  621.490004] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:33:pipe A] hw state readout: disabled
>[  621.490118] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:42:pipe B] hw state readout: disabled
>[  621.490230] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:49:pipe C] hw state readout: disabled
>[  621.490332] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0
>[  621.490431] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0
>[  621.490531] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0
>[  621.490634] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI A] hw state readout: disabled, pipe A
>[  621.490733] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI B] hw state readout: disabled, pipe A
>[  621.490879] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A
>[  621.490977] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B
>[  621.491075] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C
>[  621.491177] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:63:DDI C] hw state readout: disabled, pipe A
>[  621.491273] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST A] hw state readout: disabled, pipe A
>[  621.491368] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST B] hw state readout: disabled, pipe B
>[  621.491462] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:67:DP-MST C] hw state readout: disabled, pipe C
>[  621.491576] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:eDP-1] hw state readout: disabled
>[  621.491682] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-1] hw state readout: disabled
>[  621.491838] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:64:DP-2] hw state readout: disabled
>[  621.491949] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:68:HDMI-A-1] hw state readout: disabled
>[  621.492053] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][setup_hw_state]
>[  621.492146] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  621.492237] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  621.492327] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  621.492342] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  621.492428] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  621.492438] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  621.492529] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  621.492619] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  621.492711] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  621.492850] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  621.492943] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  621.493046] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  621.493140] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  621.493237] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  621.493331] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  621.493429] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  621.493521] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  621.493620] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][setup_hw_state]
>[  621.493712] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  621.493842] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  621.493935] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  621.493950] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  621.494038] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  621.494052] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  621.494144] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  621.494238] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  621.494333] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  621.494427] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  621.494522] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  621.494618] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  621.494713] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  621.494843] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  621.494940] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  621.495036] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  621.495134] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  621.495235] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][setup_hw_state]
>[  621.495327] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  621.495418] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  621.495509] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  621.495518] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  621.495605] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  621.495617] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  621.495705] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  621.495843] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  621.495938] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  621.496033] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  621.496127] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  621.496228] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  621.496320] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  621.496420] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  621.496516] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  621.496613] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  621.496988] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  621.497112] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  621.497311] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  621.497439] [drm:intel_huc_init [i915]] HuC firmware pending, path i915/bxt_huc_ver01_07_1398.bin
>[  621.497530] [drm:intel_uc_fw_fetch [i915]] before requesting firmware: uC fw fetch status PENDING
>[  621.498171] [drm:intel_uc_fw_fetch [i915]] fetch uC fw from i915/bxt_huc_ver01_07_1398.bin succeeded, fw ffff88016e3e22e8
>[  621.498218] [drm:intel_uc_fw_fetch [i915]] firmware version 1.7 OK (minimum 1.7)
>[  621.499276] [drm:intel_uc_fw_fetch [i915]] uC fw fetch status SUCCESS, obj ffff88016e308040
>[  621.499534] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  621.499821] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  621.500202] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  621.503122] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  621.503275] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  621.503401] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  621.503525] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  621.503595] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[  621.503604] [drm] GuC firmware load skipped
>[  621.504450] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  621.504542] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  621.504589] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  621.504635] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  621.504681] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  621.504940] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:1a001818 hp_port:38
>[  621.514509] [drm:intel_backlight_device_register [i915]] Connector eDP-1 backlight sysfs interface registered
>[  621.515144] [drm:intel_dp_connector_register [i915]] registering DPDDC-A bus for card0-eDP-1
>[  621.517588] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-1
>[  621.521414] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-2
>[  621.524029] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  621.525930] [drm:intel_opregion_register [i915]] 4 outputs detected
>[  621.543480] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  621.547087] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input12
>[  621.548927] [drm:drm_setup_crtcs] 
>[  621.548934] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  621.548997] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  621.549075] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  621.549122] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  621.549166] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  621.549210] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  621.550687] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  621.550691] [drm] DRM_I915_DEBUG enabled
>[  621.550692] [drm] DRM_I915_DEBUG_GEM enabled
>[  621.550981] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  621.552645] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] status updated from unknown to connected
>[  621.552784] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  621.552797] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  621.552801] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  621.552805] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  621.552867] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  621.552915] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  621.552996] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  621.553150] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  621.555333] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  621.555809] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  621.555858] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  621.555954] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  621.555968] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] status updated from unknown to disconnected
>[  621.555972] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  621.555981] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  621.556026] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  621.556071] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  621.556118] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  621.556180] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  621.564968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.573899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.582668] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.591384] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.600077] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.608723] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.617399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.626047] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.634686] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.643492] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.652178] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.660913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.669690] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.678521] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.687259] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.695996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.704732] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.713519] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.722259] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.730995] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.739737] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.748543] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.757286] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.766027] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.774816] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.783563] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.792313] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.801053] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.809789] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.818524] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.827263] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.835996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  621.836027] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  621.836099] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  621.836172] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  621.836266] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  621.836281] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] status updated from unknown to disconnected
>[  621.836286] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  621.836292] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  621.836363] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  621.836432] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  621.836500] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  621.916425] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  621.920604] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  621.920733] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  621.921133] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  621.921250] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  621.921392] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  621.921413] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] status updated from unknown to connected
>[  621.922387] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  621.922397] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  621.922405] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  621.922410] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  621.922551] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  621.922561] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  621.922569] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  621.922577] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  621.922584] [drm:drm_mode_debug_printmodeline] Modeline 80:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  621.922592] [drm:drm_mode_debug_printmodeline] Modeline 77:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  621.922600] [drm:drm_mode_debug_printmodeline] Modeline 79:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  621.922607] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  621.922615] [drm:drm_mode_debug_printmodeline] Modeline 76:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  621.922623] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  621.922630] [drm:drm_mode_debug_printmodeline] Modeline 97:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  621.922638] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  621.922645] [drm:drm_mode_debug_printmodeline] Modeline 86:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  621.922653] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  621.922660] [drm:drm_mode_debug_printmodeline] Modeline 81:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  621.924009] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  621.924018] [drm:drm_mode_debug_printmodeline] Modeline 92:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  621.924029] [drm:drm_mode_debug_printmodeline] Modeline 98:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  621.924037] [drm:drm_mode_debug_printmodeline] Modeline 74:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  621.924044] [drm:drm_mode_debug_printmodeline] Modeline 83:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  621.924052] [drm:drm_mode_debug_printmodeline] Modeline 99:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  621.924059] [drm:drm_mode_debug_printmodeline] Modeline 75:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  621.924067] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  621.924074] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  621.924127] [drm:drm_setup_crtcs] connector 51 enabled? yes
>[  621.924133] [drm:drm_setup_crtcs] connector 59 enabled? no
>[  621.924138] [drm:drm_setup_crtcs] connector 64 enabled? no
>[  621.924142] [drm:drm_setup_crtcs] connector 68 enabled? yes
>[  621.924278] [drm:intel_fb_initial_config [i915]] connector eDP-1 has no encoder or crtc, skipping
>[  621.924390] [drm:intel_fb_initial_config [i915]] connector DP-1 not enabled, skipping
>[  621.924496] [drm:intel_fb_initial_config [i915]] connector DP-2 not enabled, skipping
>[  621.924604] [drm:intel_fb_initial_config [i915]] connector HDMI-A-1 has no encoder or crtc, skipping
>[  621.924710] [drm:intel_fb_initial_config [i915]] fallback: Not all outputs enabled
>[  621.926165] [drm:intel_fb_initial_config [i915]] Enabled: 0, detected: 2
>[  621.926275] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  621.926305] [drm:drm_setup_crtcs] looking for cmdline mode on connector 51
>[  621.926311] [drm:drm_setup_crtcs] looking for preferred mode on connector 51 0
>[  621.926315] [drm:drm_setup_crtcs] found mode 1920x1080
>[  621.926320] [drm:drm_setup_crtcs] looking for cmdline mode on connector 68
>[  621.926324] [drm:drm_setup_crtcs] looking for preferred mode on connector 68 0
>[  621.926329] [drm:drm_setup_crtcs] found mode 1920x1080
>[  621.926333] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  621.926441] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 33 (0,0)
>[  621.926464] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 42 (0,0)
>[  621.926615] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  621.931072] [drm:intelfb_create [i915]] allocated 1920x1080 fb: 0x00040000
>[  621.933092] fbcon: inteldrmfb (fb0) is primary device
>[  621.934621] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  621.934667] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  621.934762] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  621.934808] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  621.934858] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  621.934902] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  621.934948] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  621.934993] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  621.935038] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  621.935082] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  621.935125] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  621.935169] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  621.935175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  621.935218] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  621.935222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  621.935266] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  621.935309] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  621.935353] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  621.935397] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  621.935440] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  621.935486] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  621.935530] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  621.935574] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  621.935618] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  621.935662] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  621.935731] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  621.935784] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  621.935828] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  621.935874] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  621.935917] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  621.935962] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  621.936007] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  621.936050] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  621.936093] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  621.936136] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  621.936140] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  621.936183] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  621.936187] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  621.936231] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  621.936275] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  621.936319] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  621.936363] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  621.936406] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  621.936452] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  621.936496] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  621.936541] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  621.936585] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  621.936630] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  621.936673] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  621.936749] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  621.936803] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  621.936849] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  621.936898] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  621.936942] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  621.936987] [drm:skl_update_scaler [i915]] scaler_user index 1.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  621.937513] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  621.937576] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  621.937763] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  621.939217] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  621.942784] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  621.942832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  621.942878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  621.942933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  621.942978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  621.943023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  621.943068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  621.943112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  621.943157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  621.943202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  621.943247] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  621.943296] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  621.943344] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  621.943610] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  621.943656] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  621.945238] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  621.945300] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  621.945368] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000068
>[  621.945416] [drm:wait_panel_status [i915]] Wait complete
>[  621.945465] [drm:edp_panel_on [i915]] Wait for panel power on
>[  621.945517] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 0000006b
>[  622.145875] [drm:wait_panel_status [i915]] Wait complete
>[  622.148749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  622.148898] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  622.149003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  622.150220] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  622.150308] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  622.151672] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  622.152110] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880171380008
>[  622.154870] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  622.155102] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  622.155191] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  622.155338] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  622.155459] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  622.155549] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  622.155829] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  622.155916] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  622.156314] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  622.156404] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  622.156971] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016dcdb7e8
>[  622.159415] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  622.160118] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  622.160209] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  622.160562] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  622.160650] [drm:hsw_audio_config_update [i915]] using automatic N
>[  622.177511] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  622.177640] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  622.178047] [drm:intel_ddi_get_config [i915]] pipe has 24 bpp for eDP panel, overriding BIOS-provided max 18 bpp
>[  622.178186] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  622.178555] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  622.178682] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  622.179043] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  622.179910] Console: switching to colour frame buffer device 240x67
>[  622.208374] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  622.227015] snd_hda_intel 0000:00:0e.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  622.247153] [drm] RC6 on
>[  622.251086] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC298: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker
>[  622.251091] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  622.251093] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[  622.251094] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  622.251096] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  622.251099] snd_hda_codec_realtek hdaudioC0D0:      Mic=0x18
>[  622.286339] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  622.286379] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  622.286414] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  622.286486] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  622.286521] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  622.286555] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  622.286591] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  622.286627] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  622.306147] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input13
>[  622.312450] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:0e.0/sound/card0/input14
>[  622.314118] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input15
>[  622.316290] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input16
>[  622.317521] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input17
>[  622.318686] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input18
>[  622.319833] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input19
>[  622.544220] [IGT] drv_module_reload: exiting, ret=0
>[  622.749290] Console: switching to colour dummy device 80x25
>[  622.749631] [IGT] drv_module_reload: executing
>[  622.750611] [IGT] drv_module_reload: starting subtest basic-no-display
>[  623.848115] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  623.848246] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  623.848350] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  623.848472] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  623.848577] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  623.848680] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  623.848912] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  623.849017] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  623.882930] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  623.883212] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  624.085941] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  624.086140] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  624.091834] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  624.091918] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  624.091985] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  624.142188] [drm:wait_panel_status [i915]] Wait complete
>[  624.142318] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  624.142731] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  624.143609] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  624.144310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  624.144387] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  624.144462] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  624.144535] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  624.144647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  624.144732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  624.145028] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  624.145415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  624.145491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  624.145565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  624.145640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  624.145715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  624.145841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  624.145924] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  624.146017] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  624.146104] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  624.146187] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  624.160406] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  624.160522] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  624.161081] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  624.161373] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  624.161562] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  624.178384] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  624.178568] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  624.178897] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  624.183257] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  624.183358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  624.183459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  624.183561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  624.183652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  624.183742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  624.183961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  624.184066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  624.184160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  624.184258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  624.184355] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  624.184462] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  624.184562] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  624.184664] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  624.185120] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  624.185214] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  624.185341] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  624.185477] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  624.185578] [drm:intel_power_well_disable [i915]] disabling DC off
>[  624.185671] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  624.185852] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  624.186464] [drm:intel_power_well_disable [i915]] disabling always-on
>[  624.187690] [drm:intel_runtime_pm_get_noresume [i915]] RPM wakelock ref not held during HW access
>[  624.205160] [drm:intel_uncore_forcewake_get [i915]] RPM wakelock ref not held during HW access
>[  624.209307] [drm:intel_power_well_enable [i915]] enabling always-on
>[  624.209363] [drm:intel_power_well_enable [i915]] enabling DC off
>[  624.209673] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  624.210303] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  624.210363] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  624.210600] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  624.212384] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  624.267454] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 0
>[  624.395317] [drm:i915_driver_load [i915]] No PCH found.
>[  624.395367] [drm:intel_power_domains_init [i915]] Allowed DC state mask 09
>[  624.398111] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROXTON gen=9 pciid=0x5a84 rev=0x0a
>[  624.398153] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  624.398193] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: yes
>[  624.398232] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  624.398270] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  624.398309] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  624.398348] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  624.398386] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  624.398425] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: yes
>[  624.398464] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  624.398503] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  624.398542] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  624.398580] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  624.398619] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  624.398658] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  624.398696] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  624.400054] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  624.400094] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  624.400132] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  624.400171] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  624.400210] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: no
>[  624.400248] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  624.400287] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  624.400326] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  624.400365] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  624.400404] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: no
>[  624.400443] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  624.400481] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  624.400520] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  624.400559] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  624.400598] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  624.400637] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  624.400676] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  624.401503] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  624.401543] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  624.404528] [drm] Display disabled (module parameter)
>[  624.404600] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001
>[  624.404642] [drm:intel_device_info_runtime_init [i915]] slice total: 1
>[  624.404681] [drm:intel_device_info_runtime_init [i915]] subslice total: 3
>[  624.404805] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  624.404845] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  624.404885] [drm:intel_device_info_runtime_init [i915]] EU total: 18
>[  624.404926] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 6
>[  624.404970] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n
>[  624.405010] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: y
>[  624.405051] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[  624.405094] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  624.405134] [drm:i915_driver_load [i915]] use GPU sempahores? no
>[  624.405202] [drm] Memory usable by graphics device = 4096M
>[  624.405247] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  624.405291] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  624.405309] [drm] Replacing VGA console driver
>[  624.405449] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  624.405509] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 0
>[  624.405872] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x79df2018
>[  624.405985] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  624.406029] [drm:intel_opregion_setup [i915]] ASLE supported
>[  624.406100] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA)
>[  624.406548] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  624.406595] [drm:intel_bios_init [i915]] Set default to SSC at 100000 kHz
>[  624.406640] [drm:intel_bios_init [i915]] VBT signature "$VBT BROXTON        ", BDB version 207
>[  624.406685] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[  624.406794] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  624.406843] [drm:intel_opregion_get_panel_type [i915]] Failed to get panel details from OpRegion (-19)
>[  624.406891] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  624.406939] [drm:intel_bios_init [i915]] DRRS supported mode is seamless
>[  624.406996] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  624.407004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  624.407047] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  624.407094] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 180, controller 0
>[  624.407139] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[  624.407185] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 207 not known; assuming 38
>[  624.407240] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  624.407287] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  624.407333] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  624.407379] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  624.407425] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8
>[  624.407471] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  624.407517] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8
>[  624.408139] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  624.408208] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  624.408426] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  624.408496] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  624.408558] [drm:intel_power_well_enable [i915]] enabling always-on
>[  624.408598] [drm:intel_power_well_enable [i915]] enabling DC off
>[  624.408642] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  624.408698] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  624.408800] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  624.408888] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 1 already enabled, won't reprogram it
>[  624.408930] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  624.409045] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>[  624.409090] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  624.409262] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 1 already enabled, won't reprogram it
>[  624.409383] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>[  624.409439] [drm:intel_csr_ucode_init [i915]] Loading i915/bxt_dmc_ver1_07.bin
>[  624.411484] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  624.412401] [drm] Finished loading DMC firmware i915/bxt_dmc_ver1_07.bin (v1.7)
>[  624.414222] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  624.414283] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 7 (7.0 usec)
>[  624.414323] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 7 (7.0 usec)
>[  624.414363] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 8 (8.0 usec)
>[  624.414402] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 22 (22.0 usec)
>[  624.414441] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 22 (22.0 usec)
>[  624.414480] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 22 (22.0 usec)
>[  624.414519] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 22 (22.0 usec)
>[  624.414559] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 22 (22.0 usec)
>[  624.414604] [drm:intel_huc_init [i915]] HuC firmware pending, path i915/bxt_huc_ver01_07_1398.bin
>[  624.414648] [drm:intel_uc_fw_fetch [i915]] before requesting firmware: uC fw fetch status PENDING
>[  624.415102] [drm:intel_uc_fw_fetch [i915]] fetch uC fw from i915/bxt_huc_ver01_07_1398.bin succeeded, fw ffff88016e7dab88
>[  624.415150] [drm:intel_uc_fw_fetch [i915]] firmware version 1.7 OK (minimum 1.7)
>[  624.416206] [drm:intel_uc_fw_fetch [i915]] uC fw fetch status SUCCESS, obj ffff880172c40040
>[  624.416579] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  624.417098] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  624.417497] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  624.420244] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  624.420397] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  624.420523] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  624.420646] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  624.420783] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[  624.420793] [drm] GuC firmware load skipped
>[  624.421855] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  624.423200] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  624.425073] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  624.425075] [drm] DRM_I915_DEBUG enabled
>[  624.425076] [drm] DRM_I915_DEBUG_GEM enabled
>[  624.434065] [IGT] drv_module_reload: exiting, ret=0
>[  624.441411] snd_hda_intel 0000:00:0e.0: failed to add i915 component master (-19)
>[  624.458516] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC298: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker
>[  624.458520] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  624.458523] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[  624.458525] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  624.458527] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  624.458530] snd_hda_codec_realtek hdaudioC0D0:      Mic=0x18
>[  624.482511] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  624.490082] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  624.517663] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input20
>[  624.521488] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:0e.0/sound/card0/input21
>[  624.524082] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input22
>[  624.631582] [IGT] drv_module_reload: executing
>[  624.632406] [IGT] drv_module_reload: starting subtest basic-reload-inject
>[  624.750538] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 0
>[  624.841900] Setting dangerous option inject_load_failure - tainting kernel
>[  624.870973] [drm:i915_driver_load [i915]] No PCH found.
>[  624.871025] [drm:intel_power_domains_init [i915]] Allowed DC state mask 09
>[  624.874405] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROXTON gen=9 pciid=0x5a84 rev=0x0a
>[  624.874448] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  624.874489] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: yes
>[  624.874528] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  624.874567] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  624.874606] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  624.874645] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  624.874684] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  624.874777] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: yes
>[  624.874819] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  624.874864] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  624.874907] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  624.874948] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  624.874988] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  624.875032] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  624.875074] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  624.875118] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  624.875160] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  624.875202] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  624.875244] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  624.875287] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: no
>[  624.875329] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  624.875372] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  624.875414] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  624.875457] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  624.875499] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: no
>[  624.875542] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  624.875584] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  624.875627] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  624.875671] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  624.875729] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  624.875772] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  624.875815] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  624.875858] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  624.875901] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  624.879040] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001
>[  624.879083] [drm:intel_device_info_runtime_init [i915]] slice total: 1
>[  624.879122] [drm:intel_device_info_runtime_init [i915]] subslice total: 3
>[  624.879161] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  624.879200] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  624.879239] [drm:intel_device_info_runtime_init [i915]] EU total: 18
>[  624.879278] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 6
>[  624.879316] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n
>[  624.879355] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: y
>[  624.879394] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[  624.879434] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  624.879472] [drm:i915_driver_load [i915]] use GPU sempahores? no
>[  624.879553] [drm] Memory usable by graphics device = 4096M
>[  624.879604] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  624.879646] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  624.879723] [drm] Replacing VGA console driver
>[  624.879886] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  624.879947] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 0
>[  624.880236] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x79df2018
>[  624.880354] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  624.880399] [drm:intel_opregion_setup [i915]] ASLE supported
>[  624.880469] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA)
>[  624.880988] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  624.881006] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  624.881007] [drm] Driver supports precise vblank timestamp query.
>[  624.881054] [drm:intel_bios_init [i915]] Set default to SSC at 100000 kHz
>[  624.881099] [drm:intel_bios_init [i915]] VBT signature "$VBT BROXTON        ", BDB version 207
>[  624.881146] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[  624.881190] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  624.881238] [drm:intel_opregion_get_panel_type [i915]] Failed to get panel details from OpRegion (-19)
>[  624.881283] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  624.881328] [drm:intel_bios_init [i915]] DRRS supported mode is seamless
>[  624.881380] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  624.881387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  624.881433] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  624.881478] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 180, controller 0
>[  624.881524] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[  624.881568] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 207 not known; assuming 38
>[  624.881621] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  624.881667] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  624.881799] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  624.881847] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  624.881893] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8
>[  624.881940] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  624.881985] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8
>[  624.882583] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  624.882655] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  624.882919] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  624.882989] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  624.883051] [drm:intel_power_well_enable [i915]] enabling always-on
>[  624.883093] [drm:intel_power_well_enable [i915]] enabling DC off
>[  624.883136] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  624.883192] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  624.883236] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  624.883321] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 1 already enabled, won't reprogram it
>[  624.883363] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  624.883477] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>[  624.883521] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  624.883690] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 1 already enabled, won't reprogram it
>[  624.883864] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>[  624.883922] [drm:intel_csr_ucode_init [i915]] Loading i915/bxt_dmc_ver1_07.bin
>[  624.885327] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  624.887026] [drm] Finished loading DMC firmware i915/bxt_dmc_ver1_07.bin (v1.7)
>[  624.888349] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  624.888412] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 7 (7.0 usec)
>[  624.888452] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 7 (7.0 usec)
>[  624.888491] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 8 (8.0 usec)
>[  624.888530] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 22 (22.0 usec)
>[  624.888570] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 22 (22.0 usec)
>[  624.888609] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 22 (22.0 usec)
>[  624.888648] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 22 (22.0 usec)
>[  624.888687] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 22 (22.0 usec)
>[  624.888855] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  624.889465] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  624.889513] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 624000 kHz
>[  624.889557] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 624000 kHz
>[  624.889966] [drm:intel_dp_init_connector [i915]] Adding eDP connector on port A
>[  624.890113] [drm:intel_dp_init_connector [i915]] using AUX A for port A (VBT)
>[  624.890356] [drm:intel_pps_dump_state [i915]] cur t1_t3 2000 t8 1 t9 1 t10 500 t11_t12 5000
>[  624.890402] [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
>[  624.890448] [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 50, power cycle delay 500
>[  624.890492] [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 1, off delay 200
>[  624.890546] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  624.890703] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  624.890976] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  625.398018] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  625.398069] [drm:wait_panel_status [i915]] Wait complete
>[  625.398120] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000068
>[  625.398167] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[  625.606861] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  625.607365] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  625.607796] [drm:intel_dp_init_connector [i915]] Detected EDP PSR Panel.
>[  625.608264] [drm:intel_dp_init_connector [i915]] EDP DPCD : 02 fb c7
>[  625.614009] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  625.614118] [drm:intel_dp_init_connector [i915]] Downclock mode is not found. DRRS not supported
>[  625.614368] [drm:intel_panel_setup_backlight [i915]] Connector eDP-1 backlight initialized, disabled, brightness 0/96000
>[  625.614580] [drm:intel_ddi_init [i915]] VBT says port B has lspcon
>[  625.614700] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B
>[  625.614966] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT)
>[  625.615583] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  625.616091] [drm:drm_dp_i2c_do_msg] native defer
>[  625.617442] [drm:drm_dp_i2c_do_msg] native defer
>[  625.618788] [drm:drm_dp_i2c_do_msg] native defer
>[  625.620120] [drm:drm_dp_i2c_do_msg] native defer
>[  625.621574] [drm:drm_dp_i2c_do_msg] native defer
>[  625.622430] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  625.622934] [drm:drm_dp_i2c_do_msg] native defer
>[  625.624288] [drm:drm_dp_i2c_do_msg] native defer
>[  625.625641] [drm:drm_dp_i2c_do_msg] native defer
>[  625.626994] [drm:drm_dp_i2c_do_msg] native defer
>[  625.628328] [drm:drm_dp_i2c_do_msg] native defer
>[  625.629178] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: a8 (err 0)
>[  625.629275] [drm:lspcon_init [i915]] LSPCON detected
>[  625.629788] [drm:drm_dp_i2c_do_msg] native defer
>[  625.631145] [drm:drm_dp_i2c_do_msg] native defer
>[  625.632651] [drm:drm_dp_i2c_do_msg] native defer
>[  625.634016] [drm:drm_dp_i2c_do_msg] native defer
>[  625.635498] [drm:drm_dp_i2c_do_msg] native defer
>[  625.636452] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  625.637230] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  625.637851] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.1 SW-rev 1.39
>[  625.637943] [drm:lspcon_init [i915]] Success: LSPCON init
>[  625.638030] [drm:intel_ddi_init [i915]] LSPCON init success on port B
>[  625.638183] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  625.638362] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  625.638564] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[  625.638706] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x2 for port C (VBT)
>[  625.638933] [drm:intel_dsi_init [i915]] 
>[  625.639200] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:33:pipe A] hw state readout: disabled
>[  625.639306] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:42:pipe B] hw state readout: disabled
>[  625.639411] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:49:pipe C] hw state readout: disabled
>[  625.639505] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0
>[  625.639595] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0
>[  625.639686] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0
>[  625.639856] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI A] hw state readout: disabled, pipe A
>[  625.639955] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI B] hw state readout: disabled, pipe A
>[  625.640043] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A
>[  625.640131] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B
>[  625.640216] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C
>[  625.640312] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:63:DDI C] hw state readout: disabled, pipe A
>[  625.640399] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST A] hw state readout: disabled, pipe A
>[  625.640487] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST B] hw state readout: disabled, pipe B
>[  625.640574] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:67:DP-MST C] hw state readout: disabled, pipe C
>[  625.640671] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:eDP-1] hw state readout: disabled
>[  625.640830] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-1] hw state readout: disabled
>[  625.640933] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:64:DP-2] hw state readout: disabled
>[  625.641033] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:68:HDMI-A-1] hw state readout: disabled
>[  625.641129] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][setup_hw_state]
>[  625.641214] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  625.641299] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  625.641383] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  625.641398] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  625.641478] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  625.641489] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  625.641570] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  625.641655] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  625.641761] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  625.641930] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  625.642015] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  625.642078] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  625.642135] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  625.642193] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  625.642249] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  625.642309] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  625.642366] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  625.642431] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][setup_hw_state]
>[  625.642488] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  625.642545] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  625.642600] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  625.642609] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  625.642662] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  625.642697] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  625.642752] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  625.642809] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  625.642867] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  625.642923] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  625.642979] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  625.643039] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  625.643097] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  625.643152] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  625.643208] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  625.643263] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  625.643319] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  625.643378] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][setup_hw_state]
>[  625.643434] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  625.643488] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  625.643543] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  625.643551] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  625.643605] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  625.643612] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  625.643665] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  625.643766] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  625.643824] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  625.643883] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  625.643938] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  625.643998] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  625.644054] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  625.644111] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  625.644168] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  625.644227] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  625.644457] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  625.644545] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  625.644674] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  625.644805] [drm:intel_huc_init [i915]] HuC firmware pending, path i915/bxt_huc_ver01_07_1398.bin
>[  625.644860] [drm:intel_uc_fw_fetch [i915]] before requesting firmware: uC fw fetch status PENDING
>[  625.645277] [drm:intel_uc_fw_fetch [i915]] fetch uC fw from i915/bxt_huc_ver01_07_1398.bin succeeded, fw ffff88016e7db148
>[  625.645331] [drm:intel_uc_fw_fetch [i915]] firmware version 1.7 OK (minimum 1.7)
>[  625.646507] [drm:intel_uc_fw_fetch [i915]] uC fw fetch status SUCCESS, obj ffff880119788040
>[  625.646894] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  625.647141] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  625.647508] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  625.650244] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  625.650406] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  625.650542] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  625.650674] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  625.650876] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[  625.650890] [drm] GuC firmware load skipped
>[  625.651952] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  625.652051] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  625.652104] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  625.652156] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  625.652208] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  625.652349] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:1a001818 hp_port:38
>[  625.659132] [drm:intel_backlight_device_register [i915]] Connector eDP-1 backlight sysfs interface registered
>[  625.659660] [drm:intel_dp_connector_register [i915]] registering DPDDC-A bus for card0-eDP-1
>[  625.661701] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-1
>[  625.663589] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-2
>[  625.665157] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  625.666917] [drm:intel_opregion_register [i915]] 4 outputs detected
>[  625.683560] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  625.686999] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input23
>[  625.688181] [drm:drm_setup_crtcs] 
>[  625.688189] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  625.688251] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  625.688337] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  625.688384] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  625.688428] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  625.688471] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  625.689915] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  625.689918] [drm] DRM_I915_DEBUG enabled
>[  625.689919] [drm] DRM_I915_DEBUG_GEM enabled
>[  625.690306] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  625.691009] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] status updated from unknown to connected
>[  625.691074] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  625.691086] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  625.691090] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  625.691094] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  625.691157] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  625.691202] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  625.691280] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  625.691433] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  625.695314] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  625.695877] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  625.695928] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  625.696027] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  625.696042] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] status updated from unknown to disconnected
>[  625.696045] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  625.696050] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  625.696096] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  625.696141] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  625.696186] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  625.696246] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  625.705941] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.714613] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.723968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.732649] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.741400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.750102] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.758754] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.767534] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.776311] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.785085] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.793866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.802651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.811511] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.820306] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.829096] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.837879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.846657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.855518] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.864297] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.873098] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.881899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.890756] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.899593] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.908395] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.917323] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.926203] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.935076] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.943947] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.952840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.961747] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.970792] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.979897] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  625.979948] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  625.980065] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  625.980185] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  625.980336] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  625.980358] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] status updated from unknown to disconnected
>[  625.980367] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  625.980376] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  625.980495] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  625.980609] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  625.980723] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  626.062897] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  626.067091] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  626.067249] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  626.067263] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  626.067393] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  626.067566] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  626.067592] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] status updated from unknown to connected
>[  626.069079] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  626.069092] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  626.069102] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  626.069108] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  626.069279] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  626.069291] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  626.069301] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  626.069311] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  626.069320] [drm:drm_mode_debug_printmodeline] Modeline 80:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  626.069330] [drm:drm_mode_debug_printmodeline] Modeline 77:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  626.069339] [drm:drm_mode_debug_printmodeline] Modeline 79:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  626.069349] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  626.069359] [drm:drm_mode_debug_printmodeline] Modeline 76:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  626.069368] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  626.069378] [drm:drm_mode_debug_printmodeline] Modeline 97:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  626.069387] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  626.069397] [drm:drm_mode_debug_printmodeline] Modeline 86:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  626.069406] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  626.069416] [drm:drm_mode_debug_printmodeline] Modeline 81:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  626.069425] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  626.069434] [drm:drm_mode_debug_printmodeline] Modeline 92:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  626.069444] [drm:drm_mode_debug_printmodeline] Modeline 98:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  626.069453] [drm:drm_mode_debug_printmodeline] Modeline 74:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  626.069463] [drm:drm_mode_debug_printmodeline] Modeline 83:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  626.069472] [drm:drm_mode_debug_printmodeline] Modeline 99:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  626.069481] [drm:drm_mode_debug_printmodeline] Modeline 75:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  626.069490] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  626.069500] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  626.069557] [drm:drm_setup_crtcs] connector 51 enabled? yes
>[  626.069564] [drm:drm_setup_crtcs] connector 59 enabled? no
>[  626.069570] [drm:drm_setup_crtcs] connector 64 enabled? no
>[  626.069576] [drm:drm_setup_crtcs] connector 68 enabled? yes
>[  626.069743] [drm:intel_fb_initial_config [i915]] connector eDP-1 has no encoder or crtc, skipping
>[  626.071446] [drm:intel_fb_initial_config [i915]] connector DP-1 not enabled, skipping
>[  626.071588] [drm:intel_fb_initial_config [i915]] connector DP-2 not enabled, skipping
>[  626.071724] [drm:intel_fb_initial_config [i915]] connector HDMI-A-1 has no encoder or crtc, skipping
>[  626.071914] [drm:intel_fb_initial_config [i915]] fallback: Not all outputs enabled
>[  626.071987] [drm:intel_fb_initial_config [i915]] Enabled: 0, detected: 2
>[  626.072060] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  626.072083] [drm:drm_setup_crtcs] looking for cmdline mode on connector 51
>[  626.072088] [drm:drm_setup_crtcs] looking for preferred mode on connector 51 0
>[  626.072091] [drm:drm_setup_crtcs] found mode 1920x1080
>[  626.072094] [drm:drm_setup_crtcs] looking for cmdline mode on connector 68
>[  626.072097] [drm:drm_setup_crtcs] looking for preferred mode on connector 68 0
>[  626.072100] [drm:drm_setup_crtcs] found mode 1920x1080
>[  626.072103] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  626.072179] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 33 (0,0)
>[  626.072196] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 42 (0,0)
>[  626.072301] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  626.075780] [drm:intelfb_create [i915]] allocated 1920x1080 fb: 0x00040000
>[  626.076878] fbcon: inteldrmfb (fb0) is primary device
>[  626.078109] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  626.078177] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  626.078248] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  626.078316] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  626.078390] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  626.078455] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  626.078524] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  626.078591] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  626.078657] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  626.078724] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  626.078850] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  626.078915] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  626.078923] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  626.078988] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  626.078993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  626.079059] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  626.079125] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  626.079190] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  626.079256] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  626.079321] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  626.079391] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  626.079456] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  626.079522] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  626.079587] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  626.079653] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  626.079718] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  626.079831] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  626.079898] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  626.079967] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  626.080032] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  626.080099] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  626.080166] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  626.080231] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  626.080296] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  626.080361] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  626.080366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  626.080431] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  626.080436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  626.080502] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  626.080567] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  626.080632] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  626.080698] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  626.080793] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  626.080861] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  626.080928] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  626.080994] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  626.081059] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  626.081125] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  626.081191] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  626.081261] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  626.081339] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  626.081407] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  626.081481] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  626.081547] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  626.081614] [drm:skl_update_scaler [i915]] scaler_user index 1.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  626.082307] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  626.082397] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  626.082614] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  626.084409] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  626.087801] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  626.087849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  626.087895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  626.087950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  626.087995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  626.088040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  626.088084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  626.088129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  626.088173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  626.088217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  626.088262] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  626.088312] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  626.088360] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  626.088631] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  626.088676] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  626.090910] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  626.090975] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  626.091043] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000068
>[  626.091093] [drm:wait_panel_status [i915]] Wait complete
>[  626.091141] [drm:edp_panel_on [i915]] Wait for panel power on
>[  626.091193] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 0000006b
>[  626.292007] [drm:wait_panel_status [i915]] Wait complete
>[  626.294679] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  626.294831] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  626.294919] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  626.295944] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  626.296025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  626.297373] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  626.297737] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016eba6fc8
>[  626.300349] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  626.300565] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  626.300647] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  626.300846] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  626.300962] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  626.301044] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  626.301199] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  626.301281] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  626.301634] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  626.301715] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  626.302202] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88016eba2548
>[  626.304552] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  626.305227] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  626.305316] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  626.305544] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  626.305589] [drm:hsw_audio_config_update [i915]] using automatic N
>[  626.322291] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  626.322352] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  626.322526] [drm:intel_ddi_get_config [i915]] pipe has 24 bpp for eDP panel, overriding BIOS-provided max 18 bpp
>[  626.322599] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  626.322995] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  626.323087] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  626.323335] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  626.324015] Console: switching to colour frame buffer device 240x67
>[  626.353712] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  626.369659] snd_hda_intel 0000:00:0e.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  626.371207] Console: switching to colour dummy device 80x25
>[  626.394201] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC298: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker
>[  626.394206] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  626.394208] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[  626.394209] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  626.394211] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  626.394213] snd_hda_codec_realtek hdaudioC0D0:      Mic=0x18
>[  626.431166] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  626.431207] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  626.431242] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  626.431313] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  626.431350] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  626.431386] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  626.431422] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  626.431456] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  626.450511] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input24
>[  626.455596] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:0e.0/sound/card0/input25
>[  626.457001] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input26
>[  626.461315] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input27
>[  626.462547] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input28
>[  626.463786] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input29
>[  626.465056] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input30
>[  626.543078] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  626.543126] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  626.543161] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  626.543205] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  626.543241] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  626.543276] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  626.543310] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  626.543345] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  626.576025] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  626.576273] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  626.775581] [drm] RC6 on
>[  626.781970] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  626.782160] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  626.785678] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  626.785823] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  626.785890] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  626.836137] [drm:wait_panel_status [i915]] Wait complete
>[  626.836242] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  626.836610] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  626.837265] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  626.837488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  626.837562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  626.837632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  626.837695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  626.837842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  626.837907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  626.837972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  626.838037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  626.838102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  626.838166] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  626.838232] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  626.838301] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  626.838364] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  626.838674] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  626.838888] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  626.838953] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  626.839018] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  626.855575] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  626.855705] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  626.856610] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  626.857166] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  626.857352] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  626.872106] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  626.872277] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  626.872469] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  626.876699] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  626.876868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  626.876962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  626.877053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  626.877135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  626.877216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  626.877298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  626.877388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  626.877470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  626.877551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  626.877631] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  626.877725] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  626.877908] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  626.877996] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  626.878128] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  626.878212] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  626.878330] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  626.878450] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  626.878541] [drm:intel_power_well_disable [i915]] disabling DC off
>[  626.878624] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  626.878700] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  626.879406] [drm:intel_power_well_disable [i915]] disabling always-on
>[  626.893811] [drm:intel_uncore_forcewake_get [i915]] RPM wakelock ref not held during HW access
>[  626.897919] [drm:intel_power_well_enable [i915]] enabling always-on
>[  626.897976] [drm:intel_power_well_enable [i915]] enabling DC off
>[  626.898286] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  626.898361] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  626.898419] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  626.898620] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  626.900322] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  626.951368] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 0
>[  627.042893] Setting dangerous option inject_load_failure - tainting kernel
>[  627.071319] [drm] Injecting failure at checkpoint 1 [i915_driver_init_early:815]
>[  627.071382] i915 0000:00:02.0: [drm:i915_driver_load [i915]] Device initialization failed (-19)
>[  627.084885] snd_hda_intel 0000:00:0e.0: failed to add i915 component master (-19)
>[  627.101327] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC298: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker
>[  627.101331] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  627.101333] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[  627.101335] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  627.101337] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  627.101339] snd_hda_codec_realtek hdaudioC0D0:      Mic=0x18
>[  627.125022] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  627.132024] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  627.159070] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input31
>[  627.162467] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:0e.0/sound/card0/input32
>[  627.165037] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input33
>[  627.300289] Setting dangerous option inject_load_failure - tainting kernel
>[  627.328913] [drm:i915_driver_load [i915]] No PCH found.
>[  627.328965] [drm:intel_power_domains_init [i915]] Allowed DC state mask 09
>[  627.331546] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROXTON gen=9 pciid=0x5a84 rev=0x0a
>[  627.331588] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  627.331627] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: yes
>[  627.331666] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  627.331759] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  627.331808] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  627.331852] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  627.331892] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  627.331937] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: yes
>[  627.331980] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  627.332021] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  627.332064] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  627.332108] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  627.332151] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  627.332192] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  627.332233] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  627.332274] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  627.332316] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  627.332356] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  627.332398] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  627.332439] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: no
>[  627.332481] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  627.332521] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  627.332563] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  627.332604] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  627.332645] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: no
>[  627.332686] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  627.332755] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  627.332798] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  627.332842] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  627.332885] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  627.332929] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  627.332972] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  627.333016] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  627.333060] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  627.333071] [drm] Injecting failure at checkpoint 2 [i915_driver_init_mmio:947]
>[  627.354021] i915 0000:00:02.0: [drm:i915_driver_load [i915]] Device initialization failed (-19)
>[  627.370099] snd_hda_intel 0000:00:0e.0: failed to add i915 component master (-19)
>[  627.386012] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC298: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker
>[  627.386016] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  627.386018] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[  627.386020] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  627.386021] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  627.386024] snd_hda_codec_realtek hdaudioC0D0:      Mic=0x18
>[  627.409214] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  627.416224] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  627.442504] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input34
>[  627.445973] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:0e.0/sound/card0/input35
>[  627.447271] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input36
>[  627.594241] Setting dangerous option inject_load_failure - tainting kernel
>[  627.622669] [drm:i915_driver_load [i915]] No PCH found.
>[  627.622757] [drm:intel_power_domains_init [i915]] Allowed DC state mask 09
>[  627.625397] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROXTON gen=9 pciid=0x5a84 rev=0x0a
>[  627.625439] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  627.625479] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: yes
>[  627.625517] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  627.625556] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  627.625595] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  627.625634] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  627.625673] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  627.625755] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: yes
>[  627.625800] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  627.625847] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  627.625890] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  627.625933] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  627.625977] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  627.626020] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  627.626065] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  627.626107] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  627.626149] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  627.626192] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  627.626236] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  627.626277] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: no
>[  627.626318] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  627.626359] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  627.626401] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  627.626440] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  627.626481] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: no
>[  627.626523] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  627.626564] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  627.626605] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  627.626647] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  627.626687] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  627.626752] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  627.626797] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  627.626839] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  627.626883] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  627.629517] [drm] Injecting failure at checkpoint 3 [i915_driver_init_hw:1011]
>[  627.629588] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 0
>[  627.629635] [drm:sanitize_rc6_option [i915]] RC6 Base address not as expected.
>[  627.629656] [drm] RC6 disabled by BIOS
>[  627.645120] i915 0000:00:02.0: [drm:i915_driver_load [i915]] Device initialization failed (-19)
>[  627.654507] [IGT] drv_module_reload: exiting, ret=0
>[  627.659165] snd_hda_intel 0000:00:0e.0: failed to add i915 component master (-19)
>[  627.683566] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC298: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker
>[  627.683571] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  627.683574] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[  627.683576] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  627.683579] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  627.683581] snd_hda_codec_realtek hdaudioC0D0:      Mic=0x18
>[  627.706471] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  627.713750] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  627.743575] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input37
>[  627.747853] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:0e.0/sound/card0/input38
>[  627.749068] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input39
>[  627.867936] [IGT] drv_module_reload: executing
>[  627.868783] [IGT] drv_module_reload: starting subtest basic-reload-final
>[  628.062592] [drm:i915_driver_load [i915]] No PCH found.
>[  628.062644] [drm:intel_power_domains_init [i915]] Allowed DC state mask 09
>[  628.065222] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROXTON gen=9 pciid=0x5a84 rev=0x0a
>[  628.065264] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  628.065303] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: yes
>[  628.065342] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  628.065381] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  628.065419] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  628.065458] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  628.065496] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  628.065535] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: yes
>[  628.065573] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  628.065612] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  628.065650] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  628.065688] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  628.065792] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  628.065836] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  628.065879] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  628.065922] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  628.065965] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  628.066009] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  628.066052] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  628.066096] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: no
>[  628.066139] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  628.066182] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  628.066227] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  628.066270] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  628.066312] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: no
>[  628.066357] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  628.066397] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  628.066440] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  628.066483] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  628.066525] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  628.066568] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  628.066612] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  628.066655] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  628.066696] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  628.069618] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001
>[  628.069662] [drm:intel_device_info_runtime_init [i915]] slice total: 1
>[  628.069800] [drm:intel_device_info_runtime_init [i915]] subslice total: 3
>[  628.069844] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  628.069883] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  628.069923] [drm:intel_device_info_runtime_init [i915]] EU total: 18
>[  628.069963] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 6
>[  628.070003] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n
>[  628.070043] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: y
>[  628.070082] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[  628.070124] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  628.070164] [drm:i915_driver_load [i915]] use GPU sempahores? no
>[  628.070245] [drm] Memory usable by graphics device = 4096M
>[  628.070298] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  628.070341] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  628.070358] [drm] Replacing VGA console driver
>[  628.070499] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  628.070559] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 0
>[  628.070916] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x79df2018
>[  628.071022] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  628.071067] [drm:intel_opregion_setup [i915]] ASLE supported
>[  628.071137] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA)
>[  628.071587] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  628.071601] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  628.071603] [drm] Driver supports precise vblank timestamp query.
>[  628.071650] [drm:intel_bios_init [i915]] Set default to SSC at 100000 kHz
>[  628.071695] [drm:intel_bios_init [i915]] VBT signature "$VBT BROXTON        ", BDB version 207
>[  628.071797] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[  628.071843] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  628.071895] [drm:intel_opregion_get_panel_type [i915]] Failed to get panel details from OpRegion (-19)
>[  628.071941] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  628.071986] [drm:intel_bios_init [i915]] DRRS supported mode is seamless
>[  628.072042] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  628.072049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  628.072094] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  628.072139] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 180, controller 0
>[  628.072185] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[  628.072229] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 207 not known; assuming 38
>[  628.072283] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  628.072329] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  628.072376] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  628.072421] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  628.072467] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8
>[  628.072513] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  628.072559] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8
>[  628.073183] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  628.073251] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  628.073456] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  628.073526] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  628.073587] [drm:intel_power_well_enable [i915]] enabling always-on
>[  628.073628] [drm:intel_power_well_enable [i915]] enabling DC off
>[  628.073671] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  628.073778] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  628.073822] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  628.073907] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 1 already enabled, won't reprogram it
>[  628.073948] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  628.074063] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>[  628.074108] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  628.074281] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 1 already enabled, won't reprogram it
>[  628.074403] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>[  628.074461] [drm:intel_csr_ucode_init [i915]] Loading i915/bxt_dmc_ver1_07.bin
>[  628.077379] [drm] Finished loading DMC firmware i915/bxt_dmc_ver1_07.bin (v1.7)
>[  628.077836] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  628.080551] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  628.080618] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 7 (7.0 usec)
>[  628.080657] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 7 (7.0 usec)
>[  628.080697] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 8 (8.0 usec)
>[  628.080806] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 22 (22.0 usec)
>[  628.080848] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 22 (22.0 usec)
>[  628.080887] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 22 (22.0 usec)
>[  628.080927] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 22 (22.0 usec)
>[  628.080968] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 22 (22.0 usec)
>[  628.081016] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  628.081625] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  628.081674] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 624000 kHz
>[  628.081763] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 624000 kHz
>[  628.082161] [drm:intel_dp_init_connector [i915]] Adding eDP connector on port A
>[  628.082306] [drm:intel_dp_init_connector [i915]] using AUX A for port A (VBT)
>[  628.082540] [drm:intel_pps_dump_state [i915]] cur t1_t3 2000 t8 1 t9 1 t10 500 t11_t12 5000
>[  628.082586] [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
>[  628.082630] [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 50, power cycle delay 500
>[  628.082674] [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 1, off delay 200
>[  628.082759] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  628.082917] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  628.082963] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  628.590088] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  628.590173] [drm:wait_panel_status [i915]] Wait complete
>[  628.590259] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000068
>[  628.590338] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[  628.799412] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  628.800256] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  628.800913] [drm:intel_dp_init_connector [i915]] Detected EDP PSR Panel.
>[  628.801554] [drm:intel_dp_init_connector [i915]] EDP DPCD : 02 fb c7
>[  628.808627] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  628.808706] [drm:intel_dp_init_connector [i915]] Downclock mode is not found. DRRS not supported
>[  628.808971] [drm:intel_panel_setup_backlight [i915]] Connector eDP-1 backlight initialized, disabled, brightness 0/96000
>[  628.809116] [drm:intel_ddi_init [i915]] VBT says port B has lspcon
>[  628.809200] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B
>[  628.809297] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT)
>[  628.809911] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  628.810383] [drm:drm_dp_i2c_do_msg] native defer
>[  628.811661] [drm:drm_dp_i2c_do_msg] native defer
>[  628.812941] [drm:drm_dp_i2c_do_msg] native defer
>[  628.814213] [drm:drm_dp_i2c_do_msg] native defer
>[  628.815612] [drm:drm_dp_i2c_do_msg] native defer
>[  628.816418] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  628.816888] [drm:drm_dp_i2c_do_msg] native defer
>[  628.818203] [drm:drm_dp_i2c_do_msg] native defer
>[  628.819482] [drm:drm_dp_i2c_do_msg] native defer
>[  628.820755] [drm:drm_dp_i2c_do_msg] native defer
>[  628.822023] [drm:drm_dp_i2c_do_msg] native defer
>[  628.822871] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: a8 (err 0)
>[  628.822937] [drm:lspcon_init [i915]] LSPCON detected
>[  628.823402] [drm:drm_dp_i2c_do_msg] native defer
>[  628.824710] [drm:drm_dp_i2c_do_msg] native defer
>[  628.825980] [drm:drm_dp_i2c_do_msg] native defer
>[  628.827318] [drm:drm_dp_i2c_do_msg] native defer
>[  628.828659] [drm:drm_dp_i2c_do_msg] native defer
>[  628.829630] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  628.830249] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  628.830831] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.1 SW-rev 1.39
>[  628.830902] [drm:lspcon_init [i915]] Success: LSPCON init
>[  628.830979] [drm:intel_ddi_init [i915]] LSPCON init success on port B
>[  628.831113] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  628.831275] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  628.831450] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[  628.831574] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x2 for port C (VBT)
>[  628.831683] [drm:intel_dsi_init [i915]] 
>[  628.831985] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:33:pipe A] hw state readout: disabled
>[  628.832076] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:42:pipe B] hw state readout: disabled
>[  628.832169] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:49:pipe C] hw state readout: disabled
>[  628.832251] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0
>[  628.832331] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0
>[  628.832412] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0
>[  628.832495] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI A] hw state readout: disabled, pipe A
>[  628.832576] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI B] hw state readout: disabled, pipe A
>[  628.832650] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A
>[  628.832725] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B
>[  628.832842] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C
>[  628.832925] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:63:DDI C] hw state readout: disabled, pipe A
>[  628.833002] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST A] hw state readout: disabled, pipe A
>[  628.833077] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST B] hw state readout: disabled, pipe B
>[  628.833154] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:67:DP-MST C] hw state readout: disabled, pipe C
>[  628.833242] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:eDP-1] hw state readout: disabled
>[  628.833330] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-1] hw state readout: disabled
>[  628.833415] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:64:DP-2] hw state readout: disabled
>[  628.833495] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:68:HDMI-A-1] hw state readout: disabled
>[  628.833576] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][setup_hw_state]
>[  628.833648] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  628.833719] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  628.833830] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  628.833841] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  628.833915] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  628.833929] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  628.834003] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  628.834078] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  628.834156] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  628.834230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  628.834308] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  628.834389] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  628.834466] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  628.834537] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  628.834610] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  628.834681] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  628.834792] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  628.834874] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][setup_hw_state]
>[  628.834951] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  628.835025] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  628.835102] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  628.835112] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  628.835184] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  628.835194] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  628.835269] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  628.835339] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  628.835411] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  628.835482] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  628.835553] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  628.835629] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  628.835703] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  628.835815] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  628.835893] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  628.835970] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  628.836046] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  628.836129] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][setup_hw_state]
>[  628.836205] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  628.836279] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  628.836352] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  628.836364] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  628.836434] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  628.836444] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  628.836517] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  628.836592] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  628.836668] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  628.836771] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  628.836848] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  628.836925] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  628.837002] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  628.837078] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  628.837155] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  628.837227] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  628.837510] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  628.837608] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  628.837821] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  628.837923] [drm:intel_huc_init [i915]] HuC firmware pending, path i915/bxt_huc_ver01_07_1398.bin
>[  628.837967] [drm:intel_uc_fw_fetch [i915]] before requesting firmware: uC fw fetch status PENDING
>[  628.838362] [drm:intel_uc_fw_fetch [i915]] fetch uC fw from i915/bxt_huc_ver01_07_1398.bin succeeded, fw ffff88016d470458
>[  628.838408] [drm:intel_uc_fw_fetch [i915]] firmware version 1.7 OK (minimum 1.7)
>[  628.839459] [drm:intel_uc_fw_fetch [i915]] uC fw fetch status SUCCESS, obj ffff880174608040
>[  628.839813] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  628.840020] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  628.840389] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  628.842797] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  628.842950] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  628.843076] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  628.843199] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  628.843269] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[  628.843278] [drm] GuC firmware load skipped
>[  628.844150] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  628.844237] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  628.844283] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  628.844330] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  628.844378] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  628.844500] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:1a001818 hp_port:38
>[  628.847359] [drm:intel_backlight_device_register [i915]] Connector eDP-1 backlight sysfs interface registered
>[  628.847474] [drm:intel_dp_connector_register [i915]] registering DPDDC-A bus for card0-eDP-1
>[  628.849331] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-1
>[  628.851417] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-2
>[  628.854372] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  628.856163] [drm:intel_opregion_register [i915]] 4 outputs detected
>[  628.873172] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  628.876736] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input40
>[  628.877666] [drm:drm_setup_crtcs] 
>[  628.877744] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  628.877808] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  628.877895] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  628.877942] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  628.877991] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  628.878035] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  628.879212] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  628.879215] [drm] DRM_I915_DEBUG enabled
>[  628.879215] [drm] DRM_I915_DEBUG_GEM enabled
>[  628.879506] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  628.879952] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] status updated from unknown to connected
>[  628.880014] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  628.880027] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  628.880031] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  628.880034] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  628.880095] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  628.880141] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  628.880220] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  628.880375] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  628.882646] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  628.883131] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  628.883178] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  628.883270] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  628.883283] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] status updated from unknown to disconnected
>[  628.883287] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  628.883291] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  628.883336] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  628.883379] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  628.883423] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  628.883482] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  628.893352] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  628.902072] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  628.910930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  628.919660] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  628.928326] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  628.937051] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  628.945786] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  628.954488] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  628.963252] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  628.972070] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  628.980878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  628.989741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  628.998589] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.007426] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.016271] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.025111] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.033946] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.042840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.051674] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.060640] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.069862] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.078882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.087839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.096859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.105890] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.114849] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.123869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.132937] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.141959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.150988] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.160020] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.169051] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  629.169101] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  629.169231] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  629.169365] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  629.169534] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  629.169559] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] status updated from unknown to disconnected
>[  629.169568] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  629.169579] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  629.169714] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  629.170175] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  629.170309] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  629.251807] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  629.255996] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  629.256153] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  629.256167] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  629.256298] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  629.256470] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  629.256495] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] status updated from unknown to connected
>[  629.257496] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  629.257506] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  629.257516] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  629.257522] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  629.258091] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  629.258106] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  629.258116] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  629.258126] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  629.258136] [drm:drm_mode_debug_printmodeline] Modeline 80:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  629.258145] [drm:drm_mode_debug_printmodeline] Modeline 77:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  629.258158] [drm:drm_mode_debug_printmodeline] Modeline 79:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  629.258170] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  629.258180] [drm:drm_mode_debug_printmodeline] Modeline 76:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  629.258190] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  629.258199] [drm:drm_mode_debug_printmodeline] Modeline 97:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  629.258209] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  629.258219] [drm:drm_mode_debug_printmodeline] Modeline 86:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  629.258228] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  629.258241] [drm:drm_mode_debug_printmodeline] Modeline 81:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  629.258251] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  629.258260] [drm:drm_mode_debug_printmodeline] Modeline 92:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  629.258272] [drm:drm_mode_debug_printmodeline] Modeline 98:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  629.258282] [drm:drm_mode_debug_printmodeline] Modeline 74:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  629.258291] [drm:drm_mode_debug_printmodeline] Modeline 83:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  629.258301] [drm:drm_mode_debug_printmodeline] Modeline 99:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  629.258311] [drm:drm_mode_debug_printmodeline] Modeline 75:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  629.258323] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  629.258333] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  629.258387] [drm:drm_setup_crtcs] connector 51 enabled? yes
>[  629.258397] [drm:drm_setup_crtcs] connector 59 enabled? no
>[  629.258403] [drm:drm_setup_crtcs] connector 64 enabled? no
>[  629.258409] [drm:drm_setup_crtcs] connector 68 enabled? yes
>[  629.258575] [drm:intel_fb_initial_config [i915]] connector eDP-1 has no encoder or crtc, skipping
>[  629.258712] [drm:intel_fb_initial_config [i915]] connector DP-1 not enabled, skipping
>[  629.259323] [drm:intel_fb_initial_config [i915]] connector DP-2 not enabled, skipping
>[  629.259459] [drm:intel_fb_initial_config [i915]] connector HDMI-A-1 has no encoder or crtc, skipping
>[  629.259597] [drm:intel_fb_initial_config [i915]] fallback: Not all outputs enabled
>[  629.259731] [drm:intel_fb_initial_config [i915]] Enabled: 0, detected: 2
>[  629.260028] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  629.260047] [drm:drm_setup_crtcs] looking for cmdline mode on connector 51
>[  629.260052] [drm:drm_setup_crtcs] looking for preferred mode on connector 51 0
>[  629.260055] [drm:drm_setup_crtcs] found mode 1920x1080
>[  629.260058] [drm:drm_setup_crtcs] looking for cmdline mode on connector 68
>[  629.260061] [drm:drm_setup_crtcs] looking for preferred mode on connector 68 0
>[  629.260064] [drm:drm_setup_crtcs] found mode 1920x1080
>[  629.260068] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  629.260145] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 33 (0,0)
>[  629.260160] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 42 (0,0)
>[  629.260275] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  629.264081] [drm:intelfb_create [i915]] allocated 1920x1080 fb: 0x00040000
>[  629.265300] fbcon: inteldrmfb (fb0) is primary device
>[  629.266716] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  629.266844] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  629.266925] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  629.267004] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  629.267088] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  629.267162] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  629.267242] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  629.267319] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  629.267394] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  629.267470] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  629.267545] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  629.267618] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  629.267627] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  629.267701] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  629.267745] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  629.267822] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  629.267897] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  629.267972] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  629.268047] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  629.268121] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  629.268200] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  629.268275] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  629.268351] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  629.268426] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  629.268500] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  629.268575] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  629.268663] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  629.268773] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  629.268853] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  629.268927] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  629.269004] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  629.269080] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  629.269155] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  629.269229] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  629.269303] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  629.269309] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  629.269384] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  629.269390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  629.269466] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  629.269540] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  629.269615] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  629.269689] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  629.269851] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  629.269931] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  629.270006] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  629.270082] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  629.270157] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  629.270232] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  629.270307] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  629.270387] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  629.270477] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  629.270553] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  629.270637] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  629.270713] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  629.270848] [drm:skl_update_scaler [i915]] scaler_user index 1.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  629.271408] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  629.271471] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  629.271625] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  629.273134] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  629.277422] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  629.277470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  629.277516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  629.277571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  629.277615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  629.277660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  629.277705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  629.277802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  629.277846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  629.277892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  629.277938] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  629.277988] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  629.278036] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  629.278295] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  629.278340] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  629.279667] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  629.279756] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  629.279824] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000068
>[  629.279871] [drm:wait_panel_status [i915]] Wait complete
>[  629.279919] [drm:edp_panel_on [i915]] Wait for panel power on
>[  629.279971] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 0000006b
>[  629.480118] [drm:wait_panel_status [i915]] Wait complete
>[  629.482325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  629.482379] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  629.482436] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  629.483328] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  629.483381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  629.484530] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  629.484815] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b4a88
>[  629.486569] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  629.486761] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  629.486815] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  629.486908] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  629.486986] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  629.487041] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  629.487143] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  629.487196] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  629.487457] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  629.487510] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  629.487888] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8801720b0958
>[  629.489422] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  629.490004] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  629.490059] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  629.490317] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  629.490370] [drm:hsw_audio_config_update [i915]] using automatic N
>[  629.507239] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  629.507310] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  629.507507] [drm:intel_ddi_get_config [i915]] pipe has 24 bpp for eDP panel, overriding BIOS-provided max 18 bpp
>[  629.507590] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  629.507897] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  629.507968] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  629.508189] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  629.508731] Console: switching to colour frame buffer device 240x67
>[  629.535829] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  629.549976] snd_hda_intel 0000:00:0e.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  629.560952] [drm] RC6 on
>[  629.573778] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC298: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker
>[  629.573783] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  629.573785] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[  629.573787] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  629.573788] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  629.573791] snd_hda_codec_realtek hdaudioC0D0:      Mic=0x18
>[  629.607756] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  629.607796] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  629.607830] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  629.607902] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  629.607938] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  629.607972] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  629.608008] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  629.608044] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  629.636110] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input41
>[  629.640634] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:0e.0/sound/card0/input42
>[  629.646569] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input43
>[  629.648186] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input44
>[  629.649780] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input45
>[  629.651260] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input46
>[  629.653492] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input47
>[  629.840877] [IGT] drv_module_reload: exiting, ret=0
>[  630.061042] Console: switching to colour dummy device 80x25
>[  630.061386] [IGT] gvt_basic: executing
>[  630.164844] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  630.164884] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  630.164919] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  630.164970] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  630.165005] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  630.165040] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  630.165075] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  630.165110] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  630.194970] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  630.195225] [drm:intel_edp_backlight_off.part.24 [i915]] 
>[  630.397937] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  630.398151] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  630.406097] [drm:edp_panel_off [i915]] Turn eDP port A panel power off
>[  630.406192] [drm:edp_panel_off [i915]] Wait for panel power off time
>[  630.406268] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  630.456384] [drm:wait_panel_status [i915]] Wait complete
>[  630.456491] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  630.457023] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 33
>[  630.457302] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  630.457581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  630.457675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  630.457852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  630.457938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  630.458023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  630.458110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  630.458195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  630.458282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  630.458366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  630.458453] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  630.458538] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  630.458621] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  630.458708] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  630.459132] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  630.459272] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  630.459365] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  630.459457] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  630.473717] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  630.473919] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  630.474400] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 144000, actual 144000
>[  630.474704] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  630.475453] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  630.492269] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 2, on? 1) for crtc 42
>[  630.492442] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  630.492637] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 144000 kHz (VCO 1152000 kHz)
>[  630.497267] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  630.497354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  630.497445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  630.497536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  630.497618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  630.497699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  630.497907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  630.498007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  630.498120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  630.498221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  630.498315] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  630.498425] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  630.498527] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  630.498626] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  630.498997] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  630.499093] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  630.499220] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  630.499357] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  630.499459] [drm:intel_power_well_disable [i915]] disabling DC off
>[  630.499552] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  630.499634] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  630.500323] [drm:intel_power_well_disable [i915]] disabling always-on
>[  630.501631] [drm:intel_runtime_pm_get_noresume [i915]] RPM wakelock ref not held during HW access
>[  630.511092] [drm:intel_uncore_forcewake_get [i915]] RPM wakelock ref not held during HW access
>[  630.515162] [drm:intel_power_well_enable [i915]] enabling always-on
>[  630.515194] [drm:intel_power_well_enable [i915]] enabling DC off
>[  630.515482] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  630.515526] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  630.515562] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  630.515742] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  630.517111] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  630.563552] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 0
>[  630.693824] [drm:i915_driver_load [i915]] No PCH found.
>[  630.693876] [drm:intel_power_domains_init [i915]] Allowed DC state mask 09
>[  630.696461] [drm:intel_device_info_dump [i915]] i915 device info: platform=BROXTON gen=9 pciid=0x5a84 rev=0x0a
>[  630.696503] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  630.696542] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: yes
>[  630.696581] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  630.696620] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  630.696659] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  630.696697] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  630.696782] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  630.696823] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: yes
>[  630.696862] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  630.696904] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  630.696945] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  630.696986] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  630.697028] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  630.697069] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  630.697111] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  630.697152] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  630.697194] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  630.697235] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  630.697276] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  630.697317] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: no
>[  630.697359] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  630.697400] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  630.697441] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  630.697482] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  630.697524] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: no
>[  630.697565] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  630.697606] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  630.697646] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  630.697685] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  630.697748] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  630.697789] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  630.697830] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  630.697872] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  630.697913] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  630.702536] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001
>[  630.702578] [drm:intel_device_info_runtime_init [i915]] slice total: 1
>[  630.702617] [drm:intel_device_info_runtime_init [i915]] subslice total: 3
>[  630.702657] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  630.702696] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  630.702785] [drm:intel_device_info_runtime_init [i915]] EU total: 18
>[  630.702826] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 6
>[  630.702869] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n
>[  630.702910] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: y
>[  630.702950] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[  630.702994] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  630.703034] [drm:i915_driver_load [i915]] use GPU sempahores? no
>[  630.703111] [drm] Memory usable by graphics device = 4096M
>[  630.703160] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  630.703202] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  630.703217] [drm] Replacing VGA console driver
>[  630.703358] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  630.703417] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 0
>[  630.703704] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x79df2018
>[  630.704050] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  630.704095] [drm:intel_opregion_setup [i915]] ASLE supported
>[  630.704169] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA)
>[  630.704622] [drm:intel_gvt_init [i915]] Unsupported device. GVT-g is disabled
>[  630.704641] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  630.704642] [drm] Driver supports precise vblank timestamp query.
>[  630.704688] [drm:intel_bios_init [i915]] Set default to SSC at 100000 kHz
>[  630.704779] [drm:intel_bios_init [i915]] VBT signature "$VBT BROXTON        ", BDB version 207
>[  630.704828] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[  630.704874] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  630.704924] [drm:intel_opregion_get_panel_type [i915]] Failed to get panel details from OpRegion (-19)
>[  630.704972] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  630.705018] [drm:intel_bios_init [i915]] DRRS supported mode is seamless
>[  630.705074] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  630.705082] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  630.705126] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  630.705176] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 180, controller 0
>[  630.705224] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[  630.705270] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 207 not known; assuming 38
>[  630.705325] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  630.705371] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[  630.705417] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[  630.705462] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  630.705507] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8
>[  630.705552] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  630.705597] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8
>[  630.706238] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  630.706313] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  630.706518] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  630.706589] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  630.706651] [drm:intel_power_well_enable [i915]] enabling always-on
>[  630.706692] [drm:intel_power_well_enable [i915]] enabling DC off
>[  630.706868] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  630.706926] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  630.706971] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  630.707056] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 1 already enabled, won't reprogram it
>[  630.707098] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  630.707212] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>[  630.707258] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  630.707428] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 1 already enabled, won't reprogram it
>[  630.707550] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>[  630.707606] [drm:intel_csr_ucode_init [i915]] Loading i915/bxt_dmc_ver1_07.bin
>[  630.708861] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>[  630.710724] [drm] Finished loading DMC firmware i915/bxt_dmc_ver1_07.bin (v1.7)
>[  630.711923] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  630.711987] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 7 (7.0 usec)
>[  630.712027] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 7 (7.0 usec)
>[  630.712066] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 8 (8.0 usec)
>[  630.712106] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 22 (22.0 usec)
>[  630.712145] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 22 (22.0 usec)
>[  630.712184] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 22 (22.0 usec)
>[  630.712223] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 22 (22.0 usec)
>[  630.712262] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 22 (22.0 usec)
>[  630.712308] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  630.713396] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  630.713446] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 624000 kHz
>[  630.713490] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 624000 kHz
>[  630.713986] [drm:intel_dp_init_connector [i915]] Adding eDP connector on port A
>[  630.714133] [drm:intel_dp_init_connector [i915]] using AUX A for port A (VBT)
>[  630.714370] [drm:intel_pps_dump_state [i915]] cur t1_t3 2000 t8 1 t9 1 t10 500 t11_t12 5000
>[  630.714416] [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
>[  630.714460] [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 50, power cycle delay 500
>[  630.714503] [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 1, off delay 200
>[  630.714557] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[  630.715198] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  630.715248] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  631.222014] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  631.222077] [drm:wait_panel_status [i915]] Wait complete
>[  631.222141] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000068
>[  631.222200] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[  631.430938] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  631.431484] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  631.432222] [drm:intel_dp_init_connector [i915]] Detected EDP PSR Panel.
>[  631.432682] [drm:intel_dp_init_connector [i915]] EDP DPCD : 02 fb c7
>[  631.438260] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  631.438352] [drm:intel_dp_init_connector [i915]] Downclock mode is not found. DRRS not supported
>[  631.438574] [drm:intel_panel_setup_backlight [i915]] Connector eDP-1 backlight initialized, disabled, brightness 0/96000
>[  631.439217] [drm:intel_ddi_init [i915]] VBT says port B has lspcon
>[  631.439319] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B
>[  631.439437] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT)
>[  631.440382] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  631.441010] [drm:drm_dp_i2c_do_msg] native defer
>[  631.442412] [drm:drm_dp_i2c_do_msg] native defer
>[  631.443712] [drm:drm_dp_i2c_do_msg] native defer
>[  631.444989] [drm:drm_dp_i2c_do_msg] native defer
>[  631.446399] [drm:drm_dp_i2c_do_msg] native defer
>[  631.447216] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  631.447912] [drm:drm_dp_i2c_do_msg] native defer
>[  631.449410] [drm:drm_dp_i2c_do_msg] native defer
>[  631.450711] [drm:drm_dp_i2c_do_msg] native defer
>[  631.452027] [drm:drm_dp_i2c_do_msg] native defer
>[  631.453605] [drm:drm_dp_i2c_do_msg] native defer
>[  631.454425] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: a8 (err 0)
>[  631.454501] [drm:lspcon_init [i915]] LSPCON detected
>[  631.455005] [drm:drm_dp_i2c_do_msg] native defer
>[  631.456419] [drm:drm_dp_i2c_do_msg] native defer
>[  631.457729] [drm:drm_dp_i2c_do_msg] native defer
>[  631.459012] [drm:drm_dp_i2c_do_msg] native defer
>[  631.460406] [drm:drm_dp_i2c_do_msg] native defer
>[  631.461296] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  631.462045] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  631.462588] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-60-ad(NS) dev-ID MC2800 HW-rev 2.1 SW-rev 1.39
>[  631.462645] [drm:lspcon_init [i915]] Success: LSPCON init
>[  631.462703] [drm:intel_ddi_init [i915]] LSPCON init success on port B
>[  631.463120] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  631.463250] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  631.463397] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[  631.463495] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x2 for port C (VBT)
>[  631.463582] [drm:intel_dsi_init [i915]] 
>[  631.464158] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:33:pipe A] hw state readout: disabled
>[  631.464234] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:42:pipe B] hw state readout: disabled
>[  631.464306] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:49:pipe C] hw state readout: disabled
>[  631.464371] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0
>[  631.464432] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000000, on 0
>[  631.464494] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0
>[  631.464560] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI A] hw state readout: disabled, pipe A
>[  631.464623] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DDI B] hw state readout: disabled, pipe A
>[  631.464682] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DP-MST A] hw state readout: disabled, pipe A
>[  631.465189] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:61:DP-MST B] hw state readout: disabled, pipe B
>[  631.465248] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST C] hw state readout: disabled, pipe C
>[  631.465315] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:63:DDI C] hw state readout: disabled, pipe A
>[  631.465373] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST A] hw state readout: disabled, pipe A
>[  631.465431] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST B] hw state readout: disabled, pipe B
>[  631.465489] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:67:DP-MST C] hw state readout: disabled, pipe C
>[  631.465555] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:eDP-1] hw state readout: disabled
>[  631.465622] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:59:DP-1] hw state readout: disabled
>[  631.465687] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:64:DP-2] hw state readout: disabled
>[  631.466084] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:68:HDMI-A-1] hw state readout: disabled
>[  631.466154] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][setup_hw_state]
>[  631.466213] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  631.466269] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  631.466325] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  631.466333] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  631.466388] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  631.466397] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  631.466453] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  631.466510] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  631.466566] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  631.466622] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  631.466678] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  631.467051] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  631.467108] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  631.467167] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  631.467225] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  631.467284] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  631.467342] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  631.467408] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][setup_hw_state]
>[  631.467464] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  631.467520] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  631.467575] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  631.467582] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  631.467636] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  631.467645] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  631.467700] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  631.468197] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  631.468255] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  631.468312] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  631.468369] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  631.468432] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  631.468489] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  631.468548] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  631.468607] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  631.468664] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  631.469024] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  631.469090] [drm:intel_dump_pipe_config [i915]] [CRTC:49:pipe C][setup_hw_state]
>[  631.469146] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  631.469202] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  631.469258] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  631.469265] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  631.469320] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  631.469328] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  631.469386] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  631.469442] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0
>[  631.469501] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  631.469557] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  631.469612] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  631.469675] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  631.470048] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  631.470105] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 1C] disabled, scaler_id = -1
>[  631.470164] [drm:intel_dump_pipe_config [i915]] [PLANE:45:plane 2C] disabled, scaler_id = -1
>[  631.470221] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor C] disabled, scaler_id = -1
>[  631.470459] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  631.470558] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  631.470689] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  631.471178] [drm:intel_huc_init [i915]] HuC firmware pending, path i915/bxt_huc_ver01_07_1398.bin
>[  631.471236] [drm:intel_uc_fw_fetch [i915]] before requesting firmware: uC fw fetch status PENDING
>[  631.471678] [drm:intel_uc_fw_fetch [i915]] fetch uC fw from i915/bxt_huc_ver01_07_1398.bin succeeded, fw ffff88016f804fd8
>[  631.472077] [drm:intel_uc_fw_fetch [i915]] firmware version 1.7 OK (minimum 1.7)
>[  631.473363] [drm:intel_uc_fw_fetch [i915]] uC fw fetch status SUCCESS, obj ffff880121ea8040
>[  631.473634] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  631.474151] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  631.474497] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  631.477150] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  631.477302] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  631.477428] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  631.477553] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  631.477625] [drm:intel_guc_setup [i915]] GuC fw status: path i915/bxt_guc_ver8_7.bin, fetch NONE, load NONE
>[  631.477634] [drm] GuC firmware load skipped
>[  631.478829] [drm:intel_update_cdclk [i915]] Current CD clock rate: 144000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  631.478916] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  631.478960] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  631.479004] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  631.479047] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  631.479166] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:1a001818 hp_port:38
>[  631.482267] [drm:intel_backlight_device_register [i915]] Connector eDP-1 backlight sysfs interface registered
>[  631.482380] [drm:intel_dp_connector_register [i915]] registering DPDDC-A bus for card0-eDP-1
>[  631.484299] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-1
>[  631.486355] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-2
>[  631.488455] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  631.490494] [drm:intel_opregion_register [i915]] 4 outputs detected
>[  631.507471] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  631.511114] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input48
>[  631.512553] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  631.512556] [drm] DRM_I915_DEBUG enabled
>[  631.512557] [drm] DRM_I915_DEBUG_GEM enabled
>[  631.512579] [drm:drm_setup_crtcs] 
>[  631.512585] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1]
>[  631.512649] [drm:intel_dp_detect [i915]] [CONNECTOR:51:eDP-1]
>[  631.512789] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  631.512837] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  631.512886] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  631.512931] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  631.514498] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID b\006UA\021\001 HW-rev 10.0 SW-rev 1.8
>[  631.514931] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] status updated from unknown to connected
>[  631.514994] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  631.515005] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:eDP-1] probed modes :
>[  631.515009] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  631.515013] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1]
>[  631.515074] [drm:intel_dp_detect [i915]] [CONNECTOR:59:DP-1]
>[  631.515119] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  631.515194] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  631.515352] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  631.518155] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 00
>[  631.518578] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  631.518626] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  631.518924] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  631.518940] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] status updated from unknown to disconnected
>[  631.518943] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:59:DP-1] disconnected
>[  631.518948] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2]
>[  631.518994] [drm:intel_dp_detect [i915]] [CONNECTOR:64:DP-2]
>[  631.519040] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  631.519084] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  631.519144] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  631.528834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.537512] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.546227] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.554925] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.563663] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.572537] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.581321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.590007] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.598701] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.607524] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.616303] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.625161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.634033] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.642903] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.651861] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.660890] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.669888] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.678932] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.687976] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.697005] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.706037] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.715073] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.724169] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.733204] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.742240] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.751272] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.760306] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.769521] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.778554] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.787672] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.796783] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.805933] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  631.805984] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  631.806114] [drm:intel_power_well_disable [i915]] disabling dpio-common-bc
>[  631.806248] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  631.806418] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  631.806443] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] status updated from unknown to disconnected
>[  631.806452] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:64:DP-2] disconnected
>[  631.806462] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1]
>[  631.806597] [drm:intel_hdmi_detect [i915]] [CONNECTOR:68:HDMI-A-1]
>[  631.806724] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  631.806993] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  631.887897] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  631.892081] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: 44 (err 0)
>[  631.892238] [drm:intel_hdmi_set_edid [i915]] DP dual mode adaptor (type 1 HDMI) detected (max TMDS clock: 165000 kHz)
>[  631.892251] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  631.892380] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  631.892553] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  631.892578] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] status updated from unknown to connected
>[  631.893395] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 0 kHz
>[  631.893407] [drm:drm_edid_to_eld] ELD monitor G246HYL
>[  631.893417] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  631.893423] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[  631.893596] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:HDMI-A-1] probed modes :
>[  631.893609] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  631.893619] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  631.893629] [drm:drm_mode_debug_printmodeline] Modeline 94:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  631.893638] [drm:drm_mode_debug_printmodeline] Modeline 80:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  631.893648] [drm:drm_mode_debug_printmodeline] Modeline 77:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  631.893657] [drm:drm_mode_debug_printmodeline] Modeline 79:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  631.893667] [drm:drm_mode_debug_printmodeline] Modeline 78:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  631.893754] [drm:drm_mode_debug_printmodeline] Modeline 76:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  631.893768] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  631.893784] [drm:drm_mode_debug_printmodeline] Modeline 97:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  631.893796] [drm:drm_mode_debug_printmodeline] Modeline 93:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  631.893814] [drm:drm_mode_debug_printmodeline] Modeline 86:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  631.893826] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  631.893838] [drm:drm_mode_debug_printmodeline] Modeline 81:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  631.893850] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  631.893862] [drm:drm_mode_debug_printmodeline] Modeline 92:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  631.893875] [drm:drm_mode_debug_printmodeline] Modeline 98:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  631.893887] [drm:drm_mode_debug_printmodeline] Modeline 74:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  631.893909] [drm:drm_mode_debug_printmodeline] Modeline 83:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  631.893921] [drm:drm_mode_debug_printmodeline] Modeline 99:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  631.893933] [drm:drm_mode_debug_printmodeline] Modeline 75:"640x480" 60 25180 640 648 744 800 480 482 484 525 0x40 0xa
>[  631.893945] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  631.893957] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  631.894020] [drm:drm_setup_crtcs] connector 51 enabled? yes
>[  631.894029] [drm:drm_setup_crtcs] connector 59 enabled? no
>[  631.894039] [drm:drm_setup_crtcs] connector 64 enabled? no
>[  631.894047] [drm:drm_setup_crtcs] connector 68 enabled? yes
>[  631.894214] [drm:intel_fb_initial_config [i915]] connector eDP-1 has no encoder or crtc, skipping
>[  631.894359] [drm:intel_fb_initial_config [i915]] connector DP-1 not enabled, skipping
>[  631.894501] [drm:intel_fb_initial_config [i915]] connector DP-2 not enabled, skipping
>[  631.894642] [drm:intel_fb_initial_config [i915]] connector HDMI-A-1 has no encoder or crtc, skipping
>[  631.894777] [drm:intel_fb_initial_config [i915]] fallback: Not all outputs enabled
>[  631.894966] [drm:intel_fb_initial_config [i915]] Enabled: 0, detected: 2
>[  631.895100] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  631.895131] [drm:drm_setup_crtcs] looking for cmdline mode on connector 51
>[  631.895138] [drm:drm_setup_crtcs] looking for preferred mode on connector 51 0
>[  631.895144] [drm:drm_setup_crtcs] found mode 1920x1080
>[  631.895150] [drm:drm_setup_crtcs] looking for cmdline mode on connector 68
>[  631.895155] [drm:drm_setup_crtcs] looking for preferred mode on connector 68 0
>[  631.895160] [drm:drm_setup_crtcs] found mode 1920x1080
>[  631.895166] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  631.895292] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 33 (0,0)
>[  631.895317] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 42 (0,0)
>[  631.895504] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  631.900198] [drm:intelfb_create [i915]] allocated 1920x1080 fb: 0x00040000
>[  631.901640] fbcon: inteldrmfb (fb0) is primary device
>[  631.903013] [drm:intel_atomic_check [i915]] [CONNECTOR:51:eDP-1] checking for sink bpp constrains
>[  631.903058] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  631.903107] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  631.903152] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138120KHz
>[  631.903203] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  631.903246] [drm:intel_dp_compute_config [i915]] DP link bw required 414360 available 540000
>[  631.903293] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  631.903338] [drm:intel_dump_pipe_config [i915]] [CRTC:33:pipe A][modeset]
>[  631.903382] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  631.903427] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64
>[  631.903470] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  631.903513] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  631.903519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  631.903563] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  631.903566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa
>[  631.903611] [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa
>[  631.903655] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080
>[  631.903699] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  631.903778] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  631.903821] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  631.903868] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  631.903913] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  631.903958] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  631.904002] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  631.904046] [drm:intel_dump_pipe_config [i915]] [PLANE:29:plane 3A] disabled, scaler_id = -1
>[  631.904090] [drm:intel_dump_pipe_config [i915]] [PLANE:31:cursor A] disabled, scaler_id = -1
>[  631.904149] [drm:intel_atomic_check [i915]] [CONNECTOR:68:HDMI-A-1] checking for sink bpp constrains
>[  631.904193] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  631.904241] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  631.904285] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  631.904330] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  631.904376] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe B][modeset]
>[  631.904419] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  631.904463] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 1
>[  631.904506] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  631.904512] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  631.904555] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  631.904559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  631.904604] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  631.904647] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080
>[  631.904691] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  631.904771] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  631.904815] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  631.904862] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>[  631.904906] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  631.904950] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 1B] disabled, scaler_id = -1
>[  631.904994] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 2B] disabled, scaler_id = -1
>[  631.905038] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 3B] disabled, scaler_id = -1
>[  631.905082] [drm:intel_dump_pipe_config [i915]] [PLANE:40:cursor B] disabled, scaler_id = -1
>[  631.905131] [drm:intel_atomic_check [i915]] New cdclk calculated to be atomic 288000, actual 288000
>[  631.905186] [drm:bxt_get_dpll [i915]] [CRTC:33:pipe A] using pre-allocated PORT PLL A
>[  631.905231] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  631.905280] [drm:bxt_get_dpll [i915]] [CRTC:42:pipe B] using pre-allocated PORT PLL C
>[  631.905324] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe B
>[  631.905370] [drm:skl_update_scaler [i915]] scaler_user index 1.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  631.905992] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  631.906055] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  631.906208] [drm:intel_power_well_enable [i915]] enabling dpio-common-bc
>[  631.907814] [drm:bxt_set_cdclk [i915]] Changing CDCLK to 288000 kHz (VCO 1152000 kHz)
>[  631.911952] [drm:intel_update_cdclk [i915]] Current CD clock rate: 288000 kHz, VCO: 1152000 kHz, ref: 19200 kHz
>[  631.911999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI A]
>[  631.912047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DDI B]
>[  631.912104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST A]
>[  631.912150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST B]
>[  631.912196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST C]
>[  631.912242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DDI C]
>[  631.912288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST A]
>[  631.912334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST B]
>[  631.912380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DP-MST C]
>[  631.912426] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  631.912475] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL B
>[  631.912523] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  631.912899] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 33
>[  631.912944] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  631.914242] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  631.914304] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  631.914372] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000068
>[  631.914420] [drm:wait_panel_status [i915]] Wait complete
>[  631.914469] [drm:edp_panel_on [i915]] Wait for panel power on
>[  631.914521] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 0000006b
>[  632.116073] [drm:wait_panel_status [i915]] Wait complete
>[  632.118367] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  632.118424] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  632.118484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  632.119370] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  632.119426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  632.120663] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  632.120998] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880171f1ca88
>[  632.122871] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  632.123029] [drm:intel_edp_backlight_on.part.23 [i915]] 
>[  632.123085] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  632.123181] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 96000
>[  632.123262] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  632.123319] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  632.123470] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  632.123526] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  632.123811] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 2, on? 0) for crtc 42
>[  632.123866] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  632.124204] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880171f1d3d8
>[  632.125857] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  632.126438] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:68:HDMI-A-1], [ENCODER:63:DDI C]
>[  632.126496] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 32 bytes ELD
>[  632.126792] [drm:audio_config_hdmi_pixel_clock.isra.3 [i915]] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  632.126847] [drm:hsw_audio_config_update [i915]] using automatic N
>[  632.143670] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:51:eDP-1]
>[  632.143814] [drm:intel_atomic_commit_tail [i915]] [CRTC:33:pipe A]
>[  632.144024] [drm:intel_ddi_get_config [i915]] pipe has 24 bpp for eDP panel, overriding BIOS-provided max 18 bpp
>[  632.144112] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL A
>[  632.144349] [drm:verify_connector_state.isra.50 [i915]] [CONNECTOR:68:HDMI-A-1]
>[  632.144432] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe B]
>[  632.144652] [drm:verify_single_dpll_state.isra.76 [i915]] PORT PLL C
>[  632.145217] Console: switching to colour frame buffer device 240x67
>[  632.173001] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  632.188662] snd_hda_intel 0000:00:0e.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  632.206716] [IGT] gvt_basic: exiting, ret=77
>[  632.212044] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC298: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker
>[  632.212049] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  632.212051] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[  632.212053] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  632.212054] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  632.212057] snd_hda_codec_realtek hdaudioC0D0:      Mic=0x18
>[  632.245438] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  632.245477] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  632.245512] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  632.245585] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  632.245621] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  632.245656] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  632.245692] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  632.245807] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  632.265031] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input49
>[  632.271422] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:0e.0/sound/card0/input50
>[  632.272960] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input51
>[  632.274761] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input52
>[  632.276185] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input53
>[  632.277580] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input54
>[  632.278876] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:0e.0/sound/card0/input55
>[  632.791583] [drm] RC6 on

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